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drivers: sensor: adxl372: Updated driver with RTIO stream functionality #78941
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drivers: sensor: adxl372: Updated driver with RTIO stream functionality #78941
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Hello @vladislav-pejic, and thank you very much for your first pull request to the Zephyr project! |
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Looks like a really nice driver, very happy to see another device taking advantage of this functionality. Now I need to get an analog adxl372 on my bench it seems 💯
uint8_t has_z: 1; | ||
uint16_t accel_odr: 4; | ||
uint16_t fifo_byte_count: 12; | ||
} __attribute__((__packed__)); |
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Since its packed, its likely worth asserting the size is aligned to 4 bytes with a build assert here.
BUILD_ASSERT(sizeof(struct adxl372_fifo_data) % 4 == 0, "struct should be word aligned");
Or something along these lines, otherwise unaligned access is likely to bite someone as soon as the struct is changed.
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I agree and changes are in the latest code. I needed to do some rearranging to align it and should be ok now.
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#ifdef CONFIG_ADXL372_STREAM | ||
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static uint32_t accel_period_ns[] = { |
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possible to make const?
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Yes. Changes are in the latest code.
[ADXL372_ODR_6400HZ] = UINT32_C(100000000) / 6400, | ||
}; | ||
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static void adxl372_accel_convert_q31(q31_t *out, uint16_t data_in) |
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This should be doable with a constant multiplier that is pre-calculated, and the function can be inlined in that case.
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Can you check the latest code to see if this is what you had in mind?
{ | ||
struct sensor_value *out = (struct sensor_value *) data_out; | ||
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if (*fit > 0) { |
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looks like a spacing thing, missing a tab?
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Fixed
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__ASSERT_NO_MSG(req); | ||
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rtio_work_req_submit(req, iodev_sqe, adxl372_submit_helper); |
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Is the work queue usage really needed here? Ideally you'd use RTIO with the spi bus as well to allow for the gpio ISR to directly start a spi transfer and avoid the context swaps.
It seems like the fetch vs stream path are using different methods, which is fine but in the stream case the work queue can be bypassed.
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It is not necessary. I updated the implementation in the latest code.
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Updated ADXL372 driver with RTIO stream functionality. RTIO stream is using both FIFO threshold and FIFO full triggers. Together with RTIO stream, RTIO async read is also implemented. Signed-off-by: Vladislav Pejic <[email protected]>
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The following west manifest projects have been modified in this Pull Request:
Note: This message is automatically posted and updated by the Manifest GitHub Action. |
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Looks pretty good, some minor things I noticed and commented on
if (fifo_samples > sample_set_size/2) { | ||
fifo_samples -= sample_set_size/2; | ||
} else { | ||
LOG_ERR("fifo sample caunt error %d\n", fifo_samples); |
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s/caunt/count I think? or caught?
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Fixed
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uint32_t buf_avail = buf_len; | ||
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memcpy(buf, &hdr, sizeof(hdr)); |
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Could avoid the memcpy here perhaps by treating the buffer as a *hdr and initializing from there, though that requires that everything is word aligned.
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Done
/* Flush completions */ | ||
struct rtio_cqe *cqe; | ||
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do { |
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It's likely worth checking error codes here and bailing with rtio_iodev_sqe_err() on a bus error if one occurs.
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Can you give me more information? rtio_cqe_consume returns NULL when there is no CQE and that is cowered, and rtio_cqe_release is void func.
Did you mean for this part:
struct rtio_sqe *write_fifo_addr = rtio_sqe_acquire(data->rtio_ctx); ?
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When there is a completion queue event from the bus request, its result may be -errno, e.g.
struct rtio_cqe *cqe;
int res = 0;
do {
cqe = rtio_cqe_consume(...);
if (cqe != NULL) {
if(cqe->result < 0 && res == 0) {
/* handle spi/i2c bus error here */
LOG_ERR("first bus error: %d", cqe->result);
res = cqe->result;
}
rtio_cqe_release(cqe);
}
} while (cqe != NULL);
/* Bail/cancel attempt to read sensor on any error */
if (res != 0) {
rtio_iodev_sqe_err(...);
return;
}
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Fixed some formating issues. Signed-off-by: Vladislav Pejic <[email protected]>
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Updated ADXL372 driver with RTIO stream functionality.
RTIO stream is using both FIFO threshold and FIFO full triggers.
Together with RTIO stream, RTIO async read is also implemented.
Signed-off-by: Vladislav Pejic [email protected]