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Base implementation of the MMU + TLB + Exceptions #4

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Base implementation of the MMU + TLB + Exceptions #4

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+1,775 −106

Commits on Aug 22, 2018

  1. chore: add new deps

    @dignifiedquire
    dignifiedquire committed Aug 22, 2018
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  2. feat(cpu): implement mi registers

    @dignifiedquire
    dignifiedquire committed Aug 22, 2018
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  3. feat(fpu): gracefully handle unknown fmts 

    Seen these come up in a couple of places, for now just log warnings for unknowns and panic for those that are known.
    @dignifiedquire
    dignifiedquire committed Aug 22, 2018
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  4. feat(cp0): add missing registers 

    and implement details for status_reg
    @dignifiedquire
    dignifiedquire committed Aug 22, 2018
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Commits on Aug 23, 2018

  1. feat(pi): implement status and read dma

    @dignifiedquire
    dignifiedquire committed Aug 23, 2018
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  2. refactor(cp0): use constants instead of enum

    @dignifiedquire
    dignifiedquire committed Aug 23, 2018
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Commits on Aug 25, 2018

  1. feat(cp0): initial setup for address regions

    @dignifiedquire
    dignifiedquire committed Aug 25, 2018
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  2. feat(segment): improved lookups

    @dignifiedquire
    dignifiedquire committed Aug 25, 2018
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  3. start tlb impl

    @dignifiedquire
    dignifiedquire committed Aug 25, 2018
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Commits on Aug 26, 2018

  1. implement tlb opcodes

    @dignifiedquire
    dignifiedquire committed Aug 26, 2018
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  2. remove debug file

    @dignifiedquire
    dignifiedquire committed Aug 26, 2018
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  3. wip: exception handling

    @dignifiedquire
    dignifiedquire committed Aug 26, 2018
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  4. cleanup and set registers on tlb exceptions

    @dignifiedquire
    dignifiedquire committed Aug 26, 2018
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  5. add some more sp registers

    @dignifiedquire
    dignifiedquire committed Aug 26, 2018
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