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2018 10_2018 11_Report
In order to open up the Sinara ecosystem to rapid prototype development involving different microprocessor/connectivity boards, the Humpback EEM is being developed.
It will initially support connectivity to a flexible mixture of up to three downstream EEMs and/or Kasli upstream and allows one of several well known microprocess-like boards (WizNet, ESP32, Beaglebone Black, STM32 Nucleo 144, or Orange Pi Zero) to be used. It supports different ways of powering and features a small on-board FPGA to interface with the EEMs/Kasli.
Humpback offers an easy path to using the EEMs without Kasli and with cheap existing development boards. It can be used separate and decentralized, autonomous or with Ethernet connectivity or it can be used to adapt other devices to be used as EEMs.
The Kasli host side I2C tools have been extended to support automatic detection and enumeration of I2C switch trees. This is in preparation for Humpback and Banker where the EEM also constains an I2C switch and the EEPROM is not always visible from the root EEM port.
Several changes to the management of the internal attenuator state were made to enable state retrieval without side effects.
The Udukul-AD9910 variant has been extended to allow fully deterministic synchronization of the DDS internal dividers to the Kasli RTIO clock. This involves generation and configuration of the synchronization signals, configuration of the DDS to use those signals, automatic identification and tuning of the synchronization delays, monitoring of the synchronization setup and hold margins, and management of the delay parameters.
The work leads to deterministic synchronization across multiple Urukul devices, Urukul DDS channels, and between the RF switch/digital IO/attenuator action and the DDS phase/settings. It naturally extends to DRTIO.
Additional phase update modes (relative/continuous, absolute, and tracking/coherent) have been implemented.
A range of HITL unittests for Urukul and the Urukul-AD9910 variant have also been added to ARTIQ and are used in the ARTIQ CI infrastructure.
The design of the VCO/PLL based multi-GHz synthesizer Mirny is close to being complete. We expect the design to cover frequency ranges up to 4-6 GHz internally and up to >10 Ghz with a user-defined analog frontend mezzanine.