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Welcome to the Rapid Design Methods for Developing Hardware Accelerators Wiki

Design flow from SW to Xeon/FPGA

0. Environment Setup: Setup Instructions

1. Partition code into a Software Driver and a Software Version of the To-Be-Developed Hardware Accelerator: Software first

2. Accelerator Structure and SystemC Code Generation. Code Generation

3. Kernel-Level Development and Testing: Kernel development

4. Accelerator-Level Development and Testing, Multiple AU Template Memory Wrapper Integration

5. High-Level Synthesis and Generated RTL: HLS

6. Integration with CCIP RTL and hld_defines: CCIP integration

7. ASE-level Testing of Complete System: ASE testing

8. Running Quartus: Quartus flow

Chisel-based Hardware Design (beta)

We provide an alternative to SystemC-based hardware creation flow which is Chisel-based.

0. Introduction
1. Chisel HW library
2. Vector Add Example
3. Integration of a Chisel accelerator
4. ASE simulation and host code

Performance Simulator

1. User Guide for ASE Performance Simulator: ASE Perf User Guide

Tutorials

• Memory Copy

• Vector Addition

• Multi-threaded Cycle Detection

Design Examples

• Page Ranking

• Sobel Filter

• Burrows Wheeler Exact Match

Reference Guides

1. Python Interface Spec API

2. Memory Interface Spec

3. HLS Interface Spec