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Adding companion main class to generate GCD.v verilog source #126

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merged 5 commits into from
Mar 7, 2024
Merged

Adding companion main class to generate GCD.v verilog source #126

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a4415ab
Adding companion main class to generate GCD.v verilog source
Martoni Mar 7, 2024
0661927
Remove verilog file if exists before generate it
Martoni Mar 7, 2024
51c49d1
Use emitSystemVerilogFile to simplify
Martoni Mar 7, 2024
149c75c
Apply suggestions from code review
jackkoenig Mar 7, 2024
a066306
Merge branch 'main' into generate_verilog
jackkoenig Mar 7, 2024
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11 changes: 11 additions & 0 deletions src/main/scala/gcd/GCD.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,7 @@
package gcd

import chisel3._
import circt.stage.ChiselStage
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/**
* Compute GCD using subtraction method.
Expand Down Expand Up @@ -32,3 +33,13 @@ class GCD extends Module {
io.outputGCD := x
io.outputValid := y === 0.U
}

/**
* Generate Verilog sources and save it in file GCD.v
*/
object GCD extends App {
val verilog_src = ChiselStage.emitSystemVerilogFile(
new GCD(),
firtoolOpts = Array("-disable-all-randomization",
"-strip-debug-info"))
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}