Adding companion main class to generate GCD.v verilog source #126
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hutch31
reviewed
Mar 7, 2024
src/main/scala/gcd/GCD.scala
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| * Generate Verilog sources and save it in file GCD.v | ||
| */ | ||
| object GCD extends App { | ||
| val verilog_src = ChiselStage.emitSystemVerilog( |
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Would it not be simpler to call ChiselStage.emitSystemVerilogFile rather than emitting as a string and then writing?
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Yes of course ! I didn't know about this function.
That's why it's useful to provide an example :)
jackkoenig
approved these changes
Mar 7, 2024
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It's not straightforward to write code for generating verilog.
So this merge request provide a way to do it.
Fixes #54