fix(csr): add support non register interrupt pending and refactor xip/xie csr read/write #523
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sinceforYy
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Sep 13, 2024
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sinceforYy
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- menvcfg.stce, henvcfg.stce = 1 when enable sstc extension
- init stimecmp, vstimecmp all of 1s
- fix menvcfg, henvcfg wmask
- get platform interrupts (XiangShan->difftest->NEMU) to diff xip
- add read/write stimecmp in v mode
- refactor xip, xie csr read/write
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…/xie csr read/write * menvcfg.stce, henvcfg.stce = 1 when enable sstc extension * init stimecmp, vstimecmp all of 1s * fix menvcfg, henvcfg wmask * get platform interrupts (XiangShan->difftest->NEMU) to diff xip * refactor xip, xie csr read/write * add read/write stimecmp in v mode
huxuan0307
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Sep 20, 2024
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