fix(csr): add support non register interrupt pending and refactor xip…

…/xie csr read/write * menvcfg.stce, henvcfg.stce = 1 when enable sstc extension * init stimecmp, vstimecmp all of 1s * fix menvcfg, henvcfg wmask * get platform interrupts (XiangShan->difftest->NEMU) to diff xip * refactor xip, xie csr read/write * add read/write stimecmp in v mode
OpenXiangShan · Sep 20, 2024 · 8953fd8 · 8953fd8
1 parent e2a36f7
commit 8953fd8
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Showing 8 changed files with 374 additions and 160 deletions.
diff --git a/src/cpu/difftest/ref.c b/src/cpu/difftest/ref.c
@@ -230,6 +230,10 @@ void difftest_virtual_interrupt_is_hvictl_inject(bool virtualInterruptIsHvictlIn
 #endif
 }
 
+void difftest_non_reg_interrupt_pending(void *nonRegInterruptPending) {
+  memcpy(&cpu.non_reg_interrupt_pending, nonRegInterruptPending, sizeof(struct NonRegInterruptPending));
+}
+
 void difftest_enable_debug() {
 #ifdef CONFIG_SHARE
   dynamic_config.debug_difftest = true;

diff --git a/src/isa/riscv64/difftest/ref.c b/src/isa/riscv64/difftest/ref.c
@@ -52,7 +52,7 @@ void csr_prepare() {
   cpu.sepc    = sepc->val;
 
   cpu.satp     = satp->val;
-  cpu.mip      = mip->val;
+  cpu.mip      = get_mip();
   cpu.mie      = mie->val;
   cpu.mscratch = mscratch->val;
   cpu.sscratch = sscratch->val;

diff --git a/src/isa/riscv64/include/isa-def.h b/src/isa/riscv64/include/isa-def.h
@@ -41,6 +41,17 @@ struct ExecutionGuide {
   uint64_t jump_target;
 };
 
+struct NonRegInterruptPending {
+  bool platform_irp_meip;
+  bool platform_irp_mtip;
+  bool platform_irp_msip;
+  bool platform_irp_seip;
+  bool platform_irp_stip;
+  bool platform_irp_vseip;
+  bool platform_irp_vstip;
+  bool lcofi_req;
+};
+
 struct DebugInfo {
   uint64_t current_pc;
 };
@@ -136,6 +147,8 @@ typedef struct {
   bool guided_exec;
   struct ExecutionGuide execution_guide;
 
+  struct NonRegInterruptPending non_reg_interrupt_pending;
+
   // User defined debug info
   struct DebugInfo debug;
 #ifdef CONFIG_QUERY_REF

diff --git a/src/isa/riscv64/init.c b/src/isa/riscv64/init.c
@@ -82,6 +82,15 @@ void init_isa() {
   mnstatus->nmie = 1;
 #endif //CONFIG_RV_SMRNMI
 
+#ifdef CONFIG_RV_SSTC
+  menvcfg->stce = 1;
+  stimecmp->val = 0xffffffffffffffffULL;
+#ifdef CONFIG_RVH
+  henvcfg->stce = 1;
+  vstimecmp->val = 0xffffffffffffffffULL;
+#endif
+#endif
+
 #ifdef CONFIG_RV_PMP_ENTRY_16
   pmpcfg0->val = 0;
   pmpcfg2->val = 0;

diff --git a/src/isa/riscv64/local-include/csr.h b/src/isa/riscv64/local-include/csr.h
@@ -1487,6 +1487,7 @@ MAP(CSRS, CSRS_DECL)
 void csr_prepare();
 
 word_t gen_status_sd(word_t status);
+word_t get_mip();
 
 word_t csrid_read(uint32_t csrid);
 

diff --git a/src/isa/riscv64/reg.c b/src/isa/riscv64/reg.c
@@ -58,7 +58,7 @@ void isa_reg_display() {
       "", cpu.sstatus, scause->val, sepc->val);
   printf("satp: " FMT_WORD "\n", satp->val);
   printf("mip: " FMT_WORD " mie: " FMT_WORD " mscratch: " FMT_WORD " sscratch: " FMT_WORD "\n",
-      mip->val, mie->val, mscratch->val, sscratch->val);
+      get_mip(), mie->val, mscratch->val, sscratch->val);
   printf("mideleg: " FMT_WORD " medeleg: " FMT_WORD "\n",
       mideleg->val, medeleg->val);
   printf("mtval: " FMT_WORD " stval: " FMT_WORD " mtvec: " FMT_WORD " stvec: " FMT_WORD "\n",

diff --git a/src/isa/riscv64/system/intr.c b/src/isa/riscv64/system/intr.c
@@ -270,7 +270,7 @@ word_t raise_intr(word_t NO, vaddr_t epc) {
 }
 
 word_t isa_query_intr() {
-  word_t intr_vec = mie->val & mip->val;
+  word_t intr_vec = mie->val & (get_mip() | (mip->mtip << 7)); // In xs-diff-spike_defconfig, mip.mtip may be 1, while get_mip().mtip come from XiangShan, which is 0.
   if (!intr_vec || MUXDEF(CONFIG_RV_SMRNMI,!mnstatus->nmie, false)) return INTR_EMPTY;
   int intr_num;
 #ifdef CONFIG_RVH