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Update HAL STM32 #79089

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Update HAL STM32 #79089

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6c9c843
west.yml: update hal_stm32 to use latest version
gautierg-st Sep 27, 2024
17a1d87
drivers: clock: stm32 common: update ahb prescaler
gautierg-st Sep 27, 2024
1f85e60
drivers: dma: stm32 dmamux: fix for c0 hal update
gautierg-st Oct 2, 2024
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13 changes: 9 additions & 4 deletions drivers/clock_control/clock_stm32_ll_common.c
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Original file line number Diff line number Diff line change
Expand Up @@ -24,8 +24,13 @@
#define z_hsi_divider(v) LL_RCC_HSI_DIV_ ## v
#define hsi_divider(v) z_hsi_divider(v)

#if defined(LL_RCC_HCLK_DIV_1)
#define fn_ahb_prescaler(v) LL_RCC_HCLK_DIV_ ## v
#define ahb_prescaler(v) fn_ahb_prescaler(v)
#else

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drivers/clock_control/clock_stm32_ll_common.c:30 
-#define fn_ahb_prescaler(v) LL_RCC_HCLK_DIV_ ## v
-#define ahb_prescaler(v) fn_ahb_prescaler(v)
+#define fn_ahb_prescaler(v) LL_RCC_HCLK_DIV_##v
+#define ahb_prescaler(v)    fn_ahb_prescaler(v)
#define fn_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
#define ahb_prescaler(v) fn_ahb_prescaler(v)
#endif

#define fn_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
#define apb1_prescaler(v) fn_apb1_prescaler(v)
Expand Down Expand Up @@ -537,7 +542,7 @@
*/
if (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {
stm32_clock_switch_to_hsi();
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
LL_RCC_SetAHBPrescaler(ahb_prescaler(1));
}
LL_RCC_PLL_Disable();

Expand Down Expand Up @@ -800,9 +805,9 @@
set_up_plls();

if (DT_PROP(DT_NODELABEL(rcc), undershoot_prevention) &&
(STM32_CORE_PRESCALER == LL_RCC_SYSCLK_DIV_1) &&
(ahb_prescaler(STM32_CORE_PRESCALER) == ahb_prescaler(1)) &&
(MHZ(80) < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC)) {
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
LL_RCC_SetAHBPrescaler(ahb_prescaler(2));

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drivers/clock_control/clock_stm32_ll_common.c:810 
-		(ahb_prescaler(STM32_CORE_PRESCALER) == ahb_prescaler(1)) &&
-		(MHZ(80) < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC)) {
+	    (ahb_prescaler(STM32_CORE_PRESCALER) == ahb_prescaler(1)) &&
+	    (MHZ(80) < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC)) {
} else {
LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_CORE_PRESCALER));
}
Expand All @@ -827,9 +832,9 @@
#endif /* STM32_SYSCLK_SRC_... */

if (DT_PROP(DT_NODELABEL(rcc), undershoot_prevention) &&
(STM32_CORE_PRESCALER == LL_RCC_SYSCLK_DIV_1) &&
(ahb_prescaler(STM32_CORE_PRESCALER) == ahb_prescaler(1)) &&
(MHZ(80) < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC)) {
LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_CORE_PRESCALER));

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drivers/clock_control/clock_stm32_ll_common.c:837 
-		(ahb_prescaler(STM32_CORE_PRESCALER) == ahb_prescaler(1)) &&
-		(MHZ(80) < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC)) {
+	    (ahb_prescaler(STM32_CORE_PRESCALER) == ahb_prescaler(1)) &&
+	    (MHZ(80) < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC)) {
}

#if defined(FLASH_ACR_LATENCY)
Expand Down
3 changes: 2 additions & 1 deletion drivers/dma/dmamux_stm32.c
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Original file line number Diff line number Diff line change
Expand Up @@ -70,8 +70,9 @@
LISTIFY(DT_INST_PROP(0, dma_channels), DMAMUX_CHANNEL, (,))
};

#if !defined(CONFIG_SOC_SERIES_STM32G0X)
#if !defined(CONFIG_SOC_SERIES_STM32G0X) && \
!defined(CONFIG_SOC_SERIES_STM32C0X)
#define dmamux_channel_typedef DMAMUX_Channel_TypeDef

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drivers/dma/dmamux_stm32.c:75 
-#if !defined(CONFIG_SOC_SERIES_STM32G0X) && \
-	!defined(CONFIG_SOC_SERIES_STM32C0X)
+#if !defined(CONFIG_SOC_SERIES_STM32G0X) && !defined(CONFIG_SOC_SERIES_STM32C0X)
#else
#define dmamux_channel_typedef const DMAMUX_Channel_TypeDef
#endif
Expand Down
2 changes: 1 addition & 1 deletion west.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -233,7 +233,7 @@ manifest:
groups:
- hal
- name: hal_stm32
revision: 1ff820533c1b1c17f1a4d7d28ab99a94a234883b
revision: 6f0e5f70cb540c487e3e3678af2e95d0937f9863
path: modules/hal/stm32
groups:
- hal
Expand Down
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