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arch/xtensa: Add special register allocation generator #41676

Merged
merged 5 commits into from
Jan 20, 2022

Commits on Jan 10, 2022

  1. arch/xtensa: Add special register allocation generator

    Zephyr likes to use the various Xtensa scratch registers for its own
    purposes in several places.  Unfortunately, owing to the
    configurability of the architecture, we have to use different
    registers for different platforms.  This has been done so far with a
    collection of different tricks, some... less elegant than others.
    
    Put it all in one place.  This is a python script that emites a
    "zsr.h" header with register assignments for all the existing users.
    
    Signed-off-by: Andy Ross <[email protected]>
    Andy Ross committed Jan 10, 2022
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  2. arch/xtensa: Use ZSR assignments for the CPU pointer

    Use the zsr.h assignments for the special register containing the
    current CPU pointer.
    
    Signed-off-by: Andy Ross <[email protected]>
    Andy Ross committed Jan 10, 2022
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  3. arch/xtensa: Use ZSR assignments for the alloca exception

    This is actually Cadence-authored code, but its use of EXCSAVE1 as a
    sideband input to the exception handler is very much in the same
    family of tricks.  Use ZSR assignments here too.
    
    Signed-off-by: Andy Ross <[email protected]>
    Andy Ross committed Jan 10, 2022
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  4. arch/xtensa: Use ZSR assignments for stack flush markers

    The kernel coherence cache flush code was using a scratch register to
    mark the top of the stack.  Likewise a good candidate for ZSR use.
    
    Signed-off-by: Andy Ross <[email protected]>
    Andy Ross committed Jan 10, 2022
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  5. arch/xtensa: Use ZSR assignments for interrupt return

    We had a similar sequence for interrupt return, where we were
    selecting (actually only for the benefit of qemu) the highest priority
    EPCn/EPSn registers for our RFI instruction.  That works much better
    in python the preprocessor.
    
    Signed-off-by: Andy Ross <[email protected]>
    Andy Ross committed Jan 10, 2022
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