verilog-training

This repo contains the Verilog Training I started as a side project during my thesis journey at Nokia. To write this down, I'm using and following Jaywant's explanations and invaluable experience in the field.

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🔝 Table of Contents

The aim of this repo is to build a foundation in Verilog.

• 01 Simple Add Gate
• 02 Simple OR Gate
• 03 Simple XOR Gate
• 04 Simple NOR Gate
• 05 Simple NAND Gate
• 06 8-bit Add Gate
• 07 8-bit OR Gate
• 08 8-bit XOR Gate
• 09 8-bit NOR Gate
• 10 8-bit NAND Gate
• 11 2:1 MUX
• 12 4:1 MUX
• 13 8:1 MUX
• 14 16:1 MUX
• 15 16:1 MUX using 8:1 MUX
• 16 16:1 MUX using 4:1 MUX
• 17 ...

1- Simple Add Gate

• Verilog: ---.
• Modlue: ----.
• Test Bench: ----.