VTR seems to struggle with being smart about how it packs into memories

[WhiteNinjaZ]

While testing some small memory designs on the 7-series architecture I found that the order in which the diffrent BRAM sizes are specified matters greatly when it comes to which BRAMs VTR chooses to use for implementing the design. It appears that as long as the first BRAM given in the xml is large enough to fit a given memory it is chosen by default even if using smaller memories would be more efficient.

Expected Behaviour

VTR should try to be more efficient in how it chooses which RAM sizes to use (i.e. for a 16k memory should be packed into a RAMB18 and not a RAMB36). The type of BRAM chosen should not be dependent upon the order in which the BRAMs are given in the architecture.

Steps to Reproduce

On the current Xilinx architecture given here run the following infer_dual_port18.txt which should result in the pb usage given bellow:

Now switch the order of the RAMB36 and RAMB18 modes in the xml description and re-run. This should result in the following Pb type usage:

As you can see the type of BRAM used is completely changed by switching the order in which they are given in the xml