Skip to content

Issues: ucb-bar/chipyard

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

173 Open 484 Closed
173 Open 484 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

The current default IOBinder for Debug Module does not punch out the ndreset (and hartResetReq)? bug
#2048 opened Sep 15, 2024 by DecodeTheEncoded
3 tasks done
3
How to export my custom IO signals at RocketTile module to DigitalTop's IO? enhancement
#2046 opened Sep 14, 2024 by csgxiong
2 tasks done
2
Error while executing "make buildfile CONFIG=GemminiRocketConfig tutorial=sky130-openroad" bug
#2035 opened Sep 7, 2024 by chihyu-box
3 tasks done
2
How to Add a prefix at every module name when generating system verilog? enhancement
#2033 opened Sep 6, 2024 by csgxiong
2 tasks done
1
VLSI Flow broken for OpenRoad+Sky130 on chipyard 1.11.0 or above? bug
#2017 opened Aug 26, 2024 by Jerry-Tianchen
3 tasks done
Build-setup issue bug
#2016 opened Aug 26, 2024 by alsrbok
3 tasks done
4
build-setup.sh $(which conda) returns function bug
#2002 opened Aug 15, 2024 by allpan3
3 tasks done
1
Verilator simulations can be made an order of magnitude faster enhancement
#2000 opened Aug 13, 2024 by mayyxeng
2 tasks done
3
Program runs extremely slow on VCU118 for larger testcases bug
#1992 opened Aug 11, 2024 by Nerotos
3 tasks done
Error while running the coremark on largeBoomcore in chipyard bug
#1989 opened Aug 9, 2024 by waseem-10xe
3 tasks done
RoCC Punch Trough Signal enhancement
#1987 opened Aug 9, 2024 by eric900115
2 tasks done
6
ASAP7 + OpenRoad. ERROR: Can't open ABC output file. bug
#1936 opened Aug 1, 2024 by exhaust-create
3 tasks done
3
Tutorial for sky130+openroad vlsi fails due to unbounded memory usage bug
#1934 opened Jul 30, 2024 by TheMichaelGionet
3 tasks done
2
Chipyard1.110 version, vcs make failed bug
#1922 opened Jul 18, 2024 by YeyeQian
3 tasks done
2
Bare Metal VCU118 capability (similar to Arty100T) and Update to VCU118 documentation enhancement
#1889 opened May 29, 2024 by BMorgan1296
2 tasks done
4
Verilator simulation (RocketConfig default example) crashes on MacOS bug
#1886 opened May 28, 2024 by Frank-Zeyda
3 tasks done
4
Segfault running SimNetwork under verilator bug
#1885 opened May 24, 2024 by sethp
3 tasks done
11
SD Card interfaces times-out on the VCU118 (3 April 2024 commit) bug
#1875 opened May 9, 2024 by bchetwynd
3 tasks done
@T-K-233
1
IBex on VCU118 is not working (Probably bootrom issue) bug
#1867 opened Apr 30, 2024 by ksungkeun84
3 tasks done
Chip bringup documentation? enhancement
#1861 opened Apr 23, 2024 by noahgaertner
2 tasks done
@T-K-233
Compiling issues with chipyard/tests/nvdla.c bug
#1851 opened Apr 17, 2024 by Darol23
3 tasks done
LOADMEM= on non-LOADMEM-Capable Memory Models is Silently Ignored bug
#1844 opened Apr 9, 2024 by elamdf
3 tasks done
1
How to Bring Core signals to DigitalTop enhancement
#1843 opened Apr 9, 2024 by ashu-bitspilani
2 tasks done
How to print the cycle along with the instruction being executed at that cycle in RTL simulation. enhancement
#1821 opened Mar 14, 2024 by YiKangOY
2 tasks done
'Debugging with JTAG' section incomplete in docs enhancement
#1811 opened Mar 5, 2024 by sebastianornelas
2 tasks done
@T-K-233
2
ProTip! Adding no:label will show everything without a label.