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Proposal for a RISC-V extension allowing the use of 64-bit load/store operations in a 32-bit (RV32) architecture

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Zilsp (Integer Load/Store Pairs)

This repository contains the initial proposal for a RISC-V extension to enable new instructions that load/store 2*XLEN bits of data into/from pairs of registers.

DEPRECATED

NOTE: This repository has now been deprecated in favor of the fast-track extension that can be found here: https://github.com/riscv/riscv-zilsd

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Proposal for a RISC-V extension allowing the use of 64-bit load/store operations in a 32-bit (RV32) architecture

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