Initial support for riscv32{e|em|emc}_unknown_none_elf

[hegza]

We have a research prototype of an RV32EMC target and have been successfully running the e, em, emc programs on it. I'm hoping upstreaming this configuration would make the target maintenance slightly easier.

Configuration is based on the respective {i, im, imc} variants. As defined in RISC-V Unprivileged Spec. 20191213, the only change in RVE wrt. RVI is to reduce the number of integer registers to 16 (x0-x15), which also implies

• 2 callee saved registers instead of 12
• 32-bit / 4-byte stack alignment instead of 128 bits / 16 bytes

My initial presumption is that this will not impact how the target is defined for the compiler but only becomes relevant at the runtime level. I am willing to investigate, though.

EDIT: LLVM is now told about the presumed 32-bit stack alignment.

@Disasm @romancardenas

[rustbot]

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[rustbot]

Some changes occurred in src/doc/rustc/src/platform-support

cc @Noratrieb

These commits modify compiler targets.
(See the Target Tier Policy.)

[hegza]

error: data-layout for target riscv32e-unknown-none-elf, e-m:e-p:32:32-i64:64-n32-S32, differs from LLVM target's riscv32 default layout, e-m:e-p:32:32-i64:64-n32-S128

Apparently this test case wants the stack to be 128-bit aligned as is the default behavior on RISC-V. I revert back to 128-bit stack alignment to respect the test case.

[hegza]

@rustbot label +O-riscv