Add riscv vxworks targets

[biabbas]

Risc 32 and risc 64 targets are to be added in the target list.

[rustbot]

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[rustbot]

These commits modify compiler targets.
(See the Target Tier Policy.)

[rustbot]

Some changes occurred in src/doc/rustc/src/platform-support

cc @Noratrieb

[michaelmaitland]

What is // ? for?

[michaelmaitland]

On clang there is the -print-enabled-extensions option. When I pass that with -mcpu=generic-rv64 which is defined by the RISC-V LLVM backend, this is the output:

Extensions enabled for the given RISC-V target

    Name                 Version   Description
    i                    2.1       'I' (Base Integer Instruction Set)
    m                    2.0       'M' (Integer Multiplication and Division)
    a                    2.1       'A' (Atomic Instructions)
    f                    2.2       'F' (Single-Precision Floating-Point)
    d                    2.2       'D' (Double-Precision Floating-Point)
    c                    2.0       'C' (Compressed Instructions)
    zicsr                2.0       'zicsr' (CSRs)
    zifencei             2.0       'Zifencei' (fence.i)
    zmmul                1.0       'Zmmul' (Integer Multiplication)

Are we missing features here?

[michaelmaitland]

On clang there is the -print-enabled-extensions option. When I pass that with -mcpu=generic-rv32 which is defined by the RISC-V LLVM backend, this is the output:

Extensions enabled for the given RISC-V target

    Name                 Version   Description
    i                    2.1       'I' (Base Integer Instruction Set)
    m                    2.0       'M' (Integer Multiplication and Division)
    a                    2.1       'A' (Atomic Instructions)
    f                    2.2       'F' (Single-Precision Floating-Point)
    d                    2.2       'D' (Double-Precision Floating-Point)
    c                    2.0       'C' (Compressed Instructions)
    zicsr                2.0       'zicsr' (CSRs)
    zifencei             2.0       'Zifencei' (fence.i)
    zmmul                1.0       'Zmmul' (Integer Multiplication)

Are we missing features here?

[michaelmaitland]

Nit: Risc 32 and risc 64 targets are to be added in the target list. should say RISC-V instead of Risc and risc in PR description.