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riscv: add CSR-defining macros #219

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riscv: add CSR-defining macros #219

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b3d3f29
riscv: add CSR-defining macros
rmsyn May 30, 2024
5777e5f
riscv: add enum branch to CSR macro
rmsyn Jun 6, 2024
e4b5b12
fixup: fixes for rebase on latest HEAD
rmsyn Sep 14, 2024
f35b2bd
fixup: riscv: do not repeat macro field arguments
rmsyn Sep 14, 2024
7a6bca0
riscv: add try variants to read-only CSR macros
rmsyn Sep 15, 2024
545a30e
riscv: add try variants to write-only CSR macros
rmsyn Sep 15, 2024
575c6ff
riscv: modularize CSR macro field helpers
rmsyn Sep 15, 2024
699faa4
riscv: add explicit mask field to CSR macros
rmsyn Sep 15, 2024
1887cf6
riscv: add field label to CSR macros
rmsyn Sep 15, 2024
8a4027e
fixup: riscv: remove field args from CSR macro
rmsyn Sep 18, 2024
158db4f
fixup: riscv: remove CSR number from csr macro
rmsyn Sep 18, 2024
7ad499a
fixup: riscv: use result for CSR enum conversion
rmsyn Sep 18, 2024
7c3bed7
fixup: riscv: read-only CSR compile-time asserts
rmsyn Sep 20, 2024
359a834
fixup: riscv: write-only CSR compile-time asserts
rmsyn Sep 20, 2024
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1 change: 1 addition & 0 deletions riscv/CHANGELOG.md
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Expand Up @@ -20,6 +20,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- Add `Mcounteren` in-memory update functions
- Add `Mstatus` vector extension support
- Add fallible counterparts to all functions that `panic`
- Add CSR-defining macros to create in-memory types

### Fixed

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2 changes: 1 addition & 1 deletion riscv/src/lib.rs
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Expand Up @@ -36,7 +36,7 @@
#![allow(clippy::missing_safety_doc)]

pub mod asm;
pub(crate) mod bits;
pub mod bits;
pub mod delay;
pub mod interrupt;
pub mod register;
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3 changes: 3 additions & 0 deletions riscv/src/register.rs
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Expand Up @@ -107,6 +107,9 @@ pub mod minstreth;
mod mhpmeventx;
pub use self::mhpmeventx::*;

#[cfg(test)]
mod tests;

// TODO: Debug/Trace Registers (shared with Debug Mode)

// TODO: Debug Mode Registers
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