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clarify explicit store behavior for D bit
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@ved-rivos
ved-rivos committed Sep 10, 2023
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Expand Up @@ -42,7 +42,7 @@ A/D bits. The A and D bits are managed by these extensions as follows:
[NOTE]
====
The PTE updates due to memory accesses ordered-after a FENCE are not themselves
ordered-after the FENCE.
ordered by the FENCE.
Simpler implementations that cannot precisely order the PTE update before
subsequent explicit memory accesses to the associated virtual page by the local
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