Frozen

riscv · Oct 27, 2023 · a3efebc · a3efebc
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diff --git a/doc/riscv-bfloat16-preamble.adoc b/doc/riscv-bfloat16-preamble.adoc
@@ -6,9 +6,11 @@
 This document describes the BF16 format and instruction extensions to the 
 RISC-V Instruction Set Architecture.
 
-This document is in the link:http://riscv.org/spec-state[Stable State].
-Only limited changes may occur.
-For more information, see link:http://riscv.org/spec-state[here].
+[WARNING]
+.This document is in the link:http://riscv.org/spec-state[Frozen] State
+====
+Change is extremely unlikely. A high threshold will be used, and a change will only occur because of some truly critical issue being identified during the public review cycle. Any other desired or needed changes can be the subject of a follow-on new extension.
+====
 
 [NOTE]
 .Copyright and licensure:

diff --git a/doc/riscv-bfloat16.adoc b/doc/riscv-bfloat16.adoc
@@ -2,9 +2,9 @@
 = RISC-V BF16 Extensions
 :description: The BF16 format and instruction extensions for the RISC-V ISA.
 :company: RISC-V.org
-:revdate:  29 June, 2023
-:revnumber: v0.8.0
-:revremark: Draft
+:revdate: 27 October 2023
+:revnumber: 1.0.0-rc1
+:revremark: Frozen
 :url-riscv: http://riscv.org
 :doctype: book
 //:doctype: report