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VLSU Support #183

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VLSU Support #183

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9027a84
Last of master merge commit
aarongchan Jul 15, 2024
6510dd2
Unit and strided implemented
aarongchan Jul 18, 2024
b9afca0
Fixing bug in Decode, adapting new uop generator code with vlsu
aarongchan Jul 18, 2024
4794361
Fixing bugs, credit system should be good
aarongchan Jul 18, 2024
8d28028
Working version
aarongchan Jul 23, 2024
2d2deec
Updating test yaml
aarongchan Jul 23, 2024
6575562
Uop memory generator in VLSU, adding mem request status to loadstore …
aarongchan Jul 30, 2024
1adf72f
Rebased with master, vlsu_test
aarongchan Aug 1, 2024
b371d6f
Rebased, vlsu test
aarongchan Aug 1, 2024
a8df2e8
Updating expected output
aarongchan Aug 1, 2024
04b750c
Fixing test, removing vaddr ouptut for LSU, only for vector
aarongchan Aug 1, 2024
5fbdc4b
Merge remote-tracking branch 'origin' into vlsu
aarongchan Aug 1, 2024
c4e5384
Merging master into branch, restructuring some code
aarongchan Aug 2, 2024
5ddec1c
Merge remote-tracking branch 'origin' into vlsu
aarongchan Aug 2, 2024
a0052f5
Merging new non-blocking-cache changes for VLSU
aarongchan Aug 3, 2024
5ab2f6b
Cleanup and documentation
aarongchan Aug 5, 2024
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53 changes: 28 additions & 25 deletions arches/big_core.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ top.cpu.core0.extension.core_extensions:
pipelines:
[
["sys"], # exe0
["int", "div"], # exe1
["int", "div", "vset"], # exe1
["int", "mul"], # exe2
["int", "mul", "i2f", "cmov"], # exe3
["int"], # exe4
Expand Down Expand Up @@ -57,29 +57,32 @@ top.cpu.core0.rename.scoreboards:
# |
# V
integer.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"],
["lsu", 1, 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1, 1],
["iq5", 1, 1, 1, 1, 1, 1, 1]]
[["", "lsu", "vlsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"],
["lsu", 1, 1, 1, 1, 1, 1, 1, 1],
["vlsu", 1, 1, 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1, 1, 1],
["iq5", 1, 1, 1, 1, 1, 1, 1, 1]]
float.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"],
["lsu", 1, 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1, 1],
["iq5", 1, 1, 1, 1, 1, 1, 1]]
[["", "lsu", "vlsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"],
["lsu", 1, 1, 1, 1, 1, 1, 1, 1],
["vlsu", 1, 1, 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1, 1, 1],
["iq5", 1, 1, 1, 1, 1, 1, 1, 1]]
vector.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"],
["lsu", 1, 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1, 1],
["iq5", 1, 1, 1, 1, 1, 1, 1]]
[["", "lsu", "vlsu", "iq0", "iq1", "iq2", "iq3", "iq4", "iq5"],
["lsu", 1, 1, 1, 1, 1, 1, 1, 1],
["vlsu", 1, 1, 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1, 1, 1],
["iq5", 1, 1, 1, 1, 1, 1, 1, 1]]
16 changes: 16 additions & 0 deletions arches/isa_json/gen_uarch_rv64v_json.py
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,23 @@
"vsetivli" : {"pipe" : "vset", "latency" : 1},

# TODO: Vector Loads and Stores: Vector Unit-Stride Instructions
"vse8.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
"vse16.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
"vse32.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
"vse64.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
"vle8.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
"vle16.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
"vle32.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
"vle64.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
# TODO: Vector Loads and Stores: Vector Strided Instructions
"vsse8.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
"vsse16.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
"vsse32.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
"vsse64.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
"vlse8.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
"vlse16.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
"vlse32.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
"vlse64.v" : {"pipe" : "vlsu", "uop_gen" : "ARITH", "latency" : 1},
# TODO: Vector Loads and Stores: Vector Indexed Instructions
# TODO: Vector Loads and Stores: Unit-stride Fault-Only-First Loads
# TODO: Vector Loads and Stores: Vector Load/Store Segment Instructions
Expand Down
96 changes: 48 additions & 48 deletions arches/isa_json/olympia_uarch_rv64v.json
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Original file line number Diff line number Diff line change
Expand Up @@ -799,9 +799,9 @@
},
{
"mnemonic": "vle16.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vle16ff.v",
Expand All @@ -811,9 +811,9 @@
},
{
"mnemonic": "vle32.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vle32ff.v",
Expand All @@ -823,9 +823,9 @@
},
{
"mnemonic": "vle64.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vle64ff.v",
Expand All @@ -835,9 +835,9 @@
},
{
"mnemonic": "vle8.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vle8ff.v",
Expand Down Expand Up @@ -877,27 +877,27 @@
},
{
"mnemonic": "vlse16.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vlse32.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vlse64.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vlse8.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vluxei16.v",
Expand Down Expand Up @@ -1693,27 +1693,27 @@
},
{
"mnemonic": "vse16.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vse32.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vse64.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vse8.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vsetivli",
Expand Down Expand Up @@ -1885,27 +1885,27 @@
},
{
"mnemonic": "vsse16.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vsse32.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vsse64.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vsse8.v",
"pipe": "?",
"uop_gen": "NONE",
"latency": 0
"pipe": "vlsu",
"uop_gen": "ARITH",
"latency": 1
},
{
"mnemonic": "vssra.vi",
Expand Down
45 changes: 24 additions & 21 deletions arches/medium_core.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -50,26 +50,29 @@ top.cpu.core0.rename.scoreboards:
# |
# V
integer.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["lsu", 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1]]
[["", "lsu", "vlsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["lsu", 1, 1, 1, 1, 1, 1, 1],
["vlsu", 1, 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1, 1]]
float.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["lsu", 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1]]
[["", "lsu", "vlsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["lsu", 1, 1, 1, 1, 1, 1, 1],
["vlsu", 1, 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1, 1]]
vector.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["lsu", 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1]]
[["", "lsu", "vlsu", "iq0", "iq1", "iq2", "iq3", "iq4"],
["lsu", 1, 1, 1, 1, 1, 1, 1],
["vlsu", 1, 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1, 1],
["iq4", 1, 1, 1, 1, 1, 1, 1]]
39 changes: 21 additions & 18 deletions arches/small_core.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -42,23 +42,26 @@ top.cpu.core0.rename.scoreboards:
# |
# V
integer.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3"],
["lsu", 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1]]
[["", "lsu", "vlsu", "iq0", "iq1", "iq2", "iq3"],
["lsu", 1, 1, 1, 1, 1, 1],
["vlsu", 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1]]
float.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3"],
["lsu", 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1]]
[["", "lsu", "vlsu", "iq0", "iq1", "iq2", "iq3"],
["lsu", 1, 1, 1, 1, 1, 1],
["vlsu", 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1]]
vector.params.latency_matrix: |
[["", "lsu", "iq0", "iq1", "iq2", "iq3"],
["lsu", 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1]]
[["", "lsu", "vlsu", "iq0", "iq1", "iq2", "iq3"],
["lsu", 1, 1, 1, 1, 1, 1],
["vlsu", 1, 1, 1, 1, 1, 1],
["iq0", 1, 1, 1, 1, 1, 1],
["iq1", 1, 1, 1, 1, 1, 1],
["iq2", 1, 1, 1, 1, 1, 1],
["iq3", 1, 1, 1, 1, 1, 1]]
1 change: 1 addition & 0 deletions core/CMakeLists.txt
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Expand Up @@ -18,6 +18,7 @@ add_library(core
IssueQueue.cpp
ROB.cpp
LSU.cpp
VLSU.cpp
MMU.cpp
DCache.cpp
MavisUnit.cpp
Expand Down
5 changes: 5 additions & 0 deletions core/CPUFactories.hpp
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Expand Up @@ -12,6 +12,7 @@
#include "Dispatch.hpp"
#include "Execute.hpp"
#include "LSU.hpp"
#include "VLSU.hpp"
#include "MMU.hpp"
#include "SimpleTLB.hpp"
#include "BIU.hpp"
Expand Down Expand Up @@ -77,6 +78,10 @@ namespace olympia{
sparta::ResourceFactory<olympia::LSU,
olympia::LSU::LSUParameterSet> lsu_rf;

//! \brief Resource Factory to build a LSU Unit
sparta::ResourceFactory<olympia::VLSU,
olympia::VLSU::VLSUParameterSet> vlsu_rf;

//! \brief Resouce Factory to build a L2Cache Unit
sparta::ResourceFactory<olympia_mss::L2Cache,
olympia_mss::L2Cache::L2CacheParameterSet> l2cache_rf;
Expand Down
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