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change port naming in line with style guide
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@micprog
micprog committed Apr 10, 2023
1 parent d0f8e6f commit c94b1fb
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2 changes: 1 addition & 1 deletion doc/svg/axi_lite_mux.svg
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132 changes: 66 additions & 66 deletions src/axi_atop_filter.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -49,13 +49,13 @@ module axi_atop_filter #(
/// Asynchronous reset, active low
input logic rst_ni,
/// Subordinate port request
input axi_req_t sbr_req_i,
input axi_req_t sbr_port_req_i,
/// Subordinate port response
output axi_rsp_t sbr_rsp_o,
output axi_rsp_t sbr_port_rsp_o,
/// Manager port request
output axi_req_t mgr_req_o,
output axi_req_t mgr_port_req_o,
/// Manager port response
input axi_rsp_t mgr_rsp_i
input axi_rsp_t mgr_port_rsp_i
);

// Minimum counter width is 2 to detect underflows.
Expand Down Expand Up @@ -100,14 +100,14 @@ module axi_atop_filter #(
always_comb begin
// Defaults:
// Disable AW and W handshakes.
mgr_req_o.aw_valid = 1'b0;
sbr_rsp_o.aw_ready = 1'b0;
mgr_req_o.w_valid = 1'b0;
sbr_rsp_o.w_ready = 1'b0;
mgr_port_req_o.aw_valid = 1'b0;
sbr_port_rsp_o.aw_ready = 1'b0;
mgr_port_req_o.w_valid = 1'b0;
sbr_port_rsp_o.w_ready = 1'b0;
// Feed write responses through.
mgr_req_o.b_ready = sbr_req_i.b_ready;
sbr_rsp_o.b_valid = mgr_rsp_i.b_valid;
sbr_rsp_o.b = mgr_rsp_i.b;
mgr_port_req_o.b_ready = sbr_port_req_i.b_ready;
sbr_port_rsp_o.b_valid = mgr_port_rsp_i.b_valid;
sbr_port_rsp_o.b = mgr_port_rsp_i.b;
// Keep ID stored for B and R response.
id_d = id_q;
// Do not push R response commands.
Expand All @@ -119,26 +119,26 @@ module axi_atop_filter #(
W_FEEDTHROUGH: begin
// Feed AW channel through if the maximum number of outstanding bursts is not reached.
if (complete_w_without_aw_downstream || (w_cnt_q.cnt < MaxWriteTxns)) begin
mgr_req_o.aw_valid = sbr_req_i.aw_valid;
sbr_rsp_o.aw_ready = mgr_rsp_i.aw_ready;
mgr_port_req_o.aw_valid = sbr_port_req_i.aw_valid;
sbr_port_rsp_o.aw_ready = mgr_port_rsp_i.aw_ready;
end
// Feed W channel through if ..
if (aw_without_complete_w_downstream // .. downstream is missing W bursts ..
// .. or a new non-ATOP AW is being applied and there is not already a complete W burst
// downstream (to prevent underflows of w_cnt).
|| ((sbr_req_i.aw_valid && sbr_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE)
|| ((sbr_port_req_i.aw_valid && sbr_port_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE)
&& !complete_w_without_aw_downstream)
) begin
mgr_req_o.w_valid = sbr_req_i.w_valid;
sbr_rsp_o.w_ready = mgr_rsp_i.w_ready;
mgr_port_req_o.w_valid = sbr_port_req_i.w_valid;
sbr_port_rsp_o.w_ready = mgr_port_rsp_i.w_ready;
end
// Filter out AWs that are atomic operations.
if (sbr_req_i.aw_valid && sbr_req_i.aw.atop[5:4] != axi_pkg::ATOP_NONE) begin
mgr_req_o.aw_valid = 1'b0; // Do not let AW pass to manager port.
sbr_rsp_o.aw_ready = 1'b1; // Absorb AW on subordinate port.
id_d = sbr_req_i.aw.id; // Store ID for B response.
if (sbr_port_req_i.aw_valid && sbr_port_req_i.aw.atop[5:4] != axi_pkg::ATOP_NONE) begin
mgr_port_req_o.aw_valid = 1'b0; // Do not let AW pass to manager port.
sbr_port_rsp_o.aw_ready = 1'b1; // Absorb AW on subordinate port.
id_d = sbr_port_req_i.aw.id; // Store ID for B response.
// Some atomic operations require a response on the R channel.
if (sbr_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin
if (sbr_port_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin
// Push R response command. We do not have to wait for the ready of the register
// because we know it is ready: we are its only manager and will wait for the register to
// be emptied before going back to the `W_FEEDTHROUGH` state.
Expand All @@ -149,13 +149,13 @@ module axi_atop_filter #(
w_state_d = BLOCK_AW;
// If downstream is not missing W beats, absorb the W beats for this atomic AW.
end else begin
mgr_req_o.w_valid = 1'b0; // Do not let W beats pass to manager port.
sbr_rsp_o.w_ready = 1'b1; // Absorb W beats on subordinate port.
if (sbr_req_i.w_valid && sbr_req_i.w.last) begin
mgr_port_req_o.w_valid = 1'b0; // Do not let W beats pass to manager port.
sbr_port_rsp_o.w_ready = 1'b1; // Absorb W beats on subordinate port.
if (sbr_port_req_i.w_valid && sbr_port_req_i.w.last) begin
// If the W beat is valid and the last, proceed by injecting the B response.
// However, if there is a non-handshaked B on our response port, we must let that
// complete first.
if (sbr_rsp_o.b_valid && !sbr_req_i.b_ready) begin
if (sbr_port_rsp_o.b_valid && !sbr_port_req_i.b_ready) begin
w_state_d = HOLD_B;
end else begin
w_state_d = INJECT_B;
Expand All @@ -171,14 +171,14 @@ module axi_atop_filter #(
BLOCK_AW: begin
// Feed W channel through to let outstanding bursts complete.
if (aw_without_complete_w_downstream) begin
mgr_req_o.w_valid = sbr_req_i.w_valid;
sbr_rsp_o.w_ready = mgr_rsp_i.w_ready;
mgr_port_req_o.w_valid = sbr_port_req_i.w_valid;
sbr_port_rsp_o.w_ready = mgr_port_rsp_i.w_ready;
end else begin
// If there are no more outstanding W bursts, start absorbing the next W burst.
sbr_rsp_o.w_ready = 1'b1;
if (sbr_req_i.w_valid && sbr_req_i.w.last) begin
sbr_port_rsp_o.w_ready = 1'b1;
if (sbr_port_req_i.w_valid && sbr_port_req_i.w.last) begin
// If the W beat is valid and the last, proceed by injecting the B response.
if (sbr_rsp_o.b_valid && !sbr_req_i.b_ready) begin
if (sbr_port_rsp_o.b_valid && !sbr_port_req_i.b_ready) begin
w_state_d = HOLD_B;
end else begin
w_state_d = INJECT_B;
Expand All @@ -192,9 +192,9 @@ module axi_atop_filter #(

ABSORB_W: begin
// Absorb all W beats of the current burst.
sbr_rsp_o.w_ready = 1'b1;
if (sbr_req_i.w_valid && sbr_req_i.w.last) begin
if (sbr_rsp_o.b_valid && !sbr_req_i.b_ready) begin
sbr_port_rsp_o.w_ready = 1'b1;
if (sbr_port_req_i.w_valid && sbr_port_req_i.w.last) begin
if (sbr_port_rsp_o.b_valid && !sbr_port_req_i.b_ready) begin
w_state_d = HOLD_B;
end else begin
w_state_d = INJECT_B;
Expand All @@ -204,22 +204,22 @@ module axi_atop_filter #(

HOLD_B: begin
// Proceed with injection of B response upon handshake.
if (sbr_rsp_o.b_valid && sbr_req_i.b_ready) begin
if (sbr_port_rsp_o.b_valid && sbr_port_req_i.b_ready) begin
w_state_d = INJECT_B;
end
end

INJECT_B: begin
// Pause forwarding of B response.
mgr_req_o.b_ready = 1'b0;
mgr_port_req_o.b_ready = 1'b0;
// Inject error response instead. Since the B channel has an ID and the atomic burst we are
// replying to is guaranteed to be the only burst with this ID in flight, we do not have to
// observe any ordering and can immediately inject on the B channel.
sbr_rsp_o.b = '0;
sbr_rsp_o.b.id = id_q;
sbr_rsp_o.b.resp = axi_pkg::RESP_SLVERR;
sbr_rsp_o.b_valid = 1'b1;
if (sbr_req_i.b_ready) begin
sbr_port_rsp_o.b = '0;
sbr_port_rsp_o.b.id = id_q;
sbr_port_rsp_o.b.resp = axi_pkg::RESP_SLVERR;
sbr_port_rsp_o.b_valid = 1'b1;
if (sbr_port_req_i.b_ready) begin
// If not all beats of the R response have been injected, wait for them. Otherwise, return
// to `W_FEEDTHROUGH`.
if (r_resp_cmd_pop_valid && !r_resp_cmd_pop_ready) begin
Expand All @@ -246,18 +246,18 @@ module axi_atop_filter #(
// Feed-through of the AW and W vectors, make sure that downstream aw.atop is always zero
always_comb begin
// overwrite the atop signal
mgr_req_o.aw = sbr_req_i.aw;
mgr_req_o.aw.atop = '0;
mgr_port_req_o.aw = sbr_port_req_i.aw;
mgr_port_req_o.aw.atop = '0;
end
assign mgr_req_o.w = sbr_req_i.w;
assign mgr_port_req_o.w = sbr_port_req_i.w;

// Manage R channel.
always_comb begin
// Defaults:
// Feed read responses through.
sbr_rsp_o.r = mgr_rsp_i.r;
sbr_rsp_o.r_valid = mgr_rsp_i.r_valid;
mgr_req_o.r_ready = sbr_req_i.r_ready;
sbr_port_rsp_o.r = mgr_port_rsp_i.r;
sbr_port_rsp_o.r_valid = mgr_port_rsp_i.r_valid;
mgr_port_req_o.r_ready = sbr_port_req_i.r_ready;
// Do not pop R response command.
r_resp_cmd_pop_ready = 1'b0;
// Keep the current value of the beats counter.
Expand All @@ -267,7 +267,7 @@ module axi_atop_filter #(

unique case (r_state_q)
R_FEEDTHROUGH: begin
if (mgr_rsp_i.r_valid && !sbr_req_i.r_ready) begin
if (mgr_port_rsp_i.r_valid && !sbr_port_req_i.r_ready) begin
r_state_d = R_HOLD;
end else if (r_resp_cmd_pop_valid) begin
// Upon a command to inject an R response, immediately proceed with doing so because there
Expand All @@ -279,14 +279,14 @@ module axi_atop_filter #(
end

INJECT_R: begin
mgr_req_o.r_ready = 1'b0;
sbr_rsp_o.r = '0;
sbr_rsp_o.r.id = id_q;
sbr_rsp_o.r.resp = axi_pkg::RESP_SLVERR;
sbr_rsp_o.r.last = (r_beats_q == '0);
sbr_rsp_o.r_valid = 1'b1;
if (sbr_req_i.r_ready) begin
if (sbr_rsp_o.r.last) begin
mgr_port_req_o.r_ready = 1'b0;
sbr_port_rsp_o.r = '0;
sbr_port_rsp_o.r.id = id_q;
sbr_port_rsp_o.r.resp = axi_pkg::RESP_SLVERR;
sbr_port_rsp_o.r.last = (r_beats_q == '0);
sbr_port_rsp_o.r_valid = 1'b1;
if (sbr_port_req_i.r_ready) begin
if (sbr_port_rsp_o.r.last) begin
r_resp_cmd_pop_ready = 1'b1;
r_state_d = R_FEEDTHROUGH;
end else begin
Expand All @@ -296,7 +296,7 @@ module axi_atop_filter #(
end

R_HOLD: begin
if (mgr_rsp_i.r_valid && sbr_req_i.r_ready) begin
if (mgr_port_rsp_i.r_valid && sbr_port_req_i.r_ready) begin
r_state_d = R_FEEDTHROUGH;
end
end
Expand All @@ -305,17 +305,17 @@ module axi_atop_filter #(
endcase
end
// Feed all signals on AR through.
assign mgr_req_o.ar = sbr_req_i.ar;
assign mgr_req_o.ar_valid = sbr_req_i.ar_valid;
assign sbr_rsp_o.ar_ready = mgr_rsp_i.ar_ready;
assign mgr_port_req_o.ar = sbr_port_req_i.ar;
assign mgr_port_req_o.ar_valid = sbr_port_req_i.ar_valid;
assign sbr_port_rsp_o.ar_ready = mgr_port_rsp_i.ar_ready;

// Keep track of outstanding downstream write bursts and responses.
always_comb begin
w_cnt_d = w_cnt_q;
if (mgr_req_o.aw_valid && mgr_rsp_i.aw_ready) begin
if (mgr_port_req_o.aw_valid && mgr_port_rsp_i.aw_ready) begin
w_cnt_d.cnt += 1;
end
if (mgr_req_o.w_valid && mgr_rsp_i.w_ready && mgr_req_o.w.last) begin
if (mgr_port_req_o.w_valid && mgr_port_rsp_i.w_ready && mgr_port_req_o.w.last) begin
w_cnt_d.cnt -= 1;
end
if (w_cnt_q.underflow && (w_cnt_d.cnt == '0)) begin
Expand Down Expand Up @@ -355,7 +355,7 @@ module axi_atop_filter #(
.ready_i (r_resp_cmd_pop_ready),
.data_o (r_resp_cmd_pop)
);
assign r_resp_cmd_push.len = sbr_req_i.aw.len;
assign r_resp_cmd_push.len = sbr_port_req_i.aw.len;

// pragma translate_off
`ifndef VERILATOR
Expand Down Expand Up @@ -427,10 +427,10 @@ module axi_atop_filter_intf #(
) i_axi_atop_filter (
.clk_i,
.rst_ni,
.sbr_req_i ( sbr_req ),
.sbr_rsp_o ( sbr_rsp ),
.mgr_req_o ( mgr_req ),
.mgr_rsp_i ( mgr_rsp )
.sbr_port_req_i ( sbr_req ),
.sbr_port_rsp_o ( sbr_rsp ),
.mgr_port_req_o ( mgr_req ),
.mgr_port_rsp_i ( mgr_rsp )
);
// pragma translate_off
`ifndef VERILATOR
Expand Down
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