Change master/mst/slave/slv to manager/mgr/subordinate/sbr

.ci/Memora.yml

@@ -209,7 +209,7 @@ artifacts:
       - src/axi_pkg.sv
       - src/axi_intf.sv
       - src/axi_test.sv
-      - src/axi_err_slv.sv
+      - src/axi_err_sbr.sv
       - src/axi_lite_demux.sv
       - src/axi_lite_mux.sv
       - src/axi_lite_to_axi.sv
@@ -296,7 +296,7 @@ artifacts:
       - src/axi_intf.sv
       - src/axi_test.sv
       - src/axi_demux.sv
-      - src/axi_err_slv.sv
+      - src/axi_err_sbr.sv
       - src/axi_mux.sv
       - src/axi_xbar.sv
       - test/tb_axi_xbar.sv

Bender.yml

@@ -62,12 +62,12 @@ sources:
   - src/axi_rw_join.sv
   - src/axi_rw_split.sv
   - src/axi_serializer.sv
-  - src/axi_slave_compare.sv
+  - src/axi_subordinate_compare.sv
   - src/axi_throttle.sv
   - src/axi_to_mem.sv
   # Level 3
   - src/axi_cdc.sv
-  - src/axi_err_slv.sv
+  - src/axi_err_sbr.sv
   - src/axi_dw_converter.sv
   - src/axi_from_mem.sv
   - src/axi_id_serialize.sv
@@ -119,7 +119,7 @@ sources:
       - test/tb_axi_modify_address.sv
       - test/tb_axi_serializer.sv
       - test/tb_axi_sim_mem.sv
-      - test/tb_axi_slave_compare.sv
+      - test/tb_axi_subordinate_compare.sv
       - test/tb_axi_to_axi_lite.sv
       - test/tb_axi_to_mem_banked.sv
       - test/tb_axi_xbar.sv

axi.core

@@ -44,12 +44,12 @@ filesets:
       - src/axi_rw_join.sv
       - src/axi_rw_split.sv
       - src/axi_serializer.sv
-      - src/axi_slave_compare.sv
+      - src/axi_subordinate_compare.sv
       - src/axi_throttle.sv
       - src/axi_to_mem.sv
       # Level 3
       - src/axi_cdc.sv
-      - src/axi_err_slv.sv
+      - src/axi_err_sbr.sv
       - src/axi_dw_converter.sv
       - src/axi_from_mem.sv
       - src/axi_id_serialize.sv
@@ -95,7 +95,7 @@ filesets:
       - test/tb_axi_modify_address.sv
       - test/tb_axi_serializer.sv
       - test/tb_axi_sim_mem.sv
-      - test/tb_axi_slave_compare.sv
+      - test/tb_axi_subordinate_compare.sv
       - test/tb_axi_to_axi_lite.sv
       - test/tb_axi_to_mem_banked.sv
       - test/tb_axi_xbar.sv
@@ -116,34 +116,34 @@ generators:
       module where the interconnect wrapper is intended to be used.
 
       Parameters:
-        masters: A dictionary where each key names a master interface connecting
+        managers: A dictionary where each key names a manager interface connecting
                  to the interconnect and the associated value contains
                  configuration for that interface.
 
-                   id_width (int): Width of the id signals for the master
+                   id_width (int): Width of the id signals for the manager
 
-        slaves: A dictionary  where each key names a slave interface connecting
+        subordinates: A dictionary  where each key names a subordinate interface connecting
                  to the interconnect and the associated value contains
                  configuration for that interface. The following configuration
                  keys are defined
 
-                   offset (int): Base address for the slave
-                   size   (int): Size of the allocated memory map for the slave
+                   offset (int): Base address for the subordinate
+                   size   (int): Size of the allocated memory map for the subordinate
 
       Example usage:
         The following config will generate an interconnect wrapper to which two
-        AXI4 master interfaces (dma and ibus) with different id widths are
-        connected, and connects downstream to three AXI4 slaves (rom, gpio, ram)
+        AXI4 manager interfaces (dma and ibus) with different id widths are
+        connected, and connects downstream to three AXI4 subordinates (rom, gpio, ram)
 
         soc_intercon:
           generator: axi_intercon_gen
           parameters:
-            masters:
+            managers:
               dma:
                 id_width : 1
               ibus:
                 id_width : 2
-            slaves:
+            subordinates:
               ram:
                 offset : 0
                 size: 0x10000000

doc/axi_demux.md

@@ -5,15 +5,15 @@
 
 ## Design Overview
 
-The demultiplexer has one *slave port* and a configurable number of *master ports*.  A block diagram is shown below:
+The demultiplexer has one *subordinate port* and a configurable number of *manager ports*.  A block diagram is shown below:
 
 ![Block diagram of the AXI demultiplexer](axi_demux.png "Block diagram of the AXI demultiplexer")
 
-The AW and AR channels each have a *select* input, to determine the master port to which they are sent.  The select can, for example, be driven by an (external) address decoder to map address ranges to different AXI slaves.
+The AW and AR channels each have a *select* input, to determine the manager port to which they are sent.  The select can, for example, be driven by an (external) address decoder to map address ranges to different AXI subordinates.
 
 Beats on the W channel are routed by demultiplexer according to the selection for the corresponding AW beat.  This relies on the AXI property that W bursts must be sent in the same order as AW beats and beats from different W bursts may not be interleaved.
 
-Beats on the B and R channel are multiplexed from the master ports to the slave port with a round-robin arbitration tree.
+Beats on the B and R channel are multiplexed from the manager ports to the subordinate port with a round-robin arbitration tree.
 
 
 ## Configuration
@@ -23,11 +23,11 @@ This demultiplexer is configured through the parameters listed in the following
 | Name                 | Type               | Definition |
 |:---------------------|:-------------------|:-----------|
 | `IdWidth`            | `int unsigned`     | The AXI ID width (of all ports). |
-| `NumMstPorts`        | `int unsigned`     | The number of AXI master ports of the demultiplexer (in other words, how many AXI slave modules can be attached). |
-| `MaxTrans`           | `int unsigned`     | The slave port can have at most this many transactions [in flight](../doc#in-flight). |
+| `NumMgrPorts`        | `int unsigned`     | The number of AXI manager ports of the demultiplexer (in other words, how many AXI subordinate modules can be attached). |
+| `MaxTrans`           | `int unsigned`     | The subordinate port can have at most this many transactions [in flight](../doc#in-flight). |
 | `LookBits`           | `int unsigned`     | The number of ID bits (starting at the least significant) the demultiplexer uses to determine the uniqueness of an AXI ID (see section *Ordering and Stalls* below).  This value has to be less or equal than `IdWidth`. |
 | `UniqueIds`          | `bit`              | If you can guarantee that the ID of each transaction is always unique among all in-flight transactions in the same direction, setting this parameter to `1'b1` simplifies the demultiplexer (see section *Ordering and Stalls* below).  Defaults to `1'b0`. |
-| `FallThrough`        | `bit`              | Routing decisions on the AW channel fall through to the W channel.  Enabling this allows the demultiplexer to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from `slv_aw_select_i`. |
+| `FallThrough`        | `bit`              | Routing decisions on the AW channel fall through to the W channel.  Enabling this allows the demultiplexer to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from `sbr_aw_select_i`. |
 | `SpillXX`            | `bit`              | Inserts one spill register on the respective channel (AW, W, B, AR, and R) before the demultiplexer. |
 
 The other parameters are types to define the ports of the demultiplexer.  The `_*chan_t` types must be bound in accordance to the configuration using the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`.
@@ -46,21 +46,21 @@ If all `SpillXX` and `FallThrough` are disabled, all paths through this multiple
 | `clk_i`                           | Clock to which all other signals (except `rst_ni`) are synchronous. |
 | `rst_ni`                          | Reset, asynchronous, active-low. |
 | `test_i`                          | Test mode enable (active-high). |
-| `slv_*` (except `slv_*_select_i`) | Single slave port of the demultiplexer. |
-| `slv_{aw,ar}_select_i`            | Index of the master port to which a write or read, respectively, is demultiplexed.  This signal must be stable while a handshake on the AW respectively AR channel is [pending](../doc#pending). |
-| `mst_*`                           | Array of master ports of the demultiplexer.  The array index of each port is the index of the master port. |
+| `sbr_*` (except `sbr_*_select_i`) | Single subordinate port of the demultiplexer. |
+| `sbr_{aw,ar}_select_i`            | Index of the manager port to which a write or read, respectively, is demultiplexed.  This signal must be stable while a handshake on the AW respectively AR channel is [pending](../doc#pending). |
+| `mgr_*`                           | Array of manager ports of the demultiplexer.  The array index of each port is the index of the manager port. |
 
 
 ## Ordering and Stalls
 
-When the demultiplexer receives two transactions with the same ID and direction (i.e., both read or both write) but targeting two different master ports, it will not accept the second transaction until the first has completed.  During this time, the demultiplexer stalls the AR or AW channel, respectively.  To determine whether two transactions have the same ID, the `LookBits` least-significant bits are compared.  That parameter can be set to the full `IdWidth` to avoid false ID conflicts, or it can be set to a lower value to reduce area and delay at the cost of more false conflicts.
+When the demultiplexer receives two transactions with the same ID and direction (i.e., both read or both write) but targeting two different manager ports, it will not accept the second transaction until the first has completed.  During this time, the demultiplexer stalls the AR or AW channel, respectively.  To determine whether two transactions have the same ID, the `LookBits` least-significant bits are compared.  That parameter can be set to the full `IdWidth` to avoid false ID conflicts, or it can be set to a lower value to reduce area and delay at the cost of more false conflicts.
 
 The reason for this behavior are AXI ordering constraints, see the [documentation of the crossbar](axi_xbar.md#ordering-and-stalls) for details.
 
 There are use cases that do not require the demultiplexer to keep track of and enforce this ordering, and the `UniqueIds` parameter can be set to specialize the demultiplexer for these cases:
 `UniqueIds` may be set to `1'b1` if and only if
 - each transaction has an ID that is unique among all in-flight transactions in the same direction;
-- or for any ID, all transactions with that ID target the same master port as all other in-flight transactions with the same ID and direction;
+- or for any ID, all transactions with that ID target the same manager port as all other in-flight transactions with the same ID and direction;
 - or both.
 
 Setting the `UniqueIds` parameter to `1'b1` when those conditions are not always met leads to undefined behavior.
@@ -69,11 +69,11 @@ Setting the `UniqueIds` parameter to `1'b1` reduces the area complexity of the d
 
 ### Implementation
 
-`2 * 2^LookBits` counters track the number of [in-flight](../doc#in-flight) transactions.  That is, for each ID in the (potentially) reduced set of IDs of `LookBits` bits, there is one counter for write transactions and one for read transactions.  Each counter can count up to (and including) `MaxTrans`, and there is a register that holds the index of the master port to which a counter is assigned.
+`2 * 2^LookBits` counters track the number of [in-flight](../doc#in-flight) transactions.  That is, for each ID in the (potentially) reduced set of IDs of `LookBits` bits, there is one counter for write transactions and one for read transactions.  Each counter can count up to (and including) `MaxTrans`, and there is a register that holds the index of the manager port to which a counter is assigned.
 
-When the demultiplexer gets an AW or an AR, it indexes the counters with the AXI ID.  If the indexed counter has a value greater than zero and its master port index register is not equal to the index to which the AW or AR is to be sent, a transaction with the same direction and ID is already in flight to another master port.  The demultiplexer then stalls the AW or AR.  In all other cases, the demultiplexer forwards the AW or AR, increments the value of the indexed counter, and sets the master port index of the counter.  A counter is decremented upon a handshake a B respectively last R beat at a slave port.
+When the demultiplexer gets an AW or an AR, it indexes the counters with the AXI ID.  If the indexed counter has a value greater than zero and its manager port index register is not equal to the index to which the AW or AR is to be sent, a transaction with the same direction and ID is already in flight to another manager port.  The demultiplexer then stalls the AW or AR.  In all other cases, the demultiplexer forwards the AW or AR, increments the value of the indexed counter, and sets the manager port index of the counter.  A counter is decremented upon a handshake a B respectively last R beat at a subordinate port.
 
-W beats are routed to the master port defined by the value of `slv_aw_select_i` for the corresponding AW.  As the order of the W bursts is given by the order of the AWs, the select signals are stored in a FIFO queue.  This FIFO is pushed upon a handshake on the AW slave channel and popped upon a handshake of the last W beat of a burst on a W master channel.
+W beats are routed to the manager port defined by the value of `sbr_aw_select_i` for the corresponding AW.  As the order of the W bursts is given by the order of the AWs, the select signals are stored in a FIFO queue.  This FIFO is pushed upon a handshake on the AW subordinate channel and popped upon a handshake of the last W beat of a burst on a W manager channel.
 
 
 ## Atomic Transactions