Commit
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
plat-stm32mp2: add pm support on stm32mp25
Add support of low power mode on stm32mp25 and perform the needed OP-TEE bookkeeping before PSCI executes a power management sequence, with the 3 hooks called by TF-A SPD : - thread_system_off_handler() - thread_cpu_resume_handler() - thread_cpu_suspend_handler() On PSCI system off request, the STPMIC25 driver need to configure the regulators properly to handle the always on domain with the board configuration (PMIC switch OFF, with coin cell, or standby DDR off). For PSCI suspend requests, the STM32MP25 family supports 5 power levels in the PSCI topology to handle the regulators configuration done in STPMIC2 for low poser modes, in particular to differentiate the tension for LP and the LPLV modes: power level (System mode for a0= Max power level powered down) -------------------------------------------------------------------------- 0: CPU1 core#0 or core#1 (Stop1 or LP-Stop1) 1: D1 domain (LPLV-Stop1) 2: LPLV D1 (Stop2 or LP-Stop2) 3: D2 (LPLV-Stop2) 4: LPLV D2 (Standby) 5: MAX (PowerOff: Standby or VBat) The hook calls pm_change_state with generic HINT for inform STM32MP25 drivers to operation to performed on suspend/resume: - PM_HINT_CLOCK_STATE the IP clock will be deactivated, the pending operation should stop, cleanup operation can be done on HW to prepare the clock freeze (optional support by driver) - PM_HINT_CONTEXT_STATE called for System level standby when the IP configuration is lost. The state of each device must be saved in RAM which is preserved (DDR in self-refresh, mandatory) Signed-off-by: Patrick Delaunay <[email protected]>
- Loading branch information