Adding a New Sample: platform_designer_standard

[haoyanwa]

Adding a New Sample: platform_designer_standard

Description

An Intel® FPGA tutorial demonstrating how to export a reusable IP component to Intel® Quartus® Prime Standard and Platform Designer targeting Cyclone® V SoC FPGAs.

Features include:

• Updated script for building the Quartus system for Quartus® Prime Standard.
• Updated script for board testing, including System Console initialization and establishing a connection to the host.
• Revised tutorial steps, tailored for Quartus Prime Standard Edition, with updated screenshots.

This code sample is tested on a DE1-SoC board using Quartus Prime Standard 23.1std.

Checklist

Administrative

• Review sample design with the appropriate Domain Expert: @whitepau
• If you have any new dependencies/binaries, inform the oneAPI Code Samples Project Manager

Code Development

• Implement coding guidelines and ensure code quality. see wiki for details
• Adhere to readme template
• Enforce format via clang-format config file
• Adhere to sample.json specification. https://github.com/oneapi-src/oneAPI-samples/wiki/sample-json-specification
• Ensure/create CI test configurations for sample (ciTests field) https://github.com/oneapi-src/oneAPI-samples/wiki/sample-json-ci-test-object
• Run jsonlint on sample.json to verify json syntax. www.jsonlint.com
• FPGA Regtest (Linux) https://spetc.intel.com/testsummary?testRunIds=10661900
• FPGA Regtest (Windows) https://spetc.intel.com/testsummary?testRunIds=10661973

Security and Legal

• OSPDT Approval (see Project Manager for assistance)
• Compile using the following compiler flags and fix any warnings, the falgs are: "/Wall -Wformat-security -Werror=format-security"
• Bandit Scans (Python only)
• Virus scan

Review

• Review DPC++ code with Paul Peterseon. (GitHub User: pmpeter1)
• Review readme with Tom Lenth(@tomlenth) and/or Project Manager
• Tested using Dev Cloud when applicable

[tomlenth]

Very thorough, much like all the PSG sample readmes. thank you.

[yuguen-intel]

If this is a Tier 1, then it is not categorized correctly in the main README, if this is a Tier 3 sample, this section is incorrect
I can see that there is the same issue in the platform_designer sample, so both should be addressed - please synchronize with @whitepau to decide where these samples should live

[yuguen-intel]

This should align with the Tier of the sample