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RTL Digital Hardware Design, EDA Simulation and Schematic Drawing, Runtime Modeling in Common Lisp

AGPL-3.0 license

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Name		Name	Last commit message	Last commit date
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LICENSE		LICENSE
README.md		README.md
circuit_out.svg		circuit_out.svg
digital.lisp		digital.lisp
screenshot.png		screenshot.png

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CL-Digital

Common Lisp Digital Hardware Synthesis and Simulation

RTL Digital Hardware Design
EDA Simulation and Schematic Drawing
Digital Runtime Modeling in Common Lisp
Circuit Drawing

Requirements

netlistsvg for vector schematic drawing http://github.com/nturley/netlistsvg
JSOWN for netlist exports http://github.com/madnificent/jsown

Use

(load "digital.lisp")
see TEST-SIMULATE in digital.lisp for sample

Todo

re-implement in Indigo http://github.com/olewhalehunter/indigo.lisp
parts registration and layout planning, component libraries

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RTL Digital Hardware Design, EDA Simulation and Schematic Drawing, Runtime Modeling in Common Lisp

AGPL-3.0 license

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Common Lisp 100.0%