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Bump addins/riscv-arch-test from 7152865 to 02aa1d4
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dependabot[bot] authored Jul 23, 2024
1 parent bbfe8d9 commit f5417ba
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion addins/riscv-arch-test
Submodule riscv-arch-test updated 49 files
+10 −1 CHANGELOG.md
+16 −0 coverage/rvi_priv.cgf
+194 −143 riscv-test-suite/env/arch_test.h
+419 −0 riscv-test-suite/env/test_macros_vector.h
+92 −0 riscv-test-suite/rv32e_m/C/src/misalign1-cjalr-01.S
+92 −0 riscv-test-suite/rv32e_m/C/src/misalign1-cjr-01.S
+92 −0 riscv-test-suite/rv32i_m/C/src/misalign1-cjalr-01.S
+92 −0 riscv-test-suite/rv32i_m/C/src/misalign1-cjr-01.S
+2 −2 riscv-test-suite/rv32i_m/CMO/src/cbo.zero-01.S
+158 −0 riscv-test-suite/rv32i_m/Zvk/src/vaesdf.vs-01.S
+158 −0 riscv-test-suite/rv32i_m/Zvk/src/vaesdf.vv-01.S
+158 −0 riscv-test-suite/rv32i_m/Zvk/src/vaesdm.vs-01.S
+158 −0 riscv-test-suite/rv32i_m/Zvk/src/vaesdm.vv-01.S
+158 −0 riscv-test-suite/rv32i_m/Zvk/src/vaesef.vs-01.S
+158 −0 riscv-test-suite/rv32i_m/Zvk/src/vaesef.vv-01.S
+158 −0 riscv-test-suite/rv32i_m/Zvk/src/vaesem.vs-01.S
+158 −0 riscv-test-suite/rv32i_m/Zvk/src/vaesem.vv-01.S
+158 −0 riscv-test-suite/rv32i_m/Zvk/src/vaeskf1.vi-01.S
+159 −0 riscv-test-suite/rv32i_m/Zvk/src/vaeskf2.vi-01.S
+158 −0 riscv-test-suite/rv32i_m/Zvk/src/vaesz.vs-01.S
+207 −0 riscv-test-suite/rv32i_m/Zvk/src/vandn.vv-01.S
+207 −0 riscv-test-suite/rv32i_m/Zvk/src/vandn.vx-01.S
+206 −0 riscv-test-suite/rv32i_m/Zvk/src/vbrev8.v-01.S
+140 −0 riscv-test-suite/rv32i_m/Zvk/src/vclmul.vv-01.S
+140 −0 riscv-test-suite/rv32i_m/Zvk/src/vclmul.vx-01.S
+140 −0 riscv-test-suite/rv32i_m/Zvk/src/vclmulh.vv-01.S
+140 −0 riscv-test-suite/rv32i_m/Zvk/src/vclmulh.vx-01.S
+159 −0 riscv-test-suite/rv32i_m/Zvk/src/vghsh.vv-01.S
+158 −0 riscv-test-suite/rv32i_m/Zvk/src/vgmul.vv-01.S
+206 −0 riscv-test-suite/rv32i_m/Zvk/src/vrev8.v-01.S
+207 −0 riscv-test-suite/rv32i_m/Zvk/src/vrol.vv-01.S
+207 −0 riscv-test-suite/rv32i_m/Zvk/src/vrol.vx-01.S
+207 −0 riscv-test-suite/rv32i_m/Zvk/src/vror.vi-01.S
+207 −0 riscv-test-suite/rv32i_m/Zvk/src/vror.vv-01.S
+207 −0 riscv-test-suite/rv32i_m/Zvk/src/vror.vx-01.S
+159 −0 riscv-test-suite/rv32i_m/Zvk/src/vsha2ch-e32.vv-01.S
+159 −0 riscv-test-suite/rv32i_m/Zvk/src/vsha2ch-e64.vv-01.S
+159 −0 riscv-test-suite/rv32i_m/Zvk/src/vsha2cl-e32.vv-01.S
+159 −0 riscv-test-suite/rv32i_m/Zvk/src/vsha2cl-e64.vv-01.S
+159 −0 riscv-test-suite/rv32i_m/Zvk/src/vsha2ms-e32.vv-01.S
+159 −0 riscv-test-suite/rv32i_m/Zvk/src/vsha2ms-e64.vv-01.S
+159 −0 riscv-test-suite/rv32i_m/Zvk/src/vsm3c.vi-01.S
+138 −0 riscv-test-suite/rv32i_m/Zvk/src/vsm3me.vv-01.S
+158 −0 riscv-test-suite/rv32i_m/Zvk/src/vsm4k.vi-01.S
+158 −0 riscv-test-suite/rv32i_m/Zvk/src/vsm4r.vs-01.S
+158 −0 riscv-test-suite/rv32i_m/Zvk/src/vsm4r.vv-01.S
+92 −0 riscv-test-suite/rv64i_m/C/src/misalign1-cjalr-01.S
+91 −0 riscv-test-suite/rv64i_m/C/src/misalign1-cjr-01.S
+2 −2 riscv-test-suite/rv64i_m/CMO/src/cbo.zero-01.S

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