bench/sim: Update.

enjoy-digital · Sep 2, 2024 · aab5d63 · aab5d63
1 parent b243b3b
commit aab5d63
Showing 1 changed file with 4 additions and 4 deletions.
diff --git a/bench/sim.py b/bench/sim.py
@@ -34,11 +34,11 @@ def __init__(self, host_ip="192.168.1.100", host_udp_port=2000):
         # Sampler --------------------------------------------------------------------------------
         data = Signal(8)
         self.sync += data.eq(data + 1)
-        self.submodules.sampler = Sampler(data)
+        self.sampler = Sampler(data)
 
         # DRAMFIFO ---------------------------------------------------------------------------------
         from litedram.frontend.fifo import LiteDRAMFIFO
-        self.submodules.fifo = LiteDRAMFIFO(
+        self.fifo = LiteDRAMFIFO(
             data_width = 8,
             base       = 0x00000000,
             depth      = 0x01000000, # 16MB
@@ -49,10 +49,10 @@ def __init__(self, host_ip="192.168.1.100", host_udp_port=2000):
         # UDPStreamer ------------------------------------------------------------------------------
         from liteeth.common import convert_ip
         from liteeth.frontend.stream import LiteEthStream2UDPTX
-        udp_port       = self.ethcore.udp.crossbar.get_port(host_udp_port, dw=8)
+        udp_port       = self.ethcore_etherbone.udp.crossbar.get_port(host_udp_port, dw=8)
         udp_streamer   = LiteEthStream2UDPTX(
             ip_address = convert_ip(host_ip),
-            udp_port   = host_udp_port,
+            udp_port   = host_udp_port,trac
             fifo_depth = 1024
         )
         udp_streamer   = ClockDomainsRenamer("eth_tx")(udp_streamer)