phy/SDPHYIO: Fix data_i_ce (following 809ade3).

Since output clk is inverted, we also need to take this into account in SDPHYIO.

litesdcard/phy.py

@@ -509,7 +509,7 @@ def __init__(self, clocker, sdpads, round_trip_latency=2):
         # Generate a data_i_ce pulse round_trip_latency cycles after clocker.clk goes high so that
         # the data input effectively get sampled on the first sys_clk after the SDCard clk goes high.
         clocker_clk_delay = Signal(round_trip_latency)
-        self.sync += clocker_clk_delay.eq(Cat(clocker.clk, clocker_clk_delay))
+        self.sync += clocker_clk_delay.eq(Cat(~clocker.clk, clocker_clk_delay))
         self.sync += sdpads.data_i_ce.eq(clocker_clk_delay[-1] & ~clocker_clk_delay[-2])