Merge dev-goog -> dev-integrate 2023-06-28 #141
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Signed-off-by: Maciej Kurc <[email protected]>
Merge dev-integrate to main
Merge branch 'main' into dev-goog
* Adding spi_host/uart registers. These were clobbered in a merge somehwere * Update smoke test interrupts to match other tests * Remove qspi_d_io inout and replace with dedicated input/output ports * Adding QSPI / UART to L0_regression * Fix L0 regression typo * Adding ports to caliptra_top/tb/testbench/hdl_top.sv
…core (#72) * Added third-party code for JTAG DPI and TCP server necessary for communication with OpenOCD Signed-off-by: Maciej Kurc <[email protected]> * Integrated the JTAG DPI interface with the testbench Signed-off-by: Maciej Kurc <[email protected]> * Added a dummy infinite_loop test to exercise interactive JTAG connections Signed-off-by: Maciej Kurc <[email protected]> * Added OpenOCD interface and target scripts Signed-off-by: Maciej Kurc <[email protected]> * Increased TCP buffer size Signed-off-by: Maciej Kurc <[email protected]> * Added debugging capability to JTAG DPI via optional ASCII art waveform display Signed-off-by: Maciej Kurc <[email protected]> * Enable debugging in Caliptra testbench Signed-off-by: Maciej Kurc <[email protected]> * Updated the infinite loop program, tweaked OpenOCD config. Signed-off-by: Maciej Kurc <[email protected]> * Interactive debugging test in CI Signed-off-by: Maciej Kurc <[email protected]> * Updated OpenOCD config and test script Signed-off-by: Maciej Kurc <[email protected]> * Updated Interactive test CI flow Signed-off-by: Maciej Kurc <[email protected]> * Added a test that dumps core registers and compares them with a golden reference Signed-off-by: Maciej Kurc <[email protected]> * Set OpenOCD memory access mode to abstract Signed-off-by: Tomasz Michalak <[email protected]> * jtagdpi: Fix typo in README Signed-off-by: Tomasz Michalak <[email protected]> * Added a delay to the GDB script to give the simulation time to react Signed-off-by: Maciej Kurc <[email protected]> * Added FST waveform dump capability to Verilated simulation Signed-off-by: Maciej Kurc <[email protected]> * Set RISC-V abstract access in OpenOCD target config as default, limited number of parallel jobs when building verilated simulation Signed-off-by: Maciej Kurc <[email protected]> * Added tests for memory and peripheral access via JTAG (to the CI as well) Signed-off-by: Maciej Kurc <[email protected]> * Tweaked JTAG simulation CI script Signed-off-by: Maciej Kurc <[email protected]> * Add possibility to control Caliptra debug lock at the makefile invocation level Signed-off-by: Maciej Kurc <[email protected]> * Unlocked debugging in interactive simulation CI Signed-off-by: Maciej Kurc <[email protected]> * Switched to OpenOCD fork in CI Signed-off-by: Maciej Kurc <[email protected]> * Adjusted the infinite_loop test to fit in the build system for the tests. Signed-off-by: Maciej Kurc <[email protected]> * Added a makefile option to enforce reset on CPU Signed-off-by: Maciej Kurc <[email protected]> * Added OpenOCD config files for the case when the CPU is held in reset Signed-off-by: Maciej Kurc <[email protected]> * Separated bash utility functions for interactive JTAG debugging tests Signed-off-by: Maciej Kurc <[email protected]> * Added OpenOCD without GDB test to the CI Signed-off-by: Maciej Kurc <[email protected]> * Removed leftover comments. Signed-off-by: Maciej Kurc <[email protected]> --------- Signed-off-by: Maciej Kurc <[email protected]> Signed-off-by: Tomasz Michalak <[email protected]> Co-authored-by: Tomasz Michalak <[email protected]>
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