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Merge pull request #215 from chipsalliance/dev-msft
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Dev-msft -> dev-integrate
Adds:
Merged PR 122518: Enable NMI scenario in WDT test 
Merged PR 123605: TB related fixes to address soc_Ifc_tb directed nig… 
Merged PR 123991: EL2 Mem Interface modports, new double-bit error in… 
Merge pull request #214 from chipsalliance/dev-msft-20230913
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@calebofearth
calebofearth committed Sep 13, 2023
2 parents 13b1506 + 8ec2ed9 commit 1db4ff3
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Showing 42 changed files with 1,284 additions and 169 deletions.
4 changes: 2 additions & 2 deletions src/integration/asserts/caliptra_top_sva.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -284,14 +284,14 @@ module caliptra_top_sva
UDS_fuse_wr_check: assert property (
@(posedge `SVA_RDC_CLK)
disable iff(`CPTRA_TOP_PATH.cptra_in_debug_scan_mode || clear_obf_secrets_int || cptra_in_debug_scan_mode_int)
(`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value) |-> `CPTRA_TOP_PATH.obf_uds_seed_dbg == $past(`CPTRA_TOP_PATH.obf_uds_seed_dbg)
(`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value) |-> `CPTRA_TOP_PATH.obf_uds_seed == $past(`CPTRA_TOP_PATH.obf_uds_seed)
)
else $display("SVA ERROR: Unexpected write to obf uds seed!");

FE_fuse_wr_check: assert property (
@(posedge `SVA_RDC_CLK)
disable iff(`CPTRA_TOP_PATH.cptra_in_debug_scan_mode || clear_obf_secrets_int || cptra_in_debug_scan_mode_int)
(`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value) |-> `CPTRA_TOP_PATH.obf_field_entropy_dbg == $past(`CPTRA_TOP_PATH.obf_field_entropy_dbg)
(`SOC_IFC_TOP_PATH.soc_ifc_reg_hwif_out.CPTRA_FUSE_WR_DONE.done.value) |-> `CPTRA_TOP_PATH.obf_field_entropy == $past(`CPTRA_TOP_PATH.obf_field_entropy)
)
else $display("SVA ERROR: Unexpected write to obf field entropy!");

Expand Down
2 changes: 1 addition & 1 deletion src/integration/rtl/caliptra_top.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -71,7 +71,7 @@ module caliptra_top
//TODO update with I3C interface signals

// Caliptra Memory Export Interface
el2_mem_if el2_mem_export,
el2_mem_if.veer_sram_src el2_mem_export,

//SRAM interface for mbox
output logic mbox_sram_cs,
Expand Down
2 changes: 2 additions & 0 deletions src/integration/stimulus/testsuites/caliptra_top_nightly_random_regression.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -16,3 +16,5 @@ contents:
path: "{template_basename}__{seed}.yml"
templates:
$CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_rand_test : { weight 100 }
$CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_test : { weight 100 }
$CALIPTRA_ROOT/src/integration/uvmf_caliptra_top/uvmf_template_output/project_benches/caliptra_top/tb/tests/src/caliptra_top_wdt_independent_test : { weight 100 }
4 changes: 2 additions & 2 deletions src/integration/tb/caliptra_top_tb.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1092,7 +1092,7 @@ caliptra_top caliptra_top_dut (
.uart_rx(uart_loopback),
`endif

.el2_mem_export(el2_mem_export),
.el2_mem_export(el2_mem_export.veer_sram_src),

.ready_for_fuses(ready_for_fuses),
.ready_for_fw_push(ready_for_fw_push),
Expand Down Expand Up @@ -1193,7 +1193,7 @@ caliptra_top_tb_services #(
.cptra_rst_b(cptra_rst_b),

// Caliptra Memory Export Interface
.el2_mem_export (el2_mem_export),
.el2_mem_export (el2_mem_export.veer_sram_sink),

//SRAM interface for mbox
.mbox_sram_cs (mbox_sram_cs ),
Expand Down
2 changes: 1 addition & 1 deletion src/integration/tb/caliptra_top_tb_services.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ module caliptra_top_tb_services
input wire logic cptra_rst_b,

// Caliptra Memory Export Interface
el2_mem_if.top el2_mem_export,
el2_mem_if.veer_sram_sink el2_mem_export,

//SRAM interface for mbox
input wire logic mbox_sram_cs,
Expand Down
2 changes: 1 addition & 1 deletion src/integration/tb/caliptra_veer_sram_export.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ module caliptra_veer_sram_export import caliptra_top_tb_pkg::*; #(
// [2] - Single bit, DCCM Error Injection
// [3] - Double bit, DCCM Error Injection
input veer_sram_error_injection_mode_t sram_error_injection_mode,
el2_mem_if.top el2_mem_export
el2_mem_if.veer_sram_sink el2_mem_export
);

//////////////////////////////////////////////////////
Expand Down
16 changes: 8 additions & 8 deletions src/integration/test_suites/caliptra_rt/caliptra_isr.h
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Original file line number Diff line number Diff line change
Expand Up @@ -181,14 +181,14 @@ inline void service_soc_ifc_error_intr() {
*reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK;
}
if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) {
*reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
}
if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK) {
*reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
}
// if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK) {
// *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
// cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;
// }
// if (sts & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK) {
// *reg = SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
// cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;
// }
if (sts == 0) {
VPRINTF(ERROR,"bad soc_ifc_error_intr sts:%x\n", sts);
SEND_STDOUT_CTRL(0x1);
Expand Down
87 changes: 73 additions & 14 deletions src/integration/test_suites/caliptra_rt/caliptra_rt.c
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Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,15 @@ volatile caliptra_intr_received_s cptra_intr_rcv = {
flag &= mask; \
csr_set_bits_mstatus(MSTATUS_MIE_BIT_MASK);

#ifndef MY_RANDOM_SEED
#define MY_RANDOM_SEED 17
#endif // MY_RANDOM_SEED


enum gen_in_value {
WDT_CASCADE = 0x0000abab,
WDT_INDEPENDENT = 0x0000efef
};

/* --------------- Function Definitions --------------- */
void nmi_handler() {
Expand Down Expand Up @@ -123,7 +132,7 @@ void caliptra_rt() {
int i;
int wdt_rand_t1_val;
int wdt_rand_t2_val;
int mode;
int mode = 0;

VPRINTF(MEDIUM, "----------------------------------\n");
VPRINTF(LOW, "- Caliptra Validation RT!!\n" );
Expand All @@ -132,25 +141,52 @@ void caliptra_rt() {
//set NMI vector
lsu_write_32((uintptr_t) (CLP_SOC_IFC_REG_INTERNAL_NMI_VECTOR), (uint32_t) (nmi_handler));

// Initialize rand num generator
VPRINTF(LOW,"\nUsing random seed = %d\n\n", MY_RANDOM_SEED);
srand((uint32_t) MY_RANDOM_SEED);

// Runtime flow -- set ready for RT
soc_ifc_set_flow_status_field(SOC_IFC_REG_CPTRA_FLOW_STATUS_READY_FOR_RUNTIME_MASK);

#ifdef WDT_TEST
VPRINTF(LOW, "Enabling WDT intr\n");
lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER1_TIMEOUT_EN_MASK | SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTR_EN_R_ERROR_WDT_TIMER2_TIMEOUT_EN_MASK);
lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R, SOC_IFC_REG_INTR_BLOCK_RF_GLOBAL_INTR_EN_R_ERROR_EN_MASK);

//Generate constrained random WDT timer periods
wdt_rand_t1_val = rand() % 0xfff;
wdt_rand_t2_val = rand() % 0xfff;
mode = rand() % 2; //0 - independent mode, 1 - cascade mode
if (mode){
VPRINTF(LOW, "Restarting WDT in cascade mode (only t1 timeout)\n");
//TODO also add t2 timeout (NMI event)

while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_GEN_IN_TOGGLE_STS_MASK));
if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) == WDT_CASCADE) { //rand() % 2; //0 - independent mode, 1 - cascade mode
VPRINTF(LOW, "Restarting WDT in cascade mode\n");
//Enable timer1 to start cascade mode
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN, SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK);
//Set timer1 period to a small random value, so core can see timer1 timing out
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, wdt_rand_t1_val);
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0x00000000);
//Restart timer1
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK);

while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK));
//Clear timer1 intr
lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK);

//Program timer1 and 2 periods to <= 0x100 to test NMI generation
wdt_rand_t1_val = rand() % 0x100;
wdt_rand_t2_val = rand() % 0x100;
//WDT cascade mode with t2 timeout
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_EN, !SOC_IFC_REG_CPTRA_WDT_TIMER2_EN_TIMER2_EN_MASK);
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, wdt_rand_t1_val);
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0x00000000);
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0, wdt_rand_t2_val);
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1, 0x00000000);
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER1_CTRL_TIMER1_RESTART_MASK);
// lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK);

//Don't service interrupts so it can timeout and cause NMI
}
else {
else if (lsu_read_32(CLP_SOC_IFC_REG_CPTRA_GENERIC_INPUT_WIRES_0) == WDT_INDEPENDENT){
VPRINTF(LOW, "Restarting WDT in independent mode\n");
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_EN, SOC_IFC_REG_CPTRA_WDT_TIMER1_EN_TIMER1_EN_MASK);
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, wdt_rand_t1_val);
Expand All @@ -164,15 +200,27 @@ void caliptra_rt() {
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL, SOC_IFC_REG_CPTRA_WDT_TIMER2_CTRL_TIMER2_RESTART_MASK);

while (!(lsu_read_32(CLP_SOC_IFC_REG_CPTRA_WDT_STATUS) & SOC_IFC_REG_CPTRA_WDT_STATUS_T1_TIMEOUT_MASK));
//Reset timer period to avoid hangs in test
//Reset timer1 period to avoid hangs in test
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_0, 0xffffffff);
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER1_TIMEOUT_PERIOD_1, 0xffffffff);

while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK));
//Clear timer1 intr
lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK);
cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER1_TIMEOUT_STS_MASK;

//Reset timer2 period to avoid hangs in test
while (!(lsu_read_32(CLP_SOC_IFC_REG_CPTRA_WDT_STATUS) & SOC_IFC_REG_CPTRA_WDT_STATUS_T2_TIMEOUT_MASK));
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_0, 0xffffffff);
lsu_write_32(CLP_SOC_IFC_REG_CPTRA_WDT_TIMER2_TIMEOUT_PERIOD_1, 0xffffffff);

while (!(lsu_read_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R) & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK));
//Clear timer2 intr
lsu_write_32(CLP_SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R, SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK);
cptra_intr_rcv.soc_ifc_error |= SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_WDT_TIMER2_TIMEOUT_STS_MASK;

}
#endif
// Initialization
init_interrupts();
lsu_write_32(CLP_SHA512_ACC_CSR_INTR_BLOCK_RF_NOTIF_INTR_EN_R, 0); // FIXME tmp workaround to UVM issue with predicting SHA accelerator interrupts
Expand Down Expand Up @@ -288,7 +336,7 @@ void caliptra_rt() {
if (fsm_chk == 0xF) {
if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK)
VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit after servicing\n");
VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (cmd fail) after servicing\n");
} else {
VPRINTF(ERROR, "After finding an error and resetting the mailbox with force unlock, RT firmware has not received an soc_ifc_err_intr!\n");
SEND_STDOUT_CTRL(0x1);
Expand All @@ -306,7 +354,7 @@ void caliptra_rt() {
}
VPRINTF(MEDIUM, "Triggering FW update reset\n");
//Trigger firmware update reset, new fw will get copied over from ROM
soc_ifc_set_fw_update_reset();
soc_ifc_set_fw_update_reset((uint8_t) (rand() & 0xFF));
}
else if (op.cmd & MBOX_CMD_FIELD_RESP_MASK) {
VPRINTF(MEDIUM, "Received mailbox command (expecting RESP) from SOC! Got 0x%x\n", op.cmd);
Expand Down Expand Up @@ -372,7 +420,6 @@ void caliptra_rt() {
lsu_write_32((uintptr_t) (CLP_MBOX_CSR_MBOX_DLEN), temp);

// Write response data
srand((uint32_t) (op.cmd ^ read_data)); // Initialize rand num generator
for (loop_iter = 0; loop_iter<temp; loop_iter+=4) {
lsu_write_32((uintptr_t) (CLP_MBOX_CSR_MBOX_DATAIN), rand());
}
Expand All @@ -384,7 +431,7 @@ void caliptra_rt() {
if (fsm_chk == 0xF) {
if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK)
VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit after servicing\n");
VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (cmd fail) after servicing\n");
} else {
VPRINTF(ERROR, "After finding an error and resetting the mailbox with force unlock, RT firmware has not received an soc_ifc_err_intr!\n");
SEND_STDOUT_CTRL(0x1);
Expand All @@ -393,7 +440,13 @@ void caliptra_rt() {
}
continue;
}
soc_ifc_set_mbox_status_field(DATA_READY);
if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)
VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (ECC unc) after servicing\n");
soc_ifc_set_mbox_status_field(CMD_FAILURE);
} else {
soc_ifc_set_mbox_status_field(DATA_READY);
}
}
else {
VPRINTF(MEDIUM, "Received mailbox command (no expected RESP) from SOC! Got 0x%x\n", op.cmd);
Expand All @@ -420,7 +473,7 @@ void caliptra_rt() {
if (fsm_chk == 0xF) {
if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK) {
CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_CMD_FAIL_STS_MASK)
VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit after servicing\n");
VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (cmd fail) after servicing\n");
} else {
VPRINTF(ERROR, "After finding an error and resetting the mailbox with force unlock, RT firmware has not received an soc_ifc_err_intr!\n");
SEND_STDOUT_CTRL(0x1);
Expand All @@ -430,7 +483,13 @@ void caliptra_rt() {
continue;
}
//Mark the command complete
soc_ifc_set_mbox_status_field(CMD_COMPLETE);
if (cptra_intr_rcv.soc_ifc_error & SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK) {
CLEAR_INTR_FLAG_SAFELY(cptra_intr_rcv.soc_ifc_error, ~SOC_IFC_REG_INTR_BLOCK_RF_ERROR_INTERNAL_INTR_R_ERROR_MBOX_ECC_UNC_STS_MASK)
VPRINTF(LOW, "Clearing FW soc_ifc_error intr bit (ECC unc) after servicing\n");
soc_ifc_set_mbox_status_field(CMD_FAILURE);
} else {
soc_ifc_set_mbox_status_field(CMD_COMPLETE);
}
}
}
if (cptra_intr_rcv.soc_ifc_notif & SOC_IFC_REG_INTR_BLOCK_RF_NOTIF_INTERNAL_INTR_R_NOTIF_MBOX_ECC_COR_STS_MASK) {
Expand Down
13 changes: 11 additions & 2 deletions src/integration/test_suites/libs/soc_ifc/soc_ifc.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -227,9 +227,18 @@ void soc_ifc_fw_update(mbox_op_s op) {
}
}

void soc_ifc_set_fw_update_reset() {
VPRINTF(MEDIUM,"SOC_IFC: Set fw update reset\n");
void soc_ifc_set_fw_update_reset(uint8_t wait_cycles) {
uint32_t reg;
VPRINTF(MEDIUM,"SOC_IFC: Set fw update reset with wait_cycles [%d] (%s)\n", wait_cycles, wait_cycles > 5 ? "will override" : wait_cycles > 0 ? "will use default 5" : "won't override");
// A 0-value argument means don't override the current value
if (wait_cycles) {
// Enforce minimum wait_cycles of 5
if (wait_cycles > 5) {
lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES, wait_cycles);
} else {
lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_WAIT_CYCLES, 5);
}
}
reg = lsu_read_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET);
reg = (reg | SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET_CORE_RST_MASK);
lsu_write_32(CLP_SOC_IFC_REG_INTERNAL_FW_UPDATE_RESET,reg);
Expand Down
2 changes: 1 addition & 1 deletion src/integration/test_suites/libs/soc_ifc/soc_ifc.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -105,7 +105,7 @@ uint8_t soc_ifc_chk_execute_uc();
void soc_ifc_set_mbox_status_field(enum mbox_status_e field);
void soc_ifc_set_flow_status_field(uint32_t field);
void soc_ifc_clr_flow_status_field(uint32_t field);
void soc_ifc_set_fw_update_reset();
void soc_ifc_set_fw_update_reset(uint8_t wait_cycles);
inline void soc_ifc_set_iccm_lock() {
lsu_write_32((CLP_SOC_IFC_REG_INTERNAL_ICCM_LOCK), SOC_IFC_REG_INTERNAL_ICCM_LOCK_LOCK_MASK);
}
Expand Down
15 changes: 14 additions & 1 deletion src/integration/test_suites/smoke_test_cg_wdt/smoke_test_cg_wdt.c
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Original file line number Diff line number Diff line change
Expand Up @@ -156,6 +156,19 @@ void main() {
VPRINTF(LOW, "Debug mode unlocked\n====================\n");
SEND_STDOUT_CTRL(0xfa);

for (int i = 0; i < 1000; i++); //sleep

//Issue warm reset to capture debug mode
rst_count++;
SEND_STDOUT_CTRL(0xf6);
}
else if (rst_count == 1) {

rst_count++;
SEND_STDOUT_CTRL(0xf6);
}
else if (rst_count == 2) {

set_mit0_and_halt_core(mitb0, mie_timer0_ext_int_en);

//Disable ss tran
Expand All @@ -168,7 +181,7 @@ void main() {
rst_count++;
SEND_STDOUT_CTRL(0xf6);
}
else if(rst_count == 1) {
else if(rst_count == 3) {
//Enable internal timer0
__asm__ volatile ("csrwi %0, %1" \
: /* output: none */ \
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1 change: 1 addition & 0 deletions ...f_template_output/project_benches/caliptra_top/tb/sequences/caliptra_top_sequences_pkg.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -73,6 +73,7 @@ package caliptra_top_sequences_pkg;
`include "src/caliptra_top_cmdline_sequence.svh"
`include "src/caliptra_top_rom_sequence.svh"
`include "src/caliptra_top_wdt_sequence.svh"
`include "src/caliptra_top_wdt_independent_sequence.svh"
// pragma uvmf custom package_item_additional end

endpackage
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