Note about the use of silicon compiler and its output.

anikau31 · Jan 24, 2024 · 1bd8044 · 1bd8044
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diff --git a/README.rst b/README.rst
@@ -47,6 +47,16 @@ To enable compilation of tests, run cmake with the ``-DENABLE_TESTS=on`` flag an
 
 For information about running verilog conversion tests, see `this file <tests/verilog-conversion/README.md>`_.
 
+ASIC flow
+----------
+
+We have successfully been able to use the open-source ASIC flow in `systemcompiler <https://www.siliconcompiler.com/>`_ to generate the chip for ZFP's encoder. The input to siliconcompiler is the RTL generated by SCCL.  Below is what we got.
+
+.. image:: docs/zhw_encode.png
+  :width: 400
+  :alt: Alternative text
+
+
 Issues
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diff --git a/docs/zhw_encode.png b/docs/zhw_encode.png