feat: update project tt_um_NicklausThompson_SkyKing from FangameEmpir…

…e/tt08_skyking

Commit: 6346dd0a2a31cec81d6e90ce4540dc08e2bb2e84
Workflow: https://github.com/FangameEmpire/tt08_skyking/actions/runs/10743938344

projects/tt_um_NicklausThompson_SkyKing/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt08 587b6cb0",
   "repo": "https://github.com/FangameEmpire/tt08_skyking",
-  "commit": "d37f29ea1c6b99fd42c50389af1ad0749404b112",
-  "workflow_url": "https://github.com/FangameEmpire/tt08_skyking/actions/runs/10743308045",
+  "commit": "6346dd0a2a31cec81d6e90ce4540dc08e2bb2e84",
+  "workflow_url": "https://github.com/FangameEmpire/tt08_skyking/actions/runs/10743938344",
   "sort_id": 1725634925468,
   "openlane_version": "OpenLane2 2.0.8",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_NicklausThompson_SkyKing/stats/metrics.csv

@@ -1,83 +1,83 @@
 Metric,Value
 design__lint_error__count,0
 design__lint_timing_construct__count,0
-design__lint_warning__count,2
+design__lint_warning__count,0
 design__inferred_latch__count,0
-design__instance__count,835
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+design__instance__count,933
+design__instance__area,6601.33
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
-design__max_fanout_violation__count__corner:nom_tt_025C_1v80,5
+design__max_fanout_violation__count__corner:nom_tt_025C_1v80,3
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,0.00033680262276902795
-power__switching__total,0.00013537477934733033
-power__leakage__total,7.283217140496845e-09
-power__total,0.00047218467807397246
-clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.011986
-clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.011986
-timing__hold__ws__corner:nom_tt_025C_1v80,0.327012
-timing__setup__ws__corner:nom_tt_025C_1v80,9.857509
+power__internal__total,0.0003075357817579061
+power__switching__total,0.00010215105430688709
+power__leakage__total,8.008926855040954e-09
+power__total,0.00040969482506625354
+clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.025252
+clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.025252
+timing__hold__ws__corner:nom_tt_025C_1v80,0.319734
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 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
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 timing__setup__wns__corner:nom_tt_025C_1v80,0.0
 timing__hold_vio__count__corner:nom_tt_025C_1v80,0
-timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.327012
+timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.319734
 timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_vio__count__corner:nom_tt_025C_1v80,0
-timing__setup_r2r__ws__corner:nom_tt_025C_1v80,17.877186
+timing__setup_r2r__ws__corner:nom_tt_025C_1v80,17.833521
 timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
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 timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
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-timing__setup_r2r__ws__corner:nom_ss_100C_1v60,13.932044
+timing__setup_r2r__ws__corner:nom_ss_100C_1v60,13.949426
 timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
 design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
-design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,5
+design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,3
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
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-clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.009878
-timing__hold__ws__corner:nom_ff_n40C_1v95,0.11978
-timing__setup__ws__corner:nom_ff_n40C_1v95,10.55729
+clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.019541
+clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.019541
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+timing__setup__ws__corner:nom_ff_n40C_1v95,10.533063
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 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
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 timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
-timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.11978
+timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.119111
 timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
-timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,18.589054
+timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,18.52071
 timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
-design__max_slew_violation__count,2
-design__max_fanout_violation__count,5
+design__max_slew_violation__count,6
+design__max_fanout_violation__count,3
 design__max_cap_violation__count,0
-clock__skew__worst_hold,-0.009124
-clock__skew__worst_setup,-0.022391
-timing__hold__ws,0.116447
-timing__setup__ws,7.983994
+clock__skew__worst_hold,0.043025
+clock__skew__worst_setup,0.018326
+timing__hold__ws,0.116247
+timing__setup__ws,7.722068
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0.0
 timing__setup__wns,0.0
 timing__hold_vio__count,0
-timing__hold_r2r__ws,0.116447
+timing__hold_r2r__ws,0.116247
 timing__hold_r2r_vio__count,0
 timing__setup_vio__count,0
-timing__setup_r2r__ws,13.878508
+timing__setup_r2r__ws,13.895876
 timing__setup_r2r_vio__count,0
 design__die__bbox,0.0 0.0 161.0 111.52
 design__core__bbox,2.76 2.72 158.24 108.8
@@ -86,12 +86,12 @@ flow__errors__count,0
 design__io,45
 design__die__area,17954.7
 design__core__area,16493.3
-design__instance__count__stdcell,835
-design__instance__area__stdcell,5943.2
+design__instance__count__stdcell,933
+design__instance__area__stdcell,6601.33
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.36034
-design__instance__utilization__stdcell,0.36034
+design__instance__utilization,0.400243
+design__instance__utilization__stdcell,0.400243
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count,0
@@ -100,164 +100,166 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,11176.7
+route__wirelength__estimated,13865.2
 design__violations,0
 design__instance__count__setup_buffer,0
-design__instance__count__hold_buffer,46
+design__instance__count__hold_buffer,41
 antenna__violating__nets,0
 antenna__violating__pins,0
 route__antenna_violation__count,0
-route__net,629
+route__net,727
 route__net__special,2
-route__drc_errors__iter:1,408
-route__wirelength__iter:1,12819
-route__drc_errors__iter:2,128
-route__wirelength__iter:2,12712
-route__drc_errors__iter:3,114
-route__wirelength__iter:3,12602
-route__drc_errors__iter:4,19
-route__wirelength__iter:4,12536
-route__drc_errors__iter:5,0
-route__wirelength__iter:5,12546
+route__drc_errors__iter:1,455
+route__wirelength__iter:1,16116
+route__drc_errors__iter:2,271
+route__wirelength__iter:2,15964
+route__drc_errors__iter:3,192
+route__wirelength__iter:3,15940
+route__drc_errors__iter:4,21
+route__wirelength__iter:4,15894
+route__drc_errors__iter:5,4
+route__wirelength__iter:5,15891
+route__drc_errors__iter:6,0
+route__wirelength__iter:6,15887
 route__drc_errors,0
-route__wirelength,12546
-route__vias,4293
-route__vias__singlecut,4293
+route__wirelength,15887
+route__vias,5268
+route__vias__singlecut,5268
 route__vias__multicut,0
 design__disconnected_pin__count,14
 design__critical_disconnected_pin__count,0
-route__wirelength__max,163.21
+route__wirelength__max,224.42
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+design__max_fanout_violation__count__corner:max_ff_n40C_1v95,3
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.011572
-clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.011572
-timing__hold__ws__corner:max_ff_n40C_1v95,0.122682
-timing__setup__ws__corner:max_ff_n40C_1v95,10.541613
+clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.021795
+clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.021795
+timing__hold__ws__corner:max_ff_n40C_1v95,0.121762
+timing__setup__ws__corner:max_ff_n40C_1v95,10.515362
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0.0
 timing__setup__wns__corner:max_ff_n40C_1v95,0.0
 timing__hold_vio__count__corner:max_ff_n40C_1v95,0
-timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.122682
+timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.121762
 timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
-timing__setup_r2r__ws__corner:max_ff_n40C_1v95,18.570307
+timing__setup_r2r__ws__corner:max_ff_n40C_1v95,18.499603
 timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__unannotated_net__count__corner:max_ff_n40C_1v95,22
 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
 timing__unannotated_net__count,22
 timing__unannotated_net_filtered__count,0
-design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79993
+design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79995
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000678894
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000439756
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000809919
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000439756
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000500348
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000549872
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000731186
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000549872
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,0.000008130000000000000087382358293641715363264665938913822174072265625
-ir__drop__worst,0.00006789999999999999703327591138446450713672675192356109619140625
+ir__drop__avg,0.0000070099999999999997992512941469289700080480542965233325958251953125
+ir__drop__worst,0.0000500000000000000023960868011929647991564706899225711822509765625
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0