feat: update project tt_um_johshoff_metaballs from johshoff/tt08-meta…

…balls

Commit: ce37dd6b8c13ac1706fc06b203f6f3a7e497624f
Workflow: https://github.com/johshoff/tt08-metaballs/actions/runs/10744353935

projects/tt_um_johshoff_metaballs/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt08 587b6cb0",
   "repo": "https://github.com/johshoff/tt08-metaballs",
-  "commit": "43a77932c0da356f35f32cbb3e6657cbc093ef11",
-  "workflow_url": "https://github.com/johshoff/tt08-metaballs/actions/runs/10742983539",
+  "commit": "ce37dd6b8c13ac1706fc06b203f6f3a7e497624f",
+  "workflow_url": "https://github.com/johshoff/tt08-metaballs/actions/runs/10744353935",
   "sort_id": 1725631745115,
   "openlane_version": "OpenLane2 2.0.8",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_johshoff_metaballs/stats/metrics.csv

@@ -1,83 +1,83 @@
 Metric,Value
 design__lint_error__count,0
 design__lint_timing_construct__count,0
-design__lint_warning__count,4
+design__lint_warning__count,0
 design__inferred_latch__count,0
-design__instance__count,1565
-design__instance__area,11402.2
+design__instance__count,1504
+design__instance__area,10920.5
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
-design__max_fanout_violation__count__corner:nom_tt_025C_1v80,1
+design__max_fanout_violation__count__corner:nom_tt_025C_1v80,2
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
-power__internal__total,0.0001146833601524122
-power__switching__total,6.159316399134696e-05
-power__leakage__total,1.1664498700270087e-08
-power__total,0.0001762881875038147
-clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.00928
-clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.00928
-timing__hold__ws__corner:nom_tt_025C_1v80,0.332866
-timing__setup__ws__corner:nom_tt_025C_1v80,14.328883
+power__internal__total,0.00011489853932289407
+power__switching__total,6.00968451180961e-05
+power__leakage__total,1.1178526548860646e-08
+power__total,0.00017500655667390674
+clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.009802
+clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.009802
+timing__hold__ws__corner:nom_tt_025C_1v80,0.345377
+timing__setup__ws__corner:nom_tt_025C_1v80,14.527608
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0.0
 timing__setup__wns__corner:nom_tt_025C_1v80,0.0
 timing__hold_vio__count__corner:nom_tt_025C_1v80,0
-timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.332866
+timing__hold_r2r__ws__corner:nom_tt_025C_1v80,0.345377
 timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_vio__count__corner:nom_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:nom_tt_025C_1v80,inf
 timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
-design__max_slew_violation__count__corner:nom_ss_100C_1v60,9
-design__max_fanout_violation__count__corner:nom_ss_100C_1v60,1
+design__max_slew_violation__count__corner:nom_ss_100C_1v60,5
+design__max_fanout_violation__count__corner:nom_ss_100C_1v60,2
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
-clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.015853
-clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.015853
-timing__hold__ws__corner:nom_ss_100C_1v60,0.870958
-timing__setup__ws__corner:nom_ss_100C_1v60,13.156604
+clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.016057
+clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.016057
+timing__hold__ws__corner:nom_ss_100C_1v60,0.890891
+timing__setup__ws__corner:nom_ss_100C_1v60,13.484212
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0.0
 timing__setup__wns__corner:nom_ss_100C_1v60,0.0
 timing__hold_vio__count__corner:nom_ss_100C_1v60,0
-timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.870958
+timing__hold_r2r__ws__corner:nom_ss_100C_1v60,0.890891
 timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
 timing__setup_vio__count__corner:nom_ss_100C_1v60,0
-timing__setup_r2r__ws__corner:nom_ss_100C_1v60,14.65145
+timing__setup_r2r__ws__corner:nom_ss_100C_1v60,13.862963
 timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
 design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
-design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,1
+design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,2
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
-clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.007188
-clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.007188
-timing__hold__ws__corner:nom_ff_n40C_1v95,0.119945
-timing__setup__ws__corner:nom_ff_n40C_1v95,14.801385
+clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.007648
+clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.007648
+timing__hold__ws__corner:nom_ff_n40C_1v95,0.133292
+timing__setup__ws__corner:nom_ff_n40C_1v95,14.93639
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__wns__corner:nom_ff_n40C_1v95,0.0
 timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
-timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.119945
+timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.133292
 timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,inf
 timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
-design__max_slew_violation__count,19
-design__max_fanout_violation__count,1
+design__max_slew_violation__count,5
+design__max_fanout_violation__count,2
 design__max_cap_violation__count,0
-clock__skew__worst_hold,0.016
+clock__skew__worst_hold,0.016781
 clock__skew__worst_setup,0.006964
-timing__hold__ws,0.117698
-timing__setup__ws,13.082654
+timing__hold__ws,0.126976
+timing__setup__ws,13.44628
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0.0
 timing__setup__wns,0.0
 timing__hold_vio__count,0
-timing__hold_r2r__ws,0.117698
+timing__hold_r2r__ws,0.126976
 timing__hold_r2r_vio__count,0
 timing__setup_vio__count,0
-timing__setup_r2r__ws,14.56928
+timing__setup_r2r__ws,13.77201
 timing__setup_r2r_vio__count,0
 design__die__bbox,0.0 0.0 161.0 111.52
 design__core__bbox,2.76 2.72 158.24 108.8
@@ -86,12 +86,12 @@ flow__errors__count,0
 design__io,45
 design__die__area,17954.7
 design__core__area,16493.3
-design__instance__count__stdcell,1565
-design__instance__area__stdcell,11402.2
+design__instance__count__stdcell,1504
+design__instance__area__stdcell,10920.5
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.691321
-design__instance__utilization__stdcell,0.691321
+design__instance__utilization,0.662115
+design__instance__utilization__stdcell,0.662115
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count,0
@@ -100,151 +100,149 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,23006.4
+route__wirelength__estimated,21665.2
 design__violations,0
 design__instance__count__setup_buffer,0
-design__instance__count__hold_buffer,11
+design__instance__count__hold_buffer,8
 antenna__violating__nets,0
 antenna__violating__pins,0
 route__antenna_violation__count,0
-route__net,1359
+route__net,1298
 route__net__special,2
-route__drc_errors__iter:1,673
-route__wirelength__iter:1,26988
-route__drc_errors__iter:2,510
-route__wirelength__iter:2,26780
-route__drc_errors__iter:3,370
-route__wirelength__iter:3,26727
-route__drc_errors__iter:4,88
-route__wirelength__iter:4,26640
-route__drc_errors__iter:5,27
-route__wirelength__iter:5,26633
-route__drc_errors__iter:6,3
-route__wirelength__iter:6,26651
-route__drc_errors__iter:7,0
-route__wirelength__iter:7,26649
+route__drc_errors__iter:1,902
+route__wirelength__iter:1,25631
+route__drc_errors__iter:2,481
+route__wirelength__iter:2,25456
+route__drc_errors__iter:3,380
+route__wirelength__iter:3,25293
+route__drc_errors__iter:4,38
+route__wirelength__iter:4,25230
+route__drc_errors__iter:5,17
+route__wirelength__iter:5,25218
+route__drc_errors__iter:6,0
+route__wirelength__iter:6,25215
 route__drc_errors,0
-route__wirelength,26649
-route__vias,9705
-route__vias__singlecut,9705
+route__wirelength,25215
+route__vias,9192
+route__vias__singlecut,9192
 route__vias__multicut,0
 design__disconnected_pin__count,17
 design__critical_disconnected_pin__count,0
-route__wirelength__max,167.11
+route__wirelength__max,160.77
 timing__unannotated_net__count__corner:nom_tt_025C_1v80,33
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 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
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+design__max_fanout_violation__count__corner:min_tt_025C_1v80,2
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
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-timing__hold__ws__corner:min_tt_025C_1v80,0.32731
-timing__setup__ws__corner:min_tt_025C_1v80,14.367997
+clock__skew__worst_hold__corner:min_tt_025C_1v80,0.009015
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+timing__hold__ws__corner:min_tt_025C_1v80,0.339353
+timing__setup__ws__corner:min_tt_025C_1v80,14.548008
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-timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.32731
+timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.339353
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+clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.008631
+timing__hold__ws__corner:max_ff_n40C_1v95,0.142926
+timing__setup__ws__corner:max_ff_n40C_1v95,14.92025
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0.0
 timing__setup__wns__corner:max_ff_n40C_1v95,0.0
 timing__hold_vio__count__corner:max_ff_n40C_1v95,0
-timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.122266
+timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.142926
 timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,inf
@@ -255,13 +253,13 @@ timing__unannotated_net__count,33
 timing__unannotated_net_filtered__count,0
 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79996
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000429722
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000399399
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000320627
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000399399
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000387193
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000374704
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000309794
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000374704
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,0.00000323999999999999989573552967858649509480528649874031543731689453125
-ir__drop__worst,0.000043000000000000001654058834343885564521769993007183074951171875
+ir__drop__avg,0.000003189999999999999950937683290685953352294745855033397674560546875
+ir__drop__worst,0.0000386999999999999987781475196957359230509609915316104888916015625
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0