invalid opcode

[mlabaf2]

Before start

• I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册，这不是一个指令集相关的问题。
• I have read the XiangShan Documents. 我已经阅读过香山文档。
• I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions，并没有找到相关的。
• I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the question

HI
i added some new opcode to XiangShan. I modify Instruction.scala, ALU.scala, parameters.scala, DecodeUnit.scala. when I run my workspace , I recieved this message in report of .log file . I cannot find from which .scala code this message is produced "invalid opcode...."

[mlabaf2]

Another question is which .scala file call class Alu in Alu.scala file? I cannot find it to trace the mentioned error message...

[cebarobot]

This invalid opcode message is come from NEMU, the golden reference model of XiangShan. You may modify the NEMU to support your new instruction, or just add --no-diff argument to run emu in no diff mode.

[cebarobot]

Another question is which .scala file call class Alu in Alu.scala file? I cannot find it to trace the mentioned error message...

I think it's here.

XiangShan/src/main/scala/xiangshan/backend/fu/FuConfig.scala

Lines 297 to 307 in c2ce03f

	val AluCfg: FuConfig = FuConfig (
	name = "alu",
	fuType = FuType.alu,
	fuGen = (p: Parameters, cfg: FuConfig) => Module(new Alu(cfg)(p).suggestName("Alu")),
	srcData = Seq(
	Seq(IntData(), IntData()),
	),
	piped = true,
	writeIntRf = true,
	immType = Set(SelImm.IMM_I, SelImm.IMM_U, SelImm.IMM_LUI32),
	)

And this fuGen is called here.

XiangShan/src/main/scala/xiangshan/backend/exu/ExeUnit.scala

Lines 62 to 66 in 7ffbf5f

	val funcUnits = fuCfgs.map(cfg => {
	assert(cfg.fuGen != null, cfg.name + "Cfg'fuGen is null !!!")
	val module = cfg.fuGen(p, cfg)
	module
	})

[mlabaf2]

thanks solved