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feat(svpbmt): support PBMTE #532

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feat(svpbmt): support PBMTE #532

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286ec26
feat(svpbmt): support PBMTE
Maxpicca-Li Sep 19, 2024
ab9504d
feat(svpbmt): code style unified and remove read-only write ignore fo…
Maxpicca-Li Sep 19, 2024
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5 changes: 4 additions & 1 deletion src/isa/riscv64/init.c
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Original file line number Diff line number Diff line change
Expand Up @@ -81,7 +81,10 @@ void init_isa() {
// as opensbi and linux not support smrnmi, so we init nmie = 1 to pass ci
mnstatus->nmie = 1;
#endif //CONFIG_RV_SMRNMI

#ifdef CONFIG_RV_SVPBMT
menvcfg->pbmte = 1;
henvcfg->pbmte = 1;
#endif //CONFIG_RV_SVPBMT
#ifdef CONFIG_RV_PMP_ENTRY_16
pmpcfg0->val = 0;
pmpcfg2->val = 0;
Expand Down
17 changes: 13 additions & 4 deletions src/isa/riscv64/system/mmu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@
#include <cpu/cpu.h>
#include "../local-include/csr.h"
#include "../local-include/intr.h"
#include "../local-include/rtl.h"

typedef union PageTableEntry {
struct {
Expand Down Expand Up @@ -216,6 +217,7 @@ paddr_t gpa_stage(paddr_t gpaddr, vaddr_t vaddr, int type, int trap_type, bool i
}
max_level = 3;
}
bool pbmte = menvcfg->pbmte;
word_t pg_base = PGBASE(hgatp->ppn);
int level;
word_t p_pte;
Expand Down Expand Up @@ -245,7 +247,7 @@ paddr_t gpa_stage(paddr_t gpaddr, vaddr_t vaddr, int type, int trap_type, bool i
if (level < 0) { break; }
} else if (!pte.v || (!pte.r && pte.w) || pte.pad) {
break;
} else if (ISNDEF(CONFIG_RV_SVPBMT) && pte.pbmt) {
} else if ((ISNDEF(CONFIG_RV_SVPBMT) || !pbmte) && pte.pbmt) {
break;
} else if (pte.pbmt == 3) {
break;
Expand Down Expand Up @@ -323,6 +325,13 @@ static paddr_t ptw(vaddr_t vaddr, int type) {
pg_base = PGBASE(vsatp->ppn);
max_level = vsatp->mode == SATP_MODE_Sv39 ? 3 : 4;
}
#endif
bool pbmte = menvcfg->pbmte;
#ifdef CONFIG_RVH
if(virt){
// henvcfg.pbmte is read_only 0 when menvcfg.pbmte = 0
pbmte = henvcfg->pbmte & menvcfg->pbmte;
}
#endif
word_t p_pte; // pte pointer
PTE pte;
Expand All @@ -341,11 +350,11 @@ static paddr_t ptw(vaddr_t vaddr, int type) {
#ifdef CONFIG_MULTICORE_DIFF
pte.val = golden_pmem_read(p_pte, PTE_SIZE, 0, 0, 0);
#else
#ifdef CONFIG_RVH
#ifdef CONFIG_RVH
if(virt){
p_pte = gpa_stage(p_pte, vaddr, MEM_TYPE_READ, type, false, true);
}
#endif //CONFIG_RVH
#endif //CONFIG_RVH
pte.val = pte_read(p_pte, type, MODE_S, vaddr);
#endif
#ifdef CONFIG_SHARE
Expand All @@ -357,7 +366,7 @@ static paddr_t ptw(vaddr_t vaddr, int type) {
pg_base = PGBASE((uint64_t)pte.ppn);
if (!pte.v || (!pte.r && pte.w) || pte.pad) {
goto bad;
} else if (ISNDEF(CONFIG_RV_SVPBMT) && pte.pbmt) {
} else if ((ISNDEF(CONFIG_RV_SVPBMT) || !pbmte) && pte.pbmt) {
goto bad;
} else if (pte.pbmt == 3) {
goto bad;
Expand Down
12 changes: 9 additions & 3 deletions src/isa/riscv64/system/priv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -258,10 +258,15 @@ static inline word_t* csr_decode(uint32_t addr) {
#define HSTATUS_WMASK 0
#endif

#define MENVCFG_WMASK_STCE MUXDEF(CONFIG_RV_SSTC, (0x1UL << 63), 0)
#define MENVCFG_WMASK_DTE MUXDEF(CONFIG_RV_SSDBLTRP, (0x1UL << 59), 0)
#define MENVCFG_RMASK_STCE (0x1UL << 63)
#define MENVCFG_RMASK_DTE (0x1UL << 59)
#define MENVCFG_RMASK_PBMTE (0x1UL << 62)
#define MENVCFG_WMASK_STCE MUXDEF(CONFIG_RV_SSTC, (0x1UL << 63), 0)
#define MENVCFG_WMASK_DTE MUXDEF(CONFIG_RV_SSDBLTRP, (0x1UL << 59), 0)
#define MENVCFG_WMASK_PBMTE MUXDEF(CONFIG_RV_SSDBLTRP, (0x1UL << 62), 0)
#define MENVCFG_WMASK ( \
MENVCFG_WMASK_STCE | \
MENVCFG_WMASK_PBMTE | \
MENVCFG_WMASK_DTE \
)
#define HENVCFG_WMASK MENVCFG_WMASK
Expand Down Expand Up @@ -725,7 +730,8 @@ if (is_read(hie)) { return mie->val & HIE_RMASK & (mideleg->val | MID
if (is_read(hvip)) { return mip->val & HVIP_MASK;}
if (is_read(henvcfg)) {
uint64_t henvcfg_out = henvcfg->val;
henvcfg_out &= menvcfg->val & (MENVCFG_WMASK_STCE | MENVCFG_WMASK_DTE);
/* henvcfg.stce/dte/pbmte is read_only 0 when menvcfg.stce/dte/pbmte = 0 */
henvcfg_out &= menvcfg->val | ~(MENVCFG_RMASK_STCE | MENVCFG_RMASK_DTE | MENVCFG_RMASK_PBMTE);
return henvcfg_out & HENVCFG_WMASK;
}
#ifdef CONFIG_RV_AIA
Expand Down
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