MIPS CPU

This is a simple MIPS CPU written in Verilog and Logisim.

Features

ScreenShots

Logisim Pipeline Data Path:

Logisim Interrupt Version Data Path:

Name		Name	Last commit message	Last commit date
Latest commit History 9 Commits
logisim		logisim
ALU.v		ALU.v
Associative_Memory.v		Associative_Memory.v
CPU.v		CPU.v
EX.v		EX.v
ID.v		ID.v
IF.v		IF.v
Interrupt.png		Interrupt.png
MEM.v		MEM.v
Pipeline.png		Pipeline.png
RAM.v		RAM.v
README.md		README.md
ROM.v		ROM.v
WB.v		WB.v
base.v		base.v
benchmark		benchmark
control.v		control.v
redirect.v		redirect.v
regfile.v		regfile.v
sdgsd.xdc		sdgsd.xdc
test.v		test.v
test_behav.wcfg		test_behav.wcfg
testnew		testnew

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