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[WIP] Script generating symbols for Xilinx FPGA #293

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[WIP] Script generating symbols for Xilinx FPGA #293

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Commits on Apr 24, 2019

  1. First play with Xilinx's package definition files. 

    Pin extracting, bank grouping.
Some primitive symbol generation.
    @ObKo
    ObKo committed Apr 24, 2019
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Commits on Apr 25, 2019

  1. Complete symbol layout generation. 

    No electrical types yet.
    @ObKo
    ObKo committed Apr 25, 2019
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Commits on Apr 26, 2019

  1. Electrical types.

    @ObKo
    ObKo committed Apr 26, 2019
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  2. Footprint assignment.

    @ObKo
    ObKo committed Apr 26, 2019
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  3. Some polishing.

    @ObKo
    ObKo committed Apr 26, 2019
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Commits on Apr 28, 2019

  1. Artix-7 support. 

    Some small fixes.
    @ObKo
    ObKo committed Apr 28, 2019
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Commits on Apr 29, 2019

  1. Zynq-7000 support. 

    Minor layout improvements.
    @ObKo
    ObKo committed Apr 29, 2019
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  2. Cleanup layout code.

    @ObKo
    ObKo committed Apr 29, 2019
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  3. Don't save incomplete symbols. 

    Support for Kintex-7 and Virtex-7.
    @ObKo
    ObKo committed Apr 29, 2019
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Commits on Apr 30, 2019

  1. Correct footprint names.

    @ObKo
    ObKo committed Apr 30, 2019
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