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risc-v.qsf
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risc-v.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2020 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and any partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details, at
# https://fpgasoftware.intel.com/eula.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
# Date created = 12:08:44 April 27, 2023
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# risc-v_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE auto
set_global_assignment -name TOP_LEVEL_ENTITY riscv
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:08:44 APRIL 27, 2023"
set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name VHDL_FILE ALU.vhd
set_global_assignment -name VHDL_FILE InstrMemory.vhd
set_global_assignment -name VHDL_FILE RegisterFile.vhd
set_global_assignment -name VHDL_FILE DataMemory.vhd
set_global_assignment -name VHDL_FILE Datapath.vhd
set_global_assignment -name VHDL_FILE ControlUnit.vhd
set_global_assignment -name VHDL_FILE Extend.vhd
set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH riscv_tb -section_id eda_simulation
set_global_assignment -name VHDL_FILE registerfile_tb.vhd
set_global_assignment -name EDA_TEST_BENCH_NAME Registerfile_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id Registerfile_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME Registerfile_tb -section_id Registerfile_tb
set_global_assignment -name VHDL_FILE Adder.vhd
set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS 999999999
set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION OFF
set_global_assignment -name VHDL_FILE sw_tb.vhd
set_global_assignment -name VHDL_FILE lw_tb.vhd
set_global_assignment -name EDA_TEST_BENCH_NAME lw_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id lw_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME lw_tb -section_id lw_tb
set_global_assignment -name EDA_TEST_BENCH_NAME sw_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id sw_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME sw_tb -section_id sw_tb
set_global_assignment -name VHDL_FILE Mux_2_to_1.vhd
set_global_assignment -name VHDL_FILE beq_tb.vhd
set_global_assignment -name EDA_TEST_BENCH_NAME beq_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id beq_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME beq_tb -section_id beq_tb
set_global_assignment -name ALLOW_REGISTER_MERGING OFF
set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
set_global_assignment -name OPTIMIZATION_MODE BALANCED
set_global_assignment -name ALLOW_REGISTER_RETIMING OFF
set_global_assignment -name VHDL_FILE MainDecoder.vhd
set_global_assignment -name VHDL_FILE ALUDecoder.vhd
set_global_assignment -name VHDL_FILE riscv.vhd
set_global_assignment -name VHDL_FILE riscv_tb.vhd
set_global_assignment -name EDA_TEST_BENCH_FILE registerfile_tb.vhd -section_id Registerfile_tb
set_global_assignment -name EDA_TEST_BENCH_FILE lw_tb.vhd -section_id lw_tb
set_global_assignment -name EDA_TEST_BENCH_FILE sw_tb.vhd -section_id sw_tb
set_global_assignment -name EDA_TEST_BENCH_FILE beq_tb.vhd -section_id beq_tb
set_global_assignment -name EDA_TEST_BENCH_NAME riscv_tb -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id riscv_tb
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME riscv_tb -section_id riscv_tb
set_global_assignment -name EDA_TEST_BENCH_FILE riscv_tb.vhd -section_id riscv_tb
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top