From d4ded74e5796b46dae6753b389a0f0aea09c1f72 Mon Sep 17 00:00:00 2001 From: Robin Freyler Date: Fri, 4 Oct 2024 13:25:40 +0200 Subject: [PATCH] rename instructions with immediate ShiftAmount --- crates/ir/src/for_each_op.rs | 40 +++++++++---------- crates/wasmi/src/engine/executor/instrs.rs | 36 +++++++---------- .../src/engine/executor/instrs/binary.rs | 22 +++++----- crates/wasmi/src/engine/translator/mod.rs | 4 +- .../translator/tests/op/binary/i32_rotl.rs | 2 +- .../translator/tests/op/binary/i32_rotr.rs | 2 +- .../translator/tests/op/binary/i32_shl.rs | 2 +- .../translator/tests/op/binary/i32_shr_s.rs | 2 +- .../translator/tests/op/binary/i32_shr_u.rs | 2 +- .../translator/tests/op/binary/i64_rotl.rs | 2 +- .../translator/tests/op/binary/i64_rotr.rs | 2 +- .../translator/tests/op/binary/i64_shl.rs | 2 +- .../translator/tests/op/binary/i64_shr_s.rs | 2 +- .../translator/tests/op/binary/i64_shr_u.rs | 2 +- crates/wasmi/src/engine/translator/visit.rs | 20 +++++----- 15 files changed, 67 insertions(+), 75 deletions(-) diff --git a/crates/ir/src/for_each_op.rs b/crates/ir/src/for_each_op.rs index 923bc44e40..759071cbbb 100644 --- a/crates/ir/src/for_each_op.rs +++ b/crates/ir/src/for_each_op.rs @@ -4018,8 +4018,8 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i32.shl` equivalent Wasmi instruction with 16-bit immediate `rhs` operand. - #[snake_name(i32_shl_imm)] - I32ShlImm { + #[snake_name(i32_shl_by)] + I32ShlBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -4046,8 +4046,8 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i32.shr_u` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i32_shr_u_imm)] - I32ShrUImm { + #[snake_name(i32_shr_u_by)] + I32ShrUBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -4074,8 +4074,8 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i32.shr_s` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i32_shr_s_imm)] - I32ShrSImm { + #[snake_name(i32_shr_s_by)] + I32ShrSBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -4102,8 +4102,8 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i32.rotl` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i32_rotl_imm)] - I32RotlImm { + #[snake_name(i32_rotl_by)] + I32RotlBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -4130,8 +4130,8 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i32.rotr` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i32_rotr_imm)] - I32RotrImm { + #[snake_name(i32_rotr_by)] + I32RotrBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -4478,8 +4478,8 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i64.shl` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i64_shl_imm)] - I64ShlImm { + #[snake_name(i64_shl_by)] + I64ShlBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -4506,8 +4506,8 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i64.shr_u` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i64_shr_u_imm)] - I64ShrUImm { + #[snake_name(i64_shr_u_by)] + I64ShrUBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -4534,8 +4534,8 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i64.shr_s` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i64_shr_s_imm)] - I64ShrSImm { + #[snake_name(i64_shr_s_by)] + I64ShrSBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -4562,8 +4562,8 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i64.rotl` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i64_rotl_imm)] - I64RotlImm { + #[snake_name(i64_rotl_by)] + I64RotlBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -4590,8 +4590,8 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i64.rotr` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i64_rotr_imm)] - I64RotrImm { + #[snake_name(i64_rotr_by)] + I64RotrBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, diff --git a/crates/wasmi/src/engine/executor/instrs.rs b/crates/wasmi/src/engine/executor/instrs.rs index cbad15fdae..ede1c62fbc 100644 --- a/crates/wasmi/src/engine/executor/instrs.rs +++ b/crates/wasmi/src/engine/executor/instrs.rs @@ -968,35 +968,31 @@ impl<'engine> Executor<'engine> { self.execute_i32_xor_imm16(result, lhs, rhs) } Instr::I32Shl { result, lhs, rhs } => self.execute_i32_shl(result, lhs, rhs), - Instr::I32ShlImm { result, lhs, rhs } => self.execute_i32_shl_imm(result, lhs, rhs), + Instr::I32ShlBy { result, lhs, rhs } => self.execute_i32_shl_by(result, lhs, rhs), Instr::I32ShlImm16Lhs { result, lhs, rhs } => { self.execute_i32_shl_imm16_lhs(result, lhs, rhs) } Instr::I32ShrU { result, lhs, rhs } => self.execute_i32_shr_u(result, lhs, rhs), - Instr::I32ShrUImm { result, lhs, rhs } => { - self.execute_i32_shr_u_imm(result, lhs, rhs) + Instr::I32ShrUBy { result, lhs, rhs } => { + self.execute_i32_shr_u_by(result, lhs, rhs) } Instr::I32ShrUImm16Lhs { result, lhs, rhs } => { self.execute_i32_shr_u_imm16_lhs(result, lhs, rhs) } Instr::I32ShrS { result, lhs, rhs } => self.execute_i32_shr_s(result, lhs, rhs), - Instr::I32ShrSImm { result, lhs, rhs } => { - self.execute_i32_shr_s_imm(result, lhs, rhs) + Instr::I32ShrSBy { result, lhs, rhs } => { + self.execute_i32_shr_s_by(result, lhs, rhs) } Instr::I32ShrSImm16Lhs { result, lhs, rhs } => { self.execute_i32_shr_s_imm16_lhs(result, lhs, rhs) } Instr::I32Rotl { result, lhs, rhs } => self.execute_i32_rotl(result, lhs, rhs), - Instr::I32RotlImm { result, lhs, rhs } => { - self.execute_i32_rotl_imm(result, lhs, rhs) - } + Instr::I32RotlBy { result, lhs, rhs } => self.execute_i32_rotl_by(result, lhs, rhs), Instr::I32RotlImm16Lhs { result, lhs, rhs } => { self.execute_i32_rotl_imm16_lhs(result, lhs, rhs) } Instr::I32Rotr { result, lhs, rhs } => self.execute_i32_rotr(result, lhs, rhs), - Instr::I32RotrImm { result, lhs, rhs } => { - self.execute_i32_rotr_imm(result, lhs, rhs) - } + Instr::I32RotrBy { result, lhs, rhs } => self.execute_i32_rotr_by(result, lhs, rhs), Instr::I32RotrImm16Lhs { result, lhs, rhs } => { self.execute_i32_rotr_imm16_lhs(result, lhs, rhs) } @@ -1056,35 +1052,31 @@ impl<'engine> Executor<'engine> { self.execute_i64_xor_imm16(result, lhs, rhs) } Instr::I64Shl { result, lhs, rhs } => self.execute_i64_shl(result, lhs, rhs), - Instr::I64ShlImm { result, lhs, rhs } => self.execute_i64_shl_imm(result, lhs, rhs), + Instr::I64ShlBy { result, lhs, rhs } => self.execute_i64_shl_by(result, lhs, rhs), Instr::I64ShlImm16Lhs { result, lhs, rhs } => { self.execute_i64_shl_imm16_lhs(result, lhs, rhs) } Instr::I64ShrU { result, lhs, rhs } => self.execute_i64_shr_u(result, lhs, rhs), - Instr::I64ShrUImm { result, lhs, rhs } => { - self.execute_i64_shr_u_imm(result, lhs, rhs) + Instr::I64ShrUBy { result, lhs, rhs } => { + self.execute_i64_shr_u_by(result, lhs, rhs) } Instr::I64ShrUImm16Lhs { result, lhs, rhs } => { self.execute_i64_shr_u_imm16_lhs(result, lhs, rhs) } Instr::I64ShrS { result, lhs, rhs } => self.execute_i64_shr_s(result, lhs, rhs), - Instr::I64ShrSImm { result, lhs, rhs } => { - self.execute_i64_shr_s_imm(result, lhs, rhs) + Instr::I64ShrSBy { result, lhs, rhs } => { + self.execute_i64_shr_s_by(result, lhs, rhs) } Instr::I64ShrSImm16Lhs { result, lhs, rhs } => { self.execute_i64_shr_s_imm16_lhs(result, lhs, rhs) } Instr::I64Rotl { result, lhs, rhs } => self.execute_i64_rotl(result, lhs, rhs), - Instr::I64RotlImm { result, lhs, rhs } => { - self.execute_i64_rotl_imm(result, lhs, rhs) - } + Instr::I64RotlBy { result, lhs, rhs } => self.execute_i64_rotl_by(result, lhs, rhs), Instr::I64RotlImm16Lhs { result, lhs, rhs } => { self.execute_i64_rotl_imm16_lhs(result, lhs, rhs) } Instr::I64Rotr { result, lhs, rhs } => self.execute_i64_rotr(result, lhs, rhs), - Instr::I64RotrImm { result, lhs, rhs } => { - self.execute_i64_rotr_imm(result, lhs, rhs) - } + Instr::I64RotrBy { result, lhs, rhs } => self.execute_i64_rotr_by(result, lhs, rhs), Instr::I64RotrImm16Lhs { result, lhs, rhs } => { self.execute_i64_rotr_imm16_lhs(result, lhs, rhs) } diff --git a/crates/wasmi/src/engine/executor/instrs/binary.rs b/crates/wasmi/src/engine/executor/instrs/binary.rs index 58e5293065..14db0cfec3 100644 --- a/crates/wasmi/src/engine/executor/instrs/binary.rs +++ b/crates/wasmi/src/engine/executor/instrs/binary.rs @@ -110,17 +110,17 @@ macro_rules! impl_shift_by { } impl Executor<'_> { impl_shift_by! { - (i32, Instruction::I32ShlImm, execute_i32_shl_imm, UntypedVal::i32_shl), - (i32, Instruction::I32ShrUImm, execute_i32_shr_u_imm, UntypedVal::i32_shr_u), - (i32, Instruction::I32ShrSImm, execute_i32_shr_s_imm, UntypedVal::i32_shr_s), - (i32, Instruction::I32RotlImm, execute_i32_rotl_imm, UntypedVal::i32_rotl), - (i32, Instruction::I32RotrImm, execute_i32_rotr_imm, UntypedVal::i32_rotr), - - (i64, Instruction::I64ShlImm, execute_i64_shl_imm, UntypedVal::i64_shl), - (i64, Instruction::I64ShrUImm, execute_i64_shr_u_imm, UntypedVal::i64_shr_u), - (i64, Instruction::I64ShrSImm, execute_i64_shr_s_imm, UntypedVal::i64_shr_s), - (i64, Instruction::I64RotlImm, execute_i64_rotl_imm, UntypedVal::i64_rotl), - (i64, Instruction::I64RotrImm, execute_i64_rotr_imm, UntypedVal::i64_rotr), + (i32, Instruction::I32ShlImm, execute_i32_shl_by, UntypedVal::i32_shl), + (i32, Instruction::I32ShrUImm, execute_i32_shr_u_by, UntypedVal::i32_shr_u), + (i32, Instruction::I32ShrSImm, execute_i32_shr_s_by, UntypedVal::i32_shr_s), + (i32, Instruction::I32RotlImm, execute_i32_rotl_by, UntypedVal::i32_rotl), + (i32, Instruction::I32RotrImm, execute_i32_rotr_by, UntypedVal::i32_rotr), + + (i64, Instruction::I64ShlImm, execute_i64_shl_by, UntypedVal::i64_shl), + (i64, Instruction::I64ShrUImm, execute_i64_shr_u_by, UntypedVal::i64_shr_u), + (i64, Instruction::I64ShrSImm, execute_i64_shr_s_by, UntypedVal::i64_shr_s), + (i64, Instruction::I64RotlImm, execute_i64_rotl_by, UntypedVal::i64_rotl), + (i64, Instruction::I64RotrImm, execute_i64_rotr_by, UntypedVal::i64_rotr), } } diff --git a/crates/wasmi/src/engine/translator/mod.rs b/crates/wasmi/src/engine/translator/mod.rs index 063ed52b40..10d5ddceb9 100644 --- a/crates/wasmi/src/engine/translator/mod.rs +++ b/crates/wasmi/src/engine/translator/mod.rs @@ -1675,7 +1675,7 @@ impl FuncTranslator { fn translate_shift( &mut self, make_instr: fn(result: Reg, lhs: Reg, rhs: Reg) -> Instruction, - make_instr_imm: fn(result: Reg, lhs: Reg, rhs: ShiftAmount) -> Instruction, + make_instr_by: fn(result: Reg, lhs: Reg, rhs: ShiftAmount) -> Instruction, make_instr_imm16_rev: fn(result: Reg, lhs: Const16, rhs: Reg) -> Instruction, consteval: fn(TypedVal, TypedVal) -> TypedVal, make_instr_imm_reg_opt: fn(&mut Self, lhs: T, rhs: Reg) -> Result, @@ -1696,7 +1696,7 @@ impl FuncTranslator { return Ok(()); }; let result = self.alloc.stack.push_dynamic()?; - self.push_fueled_instr(make_instr_imm(result, lhs, rhs), FuelCosts::base)?; + self.push_fueled_instr(make_instr_by(result, lhs, rhs), FuelCosts::base)?; Ok(()) } (TypedProvider::Const(lhs), TypedProvider::Register(rhs)) => { diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotl.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotl.rs index fb2d279119..a74fe406ed 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotl.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotl.rs @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i32_rotl_imm(Reg::from(1), Reg::from(0), shamt(1)), + Instruction::i32_rotl_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotr.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotr.rs index 86a3d25e9b..b272707027 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotr.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotr.rs @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i32_rotr_imm(Reg::from(1), Reg::from(0), shamt(1)), + Instruction::i32_rotr_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_shl.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_shl.rs index 88621be7a7..6ccaf37ed5 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_shl.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_shl.rs @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i32_shl_imm(Reg::from(1), Reg::from(0), shamt(1)), + Instruction::i32_shl_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_s.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_s.rs index 60494dde75..1837b74c01 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_s.rs @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i32_shr_s_imm(Reg::from(1), Reg::from(0), shamt(1)), + Instruction::i32_shr_s_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_u.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_u.rs index 2dc51fbbdd..f17f5056ee 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_u.rs @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i32_shr_u_imm(Reg::from(1), Reg::from(0), shamt(1)), + Instruction::i32_shr_u_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotl.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotl.rs index 1d2340eaec..44f6cbc88c 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotl.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotl.rs @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i64_rotl_imm(Reg::from(1), Reg::from(0), shamt(1)), + Instruction::i64_rotl_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotr.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotr.rs index 2faa473a2b..26a94f3bc9 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotr.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotr.rs @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i64_rotr_imm(Reg::from(1), Reg::from(0), shamt(1)), + Instruction::i64_rotr_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_shl.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_shl.rs index d92b913590..2409ab7a30 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_shl.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_shl.rs @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i64_shl_imm(Reg::from(1), Reg::from(0), shamt(1)), + Instruction::i64_shl_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_s.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_s.rs index a9679a8888..2f99a91205 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_s.rs @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i64_shr_s_imm(Reg::from(1), Reg::from(0), shamt(1)), + Instruction::i64_shr_s_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_u.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_u.rs index eecbb52bb6..abd757e289 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_u.rs @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i64_shr_u_imm(Reg::from(1), Reg::from(0), shamt(1)), + Instruction::i64_shr_u_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); diff --git a/crates/wasmi/src/engine/translator/visit.rs b/crates/wasmi/src/engine/translator/visit.rs index 7c46786fbc..791d475b5e 100644 --- a/crates/wasmi/src/engine/translator/visit.rs +++ b/crates/wasmi/src/engine/translator/visit.rs @@ -2273,7 +2273,7 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i32_shl(&mut self) -> Self::Output { self.translate_shift::( Instruction::i32_shl, - Instruction::i32_shl_imm, + Instruction::i32_shl_by, Instruction::i32_shl_imm16_lhs, TypedVal::i32_shl, Self::no_custom_opt, @@ -2283,7 +2283,7 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i32_shr_s(&mut self) -> Self::Output { self.translate_shift( Instruction::i32_shr_s, - Instruction::i32_shr_s_imm, + Instruction::i32_shr_s_by, Instruction::i32_shr_s_imm16_lhs, TypedVal::i32_shr_s, |this, lhs: i32, _rhs: Reg| { @@ -2300,7 +2300,7 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i32_shr_u(&mut self) -> Self::Output { self.translate_shift::( Instruction::i32_shr_u, - Instruction::i32_shr_u_imm, + Instruction::i32_shr_u_by, Instruction::i32_shr_u_imm16_lhs, TypedVal::i32_shr_u, Self::no_custom_opt, @@ -2310,7 +2310,7 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i32_rotl(&mut self) -> Self::Output { self.translate_shift( Instruction::i32_rotl, - Instruction::i32_rotl_imm, + Instruction::i32_rotl_by, Instruction::i32_rotl_imm16_lhs, TypedVal::i32_rotl, |this, lhs: i32, _rhs: Reg| { @@ -2327,7 +2327,7 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i32_rotr(&mut self) -> Self::Output { self.translate_shift( Instruction::i32_rotr, - Instruction::i32_rotr_imm, + Instruction::i32_rotr_by, Instruction::i32_rotr_imm16_lhs, TypedVal::i32_rotr, |this, lhs: i32, _rhs: Reg| { @@ -2590,7 +2590,7 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i64_shl(&mut self) -> Self::Output { self.translate_shift::( Instruction::i64_shl, - Instruction::i64_shl_imm, + Instruction::i64_shl_by, Instruction::i64_shl_imm16_lhs, TypedVal::i64_shl, Self::no_custom_opt, @@ -2600,7 +2600,7 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i64_shr_s(&mut self) -> Self::Output { self.translate_shift( Instruction::i64_shr_s, - Instruction::i64_shr_s_imm, + Instruction::i64_shr_s_by, Instruction::i64_shr_s_imm16_lhs, TypedVal::i64_shr_s, |this, lhs: i64, _rhs: Reg| { @@ -2617,7 +2617,7 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i64_shr_u(&mut self) -> Self::Output { self.translate_shift::( Instruction::i64_shr_u, - Instruction::i64_shr_u_imm, + Instruction::i64_shr_u_by, Instruction::i64_shr_u_imm16_lhs, TypedVal::i64_shr_u, Self::no_custom_opt, @@ -2627,7 +2627,7 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i64_rotl(&mut self) -> Self::Output { self.translate_shift( Instruction::i64_rotl, - Instruction::i64_rotl_imm, + Instruction::i64_rotl_by, Instruction::i64_rotl_imm16_lhs, TypedVal::i64_rotl, |this, lhs: i64, _rhs: Reg| { @@ -2644,7 +2644,7 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i64_rotr(&mut self) -> Self::Output { self.translate_shift( Instruction::i64_rotr, - Instruction::i64_rotr_imm, + Instruction::i64_rotr_by, Instruction::i64_rotr_imm16_lhs, TypedVal::i64_rotr, |this, lhs: i64, _rhs: Reg| {