From c66704bbd9af2906b7c1773a14122a5265f70f0f Mon Sep 17 00:00:00 2001 From: Robin Freyler Date: Fri, 4 Oct 2024 13:45:53 +0200 Subject: [PATCH] Rename instructions with immediate values + add `ShiftAmount` (#1221) * rename *Rev instruction immediate variants to *Lhs We will begin to rename immediate variants of binary instructions to tell if `lhs` or `rhs` operand is the immediate by appending either `Rhs` or `Lhs`. * rename binary div,rem instructions with `rhs` immediates The new names are now mirroring their `lhs` immediate counterparts and make it more clear where the immediate is positioned. * add [Into]ShiftAmount definitions to wasmi_ir * use ShiftAmount in shift and rotate instructions * rename instructions with immediate ShiftAmount * remove unnecessary Lhs (_lhs) affix from shift and rotate instrs * fix intra doc links --- crates/ir/src/for_each_op.rs | 172 ++++++++--------- crates/ir/src/lib.rs | 11 +- crates/ir/src/primitive.rs | 50 ++++- crates/ir/src/visit_regs.rs | 1 + crates/wasmi/src/engine/executor/instrs.rs | 175 ++++++++++-------- .../src/engine/executor/instrs/binary.rs | 123 ++++++------ crates/wasmi/src/engine/translator/mod.rs | 20 +- .../wasmi/src/engine/translator/tests/mod.rs | 15 +- .../translator/tests/op/binary/f32_add.rs | 8 +- .../tests/op/binary/f32_copysign.rs | 4 +- .../translator/tests/op/binary/f32_div.rs | 6 +- .../translator/tests/op/binary/f32_max.rs | 10 +- .../translator/tests/op/binary/f32_min.rs | 10 +- .../translator/tests/op/binary/f32_mul.rs | 6 +- .../translator/tests/op/binary/f32_sub.rs | 6 +- .../translator/tests/op/binary/f64_add.rs | 6 +- .../tests/op/binary/f64_copysign.rs | 4 +- .../translator/tests/op/binary/f64_div.rs | 4 +- .../translator/tests/op/binary/f64_max.rs | 8 +- .../translator/tests/op/binary/f64_min.rs | 8 +- .../translator/tests/op/binary/f64_mul.rs | 4 +- .../translator/tests/op/binary/f64_sub.rs | 4 +- .../translator/tests/op/binary/i32_add.rs | 14 +- .../translator/tests/op/binary/i32_and.rs | 18 +- .../translator/tests/op/binary/i32_div_s.rs | 16 +- .../translator/tests/op/binary/i32_div_u.rs | 16 +- .../translator/tests/op/binary/i32_mul.rs | 18 +- .../translator/tests/op/binary/i32_or.rs | 18 +- .../translator/tests/op/binary/i32_rem_s.rs | 14 +- .../translator/tests/op/binary/i32_rem_u.rs | 14 +- .../translator/tests/op/binary/i32_rotl.rs | 14 +- .../translator/tests/op/binary/i32_rotr.rs | 14 +- .../translator/tests/op/binary/i32_shl.rs | 12 +- .../translator/tests/op/binary/i32_shr_s.rs | 14 +- .../translator/tests/op/binary/i32_shr_u.rs | 12 +- .../translator/tests/op/binary/i32_sub.rs | 8 +- .../translator/tests/op/binary/i32_xor.rs | 14 +- .../translator/tests/op/binary/i64_add.rs | 14 +- .../translator/tests/op/binary/i64_and.rs | 18 +- .../translator/tests/op/binary/i64_div_s.rs | 14 +- .../translator/tests/op/binary/i64_div_u.rs | 14 +- .../translator/tests/op/binary/i64_mul.rs | 18 +- .../translator/tests/op/binary/i64_or.rs | 18 +- .../translator/tests/op/binary/i64_rem_s.rs | 14 +- .../translator/tests/op/binary/i64_rem_u.rs | 14 +- .../translator/tests/op/binary/i64_rotl.rs | 14 +- .../translator/tests/op/binary/i64_rotr.rs | 14 +- .../translator/tests/op/binary/i64_shl.rs | 12 +- .../translator/tests/op/binary/i64_shr_s.rs | 14 +- .../translator/tests/op/binary/i64_shr_u.rs | 12 +- .../translator/tests/op/binary/i64_sub.rs | 8 +- .../translator/tests/op/binary/i64_xor.rs | 14 +- .../engine/translator/tests/op/binary/mod.rs | 9 + .../src/engine/translator/tests/op/br_if.rs | 2 +- .../engine/translator/tests/op/br_table.rs | 4 +- .../translator/tests/op/call/imported.rs | 10 +- .../translator/tests/op/call/indirect.rs | 6 +- .../translator/tests/op/call/internal.rs | 10 +- .../engine/translator/tests/op/cmp/f32_eq.rs | 6 +- .../engine/translator/tests/op/cmp/f32_ge.rs | 6 +- .../engine/translator/tests/op/cmp/f32_gt.rs | 8 +- .../engine/translator/tests/op/cmp/f32_le.rs | 6 +- .../engine/translator/tests/op/cmp/f32_lt.rs | 8 +- .../engine/translator/tests/op/cmp/f32_ne.rs | 6 +- .../engine/translator/tests/op/cmp/f64_eq.rs | 6 +- .../engine/translator/tests/op/cmp/f64_ge.rs | 6 +- .../engine/translator/tests/op/cmp/f64_gt.rs | 8 +- .../engine/translator/tests/op/cmp/f64_le.rs | 6 +- .../engine/translator/tests/op/cmp/f64_lt.rs | 8 +- .../engine/translator/tests/op/cmp/f64_ne.rs | 6 +- .../engine/translator/tests/op/cmp/i32_eq.rs | 10 +- .../translator/tests/op/cmp/i32_ge_s.rs | 12 +- .../translator/tests/op/cmp/i32_ge_u.rs | 12 +- .../translator/tests/op/cmp/i32_gt_s.rs | 12 +- .../translator/tests/op/cmp/i32_gt_u.rs | 12 +- .../translator/tests/op/cmp/i32_le_s.rs | 12 +- .../translator/tests/op/cmp/i32_le_u.rs | 12 +- .../translator/tests/op/cmp/i32_lt_s.rs | 12 +- .../translator/tests/op/cmp/i32_lt_u.rs | 12 +- .../engine/translator/tests/op/cmp/i32_ne.rs | 10 +- .../engine/translator/tests/op/cmp/i64_eq.rs | 10 +- .../translator/tests/op/cmp/i64_ge_s.rs | 12 +- .../translator/tests/op/cmp/i64_ge_u.rs | 12 +- .../translator/tests/op/cmp/i64_gt_s.rs | 12 +- .../translator/tests/op/cmp/i64_gt_u.rs | 12 +- .../translator/tests/op/cmp/i64_le_s.rs | 12 +- .../translator/tests/op/cmp/i64_le_u.rs | 12 +- .../translator/tests/op/cmp/i64_lt_s.rs | 12 +- .../translator/tests/op/cmp/i64_lt_u.rs | 12 +- .../engine/translator/tests/op/cmp/i64_ne.rs | 10 +- .../engine/translator/tests/op/local_set.rs | 4 +- .../src/engine/translator/tests/op/mod.rs | 10 +- .../tests/op/return_call/imported.rs | 10 +- .../tests/op/return_call/indirect.rs | 6 +- .../tests/op/return_call/internal.rs | 10 +- crates/wasmi/src/engine/translator/utils.rs | 27 --- crates/wasmi/src/engine/translator/visit.rs | 76 ++++---- 97 files changed, 837 insertions(+), 742 deletions(-) diff --git a/crates/ir/src/for_each_op.rs b/crates/ir/src/for_each_op.rs index fc9aae4af1..f4453aefa5 100644 --- a/crates/ir/src/for_each_op.rs +++ b/crates/ir/src/for_each_op.rs @@ -3694,8 +3694,8 @@ macro_rules! for_each_op { /// /// - Optimized variant of [`Instruction::I32Sub`] for 16-bit constant values. /// - Required instruction since subtraction is not commutative. - #[snake_name(i32_sub_imm16_rev)] - I32SubImm16Rev { + #[snake_name(i32_sub_imm16_lhs)] + I32SubImm16Lhs { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -3741,8 +3741,8 @@ macro_rules! for_each_op { /// /// - Optimized variant of [`Instruction::I32DivS`] for 16-bit constant values. /// - Guarantees that the right-hand side operand is not zero. - #[snake_name(i32_div_s_imm16)] - I32DivSImm16 { + #[snake_name(i32_div_s_imm16_rhs)] + I32DivSImm16Rhs { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -3756,8 +3756,8 @@ macro_rules! for_each_op { /// - Optimized variant of [`Instruction::I32DivU`] for 16-bit constant values. /// - Guarantees that the right-hand side operand is not zero. /// - Required instruction since signed-division is not commutative. - #[snake_name(i32_div_s_imm16_rev)] - I32DivSImm16Rev { + #[snake_name(i32_div_s_imm16_lhs)] + I32DivSImm16Lhs { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -3783,8 +3783,8 @@ macro_rules! for_each_op { /// # Encoding /// /// Optimized variant of [`Instruction::I32DivU`] for 16-bit constant values. - #[snake_name(i32_div_u_imm16)] - I32DivUImm16 { + #[snake_name(i32_div_u_imm16_rhs)] + I32DivUImm16Rhs { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -3798,8 +3798,8 @@ macro_rules! for_each_op { /// - Optimized variant of [`Instruction::I32DivU`] for 16-bit constant values. /// - Guarantees that the right-hand side operand is not zero. /// - Required instruction since `i32` unsigned-division is not commutative. - #[snake_name(i32_div_u_imm16_rev)] - I32DivUImm16Rev { + #[snake_name(i32_div_u_imm16_lhs)] + I32DivUImm16Lhs { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -3822,8 +3822,8 @@ macro_rules! for_each_op { /// /// - Optimized variant of [`Instruction::I32RemS`] for 16-bit constant values. /// - Guarantees that the right-hand side operand is not zero. - #[snake_name(i32_rem_s_imm16)] - I32RemSImm16 { + #[snake_name(i32_rem_s_imm16_rhs)] + I32RemSImm16Rhs { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -3837,8 +3837,8 @@ macro_rules! for_each_op { /// - Optimized variant of [`Instruction::I32RemS`] for 16-bit constant values. /// - Guarantees that the right-hand side operand is not zero. /// - Required instruction since `i32` signed-remainder is not commutative. - #[snake_name(i32_rem_s_imm16_rev)] - I32RemSImm16Rev { + #[snake_name(i32_rem_s_imm16_lhs)] + I32RemSImm16Lhs { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -3861,8 +3861,8 @@ macro_rules! for_each_op { /// /// - Optimized variant of [`Instruction::I32RemU`] for 16-bit constant values. /// - Guarantees that the right-hand side operand is not zero. - #[snake_name(i32_rem_u_imm16)] - I32RemUImm16 { + #[snake_name(i32_rem_u_imm16_rhs)] + I32RemUImm16Rhs { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -3876,8 +3876,8 @@ macro_rules! for_each_op { /// - Optimized variant of [`Instruction::I32RemU`] for 16-bit constant values. /// - Guarantees that the right-hand side operand is not zero. /// - Required instruction since unsigned-remainder is not commutative. - #[snake_name(i32_rem_u_imm16_rev)] - I32RemUImm16Rev { + #[snake_name(i32_rem_u_imm16_lhs)] + I32RemUImm16Lhs { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4018,17 +4018,17 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i32.shl` equivalent Wasmi instruction with 16-bit immediate `rhs` operand. - #[snake_name(i32_shl_imm)] - I32ShlImm { + #[snake_name(i32_shl_by)] + I32ShlBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, /// The 16-bit immediate value. - rhs: Const16, + rhs: ShiftAmount, }, /// A Wasm `i32.shl` equivalent Wasmi instruction with 16-bit immediate `lhs` operand. - #[snake_name(i32_shl_imm16_rev)] - I32ShlImm16Rev { + #[snake_name(i32_shl_imm16)] + I32ShlImm16 { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4046,17 +4046,17 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i32.shr_u` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i32_shr_u_imm)] - I32ShrUImm { + #[snake_name(i32_shr_u_by)] + I32ShrUBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, /// The 16-bit immediate value. - rhs: Const16, + rhs: ShiftAmount, }, /// A Wasm `i32.shr_u` equivalent Wasmi instruction with 16-bit immediate `lhs` value. - #[snake_name(i32_shr_u_imm16_rev)] - I32ShrUImm16Rev { + #[snake_name(i32_shr_u_imm16)] + I32ShrUImm16 { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4074,17 +4074,17 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i32.shr_s` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i32_shr_s_imm)] - I32ShrSImm { + #[snake_name(i32_shr_s_by)] + I32ShrSBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, /// The 16-bit immediate value. - rhs: Const16, + rhs: ShiftAmount, }, /// A Wasm `i32.shr_s` equivalent Wasmi instruction with 16-bit immediate `lhs` value. - #[snake_name(i32_shr_s_imm16_rev)] - I32ShrSImm16Rev { + #[snake_name(i32_shr_s_imm16)] + I32ShrSImm16 { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4102,17 +4102,17 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i32.rotl` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i32_rotl_imm)] - I32RotlImm { + #[snake_name(i32_rotl_by)] + I32RotlBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, /// The 16-bit immediate value. - rhs: Const16, + rhs: ShiftAmount, }, /// A Wasm `i32.rotl` equivalent Wasmi instruction with 16-bit immediate `lhs` value. - #[snake_name(i32_rotl_imm16_rev)] - I32RotlImm16Rev { + #[snake_name(i32_rotl_imm16)] + I32RotlImm16 { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4130,17 +4130,17 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i32.rotr` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i32_rotr_imm)] - I32RotrImm { + #[snake_name(i32_rotr_by)] + I32RotrBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, /// The 16-bit immediate value. - rhs: Const16, + rhs: ShiftAmount, }, /// A Wasm `i32.rotr` equivalent Wasmi instruction with 16-bit immediate `lhs` value. - #[snake_name(i32_rotr_imm16_rev)] - I32RotrImm16Rev { + #[snake_name(i32_rotr_imm16)] + I32RotrImm16 { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4208,8 +4208,8 @@ macro_rules! for_each_op { /// /// - Optimized variant of [`Instruction::I64Sub`] for 16-bit constant values. /// - Required instruction since subtraction is not commutative. - #[snake_name(i64_sub_imm16_rev)] - I64SubImm16Rev { + #[snake_name(i64_sub_imm16_lhs)] + I64SubImm16Lhs { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4255,8 +4255,8 @@ macro_rules! for_each_op { /// /// - Optimized variant of [`Instruction::I64DivS`] for 16-bit constant values. /// - Guarantees that the right-hand side operand is not zero. - #[snake_name(i64_div_s_imm16)] - I64DivSImm16 { + #[snake_name(i64_div_s_imm16_rhs)] + I64DivSImm16Rhs { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -4270,8 +4270,8 @@ macro_rules! for_each_op { /// - Guarantees that the right-hand side operand is not zero. /// - Required instruction since signed-division is not commutative. /// - Optimized variant of [`Instruction::I64DivU`] for 16-bit constant values. - #[snake_name(i64_div_s_imm16_rev)] - I64DivSImm16Rev { + #[snake_name(i64_div_s_imm16_lhs)] + I64DivSImm16Lhs { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4297,8 +4297,8 @@ macro_rules! for_each_op { /// # Encoding /// /// Optimized variant of [`Instruction::I64DivU`] for 16-bit constant values. - #[snake_name(i64_div_u_imm16)] - I64DivUImm16 { + #[snake_name(i64_div_u_imm16_rhs)] + I64DivUImm16Rhs { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -4312,8 +4312,8 @@ macro_rules! for_each_op { /// - Optimized variant of [`Instruction::I64DivU`] for 16-bit constant values. /// - Guarantees that the right-hand side operand is not zero. /// - Required instruction since unsigned-division is not commutative. - #[snake_name(i64_div_u_imm16_rev)] - I64DivUImm16Rev { + #[snake_name(i64_div_u_imm16_lhs)] + I64DivUImm16Lhs { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4336,8 +4336,8 @@ macro_rules! for_each_op { /// /// - Optimized variant of [`Instruction::I64RemS`] for 16-bit constant values. /// - Guarantees that the right-hand side operand is not zero. - #[snake_name(i64_rem_s_imm16)] - I64RemSImm16 { + #[snake_name(i64_rem_s_imm16_rhs)] + I64RemSImm16Rhs { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -4351,8 +4351,8 @@ macro_rules! for_each_op { /// - Optimized variant of [`Instruction::I64RemS`] for 16-bit constant values. /// - Guarantees that the right-hand side operand is not zero. /// - Required instruction since signed-remainder is not commutative. - #[snake_name(i64_rem_s_imm16_rev)] - I64RemSImm16Rev { + #[snake_name(i64_rem_s_imm16_lhs)] + I64RemSImm16Lhs { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4375,8 +4375,8 @@ macro_rules! for_each_op { /// /// - Optimized variant of [`Instruction::I64RemU`] for 16-bit constant values. /// - Guarantees that the right-hand side operand is not zero. - #[snake_name(i64_rem_u_imm16)] - I64RemUImm16 { + #[snake_name(i64_rem_u_imm16_rhs)] + I64RemUImm16Rhs { @result: Reg, /// The register holding one of the operands. lhs: Reg, @@ -4390,8 +4390,8 @@ macro_rules! for_each_op { /// - Optimized variant of [`Instruction::I64RemU`] for 16-bit constant values. /// - Guarantees that the right-hand side operand is not zero. /// - Required instruction since unsigned-remainder is not commutative. - #[snake_name(i64_rem_u_imm16_rev)] - I64RemUImm16Rev { + #[snake_name(i64_rem_u_imm16_lhs)] + I64RemUImm16Lhs { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4478,17 +4478,17 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i64.shl` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i64_shl_imm)] - I64ShlImm { + #[snake_name(i64_shl_by)] + I64ShlBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, /// The 16-bit immediate value. - rhs: Const16, + rhs: ShiftAmount, }, /// A Wasm `i64.shl` equivalent Wasmi instruction with 16-bit immediate `lhs` value. - #[snake_name(i64_shl_imm16_rev)] - I64ShlImm16Rev { + #[snake_name(i64_shl_imm16)] + I64ShlImm16 { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4506,17 +4506,17 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i64.shr_u` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i64_shr_u_imm)] - I64ShrUImm { + #[snake_name(i64_shr_u_by)] + I64ShrUBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, /// The 16-bit immediate value. - rhs: Const16, + rhs: ShiftAmount, }, /// A Wasm `i64.shr_u` equivalent Wasmi instruction with 16-bit immediate `lhs` value. - #[snake_name(i64_shr_u_imm16_rev)] - I64ShrUImm16Rev { + #[snake_name(i64_shr_u_imm16)] + I64ShrUImm16 { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4534,17 +4534,17 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i64.shr_s` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i64_shr_s_imm)] - I64ShrSImm { + #[snake_name(i64_shr_s_by)] + I64ShrSBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, /// The 16-bit immediate value. - rhs: Const16, + rhs: ShiftAmount, }, /// A Wasm `i64.shr_s` equivalent Wasmi instruction with 16-bit immediate `lhs` value. - #[snake_name(i64_shr_s_imm16_rev)] - I64ShrSImm16Rev { + #[snake_name(i64_shr_s_imm16)] + I64ShrSImm16 { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4562,17 +4562,17 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i64.rotl` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i64_rotl_imm)] - I64RotlImm { + #[snake_name(i64_rotl_by)] + I64RotlBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, /// The 16-bit immediate value. - rhs: Const16, + rhs: ShiftAmount, }, /// A Wasm `i64.rotl` equivalent Wasmi instruction with 16-bit immediate `lhs` value. - #[snake_name(i64_rotl_imm16_rev)] - I64RotlImm16Rev { + #[snake_name(i64_rotl_imm16)] + I64RotlImm16 { @result: Reg, /// The 16-bit immediate value. lhs: Const16, @@ -4590,17 +4590,17 @@ macro_rules! for_each_op { rhs: Reg, }, /// A Wasm `i64.rotr` equivalent Wasmi instruction with 16-bit immediate `rhs` value. - #[snake_name(i64_rotr_imm)] - I64RotrImm { + #[snake_name(i64_rotr_by)] + I64RotrBy { @result: Reg, /// The register holding one of the operands. lhs: Reg, /// The 16-bit immediate value. - rhs: Const16, + rhs: ShiftAmount, }, /// A Wasm `i64.rotr` equivalent Wasmi instruction with 16-bit immediate `lhs` value. - #[snake_name(i64_rotr_imm16_rev)] - I64RotrImm16Rev { + #[snake_name(i64_rotr_imm16)] + I64RotrImm16 { @result: Reg, /// The 16-bit immediate value. lhs: Const16, diff --git a/crates/ir/src/lib.rs b/crates/ir/src/lib.rs index 8ee9526986..9a553599da 100644 --- a/crates/ir/src/lib.rs +++ b/crates/ir/src/lib.rs @@ -27,7 +27,16 @@ pub use self::{ immeditate::{AnyConst16, AnyConst32, Const16, Const32}, index::Instr, index::Reg, - primitive::{BlockFuel, BranchOffset, BranchOffset16, Comparator, ComparatorAndOffset, Sign}, + primitive::{ + BlockFuel, + BranchOffset, + BranchOffset16, + Comparator, + ComparatorAndOffset, + IntoShiftAmount, + ShiftAmount, + Sign, + }, r#enum::Instruction, sequence::{InstrIter, InstrIterMut, InstrSequence}, span::{BoundedRegSpan, FixedRegSpan, RegSpan, RegSpanIter}, diff --git a/crates/ir/src/primitive.rs b/crates/ir/src/primitive.rs index ffaa29e407..1972ea5a05 100644 --- a/crates/ir/src/primitive.rs +++ b/crates/ir/src/primitive.rs @@ -1,4 +1,4 @@ -use crate::{core::UntypedVal, Error, Instr}; +use crate::{core::UntypedVal, Const16, Error, Instr}; use core::marker::PhantomData; /// The sign of a value. @@ -366,3 +366,51 @@ impl From for UntypedVal { Self::from(params.as_u64()) } } + +/// A typed shift amount for shift and rotate instructions. +#[derive(Debug, Copy, Clone, PartialEq, Eq)] +pub struct ShiftAmount { + /// The underlying wrapped shift amount. + value: Const16, +} + +/// Integer ypes that can be used as shift amount in shift or rotate instructions. +pub trait IntoShiftAmount: Sized { + /// Converts `self` into a [`ShiftAmount`] if possible. + fn into_shift_amount(self) -> Option>; +} + +macro_rules! impl_shift_amount { + ( $( ($ty:ty, $bits:literal) ),* $(,)? ) => { + $( + impl IntoShiftAmount for $ty { + fn into_shift_amount(self) -> Option> { + >::new(self) + } + } + + impl ShiftAmount<$ty> { + /// Creates a new [`ShiftAmount`] for the given `value`. + /// + /// Returns `None` if `value` causes a no-op shift. + pub fn new(value: $ty) -> Option { + let value = (value % $bits) as i16; + if value == 0 { + return None + } + Some(Self { value: Const16::from(value) }) + } + } + + impl From> for $ty { + fn from(shamt: ShiftAmount<$ty>) -> Self { + shamt.value.into() + } + } + )* + }; +} +impl_shift_amount! { + (i32, 32), + (i64, 64), +} diff --git a/crates/ir/src/visit_regs.rs b/crates/ir/src/visit_regs.rs index 8e67f23e9e..8f39cef5a4 100644 --- a/crates/ir/src/visit_regs.rs +++ b/crates/ir/src/visit_regs.rs @@ -91,6 +91,7 @@ impl_host_visitor_for!( Const16, Const32, Sign, + ShiftAmount, ); /// Type-wrapper to signal that the wrapped [`Reg`], [`RegSpan`] (etc.) is a result. diff --git a/crates/wasmi/src/engine/executor/instrs.rs b/crates/wasmi/src/engine/executor/instrs.rs index 84976a19dd..58e9cf523e 100644 --- a/crates/wasmi/src/engine/executor/instrs.rs +++ b/crates/wasmi/src/engine/executor/instrs.rs @@ -11,6 +11,7 @@ use crate::{ DedupFuncType, EngineFunc, }, + ir::ShiftAmount, memory::DataSegment, store::StoreInner, table::ElementSegment, @@ -907,40 +908,40 @@ impl<'engine> Executor<'engine> { self.execute_i32_add_imm16(result, lhs, rhs) } Instr::I32Sub { result, lhs, rhs } => self.execute_i32_sub(result, lhs, rhs), - Instr::I32SubImm16Rev { result, lhs, rhs } => { - self.execute_i32_sub_imm16_rev(result, lhs, rhs) + Instr::I32SubImm16Lhs { result, lhs, rhs } => { + self.execute_i32_sub_imm16_lhs(result, lhs, rhs) } Instr::I32Mul { result, lhs, rhs } => self.execute_i32_mul(result, lhs, rhs), Instr::I32MulImm16 { result, lhs, rhs } => { self.execute_i32_mul_imm16(result, lhs, rhs) } Instr::I32DivS { result, lhs, rhs } => self.execute_i32_div_s(result, lhs, rhs)?, - Instr::I32DivSImm16 { result, lhs, rhs } => { - self.execute_i32_div_s_imm16(result, lhs, rhs)? + Instr::I32DivSImm16Rhs { result, lhs, rhs } => { + self.execute_i32_div_s_imm16_rhs(result, lhs, rhs)? } - Instr::I32DivSImm16Rev { result, lhs, rhs } => { - self.execute_i32_div_s_imm16_rev(result, lhs, rhs)? + Instr::I32DivSImm16Lhs { result, lhs, rhs } => { + self.execute_i32_div_s_imm16_lhs(result, lhs, rhs)? } Instr::I32DivU { result, lhs, rhs } => self.execute_i32_div_u(result, lhs, rhs)?, - Instr::I32DivUImm16 { result, lhs, rhs } => { - self.execute_i32_div_u_imm16(result, lhs, rhs) + Instr::I32DivUImm16Rhs { result, lhs, rhs } => { + self.execute_i32_div_u_imm16_rhs(result, lhs, rhs) } - Instr::I32DivUImm16Rev { result, lhs, rhs } => { - self.execute_i32_div_u_imm16_rev(result, lhs, rhs)? + Instr::I32DivUImm16Lhs { result, lhs, rhs } => { + self.execute_i32_div_u_imm16_lhs(result, lhs, rhs)? } Instr::I32RemS { result, lhs, rhs } => self.execute_i32_rem_s(result, lhs, rhs)?, - Instr::I32RemSImm16 { result, lhs, rhs } => { - self.execute_i32_rem_s_imm16(result, lhs, rhs)? + Instr::I32RemSImm16Rhs { result, lhs, rhs } => { + self.execute_i32_rem_s_imm16_rhs(result, lhs, rhs)? } - Instr::I32RemSImm16Rev { result, lhs, rhs } => { - self.execute_i32_rem_s_imm16_rev(result, lhs, rhs)? + Instr::I32RemSImm16Lhs { result, lhs, rhs } => { + self.execute_i32_rem_s_imm16_lhs(result, lhs, rhs)? } Instr::I32RemU { result, lhs, rhs } => self.execute_i32_rem_u(result, lhs, rhs)?, - Instr::I32RemUImm16 { result, lhs, rhs } => { - self.execute_i32_rem_u_imm16(result, lhs, rhs) + Instr::I32RemUImm16Rhs { result, lhs, rhs } => { + self.execute_i32_rem_u_imm16_rhs(result, lhs, rhs) } - Instr::I32RemUImm16Rev { result, lhs, rhs } => { - self.execute_i32_rem_u_imm16_rev(result, lhs, rhs)? + Instr::I32RemUImm16Lhs { result, lhs, rhs } => { + self.execute_i32_rem_u_imm16_lhs(result, lhs, rhs)? } Instr::I32And { result, lhs, rhs } => self.execute_i32_and(result, lhs, rhs), Instr::I32AndEqz { result, lhs, rhs } => self.execute_i32_and_eqz(result, lhs, rhs), @@ -967,37 +968,33 @@ impl<'engine> Executor<'engine> { self.execute_i32_xor_imm16(result, lhs, rhs) } Instr::I32Shl { result, lhs, rhs } => self.execute_i32_shl(result, lhs, rhs), - Instr::I32ShlImm { result, lhs, rhs } => self.execute_i32_shl_imm(result, lhs, rhs), - Instr::I32ShlImm16Rev { result, lhs, rhs } => { - self.execute_i32_shl_imm16_rev(result, lhs, rhs) + Instr::I32ShlBy { result, lhs, rhs } => self.execute_i32_shl_by(result, lhs, rhs), + Instr::I32ShlImm16 { result, lhs, rhs } => { + self.execute_i32_shl_imm16(result, lhs, rhs) } Instr::I32ShrU { result, lhs, rhs } => self.execute_i32_shr_u(result, lhs, rhs), - Instr::I32ShrUImm { result, lhs, rhs } => { - self.execute_i32_shr_u_imm(result, lhs, rhs) + Instr::I32ShrUBy { result, lhs, rhs } => { + self.execute_i32_shr_u_by(result, lhs, rhs) } - Instr::I32ShrUImm16Rev { result, lhs, rhs } => { - self.execute_i32_shr_u_imm16_rev(result, lhs, rhs) + Instr::I32ShrUImm16 { result, lhs, rhs } => { + self.execute_i32_shr_u_imm16(result, lhs, rhs) } Instr::I32ShrS { result, lhs, rhs } => self.execute_i32_shr_s(result, lhs, rhs), - Instr::I32ShrSImm { result, lhs, rhs } => { - self.execute_i32_shr_s_imm(result, lhs, rhs) + Instr::I32ShrSBy { result, lhs, rhs } => { + self.execute_i32_shr_s_by(result, lhs, rhs) } - Instr::I32ShrSImm16Rev { result, lhs, rhs } => { - self.execute_i32_shr_s_imm16_rev(result, lhs, rhs) + Instr::I32ShrSImm16 { result, lhs, rhs } => { + self.execute_i32_shr_s_imm16(result, lhs, rhs) } Instr::I32Rotl { result, lhs, rhs } => self.execute_i32_rotl(result, lhs, rhs), - Instr::I32RotlImm { result, lhs, rhs } => { - self.execute_i32_rotl_imm(result, lhs, rhs) - } - Instr::I32RotlImm16Rev { result, lhs, rhs } => { - self.execute_i32_rotl_imm16_rev(result, lhs, rhs) + Instr::I32RotlBy { result, lhs, rhs } => self.execute_i32_rotl_by(result, lhs, rhs), + Instr::I32RotlImm16 { result, lhs, rhs } => { + self.execute_i32_rotl_imm16(result, lhs, rhs) } Instr::I32Rotr { result, lhs, rhs } => self.execute_i32_rotr(result, lhs, rhs), - Instr::I32RotrImm { result, lhs, rhs } => { - self.execute_i32_rotr_imm(result, lhs, rhs) - } - Instr::I32RotrImm16Rev { result, lhs, rhs } => { - self.execute_i32_rotr_imm16_rev(result, lhs, rhs) + Instr::I32RotrBy { result, lhs, rhs } => self.execute_i32_rotr_by(result, lhs, rhs), + Instr::I32RotrImm16 { result, lhs, rhs } => { + self.execute_i32_rotr_imm16(result, lhs, rhs) } Instr::I64Clz { result, input } => self.execute_i64_clz(result, input), Instr::I64Ctz { result, input } => self.execute_i64_ctz(result, input), @@ -1007,40 +1004,40 @@ impl<'engine> Executor<'engine> { self.execute_i64_add_imm16(result, lhs, rhs) } Instr::I64Sub { result, lhs, rhs } => self.execute_i64_sub(result, lhs, rhs), - Instr::I64SubImm16Rev { result, lhs, rhs } => { - self.execute_i64_sub_imm16_rev(result, lhs, rhs) + Instr::I64SubImm16Lhs { result, lhs, rhs } => { + self.execute_i64_sub_imm16_lhs(result, lhs, rhs) } Instr::I64Mul { result, lhs, rhs } => self.execute_i64_mul(result, lhs, rhs), Instr::I64MulImm16 { result, lhs, rhs } => { self.execute_i64_mul_imm16(result, lhs, rhs) } Instr::I64DivS { result, lhs, rhs } => self.execute_i64_div_s(result, lhs, rhs)?, - Instr::I64DivSImm16 { result, lhs, rhs } => { - self.execute_i64_div_s_imm16(result, lhs, rhs)? + Instr::I64DivSImm16Rhs { result, lhs, rhs } => { + self.execute_i64_div_s_imm16_rhs(result, lhs, rhs)? } - Instr::I64DivSImm16Rev { result, lhs, rhs } => { - self.execute_i64_div_s_imm16_rev(result, lhs, rhs)? + Instr::I64DivSImm16Lhs { result, lhs, rhs } => { + self.execute_i64_div_s_imm16_lhs(result, lhs, rhs)? } Instr::I64DivU { result, lhs, rhs } => self.execute_i64_div_u(result, lhs, rhs)?, - Instr::I64DivUImm16 { result, lhs, rhs } => { - self.execute_i64_div_u_imm16(result, lhs, rhs) + Instr::I64DivUImm16Rhs { result, lhs, rhs } => { + self.execute_i64_div_u_imm16_rhs(result, lhs, rhs) } - Instr::I64DivUImm16Rev { result, lhs, rhs } => { - self.execute_i64_div_u_imm16_rev(result, lhs, rhs)? + Instr::I64DivUImm16Lhs { result, lhs, rhs } => { + self.execute_i64_div_u_imm16_lhs(result, lhs, rhs)? } Instr::I64RemS { result, lhs, rhs } => self.execute_i64_rem_s(result, lhs, rhs)?, - Instr::I64RemSImm16 { result, lhs, rhs } => { - self.execute_i64_rem_s_imm16(result, lhs, rhs)? + Instr::I64RemSImm16Rhs { result, lhs, rhs } => { + self.execute_i64_rem_s_imm16_rhs(result, lhs, rhs)? } - Instr::I64RemSImm16Rev { result, lhs, rhs } => { - self.execute_i64_rem_s_imm16_rev(result, lhs, rhs)? + Instr::I64RemSImm16Lhs { result, lhs, rhs } => { + self.execute_i64_rem_s_imm16_lhs(result, lhs, rhs)? } Instr::I64RemU { result, lhs, rhs } => self.execute_i64_rem_u(result, lhs, rhs)?, - Instr::I64RemUImm16 { result, lhs, rhs } => { - self.execute_i64_rem_u_imm16(result, lhs, rhs) + Instr::I64RemUImm16Rhs { result, lhs, rhs } => { + self.execute_i64_rem_u_imm16_rhs(result, lhs, rhs) } - Instr::I64RemUImm16Rev { result, lhs, rhs } => { - self.execute_i64_rem_u_imm16_rev(result, lhs, rhs)? + Instr::I64RemUImm16Lhs { result, lhs, rhs } => { + self.execute_i64_rem_u_imm16_lhs(result, lhs, rhs)? } Instr::I64And { result, lhs, rhs } => self.execute_i64_and(result, lhs, rhs), Instr::I64AndImm16 { result, lhs, rhs } => { @@ -1055,37 +1052,33 @@ impl<'engine> Executor<'engine> { self.execute_i64_xor_imm16(result, lhs, rhs) } Instr::I64Shl { result, lhs, rhs } => self.execute_i64_shl(result, lhs, rhs), - Instr::I64ShlImm { result, lhs, rhs } => self.execute_i64_shl_imm(result, lhs, rhs), - Instr::I64ShlImm16Rev { result, lhs, rhs } => { - self.execute_i64_shl_imm16_rev(result, lhs, rhs) + Instr::I64ShlBy { result, lhs, rhs } => self.execute_i64_shl_by(result, lhs, rhs), + Instr::I64ShlImm16 { result, lhs, rhs } => { + self.execute_i64_shl_imm16(result, lhs, rhs) } Instr::I64ShrU { result, lhs, rhs } => self.execute_i64_shr_u(result, lhs, rhs), - Instr::I64ShrUImm { result, lhs, rhs } => { - self.execute_i64_shr_u_imm(result, lhs, rhs) + Instr::I64ShrUBy { result, lhs, rhs } => { + self.execute_i64_shr_u_by(result, lhs, rhs) } - Instr::I64ShrUImm16Rev { result, lhs, rhs } => { - self.execute_i64_shr_u_imm16_rev(result, lhs, rhs) + Instr::I64ShrUImm16 { result, lhs, rhs } => { + self.execute_i64_shr_u_imm16(result, lhs, rhs) } Instr::I64ShrS { result, lhs, rhs } => self.execute_i64_shr_s(result, lhs, rhs), - Instr::I64ShrSImm { result, lhs, rhs } => { - self.execute_i64_shr_s_imm(result, lhs, rhs) + Instr::I64ShrSBy { result, lhs, rhs } => { + self.execute_i64_shr_s_by(result, lhs, rhs) } - Instr::I64ShrSImm16Rev { result, lhs, rhs } => { - self.execute_i64_shr_s_imm16_rev(result, lhs, rhs) + Instr::I64ShrSImm16 { result, lhs, rhs } => { + self.execute_i64_shr_s_imm16(result, lhs, rhs) } Instr::I64Rotl { result, lhs, rhs } => self.execute_i64_rotl(result, lhs, rhs), - Instr::I64RotlImm { result, lhs, rhs } => { - self.execute_i64_rotl_imm(result, lhs, rhs) - } - Instr::I64RotlImm16Rev { result, lhs, rhs } => { - self.execute_i64_rotl_imm16_rev(result, lhs, rhs) + Instr::I64RotlBy { result, lhs, rhs } => self.execute_i64_rotl_by(result, lhs, rhs), + Instr::I64RotlImm16 { result, lhs, rhs } => { + self.execute_i64_rotl_imm16(result, lhs, rhs) } Instr::I64Rotr { result, lhs, rhs } => self.execute_i64_rotr(result, lhs, rhs), - Instr::I64RotrImm { result, lhs, rhs } => { - self.execute_i64_rotr_imm(result, lhs, rhs) - } - Instr::I64RotrImm16Rev { result, lhs, rhs } => { - self.execute_i64_rotr_imm16_rev(result, lhs, rhs) + Instr::I64RotrBy { result, lhs, rhs } => self.execute_i64_rotr_by(result, lhs, rhs), + Instr::I64RotrImm16 { result, lhs, rhs } => { + self.execute_i64_rotr_imm16(result, lhs, rhs) } Instr::I32WrapI64 { result, input } => self.execute_i32_wrap_i64(result, input), Instr::I32Extend8S { result, input } => self.execute_i32_extend8_s(result, input), @@ -1604,7 +1597,7 @@ impl Executor<'_> { /// Executes a generic binary [`Instruction`] with reversed operands. #[inline(always)] - fn execute_binary_imm16_rev( + fn execute_binary_imm16_lhs( &mut self, result: Reg, lhs: Const16, @@ -1620,6 +1613,24 @@ impl Executor<'_> { self.next_instr(); } + /// Executes a generic shift or rotate [`Instruction`]. + #[inline(always)] + fn execute_shift_by( + &mut self, + result: Reg, + lhs: Reg, + rhs: ShiftAmount, + op: fn(UntypedVal, UntypedVal) -> UntypedVal, + ) where + T: From>, + UntypedVal: From, + { + let lhs = self.get_register(lhs); + let rhs = UntypedVal::from(::from(rhs)); + self.set_register(result, op(lhs, rhs)); + self.next_instr(); + } + /// Executes a fallible generic binary [`Instruction`]. #[inline(always)] fn try_execute_binary( @@ -1637,7 +1648,7 @@ impl Executor<'_> { /// Executes a fallible generic binary [`Instruction`]. #[inline(always)] - fn try_execute_divrem_imm16( + fn try_execute_divrem_imm16_rhs( &mut self, result: Reg, lhs: Reg, @@ -1655,7 +1666,7 @@ impl Executor<'_> { /// Executes a fallible generic binary [`Instruction`]. #[inline(always)] - fn execute_divrem_imm16( + fn execute_divrem_imm16_rhs( &mut self, result: Reg, lhs: Reg, @@ -1672,7 +1683,7 @@ impl Executor<'_> { /// Executes a fallible generic binary [`Instruction`] with reversed operands. #[inline(always)] - fn try_execute_binary_imm16_rev( + fn try_execute_binary_imm16_lhs( &mut self, result: Reg, lhs: Const16, diff --git a/crates/wasmi/src/engine/executor/instrs/binary.rs b/crates/wasmi/src/engine/executor/instrs/binary.rs index 749a361640..788ec8a7df 100644 --- a/crates/wasmi/src/engine/executor/instrs/binary.rs +++ b/crates/wasmi/src/engine/executor/instrs/binary.rs @@ -2,6 +2,7 @@ use super::{Executor, UntypedValueExt}; use crate::{ core::{TrapCode, UntypedVal}, engine::bytecode::{Const16, Reg, Sign}, + ir::ShiftAmount, Error, }; use core::num::{NonZeroI32, NonZeroI64, NonZeroU32, NonZeroU64}; @@ -94,48 +95,62 @@ impl Executor<'_> { (i64, Instruction::I64AndImm16, execute_i64_and_imm16, UntypedVal::i64_and), (i64, Instruction::I64OrImm16, execute_i64_or_imm16, UntypedVal::i64_or), (i64, Instruction::I64XorImm16, execute_i64_xor_imm16, UntypedVal::i64_xor), + } +} - (i32, Instruction::I32ShlImm, execute_i32_shl_imm, UntypedVal::i32_shl), - (i32, Instruction::I32ShrUImm, execute_i32_shr_u_imm, UntypedVal::i32_shr_u), - (i32, Instruction::I32ShrSImm, execute_i32_shr_s_imm, UntypedVal::i32_shr_s), - (i32, Instruction::I32RotlImm, execute_i32_rotl_imm, UntypedVal::i32_rotl), - (i32, Instruction::I32RotrImm, execute_i32_rotr_imm, UntypedVal::i32_rotr), - - (i64, Instruction::I64ShlImm, execute_i64_shl_imm, UntypedVal::i64_shl), - (i64, Instruction::I64ShrUImm, execute_i64_shr_u_imm, UntypedVal::i64_shr_u), - (i64, Instruction::I64ShrSImm, execute_i64_shr_s_imm, UntypedVal::i64_shr_s), - (i64, Instruction::I64RotlImm, execute_i64_rotl_imm, UntypedVal::i64_rotl), - (i64, Instruction::I64RotrImm, execute_i64_rotr_imm, UntypedVal::i64_rotr), +macro_rules! impl_shift_by { + ( $( ($ty:ty, Instruction::$var_name:ident, $fn_name:ident, $op:expr) ),* $(,)? ) => { + $( + #[doc = concat!("Executes an [`Instruction::", stringify!($var_name), "`].")] + pub fn $fn_name(&mut self, result: Reg, lhs: Reg, rhs: ShiftAmount<$ty>) { + self.execute_shift_by(result, lhs, rhs, $op) + } + )* + }; +} +impl Executor<'_> { + impl_shift_by! { + (i32, Instruction::I32ShlBy, execute_i32_shl_by, UntypedVal::i32_shl), + (i32, Instruction::I32ShrUBy, execute_i32_shr_u_by, UntypedVal::i32_shr_u), + (i32, Instruction::I32ShrSBy, execute_i32_shr_s_by, UntypedVal::i32_shr_s), + (i32, Instruction::I32RotlBy, execute_i32_rotl_by, UntypedVal::i32_rotl), + (i32, Instruction::I32RotrBy, execute_i32_rotr_by, UntypedVal::i32_rotr), + + (i64, Instruction::I64ShlBy, execute_i64_shl_by, UntypedVal::i64_shl), + (i64, Instruction::I64ShrUBy, execute_i64_shr_u_by, UntypedVal::i64_shr_u), + (i64, Instruction::I64ShrSBy, execute_i64_shr_s_by, UntypedVal::i64_shr_s), + (i64, Instruction::I64RotlBy, execute_i64_rotl_by, UntypedVal::i64_rotl), + (i64, Instruction::I64RotrBy, execute_i64_rotr_by, UntypedVal::i64_rotr), } } -macro_rules! impl_binary_imm16_rev { +macro_rules! impl_binary_imm16_lhs { ( $( ($ty:ty, Instruction::$var_name:ident, $fn_name:ident, $op:expr) ),* $(,)? ) => { $( #[doc = concat!("Executes an [`Instruction::", stringify!($var_name), "`].")] pub fn $fn_name(&mut self, result: Reg, lhs: Const16<$ty>, rhs: Reg) { - self.execute_binary_imm16_rev(result, lhs, rhs, $op) + self.execute_binary_imm16_lhs(result, lhs, rhs, $op) } )* }; } impl Executor<'_> { - impl_binary_imm16_rev! { - (i32, Instruction::I32SubImm16Rev, execute_i32_sub_imm16_rev, UntypedVal::i32_sub), - (i64, Instruction::I64SubImm16Rev, execute_i64_sub_imm16_rev, UntypedVal::i64_sub), - - (i32, Instruction::I32ShlImm16Rev, execute_i32_shl_imm16_rev, UntypedVal::i32_shl), - (i32, Instruction::I32ShrUImm16Rev, execute_i32_shr_u_imm16_rev, UntypedVal::i32_shr_u), - (i32, Instruction::I32ShrSImm16Rev, execute_i32_shr_s_imm16_rev, UntypedVal::i32_shr_s), - (i32, Instruction::I32RotlImm16Rev, execute_i32_rotl_imm16_rev, UntypedVal::i32_rotl), - (i32, Instruction::I32RotrImm16Rev, execute_i32_rotr_imm16_rev, UntypedVal::i32_rotr), - - (i64, Instruction::I64ShlImm16Rev, execute_i64_shl_imm16_rev, UntypedVal::i64_shl), - (i64, Instruction::I64ShrUImm16Rev, execute_i64_shr_u_imm16_rev, UntypedVal::i64_shr_u), - (i64, Instruction::I64ShrSImm16Rev, execute_i64_shr_s_imm16_rev, UntypedVal::i64_shr_s), - (i64, Instruction::I64RotlImm16Rev, execute_i64_rotl_imm16_rev, UntypedVal::i64_rotl), - (i64, Instruction::I64RotrImm16Rev, execute_i64_rotr_imm16_rev, UntypedVal::i64_rotr), + impl_binary_imm16_lhs! { + (i32, Instruction::I32SubImm16Lhs, execute_i32_sub_imm16_lhs, UntypedVal::i32_sub), + (i64, Instruction::I64SubImm16Lhs, execute_i64_sub_imm16_lhs, UntypedVal::i64_sub), + + (i32, Instruction::I32ShlImm16, execute_i32_shl_imm16, UntypedVal::i32_shl), + (i32, Instruction::I32ShrUImm16, execute_i32_shr_u_imm16, UntypedVal::i32_shr_u), + (i32, Instruction::I32ShrSImm16, execute_i32_shr_s_imm16, UntypedVal::i32_shr_s), + (i32, Instruction::I32RotlImm16, execute_i32_rotl_imm16, UntypedVal::i32_rotl), + (i32, Instruction::I32RotrImm16, execute_i32_rotr_imm16, UntypedVal::i32_rotr), + + (i64, Instruction::I64ShlImm16, execute_i64_shl_imm16, UntypedVal::i64_shl), + (i64, Instruction::I64ShrUImm16, execute_i64_shr_u_imm16, UntypedVal::i64_shr_u), + (i64, Instruction::I64ShrSImm16, execute_i64_shr_s_imm16, UntypedVal::i64_shr_s), + (i64, Instruction::I64RotlImm16, execute_i64_rotl_imm16, UntypedVal::i64_rotl), + (i64, Instruction::I64RotrImm16, execute_i64_rotr_imm16, UntypedVal::i64_rotr), } } @@ -230,67 +245,67 @@ impl DivRemExt for UntypedVal { } } -macro_rules! impl_divrem_s_imm16 { +macro_rules! impl_divrem_s_imm16_rhs { ( $( ($ty:ty, Instruction::$var_name:ident, $fn_name:ident, $op:expr) ),* $(,)? ) => { $( #[doc = concat!("Executes an [`Instruction::", stringify!($var_name), "`].")] pub fn $fn_name(&mut self, result: Reg, lhs: Reg, rhs: Const16<$ty>) -> Result<(), Error> { - self.try_execute_divrem_imm16(result, lhs, rhs, $op) + self.try_execute_divrem_imm16_rhs(result, lhs, rhs, $op) } )* }; } impl Executor<'_> { - impl_divrem_s_imm16! { - (NonZeroI32, Instruction::I32DivSImm16, execute_i32_div_s_imm16, ::i32_div_s), - (NonZeroI32, Instruction::I32RemSImm16, execute_i32_rem_s_imm16, ::i32_rem_s), + impl_divrem_s_imm16_rhs! { + (NonZeroI32, Instruction::I32DivSImm16Rhs, execute_i32_div_s_imm16_rhs, ::i32_div_s), + (NonZeroI32, Instruction::I32RemSImm16Rhs, execute_i32_rem_s_imm16_rhs, ::i32_rem_s), - (NonZeroI64, Instruction::I64DivSImm16, execute_i64_div_s_imm16, ::i64_div_s), - (NonZeroI64, Instruction::I64RemSImm16, execute_i64_rem_s_imm16, ::i64_rem_s), + (NonZeroI64, Instruction::I64DivSImm16Rhs, execute_i64_div_s_imm16_rhs, ::i64_div_s), + (NonZeroI64, Instruction::I64RemSImm16Rhs, execute_i64_rem_s_imm16_rhs, ::i64_rem_s), } } -macro_rules! impl_divrem_u_imm16 { +macro_rules! impl_divrem_u_imm16_rhs { ( $( ($ty:ty, Instruction::$var_name:ident, $fn_name:ident, $op:expr) ),* $(,)? ) => { $( #[doc = concat!("Executes an [`Instruction::", stringify!($var_name), "`].")] pub fn $fn_name(&mut self, result: Reg, lhs: Reg, rhs: Const16<$ty>) { - self.execute_divrem_imm16(result, lhs, rhs, $op) + self.execute_divrem_imm16_rhs(result, lhs, rhs, $op) } )* }; } impl Executor<'_> { - impl_divrem_u_imm16! { - (NonZeroU32, Instruction::I32DivUImm16, execute_i32_div_u_imm16, ::i32_div_u), - (NonZeroU32, Instruction::I32RemUImm16, execute_i32_rem_u_imm16, ::i32_rem_u), + impl_divrem_u_imm16_rhs! { + (NonZeroU32, Instruction::I32DivUImm16Rhs, execute_i32_div_u_imm16_rhs, ::i32_div_u), + (NonZeroU32, Instruction::I32RemUImm16Rhs, execute_i32_rem_u_imm16_rhs, ::i32_rem_u), - (NonZeroU64, Instruction::I64DivUImm16, execute_i64_div_u_imm16, ::i64_div_u), - (NonZeroU64, Instruction::I64RemUImm16, execute_i64_rem_u_imm16, ::i64_rem_u), + (NonZeroU64, Instruction::I64DivUImm16Rhs, execute_i64_div_u_imm16_rhs, ::i64_div_u), + (NonZeroU64, Instruction::I64RemUImm16Rhs, execute_i64_rem_u_imm16_rhs, ::i64_rem_u), } } -macro_rules! impl_fallible_binary_imm16_rev { +macro_rules! impl_fallible_binary_imm16_lhs { ( $( ($ty:ty, Instruction::$var_name:ident, $fn_name:ident, $op:expr) ),* $(,)? ) => { $( #[doc = concat!("Executes an [`Instruction::", stringify!($var_name), "`].")] pub fn $fn_name(&mut self, result: Reg, lhs: Const16<$ty>, rhs: Reg) -> Result<(), Error> { - self.try_execute_binary_imm16_rev(result, lhs, rhs, $op).map_err(Into::into) + self.try_execute_binary_imm16_lhs(result, lhs, rhs, $op).map_err(Into::into) } )* }; } impl Executor<'_> { - impl_fallible_binary_imm16_rev! { - (i32, Instruction::I32DivSImm16Rev, execute_i32_div_s_imm16_rev, UntypedVal::i32_div_s), - (u32, Instruction::I32DivUImm16Rev, execute_i32_div_u_imm16_rev, UntypedVal::i32_div_u), - (i32, Instruction::I32RemSImm16Rev, execute_i32_rem_s_imm16_rev, UntypedVal::i32_rem_s), - (u32, Instruction::I32RemUImm16Rev, execute_i32_rem_u_imm16_rev, UntypedVal::i32_rem_u), - - (i64, Instruction::I64DivSImm16Rev, execute_i64_div_s_imm16_rev, UntypedVal::i64_div_s), - (u64, Instruction::I64DivUImm16Rev, execute_i64_div_u_imm16_rev, UntypedVal::i64_div_u), - (i64, Instruction::I64RemSImm16Rev, execute_i64_rem_s_imm16_rev, UntypedVal::i64_rem_s), - (u64, Instruction::I64RemUImm16Rev, execute_i64_rem_u_imm16_rev, UntypedVal::i64_rem_u), + impl_fallible_binary_imm16_lhs! { + (i32, Instruction::I32DivSImm16Lhs, execute_i32_div_s_imm16_lhs, UntypedVal::i32_div_s), + (u32, Instruction::I32DivUImm16Lhs, execute_i32_div_u_imm16_lhs, UntypedVal::i32_div_u), + (i32, Instruction::I32RemSImm16Lhs, execute_i32_rem_s_imm16_lhs, UntypedVal::i32_rem_s), + (u32, Instruction::I32RemUImm16Lhs, execute_i32_rem_u_imm16_lhs, UntypedVal::i32_rem_u), + + (i64, Instruction::I64DivSImm16Lhs, execute_i64_div_s_imm16_lhs, UntypedVal::i64_div_s), + (u64, Instruction::I64DivUImm16Lhs, execute_i64_div_u_imm16_lhs, UntypedVal::i64_div_u), + (i64, Instruction::I64RemSImm16Lhs, execute_i64_rem_s_imm16_lhs, UntypedVal::i64_rem_s), + (u64, Instruction::I64RemUImm16Lhs, execute_i64_rem_u_imm16_lhs, UntypedVal::i64_rem_u), } } diff --git a/crates/wasmi/src/engine/translator/mod.rs b/crates/wasmi/src/engine/translator/mod.rs index f597a7d667..9a43e43fd3 100644 --- a/crates/wasmi/src/engine/translator/mod.rs +++ b/crates/wasmi/src/engine/translator/mod.rs @@ -50,7 +50,7 @@ use crate::{ BlockType, EngineFunc, }, - ir::AnyConst16, + ir::{AnyConst16, IntoShiftAmount, ShiftAmount}, module::{FuncIdx, FuncTypeIdx, ModuleHeader}, Engine, Error, @@ -1675,13 +1675,13 @@ impl FuncTranslator { fn translate_shift( &mut self, make_instr: fn(result: Reg, lhs: Reg, rhs: Reg) -> Instruction, - make_instr_imm: fn(result: Reg, lhs: Reg, rhs: Const16) -> Instruction, - make_instr_imm16_rev: fn(result: Reg, lhs: Const16, rhs: Reg) -> Instruction, + make_instr_by: fn(result: Reg, lhs: Reg, rhs: ShiftAmount) -> Instruction, + make_instr_imm16: fn(result: Reg, lhs: Const16, rhs: Reg) -> Instruction, consteval: fn(TypedVal, TypedVal) -> TypedVal, make_instr_imm_reg_opt: fn(&mut Self, lhs: T, rhs: Reg) -> Result, ) -> Result<(), Error> where - T: WasmInteger, + T: WasmInteger + IntoShiftAmount, Const16: From, { bail_unreachable!(self); @@ -1690,17 +1690,13 @@ impl FuncTranslator { self.push_binary_instr(lhs, rhs, make_instr) } (TypedProvider::Register(lhs), TypedProvider::Const(rhs)) => { - let rhs = T::from(rhs).as_shift_amount(); - if rhs == 0 { + let Some(rhs) = T::from(rhs).into_shift_amount() else { // Optimization: Shifting or rotating by zero bits is a no-op. self.alloc.stack.push_register(lhs)?; return Ok(()); - } + }; let result = self.alloc.stack.push_dynamic()?; - self.push_fueled_instr( - make_instr_imm(result, lhs, >::from(rhs)), - FuelCosts::base, - )?; + self.push_fueled_instr(make_instr_by(result, lhs, rhs), FuelCosts::base)?; Ok(()) } (TypedProvider::Const(lhs), TypedProvider::Register(rhs)) => { @@ -1713,7 +1709,7 @@ impl FuncTranslator { self.alloc.stack.push_const(lhs); return Ok(()); } - if self.try_push_binary_instr_imm16_rev(T::from(lhs), rhs, make_instr_imm16_rev)? { + if self.try_push_binary_instr_imm16_rev(T::from(lhs), rhs, make_instr_imm16)? { // Optimization was applied: return early. return Ok(()); } diff --git a/crates/wasmi/src/engine/translator/tests/mod.rs b/crates/wasmi/src/engine/translator/tests/mod.rs index 2d4af90436..f5ec441a8d 100644 --- a/crates/wasmi/src/engine/translator/tests/mod.rs +++ b/crates/wasmi/src/engine/translator/tests/mod.rs @@ -244,7 +244,8 @@ where TranslationTest::from_wat(&wasm) } -fn test_binary_reg_imm16( +/// Variant of [`test_binary_reg_imm16`] where the `rhs` operand is an immediate value. +fn test_binary_reg_imm16_rhs( wasm_op: WasmOp, value: T, make_instr: fn(result: Reg, lhs: Reg, rhs: Const16) -> Instruction, @@ -262,8 +263,8 @@ fn test_binary_reg_imm16( test_binary_reg_imm_with(wasm_op, value, expected).run() } -/// Variant of [`test_binary_reg_imm16`] where both operands are swapped. -fn test_binary_reg_imm16_rev( +/// Variant of [`test_binary_reg_imm16`] where the `lhs` operand is an immediate value. +fn test_binary_reg_imm16_lhs( wasm_op: WasmOp, value: T, make_instr: fn(result: Reg, lhs: Const16, rhs: Reg) -> Instruction, @@ -278,7 +279,7 @@ fn test_binary_reg_imm16_rev( make_instr(Reg::from(1), immediate, Reg::from(0)), Instruction::return_reg(1), ]; - test_binary_reg_imm_rev_with(wasm_op, value, expected).run() + test_binary_reg_imm_lhs_with(wasm_op, value, expected).run() } fn test_binary_reg_imm32( @@ -299,7 +300,7 @@ fn test_binary_reg_imm32( } /// Variant of [`test_binary_reg_imm32`] where both operands are swapped. -fn test_binary_reg_imm32_rev( +fn test_binary_reg_imm32_lhs( wasm_op: WasmOp, value: T, make_instr: fn(result: Reg, lhs: Reg, rhs: Reg) -> Instruction, @@ -317,7 +318,7 @@ fn test_binary_reg_imm32_rev( } /// Variant of [`test_binary_reg_imm32`] where both operands are swapped. -fn test_binary_reg_imm32_rev_commutative( +fn test_binary_reg_imm32_lhs_commutative( wasm_op: WasmOp, value: T, make_instr: fn(result: Reg, lhs: Reg, rhs: Reg) -> Instruction, @@ -346,7 +347,7 @@ where testcase } -fn test_binary_reg_imm_rev_with(wasm_op: WasmOp, value: T, expected: E) -> TranslationTest +fn test_binary_reg_imm_lhs_with(wasm_op: WasmOp, value: T, expected: E) -> TranslationTest where T: Copy, DisplayWasm: Display, diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/f32_add.rs b/crates/wasmi/src/engine/translator/tests/op/binary/f32_add.rs index 173da14591..6a2d6d8c72 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/f32_add.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/f32_add.rs @@ -16,8 +16,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, 1.0_f32, Instruction::f32_add) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, 1.0_f32, Instruction::f32_add) } #[test] @@ -29,7 +29,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f32::NAN, [Instruction::return_imm32(f32::NAN)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f32::NAN, [Instruction::return_imm32(f32::NAN)]).run() } #[test] @@ -47,7 +47,7 @@ fn reg_zero() { #[test] #[cfg_attr(miri, ignore)] -fn reg_zero_rev() { +fn reg_zero_lhs() { // We cannot optimize `0 + x` -> `x` because `0 + -0` -> `0` according to IEEE. let expected = [ Instruction::f32_add(Reg::from(1), Reg::from(0), Reg::from(-1)), diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/f32_copysign.rs b/crates/wasmi/src/engine/translator/tests/op/binary/f32_copysign.rs index a3eb9a6e52..dc3d2fba4d 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/f32_copysign.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/f32_copysign.rs @@ -24,8 +24,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 1.0_f32, Instruction::f32_copysign) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 1.0_f32, Instruction::f32_copysign) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/f32_div.rs b/crates/wasmi/src/engine/translator/tests/op/binary/f32_div.rs index 8a05dc6829..dd2c73378b 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/f32_div.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/f32_div.rs @@ -16,8 +16,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 1.0_f32, Instruction::f32_div) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 1.0_f32, Instruction::f32_div) } #[test] @@ -29,7 +29,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f32::NAN, [Instruction::return_imm32(f32::NAN)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f32::NAN, [Instruction::return_imm32(f32::NAN)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/f32_max.rs b/crates/wasmi/src/engine/translator/tests/op/binary/f32_max.rs index 6c6baebe61..63c0bbeda3 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/f32_max.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/f32_max.rs @@ -16,8 +16,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, 1.0_f32, Instruction::f32_max) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, 1.0_f32, Instruction::f32_max) } #[test] @@ -29,7 +29,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f32::NAN, [Instruction::return_imm32(f32::NAN)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f32::NAN, [Instruction::return_imm32(f32::NAN)]).run() } #[test] @@ -41,9 +41,9 @@ fn reg_neg_infinity() { #[test] #[cfg_attr(miri, ignore)] -fn reg_neg_infinity_rev() { +fn reg_neg_infinity_lhs() { let expected = [Instruction::return_reg(0)]; - test_binary_reg_imm_rev_with(WASM_OP, f32::NEG_INFINITY, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, f32::NEG_INFINITY, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/f32_min.rs b/crates/wasmi/src/engine/translator/tests/op/binary/f32_min.rs index d084f8e679..3231439f56 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/f32_min.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/f32_min.rs @@ -16,8 +16,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, 1.0_f32, Instruction::f32_min) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, 1.0_f32, Instruction::f32_min) } #[test] @@ -29,7 +29,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f32::NAN, [Instruction::return_imm32(f32::NAN)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f32::NAN, [Instruction::return_imm32(f32::NAN)]).run() } #[test] @@ -41,9 +41,9 @@ fn reg_pos_infinity() { #[test] #[cfg_attr(miri, ignore)] -fn reg_pos_infinity_rev() { +fn reg_pos_infinity_lhs() { let expected = [Instruction::return_reg(0)]; - test_binary_reg_imm_rev_with(WASM_OP, f32::INFINITY, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, f32::INFINITY, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/f32_mul.rs b/crates/wasmi/src/engine/translator/tests/op/binary/f32_mul.rs index 6bd38f73b4..8115bf41f2 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/f32_mul.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/f32_mul.rs @@ -16,8 +16,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, 1.0_f32, Instruction::f32_mul) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, 1.0_f32, Instruction::f32_mul) } #[test] @@ -29,7 +29,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f32::NAN, [Instruction::return_imm32(f32::NAN)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f32::NAN, [Instruction::return_imm32(f32::NAN)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/f32_sub.rs b/crates/wasmi/src/engine/translator/tests/op/binary/f32_sub.rs index e669b97b67..650de15fd6 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/f32_sub.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/f32_sub.rs @@ -16,8 +16,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 1.0_f32, Instruction::f32_sub) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 1.0_f32, Instruction::f32_sub) } #[test] @@ -29,7 +29,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f32::NAN, [Instruction::return_imm32(f32::NAN)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f32::NAN, [Instruction::return_imm32(f32::NAN)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/f64_add.rs b/crates/wasmi/src/engine/translator/tests/op/binary/f64_add.rs index a2d7f4e814..c8179baefa 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/f64_add.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/f64_add.rs @@ -16,8 +16,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, 1.0_f64, Instruction::f64_add) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, 1.0_f64, Instruction::f64_add) } #[test] @@ -51,7 +51,7 @@ fn reg_zero() { #[test] #[cfg_attr(miri, ignore)] -fn reg_zero_rev() { +fn reg_zero_lhs() { // We cannot optimize `0 + x` -> `x` because `0 + -0` -> `0` according to IEEE. let expected = [ Instruction::f64_add(Reg::from(1), Reg::from(0), Reg::from(-1)), diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/f64_copysign.rs b/crates/wasmi/src/engine/translator/tests/op/binary/f64_copysign.rs index c22d87f340..ada376211e 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/f64_copysign.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/f64_copysign.rs @@ -24,8 +24,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 1.0_f64, Instruction::f64_copysign) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 1.0_f64, Instruction::f64_copysign) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/f64_div.rs b/crates/wasmi/src/engine/translator/tests/op/binary/f64_div.rs index d34be788ee..b4737dd947 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/f64_div.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/f64_div.rs @@ -16,8 +16,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 1.0_f64, Instruction::f64_div) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 1.0_f64, Instruction::f64_div) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/f64_max.rs b/crates/wasmi/src/engine/translator/tests/op/binary/f64_max.rs index e46d0b62bf..44cbbeb7fc 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/f64_max.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/f64_max.rs @@ -16,8 +16,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, 1.0_f64, Instruction::f64_max) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, 1.0_f64, Instruction::f64_max) } #[test] @@ -45,9 +45,9 @@ fn reg_neg_infinity() { #[test] #[cfg_attr(miri, ignore)] -fn reg_neg_infinity_rev() { +fn reg_neg_infinity_lhs() { let expected = [Instruction::return_reg(0)]; - test_binary_reg_imm_rev_with(WASM_OP, f64::NEG_INFINITY, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, f64::NEG_INFINITY, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/f64_min.rs b/crates/wasmi/src/engine/translator/tests/op/binary/f64_min.rs index 6f00407470..d754292b59 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/f64_min.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/f64_min.rs @@ -16,8 +16,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, 1.0_f64, Instruction::f64_min) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, 1.0_f64, Instruction::f64_min) } #[test] @@ -45,9 +45,9 @@ fn reg_pos_infinity() { #[test] #[cfg_attr(miri, ignore)] -fn reg_pos_infinity_rev() { +fn reg_pos_infinity_lhs() { let expected = [Instruction::return_reg(0)]; - test_binary_reg_imm_rev_with(WASM_OP, f64::INFINITY, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, f64::INFINITY, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/f64_mul.rs b/crates/wasmi/src/engine/translator/tests/op/binary/f64_mul.rs index c35c2e1de5..7239cf3d13 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/f64_mul.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/f64_mul.rs @@ -16,8 +16,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, 1.0_f64, Instruction::f64_mul) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, 1.0_f64, Instruction::f64_mul) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/f64_sub.rs b/crates/wasmi/src/engine/translator/tests/op/binary/f64_sub.rs index 2a114b87bd..482a79bb8e 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/f64_sub.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/f64_sub.rs @@ -16,8 +16,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 1.0_f64, Instruction::f64_sub) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 1.0_f64, Instruction::f64_sub) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_add.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_add.rs index 7a5c0e86e5..8fda2d3d08 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_add.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_add.rs @@ -11,13 +11,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_add_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_add_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_add_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_add_imm16)) } #[test] @@ -28,8 +28,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, i32::MAX, Instruction::i32_add) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, i32::MAX, Instruction::i32_add) } #[test] @@ -41,9 +41,9 @@ fn reg_zero() { #[test] #[cfg_attr(miri, ignore)] -fn reg_zero_rev() { +fn reg_zero_lhs() { let expected = [Instruction::return_reg(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 0i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_and.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_and.rs index c965a523d9..b1432a1920 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_and.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_and.rs @@ -18,13 +18,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_and_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_and_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_and_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_and_imm16)) } #[test] @@ -35,8 +35,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, i32::MAX, Instruction::i32_and) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, i32::MAX, Instruction::i32_and) } #[test] @@ -50,11 +50,11 @@ fn reg_zero() { #[test] #[cfg_attr(miri, ignore)] -fn reg_zero_rev() { +fn reg_zero_lhs() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(0), }]; - test_binary_reg_imm_rev_with(WASM_OP, 0i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0i32, expected).run() } #[test] @@ -66,9 +66,9 @@ fn reg_ones() { #[test] #[cfg_attr(miri, ignore)] -fn reg_ones_rev() { +fn reg_ones_lhs() { let expected = [Instruction::return_reg(0)]; - test_binary_reg_imm_rev_with(WASM_OP, -1_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, -1_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_div_s.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_div_s.rs index 8f22c81be3..08d9b9e36e 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_div_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_div_s.rs @@ -22,14 +22,18 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, nonzero_i32(100), Instruction::i32_div_s_imm16) +fn reg_imm16_rhs() { + test_binary_reg_imm16_rhs::( + WASM_OP, + nonzero_i32(100), + Instruction::i32_div_s_imm16_rhs, + ) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i32_div_s_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i32_div_s_imm16_lhs) } #[test] @@ -40,8 +44,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i32::MAX, Instruction::i32_div_s) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i32::MAX, Instruction::i32_div_s) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_div_u.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_div_u.rs index fe1f13ff7e..3dc6acf224 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_div_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_div_u.rs @@ -22,14 +22,18 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, nonzero_u32(100), Instruction::i32_div_u_imm16) +fn reg_imm16_rhs() { + test_binary_reg_imm16_rhs::( + WASM_OP, + nonzero_u32(100), + Instruction::i32_div_u_imm16_rhs, + ) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i32_div_u_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i32_div_u_imm16_lhs) } #[test] @@ -40,8 +44,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i32::MAX, Instruction::i32_div_u) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i32::MAX, Instruction::i32_div_u) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_mul.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_mul.rs index c7ab1fc002..2fea44bede 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_mul.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_mul.rs @@ -11,13 +11,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_mul_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_mul_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_mul_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_mul_imm16)) } #[test] @@ -28,8 +28,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, i32::MAX, Instruction::i32_mul) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, i32::MAX, Instruction::i32_mul) } #[test] @@ -43,11 +43,11 @@ fn reg_zero() { #[test] #[cfg_attr(miri, ignore)] -fn reg_zero_rev() { +fn reg_zero_lhs() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(0), }]; - test_binary_reg_imm_rev_with(WASM_OP, 0_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0_i32, expected).run() } #[test] @@ -59,9 +59,9 @@ fn reg_one() { #[test] #[cfg_attr(miri, ignore)] -fn reg_one_rev() { +fn reg_one_lhs() { let expected = [Instruction::return_reg(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 1_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 1_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_or.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_or.rs index cfebe93c34..7cd599e253 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_or.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_or.rs @@ -18,13 +18,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_or_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_or_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_or_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_or_imm16)) } #[test] @@ -35,8 +35,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, i32::MAX, Instruction::i32_or) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, i32::MAX, Instruction::i32_or) } #[test] @@ -48,9 +48,9 @@ fn reg_zero() { #[test] #[cfg_attr(miri, ignore)] -fn reg_zero_rev() { +fn reg_zero_lhs() { let expected = [Instruction::return_reg(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 0i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0i32, expected).run() } #[test] @@ -64,11 +64,11 @@ fn reg_ones() { #[test] #[cfg_attr(miri, ignore)] -fn reg_ones_rev() { +fn reg_ones_lhs() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(-1), }]; - test_binary_reg_imm_rev_with(WASM_OP, -1_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, -1_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_rem_s.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_rem_s.rs index 29453a9792..0c87a20b8a 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_rem_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_rem_s.rs @@ -23,13 +23,17 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, nonzero_i32(100), Instruction::i32_rem_s_imm16) + test_binary_reg_imm16_rhs::( + WASM_OP, + nonzero_i32(100), + Instruction::i32_rem_s_imm16_rhs, + ) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i32_rem_s_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i32_rem_s_imm16_lhs) } #[test] @@ -40,8 +44,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i32::MAX, Instruction::i32_rem_s) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i32::MAX, Instruction::i32_rem_s) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_rem_u.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_rem_u.rs index 359bbd3621..ced050fc78 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_rem_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_rem_u.rs @@ -23,13 +23,17 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, nonzero_u32(100), Instruction::i32_rem_u_imm16) + test_binary_reg_imm16_rhs::( + WASM_OP, + nonzero_u32(100), + Instruction::i32_rem_u_imm16_rhs, + ) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i32_rem_u_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i32_rem_u_imm16_lhs) } #[test] @@ -40,8 +44,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i32::MAX, Instruction::i32_rem_u) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i32::MAX, Instruction::i32_rem_u) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotl.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotl.rs index 7da4d15f90..9e67c2b033 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotl.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotl.rs @@ -10,14 +10,14 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i32::MAX, Instruction::i32_rotl) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i32::MAX, Instruction::i32_rotl) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i32_rotl_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i32_rotl_imm16) } #[test] @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i32_rotl_imm(Reg::from(1), Reg::from(0), >::from(1)), + Instruction::i32_rotl_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); @@ -54,7 +54,7 @@ fn zero_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(0_i32), }]; - test_binary_reg_imm_rev_with(WASM_OP, 0_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0_i32, expected).run() } #[test] @@ -63,7 +63,7 @@ fn minus_one_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(-1_i32), }]; - test_binary_reg_imm_rev_with(WASM_OP, -1_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, -1_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotr.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotr.rs index 9dfb8aa1d5..5df3e83349 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotr.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_rotr.rs @@ -10,14 +10,14 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i32::MAX, Instruction::i32_rotr) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i32::MAX, Instruction::i32_rotr) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i32_rotr_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i32_rotr_imm16) } #[test] @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i32_rotr_imm(Reg::from(1), Reg::from(0), >::from(1)), + Instruction::i32_rotr_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); @@ -54,7 +54,7 @@ fn zero_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(0_i32), }]; - test_binary_reg_imm_rev_with(WASM_OP, 0_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0_i32, expected).run() } #[test] @@ -63,7 +63,7 @@ fn minus_one_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(-1_i32), }]; - test_binary_reg_imm_rev_with(WASM_OP, -1_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, -1_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_shl.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_shl.rs index 36b89baf08..a7e634d9d6 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_shl.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_shl.rs @@ -10,14 +10,14 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i32::MAX, Instruction::i32_shl) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i32::MAX, Instruction::i32_shl) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i32_shl_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i32_shl_imm16) } #[test] @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i32_shl_imm(Reg::from(1), Reg::from(0), >::from(1)), + Instruction::i32_shl_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); @@ -54,7 +54,7 @@ fn zero_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(0_i32), }]; - test_binary_reg_imm_rev_with(WASM_OP, 0_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_s.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_s.rs index 492e7fcf1d..6265a0422f 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_s.rs @@ -10,14 +10,14 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i32::MAX, Instruction::i32_shr_s) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i32::MAX, Instruction::i32_shr_s) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i32_shr_s_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i32_shr_s_imm16) } #[test] @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i32_shr_s_imm(Reg::from(1), Reg::from(0), >::from(1)), + Instruction::i32_shr_s_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); @@ -54,7 +54,7 @@ fn zero_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(0_i32), }]; - test_binary_reg_imm_rev_with(WASM_OP, 0_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0_i32, expected).run() } #[test] @@ -63,7 +63,7 @@ fn minus_one_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(-1_i32), }]; - test_binary_reg_imm_rev_with(WASM_OP, -1_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, -1_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_u.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_u.rs index daa01aa512..4724f7b1ca 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_shr_u.rs @@ -10,14 +10,14 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i32::MAX, Instruction::i32_shr_u) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i32::MAX, Instruction::i32_shr_u) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i32_shr_u_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i32_shr_u_imm16) } #[test] @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i32_shr_u_imm(Reg::from(1), Reg::from(0), >::from(1)), + Instruction::i32_shr_u_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); @@ -54,7 +54,7 @@ fn zero_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(0_i32), }]; - test_binary_reg_imm_rev_with(WASM_OP, 0_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_sub.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_sub.rs index 932ce45554..576f1aaff1 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_sub.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_sub.rs @@ -35,8 +35,8 @@ fn reg_imm16() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i32_sub_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i32_sub_imm16_lhs) } #[test] @@ -64,8 +64,8 @@ fn test_reg_imm(value: i32) { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i32::MAX, Instruction::i32_sub) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i32::MAX, Instruction::i32_sub) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i32_xor.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i32_xor.rs index 5cd98f6fad..ed647e44fb 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i32_xor.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i32_xor.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_xor_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_xor_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_xor_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_xor_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, i32::MAX, Instruction::i32_xor) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, i32::MAX, Instruction::i32_xor) } #[test] @@ -50,9 +50,9 @@ fn reg_zero() { #[test] #[cfg_attr(miri, ignore)] -fn reg_zero_rev() { +fn reg_zero_lhs() { let expected = [Instruction::return_reg(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 0i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_add.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_add.rs index cbb5237b86..d482487a2a 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_add.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_add.rs @@ -11,13 +11,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_add_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_add_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_add_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_add_imm16)) } #[test] @@ -28,8 +28,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, i64::MAX, Instruction::i64_add) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, i64::MAX, Instruction::i64_add) } #[test] @@ -41,9 +41,9 @@ fn reg_zero() { #[test] #[cfg_attr(miri, ignore)] -fn reg_zero_rev() { +fn reg_zero_lhs() { let expected = [Instruction::return_reg(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 0i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_and.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_and.rs index 6ce12ffa9b..168fc212cf 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_and.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_and.rs @@ -18,13 +18,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_and_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_and_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_and_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_and_imm16)) } #[test] @@ -35,8 +35,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, i64::MAX, Instruction::i64_and) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, i64::MAX, Instruction::i64_and) } #[test] @@ -48,9 +48,9 @@ fn reg_zero() { #[test] #[cfg_attr(miri, ignore)] -fn reg_zero_rev() { +fn reg_zero_lhs() { let expected = [return_i64imm32_instr(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 0i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0i32, expected).run() } #[test] @@ -62,9 +62,9 @@ fn reg_ones() { #[test] #[cfg_attr(miri, ignore)] -fn reg_ones_rev() { +fn reg_ones_lhs() { let expected = [Instruction::return_reg(0)]; - test_binary_reg_imm_rev_with(WASM_OP, -1_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, -1_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_div_s.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_div_s.rs index 49b49aecf9..153d6479bd 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_div_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_div_s.rs @@ -23,13 +23,17 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, nonzero_i64(100), Instruction::i64_div_s_imm16) + test_binary_reg_imm16_rhs::( + WASM_OP, + nonzero_i64(100), + Instruction::i64_div_s_imm16_rhs, + ) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i64_div_s_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i64_div_s_imm16_lhs) } #[test] @@ -40,8 +44,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i64::MAX, Instruction::i64_div_s) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i64::MAX, Instruction::i64_div_s) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_div_u.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_div_u.rs index 4fda775b69..30a955e045 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_div_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_div_u.rs @@ -23,13 +23,17 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, nonzero_u64(100), Instruction::i64_div_u_imm16) + test_binary_reg_imm16_rhs::( + WASM_OP, + nonzero_u64(100), + Instruction::i64_div_u_imm16_rhs, + ) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i64_div_u_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i64_div_u_imm16_lhs) } #[test] @@ -40,8 +44,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i64::MAX, Instruction::i64_div_u) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i64::MAX, Instruction::i64_div_u) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_mul.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_mul.rs index 68c97021d0..659826deb1 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_mul.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_mul.rs @@ -11,13 +11,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_mul_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_mul_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_mul_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_mul_imm16)) } #[test] @@ -28,8 +28,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, i64::MAX, Instruction::i64_mul) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, i64::MAX, Instruction::i64_mul) } #[test] @@ -41,9 +41,9 @@ fn reg_zero() { #[test] #[cfg_attr(miri, ignore)] -fn reg_zero_rev() { +fn reg_zero_lhs() { let expected = [return_i64imm32_instr(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 0_i64, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0_i64, expected).run() } #[test] @@ -55,9 +55,9 @@ fn reg_one() { #[test] #[cfg_attr(miri, ignore)] -fn reg_one_rev() { +fn reg_one_lhs() { let expected = [Instruction::return_reg(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 1_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 1_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_or.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_or.rs index 68f4000d4a..9ab861ab87 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_or.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_or.rs @@ -18,13 +18,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_or_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_or_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_or_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_or_imm16)) } #[test] @@ -35,8 +35,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, i64::MAX, Instruction::i64_or) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, i64::MAX, Instruction::i64_or) } #[test] @@ -48,9 +48,9 @@ fn reg_zero() { #[test] #[cfg_attr(miri, ignore)] -fn reg_zero_rev() { +fn reg_zero_lhs() { let expected = [Instruction::return_reg(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 0i64, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0i64, expected).run() } #[test] @@ -62,9 +62,9 @@ fn reg_ones() { #[test] #[cfg_attr(miri, ignore)] -fn reg_ones_rev() { +fn reg_ones_lhs() { let expected = [return_i64imm32_instr(-1)]; - test_binary_reg_imm_rev_with(WASM_OP, -1_i64, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, -1_i64, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_rem_s.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_rem_s.rs index f7f2434a91..d1d2dde5f5 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_rem_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_rem_s.rs @@ -23,13 +23,17 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, nonzero_i64(100), Instruction::i64_rem_s_imm16) + test_binary_reg_imm16_rhs::( + WASM_OP, + nonzero_i64(100), + Instruction::i64_rem_s_imm16_rhs, + ) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i64_rem_s_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i64_rem_s_imm16_lhs) } #[test] @@ -40,8 +44,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i64::MAX, Instruction::i64_rem_s) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i64::MAX, Instruction::i64_rem_s) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_rem_u.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_rem_u.rs index ae3cee18db..818b01056a 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_rem_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_rem_u.rs @@ -23,13 +23,17 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, nonzero_u64(100), Instruction::i64_rem_u_imm16) + test_binary_reg_imm16_rhs::( + WASM_OP, + nonzero_u64(100), + Instruction::i64_rem_u_imm16_rhs, + ) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i64_rem_u_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i64_rem_u_imm16_lhs) } #[test] @@ -40,8 +44,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i64::MAX, Instruction::i64_rem_u) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i64::MAX, Instruction::i64_rem_u) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotl.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotl.rs index 3690575ef2..c0f18ffec8 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotl.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotl.rs @@ -10,14 +10,14 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i64::MAX, Instruction::i64_rotl) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i64::MAX, Instruction::i64_rotl) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i64_rotl_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i64_rotl_imm16) } #[test] @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i64_rotl_imm(Reg::from(1), Reg::from(0), >::from(1)), + Instruction::i64_rotl_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); @@ -52,14 +52,14 @@ fn reg_1_after_mod32() { #[cfg_attr(miri, ignore)] fn zero_reg() { let expected = [return_i64imm32_instr(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 0_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0_i32, expected).run() } #[test] #[cfg_attr(miri, ignore)] fn minus_one_reg() { let expected = [return_i64imm32_instr(-1)]; - test_binary_reg_imm_rev_with(WASM_OP, -1_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, -1_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotr.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotr.rs index cd646fa084..284b204102 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotr.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_rotr.rs @@ -10,14 +10,14 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i64::MAX, Instruction::i64_rotr) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i64::MAX, Instruction::i64_rotr) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i64_rotr_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i64_rotr_imm16) } #[test] @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i64_rotr_imm(Reg::from(1), Reg::from(0), >::from(1)), + Instruction::i64_rotr_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); @@ -52,14 +52,14 @@ fn reg_1_after_mod32() { #[cfg_attr(miri, ignore)] fn zero_reg() { let expected = [return_i64imm32_instr(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 0_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0_i32, expected).run() } #[test] #[cfg_attr(miri, ignore)] fn minus_one_reg() { let expected = [return_i64imm32_instr(-1)]; - test_binary_reg_imm_rev_with(WASM_OP, -1_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, -1_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_shl.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_shl.rs index e8f3d8b642..37876ac8b3 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_shl.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_shl.rs @@ -10,14 +10,14 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i64::MAX, Instruction::i64_shl) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i64::MAX, Instruction::i64_shl) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i64_shl_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i64_shl_imm16) } #[test] @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i64_shl_imm(Reg::from(1), Reg::from(0), >::from(1)), + Instruction::i64_shl_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); @@ -52,7 +52,7 @@ fn reg_1_after_mod32() { #[cfg_attr(miri, ignore)] fn zero_reg() { let expected = [return_i64imm32_instr(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 0_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_s.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_s.rs index 0534dc8028..1ac7ba8266 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_s.rs @@ -10,14 +10,14 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i64::MAX, Instruction::i64_shr_s) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i64::MAX, Instruction::i64_shr_s) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i64_shr_s_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i64_shr_s_imm16) } #[test] @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i64_shr_s_imm(Reg::from(1), Reg::from(0), >::from(1)), + Instruction::i64_shr_s_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); @@ -52,14 +52,14 @@ fn reg_1_after_mod32() { #[cfg_attr(miri, ignore)] fn zero_reg() { let expected = [return_i64imm32_instr(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 0_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0_i32, expected).run() } #[test] #[cfg_attr(miri, ignore)] fn minus_one_reg() { let expected = [return_i64imm32_instr(-1)]; - test_binary_reg_imm_rev_with(WASM_OP, -1_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, -1_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_u.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_u.rs index aa8ad96b1c..5cf8ce2c5c 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_shr_u.rs @@ -10,14 +10,14 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i64::MAX, Instruction::i64_shr_u) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i64::MAX, Instruction::i64_shr_u) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i64_shr_u_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i64_shr_u_imm16) } #[test] @@ -40,7 +40,7 @@ fn reg_0_after_mod32() { #[cfg_attr(miri, ignore)] fn reg_1_after_mod32() { let expected = [ - Instruction::i64_shr_u_imm(Reg::from(1), Reg::from(0), >::from(1)), + Instruction::i64_shr_u_by(Reg::from(1), Reg::from(0), shamt(1)), Instruction::return_reg(1), ]; test_binary_reg_imm_with(WASM_OP, 1_i32, expected).run(); @@ -52,7 +52,7 @@ fn reg_1_after_mod32() { #[cfg_attr(miri, ignore)] fn zero_reg() { let expected = [return_i64imm32_instr(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 0_i32, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0_i32, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_sub.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_sub.rs index ef309878f7..d688e34d53 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_sub.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_sub.rs @@ -33,8 +33,8 @@ fn reg_imm16() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, Instruction::i64_sub_imm16_rev) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, Instruction::i64_sub_imm16_lhs) } #[test] @@ -62,8 +62,8 @@ fn test_reg_imm(value: i64) { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, i64::MAX, Instruction::i64_sub) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, i64::MAX, Instruction::i64_sub) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/i64_xor.rs b/crates/wasmi/src/engine/translator/tests/op/binary/i64_xor.rs index e24e2519f2..fa46b44b37 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/i64_xor.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/i64_xor.rs @@ -18,13 +18,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_xor_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_xor_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_xor_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_xor_imm16)) } #[test] @@ -35,8 +35,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, i64::MAX, Instruction::i64_xor) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, i64::MAX, Instruction::i64_xor) } #[test] @@ -48,9 +48,9 @@ fn reg_zero() { #[test] #[cfg_attr(miri, ignore)] -fn reg_zero_rev() { +fn reg_zero_lhs() { let expected = [Instruction::return_reg(0)]; - test_binary_reg_imm_rev_with(WASM_OP, 0i64, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, 0i64, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/binary/mod.rs b/crates/wasmi/src/engine/translator/tests/op/binary/mod.rs index c7e3f49994..75249ef51a 100644 --- a/crates/wasmi/src/engine/translator/tests/op/binary/mod.rs +++ b/crates/wasmi/src/engine/translator/tests/op/binary/mod.rs @@ -5,6 +5,7 @@ //! These tests include Wasm arithmetic, logical, bitwise, shift and rotate instructions. use super::*; +use crate::ir::{IntoShiftAmount, ShiftAmount}; use core::num::{NonZeroI32, NonZeroI64, NonZeroU32, NonZeroU64}; mod f32_add; @@ -72,6 +73,14 @@ fn nonzero_u64(value: u64) -> NonZeroU64 { NonZeroU64::new(value).unwrap() } +/// Helper to create a [`ShiftAmount`]. +fn shamt(value: T) -> ShiftAmount +where + T: IntoShiftAmount, +{ + value.into_shift_amount().unwrap() +} + /// Creates an [`Instruction::ReturnF64Imm32`] from the given `f64` value. /// /// # Panics diff --git a/crates/wasmi/src/engine/translator/tests/op/br_if.rs b/crates/wasmi/src/engine/translator/tests/op/br_if.rs index 75bd0776c7..322be305d1 100644 --- a/crates/wasmi/src/engine/translator/tests/op/br_if.rs +++ b/crates/wasmi/src/engine/translator/tests/op/br_if.rs @@ -483,7 +483,7 @@ fn return_if_results_2() { #[test] #[cfg_attr(miri, ignore)] -fn return_if_results_2_rev() { +fn return_if_results_2_lhs() { let wasm = r" (module (func (param i32 i32 i32) (result i32 i32) diff --git a/crates/wasmi/src/engine/translator/tests/op/br_table.rs b/crates/wasmi/src/engine/translator/tests/op/br_table.rs index 08415996f8..d2bd089f9b 100644 --- a/crates/wasmi/src/engine/translator/tests/op/br_table.rs +++ b/crates/wasmi/src/engine/translator/tests/op/br_table.rs @@ -726,7 +726,7 @@ fn i64imm32_ok() { Instruction::return_reg(1), Instruction::i64_mul_imm16(Reg::from(1), Reg::from(1), 2_i16), Instruction::return_reg(1), - Instruction::i64_div_s_imm16( + Instruction::i64_div_s_imm16_rhs( Reg::from(1), Reg::from(1), NonZeroI16::new(2).unwrap(), @@ -787,7 +787,7 @@ fn i64imm32_err() { Instruction::return_reg(1), Instruction::i64_mul_imm16(Reg::from(1), Reg::from(1), 2_i16), Instruction::return_reg(1), - Instruction::i64_div_s_imm16( + Instruction::i64_div_s_imm16_rhs( Reg::from(1), Reg::from(1), NonZeroI16::new(2).unwrap(), diff --git a/crates/wasmi/src/engine/translator/tests/op/call/imported.rs b/crates/wasmi/src/engine/translator/tests/op/call/imported.rs index bc2cb691c1..003136805c 100644 --- a/crates/wasmi/src/engine/translator/tests/op/call/imported.rs +++ b/crates/wasmi/src/engine/translator/tests/op/call/imported.rs @@ -85,7 +85,7 @@ fn two_params_reg() { #[test] #[cfg_attr(miri, ignore)] -fn two_params_reg_rev() { +fn two_params_reg_lhs() { let wasm = r#" (module (import "env" "f" (func $f (param i32 i32) (result i32 i32))) @@ -148,7 +148,7 @@ fn three_params_reg() { #[test] #[cfg_attr(miri, ignore)] -fn three_params_reg_rev() { +fn three_params_reg_lhs() { let wasm = r#" (module (import "env" "f" (func $f (param i32 i32 i32) (result i32 i32 i32))) @@ -221,7 +221,7 @@ fn params7_reg() { #[test] #[cfg_attr(miri, ignore)] -fn params7_reg_rev() { +fn params7_reg_lhs() { let wasm = r#" (module (import "env" "f" (func $f (param i32 i32 i32 i32 i32 i32 i32) (result i32 i32 i32 i32 i32 i32 i32))) @@ -315,7 +315,7 @@ fn params8_reg() { #[test] #[cfg_attr(miri, ignore)] -fn params8_reg_rev() { +fn params8_reg_lhs() { let wasm = r#" (module (import "env" "f" (func $f (param i32 i32 i32 i32 i32 i32 i32 i32) (result i32 i32 i32 i32 i32 i32 i32 i32))) @@ -412,7 +412,7 @@ fn params9_reg() { #[test] #[cfg_attr(miri, ignore)] -fn params9_reg_rev() { +fn params9_reg_lhs() { let wasm = r#" (module (import "env" "f" (func $f (param i32 i32 i32 i32 i32 i32 i32 i32 i32) (result i32 i32 i32 i32 i32 i32 i32 i32 i32))) diff --git a/crates/wasmi/src/engine/translator/tests/op/call/indirect.rs b/crates/wasmi/src/engine/translator/tests/op/call/indirect.rs index f1f743e191..84a18be5f6 100644 --- a/crates/wasmi/src/engine/translator/tests/op/call/indirect.rs +++ b/crates/wasmi/src/engine/translator/tests/op/call/indirect.rs @@ -277,7 +277,7 @@ fn two_reg_params_reg() { #[test] #[cfg_attr(miri, ignore)] -fn two_reg_params_reg_rev() { +fn two_reg_params_reg_lhs() { let wasm = r#" (module (import "" "table" (table $table 10 funcref)) @@ -373,7 +373,7 @@ fn two_reg_params_imm16() { #[test] #[cfg_attr(miri, ignore)] -fn two_reg_params_rev_imm16() { +fn two_reg_params_lhs_imm16() { fn test_with(index: u32) { let wasm = format!( r#" @@ -479,7 +479,7 @@ fn three_reg_params_reg() { #[test] #[cfg_attr(miri, ignore)] -fn three_reg_params_reg_rev() { +fn three_reg_params_reg_lhs() { let wasm = r#" (module (import "" "table" (table $table 10 funcref)) diff --git a/crates/wasmi/src/engine/translator/tests/op/call/internal.rs b/crates/wasmi/src/engine/translator/tests/op/call/internal.rs index 821862935c..b429b70fba 100644 --- a/crates/wasmi/src/engine/translator/tests/op/call/internal.rs +++ b/crates/wasmi/src/engine/translator/tests/op/call/internal.rs @@ -96,7 +96,7 @@ fn two_params_reg() { #[test] #[cfg_attr(miri, ignore)] -fn two_params_reg_rev() { +fn two_params_reg_lhs() { let wasm = r#" (module (func $f (param i32 i32) (result i32 i32) @@ -172,7 +172,7 @@ fn three_params_reg() { #[test] #[cfg_attr(miri, ignore)] -fn three_params_reg_rev() { +fn three_params_reg_lhs() { let wasm = r#" (module (func $f (param i32 i32 i32) (result i32 i32 i32) @@ -264,7 +264,7 @@ fn params7_reg() { #[test] #[cfg_attr(miri, ignore)] -fn params7_reg_rev() { +fn params7_reg_lhs() { let wasm = r#" (module (func $f (param i32 i32 i32 i32 i32 i32 i32) (result i32 i32 i32 i32 i32 i32 i32) @@ -386,7 +386,7 @@ fn params8_reg() { #[test] #[cfg_attr(miri, ignore)] -fn params8_reg_rev() { +fn params8_reg_lhs() { let wasm = r#" (module (func $f (param i32 i32 i32 i32 i32 i32 i32 i32) (result i32 i32 i32 i32 i32 i32 i32 i32) @@ -514,7 +514,7 @@ fn params9_reg() { #[test] #[cfg_attr(miri, ignore)] -fn params9_reg_rev() { +fn params9_reg_lhs() { let wasm = r#" (module (func $f (param i32 i32 i32 i32 i32 i32 i32 i32 i32) (result i32 i32 i32 i32 i32 i32 i32 i32 i32) diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/f32_eq.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/f32_eq.rs index fe1114740a..7ac50f2e3c 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/f32_eq.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/f32_eq.rs @@ -27,8 +27,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, 1.0_f32, Instruction::f32_eq) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, 1.0_f32, Instruction::f32_eq) } #[test] @@ -40,7 +40,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f32::NAN, [Instruction::return_imm32(false)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f32::NAN, [Instruction::return_imm32(false)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/f32_ge.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/f32_ge.rs index a47e4f5f49..08d700361d 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/f32_ge.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/f32_ge.rs @@ -26,8 +26,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 1.0_f32, Instruction::f32_ge) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 1.0_f32, Instruction::f32_ge) } #[test] @@ -39,7 +39,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f32::NAN, [Instruction::return_imm32(false)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f32::NAN, [Instruction::return_imm32(false)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/f32_gt.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/f32_gt.rs index 2b5200f8f5..14da7e15b0 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/f32_gt.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/f32_gt.rs @@ -25,8 +25,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 1.0_f32, Instruction::f32_gt) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 1.0_f32, Instruction::f32_gt) } #[test] @@ -45,7 +45,7 @@ fn reg_pos_inf() { #[test] #[cfg_attr(miri, ignore)] fn neg_inf_reg() { - test_binary_reg_imm_rev_with( + test_binary_reg_imm_lhs_with( WASM_OP, f32::NEG_INFINITY, [Instruction::ReturnImm32 { @@ -64,7 +64,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f32::NAN, [Instruction::return_imm32(false)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f32::NAN, [Instruction::return_imm32(false)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/f32_le.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/f32_le.rs index 977cccae1f..6bfd7e3f23 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/f32_le.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/f32_le.rs @@ -26,8 +26,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 1.0_f32, Instruction::f32_le) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 1.0_f32, Instruction::f32_le) } #[test] @@ -39,7 +39,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f32::NAN, [Instruction::return_imm32(false)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f32::NAN, [Instruction::return_imm32(false)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/f32_lt.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/f32_lt.rs index d384d96eab..d451ed8d4f 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/f32_lt.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/f32_lt.rs @@ -25,8 +25,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 1.0_f32, Instruction::f32_lt) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 1.0_f32, Instruction::f32_lt) } #[test] @@ -45,7 +45,7 @@ fn reg_neg_inf() { #[test] #[cfg_attr(miri, ignore)] fn pos_inf_reg() { - test_binary_reg_imm_rev_with( + test_binary_reg_imm_lhs_with( WASM_OP, f32::INFINITY, [Instruction::ReturnImm32 { @@ -64,7 +64,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f32::NAN, [Instruction::return_imm32(false)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f32::NAN, [Instruction::return_imm32(false)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/f32_ne.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/f32_ne.rs index 44ad2bc203..3c8ccaf6c1 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/f32_ne.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/f32_ne.rs @@ -27,8 +27,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, 1.0_f32, Instruction::f32_ne) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, 1.0_f32, Instruction::f32_ne) } #[test] @@ -40,7 +40,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f32::NAN, [Instruction::return_imm32(true)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f32::NAN, [Instruction::return_imm32(true)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/f64_eq.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/f64_eq.rs index 9de11e957d..4ff04dd38e 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/f64_eq.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/f64_eq.rs @@ -27,8 +27,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, 1.0_f64, Instruction::f64_eq) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, 1.0_f64, Instruction::f64_eq) } #[test] @@ -40,7 +40,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f64::NAN, [Instruction::return_imm32(false)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f64::NAN, [Instruction::return_imm32(false)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/f64_ge.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/f64_ge.rs index b01d47854d..eecc59802c 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/f64_ge.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/f64_ge.rs @@ -26,8 +26,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 1.0, Instruction::f64_ge) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 1.0, Instruction::f64_ge) } #[test] @@ -39,7 +39,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f64::NAN, [Instruction::return_imm32(false)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f64::NAN, [Instruction::return_imm32(false)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/f64_gt.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/f64_gt.rs index c6066ffc5a..41cf72cdbf 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/f64_gt.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/f64_gt.rs @@ -25,8 +25,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 1.0, Instruction::f64_gt) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 1.0, Instruction::f64_gt) } #[test] @@ -45,7 +45,7 @@ fn reg_pos_inf() { #[test] #[cfg_attr(miri, ignore)] fn neg_inf_reg() { - test_binary_reg_imm_rev_with( + test_binary_reg_imm_lhs_with( WASM_OP, f64::NEG_INFINITY, [Instruction::ReturnImm32 { @@ -64,7 +64,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f64::NAN, [Instruction::return_imm32(false)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f64::NAN, [Instruction::return_imm32(false)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/f64_le.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/f64_le.rs index 1f2a045bac..0277923bbc 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/f64_le.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/f64_le.rs @@ -26,8 +26,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 1.0_f64, Instruction::f64_le) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 1.0_f64, Instruction::f64_le) } #[test] @@ -39,7 +39,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f64::NAN, [Instruction::return_imm32(false)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f64::NAN, [Instruction::return_imm32(false)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/f64_lt.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/f64_lt.rs index 231eea605c..0122f62358 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/f64_lt.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/f64_lt.rs @@ -25,8 +25,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 1.0_f64, Instruction::f64_lt) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 1.0_f64, Instruction::f64_lt) } #[test] @@ -45,7 +45,7 @@ fn reg_neg_inf() { #[test] #[cfg_attr(miri, ignore)] fn pos_inf_reg() { - test_binary_reg_imm_rev_with( + test_binary_reg_imm_lhs_with( WASM_OP, f64::INFINITY, [Instruction::ReturnImm32 { @@ -64,7 +64,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f64::NAN, [Instruction::return_imm32(false)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f64::NAN, [Instruction::return_imm32(false)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/f64_ne.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/f64_ne.rs index c955e30326..efd170b80e 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/f64_ne.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/f64_ne.rs @@ -27,8 +27,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, 1.0_f64, Instruction::f64_ne) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, 1.0_f64, Instruction::f64_ne) } #[test] @@ -40,7 +40,7 @@ fn reg_nan() { #[test] #[cfg_attr(miri, ignore)] fn nan_reg() { - test_binary_reg_imm_rev_with(WASM_OP, f64::NAN, [Instruction::return_imm32(true)]).run() + test_binary_reg_imm_lhs_with(WASM_OP, f64::NAN, [Instruction::return_imm32(true)]).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_eq.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_eq.rs index c0cf6a90d4..d789f44bff 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_eq.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_eq.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_eq_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_eq_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_eq_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_eq_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, i32::MAX, Instruction::i32_eq) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, i32::MAX, Instruction::i32_eq) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_ge_s.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_ge_s.rs index 5c3a1521de..5284659b3f 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_ge_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_ge_s.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_ge_s_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_ge_s_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_le_s_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_le_s_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i32_ge_s) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i32_ge_s) } #[test] @@ -56,7 +56,7 @@ fn max_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(true), }]; - test_binary_reg_imm_rev_with(WASM_OP, i32::MAX, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, i32::MAX, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_ge_u.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_ge_u.rs index 8ef79c6048..231e073f92 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_ge_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_ge_u.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_ge_u_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_ge_u_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_le_u_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_le_u_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i32_ge_u) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i32_ge_u) } #[test] @@ -56,7 +56,7 @@ fn max_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(true), }]; - test_binary_reg_imm_rev_with(WASM_OP, u32::MAX, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, u32::MAX, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_gt_s.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_gt_s.rs index 3ce425a31d..597e1de7d7 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_gt_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_gt_s.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_gt_s_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_gt_s_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_lt_s_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_lt_s_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i32_gt_s) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i32_gt_s) } #[test] @@ -56,7 +56,7 @@ fn min_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(false), }]; - test_binary_reg_imm_rev_with(WASM_OP, i32::MIN, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, i32::MIN, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_gt_u.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_gt_u.rs index 1a6d2a34dc..01efad216b 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_gt_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_gt_u.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_gt_u_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_gt_u_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_lt_u_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_lt_u_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i32_gt_u) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i32_gt_u) } #[test] @@ -56,7 +56,7 @@ fn min_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(false), }]; - test_binary_reg_imm_rev_with(WASM_OP, u32::MIN, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, u32::MIN, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_le_s.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_le_s.rs index 6a1859882e..c1de9e91f0 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_le_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_le_s.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_le_s_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_le_s_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_ge_s_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_ge_s_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i32_le_s) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i32_le_s) } #[test] @@ -56,7 +56,7 @@ fn min_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(true), }]; - test_binary_reg_imm_rev_with(WASM_OP, i32::MIN, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, i32::MIN, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_le_u.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_le_u.rs index 3619a03274..91befcd1b3 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_le_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_le_u.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_le_u_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_le_u_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_ge_u_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_ge_u_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i32_le_u) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i32_le_u) } #[test] @@ -56,7 +56,7 @@ fn min_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(true), }]; - test_binary_reg_imm_rev_with(WASM_OP, u32::MIN, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, u32::MIN, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_lt_s.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_lt_s.rs index 9f2fecaae1..f845cbbbba 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_lt_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_lt_s.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_lt_s_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_lt_s_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_gt_s_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_gt_s_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i32_lt_s) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i32_lt_s) } #[test] @@ -56,7 +56,7 @@ fn max_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(false), }]; - test_binary_reg_imm_rev_with(WASM_OP, i32::MAX, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, i32::MAX, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_lt_u.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_lt_u.rs index 5e668fdd66..14dc089fa4 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_lt_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_lt_u.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_lt_u_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_lt_u_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_gt_u_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_gt_u_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i32_lt_u) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i32_lt_u) } #[test] @@ -56,7 +56,7 @@ fn max_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(false), }]; - test_binary_reg_imm_rev_with(WASM_OP, u32::MAX, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, u32::MAX, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_ne.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_ne.rs index 1ea0f52d99..93de6bf96a 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i32_ne.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i32_ne.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i32_ne_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i32_ne_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i32_ne_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i32_ne_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, i32::MAX, Instruction::i32_ne) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, i32::MAX, Instruction::i32_ne) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_eq.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_eq.rs index fa034bb4d4..e045628d54 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_eq.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_eq.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_eq_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_eq_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_eq_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_eq_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, i64::MAX, Instruction::i64_eq) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, i64::MAX, Instruction::i64_eq) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_ge_s.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_ge_s.rs index 53049adbd5..a976487312 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_ge_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_ge_s.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_ge_s_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_ge_s_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_le_s_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_le_s_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i64_ge_s) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i64_ge_s) } #[test] @@ -56,7 +56,7 @@ fn max_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(true), }]; - test_binary_reg_imm_rev_with(WASM_OP, i64::MAX, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, i64::MAX, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_ge_u.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_ge_u.rs index 839e3cc854..2bb199f421 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_ge_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_ge_u.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_ge_u_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_ge_u_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_le_u_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_le_u_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i64_ge_u) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i64_ge_u) } #[test] @@ -56,7 +56,7 @@ fn max_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(true), }]; - test_binary_reg_imm_rev_with(WASM_OP, u64::MAX, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, u64::MAX, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_gt_s.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_gt_s.rs index 7316e80d54..bd704d15ba 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_gt_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_gt_s.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_gt_s_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_gt_s_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_lt_s_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_lt_s_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i64_gt_s) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i64_gt_s) } #[test] @@ -56,7 +56,7 @@ fn min_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(false), }]; - test_binary_reg_imm_rev_with(WASM_OP, i64::MIN, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, i64::MIN, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_gt_u.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_gt_u.rs index 46313993bf..a296a1f9bd 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_gt_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_gt_u.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_gt_u_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_gt_u_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_lt_u_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_lt_u_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i64_gt_u) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i64_gt_u) } #[test] @@ -56,7 +56,7 @@ fn min_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(false), }]; - test_binary_reg_imm_rev_with(WASM_OP, u64::MIN, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, u64::MIN, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_le_s.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_le_s.rs index dc467a9967..df6c5b7c30 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_le_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_le_s.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_le_s_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_le_s_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_ge_s_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_ge_s_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i64_le_s) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i64_le_s) } #[test] @@ -56,7 +56,7 @@ fn min_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(true), }]; - test_binary_reg_imm_rev_with(WASM_OP, i64::MIN, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, i64::MIN, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_le_u.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_le_u.rs index 5502e8ff4b..8db2dd1fd7 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_le_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_le_u.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_le_u_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_le_u_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_ge_u_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_ge_u_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i64_le_u) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i64_le_u) } #[test] @@ -56,7 +56,7 @@ fn min_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(true), }]; - test_binary_reg_imm_rev_with(WASM_OP, u64::MIN, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, u64::MIN, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_lt_s.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_lt_s.rs index d05392a079..6c193b5fa0 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_lt_s.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_lt_s.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_lt_s_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_lt_s_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_gt_s_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_gt_s_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i64_lt_s) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i64_lt_s) } #[test] @@ -56,7 +56,7 @@ fn max_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(false), }]; - test_binary_reg_imm_rev_with(WASM_OP, i64::MAX, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, i64::MAX, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_lt_u.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_lt_u.rs index 080a0f89c9..ef59089bbd 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_lt_u.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_lt_u.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_lt_u_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_lt_u_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_gt_u_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_gt_u_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev(WASM_OP, 100_000, Instruction::i64_lt_u) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs(WASM_OP, 100_000, Instruction::i64_lt_u) } #[test] @@ -56,7 +56,7 @@ fn max_reg() { let expected = [Instruction::ReturnImm32 { value: AnyConst32::from(false), }]; - test_binary_reg_imm_rev_with(WASM_OP, u64::MAX, expected).run() + test_binary_reg_imm_lhs_with(WASM_OP, u64::MAX, expected).run() } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_ne.rs b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_ne.rs index b6a1c89602..823095dc30 100644 --- a/crates/wasmi/src/engine/translator/tests/op/cmp/i64_ne.rs +++ b/crates/wasmi/src/engine/translator/tests/op/cmp/i64_ne.rs @@ -20,13 +20,13 @@ fn reg_reg() { #[test] #[cfg_attr(miri, ignore)] fn reg_imm16() { - test_binary_reg_imm16::(WASM_OP, 100, Instruction::i64_ne_imm16) + test_binary_reg_imm16_rhs::(WASM_OP, 100, Instruction::i64_ne_imm16) } #[test] #[cfg_attr(miri, ignore)] -fn reg_imm16_rev() { - test_binary_reg_imm16_rev::(WASM_OP, 100, swap_ops!(Instruction::i64_ne_imm16)) +fn reg_imm16_lhs() { + test_binary_reg_imm16_lhs::(WASM_OP, 100, swap_ops!(Instruction::i64_ne_imm16)) } #[test] @@ -37,8 +37,8 @@ fn reg_imm() { #[test] #[cfg_attr(miri, ignore)] -fn reg_imm_rev() { - test_binary_reg_imm32_rev_commutative(WASM_OP, i64::MAX, Instruction::i64_ne) +fn reg_imm_lhs() { + test_binary_reg_imm32_lhs_commutative(WASM_OP, i64::MAX, Instruction::i64_ne) } #[test] diff --git a/crates/wasmi/src/engine/translator/tests/op/local_set.rs b/crates/wasmi/src/engine/translator/tests/op/local_set.rs index 0971eed04e..93c7b19d6f 100644 --- a/crates/wasmi/src/engine/translator/tests/op/local_set.rs +++ b/crates/wasmi/src/engine/translator/tests/op/local_set.rs @@ -468,7 +468,7 @@ fn merge_overwriting_local_set() { #[test] #[cfg_attr(miri, ignore)] -fn merge_overwriting_local_set_rev() { +fn merge_overwriting_local_set_lhs() { let wasm = r" (module (func (result i32) @@ -526,7 +526,7 @@ fn merge_overwriting_local_set_3() { #[test] #[cfg_attr(miri, ignore)] -fn merge_overwriting_local_set_3_rev() { +fn merge_overwriting_local_set_3_lhs() { let wasm = r" (module (func (result i32) diff --git a/crates/wasmi/src/engine/translator/tests/op/mod.rs b/crates/wasmi/src/engine/translator/tests/op/mod.rs index 31f5bc7c8e..922171b2d2 100644 --- a/crates/wasmi/src/engine/translator/tests/op/mod.rs +++ b/crates/wasmi/src/engine/translator/tests/op/mod.rs @@ -30,12 +30,12 @@ use super::{ driver::ExpectedFunc, swap_ops, test_binary_consteval, - test_binary_reg_imm16, - test_binary_reg_imm16_rev, + test_binary_reg_imm16_lhs, + test_binary_reg_imm16_rhs, test_binary_reg_imm32, - test_binary_reg_imm32_rev, - test_binary_reg_imm32_rev_commutative, - test_binary_reg_imm_rev_with, + test_binary_reg_imm32_lhs, + test_binary_reg_imm32_lhs_commutative, + test_binary_reg_imm_lhs_with, test_binary_reg_imm_with, test_binary_reg_reg, test_binary_same_reg, diff --git a/crates/wasmi/src/engine/translator/tests/op/return_call/imported.rs b/crates/wasmi/src/engine/translator/tests/op/return_call/imported.rs index 023100facb..cb1d5c45f5 100644 --- a/crates/wasmi/src/engine/translator/tests/op/return_call/imported.rs +++ b/crates/wasmi/src/engine/translator/tests/op/return_call/imported.rs @@ -79,7 +79,7 @@ fn two_params_reg() { #[test] #[cfg_attr(miri, ignore)] -fn two_params_reg_rev() { +fn two_params_reg_lhs() { let wasm = r#" (module (import "env" "f" (func $f (param i32 i32) (result i32 i32))) @@ -139,7 +139,7 @@ fn three_params_reg() { #[test] #[cfg_attr(miri, ignore)] -fn three_params_reg_rev() { +fn three_params_reg_lhs() { let wasm = r#" (module (import "env" "f" (func $f (param i32 i32 i32) (result i32 i32 i32))) @@ -209,7 +209,7 @@ fn params7_reg() { #[test] #[cfg_attr(miri, ignore)] -fn params7_reg_rev() { +fn params7_reg_lhs() { let wasm = r#" (module (import "env" "f" (func $f (param i32 i32 i32 i32 i32 i32 i32) (result i32 i32 i32 i32 i32 i32 i32))) @@ -300,7 +300,7 @@ fn params8_reg() { #[test] #[cfg_attr(miri, ignore)] -fn params8_reg_rev() { +fn params8_reg_lhs() { let wasm = r#" (module (import "env" "f" (func $f (param i32 i32 i32 i32 i32 i32 i32 i32) (result i32 i32 i32 i32 i32 i32 i32 i32))) @@ -394,7 +394,7 @@ fn params9_reg() { #[test] #[cfg_attr(miri, ignore)] -fn params9_reg_rev() { +fn params9_reg_lhs() { let wasm = r#" (module (import "env" "f" (func $f (param i32 i32 i32 i32 i32 i32 i32 i32 i32) (result i32 i32 i32 i32 i32 i32 i32 i32 i32))) diff --git a/crates/wasmi/src/engine/translator/tests/op/return_call/indirect.rs b/crates/wasmi/src/engine/translator/tests/op/return_call/indirect.rs index 7137d6ce7e..1c115a1ec7 100644 --- a/crates/wasmi/src/engine/translator/tests/op/return_call/indirect.rs +++ b/crates/wasmi/src/engine/translator/tests/op/return_call/indirect.rs @@ -263,7 +263,7 @@ fn two_reg_params_reg() { #[test] #[cfg_attr(miri, ignore)] -fn two_reg_params_reg_rev() { +fn two_reg_params_reg_lhs() { let wasm = r#" (module (import "" "table" (table $table 10 funcref)) @@ -350,7 +350,7 @@ fn two_reg_params_imm16() { #[test] #[cfg_attr(miri, ignore)] -fn two_reg_params_rev_imm16() { +fn two_reg_params_lhs_imm16() { fn test_with(index: u32) { let wasm = format!( r#" @@ -447,7 +447,7 @@ fn three_reg_params_reg() { #[test] #[cfg_attr(miri, ignore)] -fn three_reg_params_reg_rev() { +fn three_reg_params_reg_lhs() { let wasm = r#" (module (import "" "table" (table $table 10 funcref)) diff --git a/crates/wasmi/src/engine/translator/tests/op/return_call/internal.rs b/crates/wasmi/src/engine/translator/tests/op/return_call/internal.rs index b26b57b28f..b1b9f8b2d2 100644 --- a/crates/wasmi/src/engine/translator/tests/op/return_call/internal.rs +++ b/crates/wasmi/src/engine/translator/tests/op/return_call/internal.rs @@ -90,7 +90,7 @@ fn two_params_reg() { #[test] #[cfg_attr(miri, ignore)] -fn two_params_reg_rev() { +fn two_params_reg_lhs() { let wasm = r#" (module (func $f (param i32 i32) (result i32 i32) @@ -163,7 +163,7 @@ fn three_params_reg() { #[test] #[cfg_attr(miri, ignore)] -fn three_params_reg_rev() { +fn three_params_reg_lhs() { let wasm = r#" (module (func $f (param i32 i32 i32) (result i32 i32 i32) @@ -252,7 +252,7 @@ fn params7_reg() { #[test] #[cfg_attr(miri, ignore)] -fn params7_reg_rev() { +fn params7_reg_lhs() { let wasm = r#" (module (func $f (param i32 i32 i32 i32 i32 i32 i32) (result i32 i32 i32 i32 i32 i32 i32) @@ -371,7 +371,7 @@ fn params8_reg() { #[test] #[cfg_attr(miri, ignore)] -fn params8_reg_rev() { +fn params8_reg_lhs() { let wasm = r#" (module (func $f (param i32 i32 i32 i32 i32 i32 i32 i32) (result i32 i32 i32 i32 i32 i32 i32 i32) @@ -496,7 +496,7 @@ fn params9_reg() { #[test] #[cfg_attr(miri, ignore)] -fn params9_reg_rev() { +fn params9_reg_lhs() { let wasm = r#" (module (func $f (param i32 i32 i32 i32 i32 i32 i32 i32 i32) (result i32 i32 i32 i32 i32 i32 i32 i32 i32) diff --git a/crates/wasmi/src/engine/translator/utils.rs b/crates/wasmi/src/engine/translator/utils.rs index 9a4e6ed431..c5af39d6e8 100644 --- a/crates/wasmi/src/engine/translator/utils.rs +++ b/crates/wasmi/src/engine/translator/utils.rs @@ -12,56 +12,29 @@ use crate::{ pub trait WasmInteger: Copy + Eq + From + Into + TryInto> { - /// Returns the `i16` shift amount. - /// - /// This computes `self % bitwsize` and returns the result as `i16` value. - /// - /// # Note - /// - /// This is commonly needed for Wasm translations of shift and rotate instructions - /// since Wasm mandates that the shift amount operand is taken modulo the bitsize - /// of the shifted value type. - fn as_shift_amount(self) -> i16; - /// Returns `true` if `self` is equal to zero (0). fn eq_zero(self) -> bool; } impl WasmInteger for i32 { - fn as_shift_amount(self) -> i16 { - (self % 32) as i16 - } - fn eq_zero(self) -> bool { self == 0 } } impl WasmInteger for u32 { - fn as_shift_amount(self) -> i16 { - (self % 32) as i16 - } - fn eq_zero(self) -> bool { self == 0 } } impl WasmInteger for i64 { - fn as_shift_amount(self) -> i16 { - (self % 64) as i16 - } - fn eq_zero(self) -> bool { self == 0 } } impl WasmInteger for u64 { - fn as_shift_amount(self) -> i16 { - (self % 64) as i16 - } - fn eq_zero(self) -> bool { self == 0 } diff --git a/crates/wasmi/src/engine/translator/visit.rs b/crates/wasmi/src/engine/translator/visit.rs index 2130e1317a..904bb5458c 100644 --- a/crates/wasmi/src/engine/translator/visit.rs +++ b/crates/wasmi/src/engine/translator/visit.rs @@ -2057,7 +2057,7 @@ impl<'a> VisitOperator<'a> for FuncTranslator { self.translate_binary( Instruction::i32_sub, |_, _, _| unreachable!("`i32.sub r c` is translated as `i32.add r -c`"), - Instruction::i32_sub_imm16_rev, + Instruction::i32_sub_imm16_lhs, TypedVal::i32_sub, |this, lhs: Reg, rhs: Reg| { if lhs == rhs { @@ -2113,8 +2113,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i32_div_s(&mut self) -> Self::Output { self.translate_divrem( Instruction::i32_div_s, - Instruction::i32_div_s_imm16, - Instruction::i32_div_s_imm16_rev, + Instruction::i32_div_s_imm16_rhs, + Instruction::i32_div_s_imm16_lhs, TypedVal::i32_div_s, Self::no_custom_opt, |this, lhs: Reg, rhs: i32| { @@ -2131,8 +2131,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i32_div_u(&mut self) -> Self::Output { self.translate_divrem::( Instruction::i32_div_u, - Instruction::i32_div_u_imm16, - Instruction::i32_div_u_imm16_rev, + Instruction::i32_div_u_imm16_rhs, + Instruction::i32_div_u_imm16_lhs, TypedVal::i32_div_u, Self::no_custom_opt, |this, lhs: Reg, rhs: u32| { @@ -2149,8 +2149,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i32_rem_s(&mut self) -> Self::Output { self.translate_divrem( Instruction::i32_rem_s, - Instruction::i32_rem_s_imm16, - Instruction::i32_rem_s_imm16_rev, + Instruction::i32_rem_s_imm16_rhs, + Instruction::i32_rem_s_imm16_lhs, TypedVal::i32_rem_s, Self::no_custom_opt, |this, _lhs: Reg, rhs: i32| { @@ -2167,8 +2167,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i32_rem_u(&mut self) -> Self::Output { self.translate_divrem::( Instruction::i32_rem_u, - Instruction::i32_rem_u_imm16, - Instruction::i32_rem_u_imm16_rev, + Instruction::i32_rem_u_imm16_rhs, + Instruction::i32_rem_u_imm16_lhs, TypedVal::i32_rem_u, Self::no_custom_opt, |this, _lhs: Reg, rhs: u32| { @@ -2273,8 +2273,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i32_shl(&mut self) -> Self::Output { self.translate_shift::( Instruction::i32_shl, - Instruction::i32_shl_imm, - Instruction::i32_shl_imm16_rev, + Instruction::i32_shl_by, + Instruction::i32_shl_imm16, TypedVal::i32_shl, Self::no_custom_opt, ) @@ -2283,8 +2283,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i32_shr_s(&mut self) -> Self::Output { self.translate_shift( Instruction::i32_shr_s, - Instruction::i32_shr_s_imm, - Instruction::i32_shr_s_imm16_rev, + Instruction::i32_shr_s_by, + Instruction::i32_shr_s_imm16, TypedVal::i32_shr_s, |this, lhs: i32, _rhs: Reg| { if lhs == -1 { @@ -2300,8 +2300,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i32_shr_u(&mut self) -> Self::Output { self.translate_shift::( Instruction::i32_shr_u, - Instruction::i32_shr_u_imm, - Instruction::i32_shr_u_imm16_rev, + Instruction::i32_shr_u_by, + Instruction::i32_shr_u_imm16, TypedVal::i32_shr_u, Self::no_custom_opt, ) @@ -2310,8 +2310,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i32_rotl(&mut self) -> Self::Output { self.translate_shift( Instruction::i32_rotl, - Instruction::i32_rotl_imm, - Instruction::i32_rotl_imm16_rev, + Instruction::i32_rotl_by, + Instruction::i32_rotl_imm16, TypedVal::i32_rotl, |this, lhs: i32, _rhs: Reg| { if lhs == -1 { @@ -2327,8 +2327,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i32_rotr(&mut self) -> Self::Output { self.translate_shift( Instruction::i32_rotr, - Instruction::i32_rotr_imm, - Instruction::i32_rotr_imm16_rev, + Instruction::i32_rotr_by, + Instruction::i32_rotr_imm16, TypedVal::i32_rotr, |this, lhs: i32, _rhs: Reg| { if lhs == -1 { @@ -2374,7 +2374,7 @@ impl<'a> VisitOperator<'a> for FuncTranslator { self.translate_binary( Instruction::i64_sub, |_, _, _| unreachable!("`i64.sub r c` is translated as `i64.add r -c`"), - Instruction::i64_sub_imm16_rev, + Instruction::i64_sub_imm16_lhs, TypedVal::i64_sub, |this, lhs: Reg, rhs: Reg| { if lhs == rhs { @@ -2430,8 +2430,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i64_div_s(&mut self) -> Self::Output { self.translate_divrem( Instruction::i64_div_s, - Instruction::i64_div_s_imm16, - Instruction::i64_div_s_imm16_rev, + Instruction::i64_div_s_imm16_rhs, + Instruction::i64_div_s_imm16_lhs, TypedVal::i64_div_s, Self::no_custom_opt, |this, lhs: Reg, rhs: i64| { @@ -2448,8 +2448,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i64_div_u(&mut self) -> Self::Output { self.translate_divrem::( Instruction::i64_div_u, - Instruction::i64_div_u_imm16, - Instruction::i64_div_u_imm16_rev, + Instruction::i64_div_u_imm16_rhs, + Instruction::i64_div_u_imm16_lhs, TypedVal::i64_div_u, Self::no_custom_opt, |this, lhs: Reg, rhs: u64| { @@ -2466,8 +2466,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i64_rem_s(&mut self) -> Self::Output { self.translate_divrem( Instruction::i64_rem_s, - Instruction::i64_rem_s_imm16, - Instruction::i64_rem_s_imm16_rev, + Instruction::i64_rem_s_imm16_rhs, + Instruction::i64_rem_s_imm16_lhs, TypedVal::i64_rem_s, Self::no_custom_opt, |this, _lhs: Reg, rhs: i64| { @@ -2484,8 +2484,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i64_rem_u(&mut self) -> Self::Output { self.translate_divrem::( Instruction::i64_rem_u, - Instruction::i64_rem_u_imm16, - Instruction::i64_rem_u_imm16_rev, + Instruction::i64_rem_u_imm16_rhs, + Instruction::i64_rem_u_imm16_lhs, TypedVal::i64_rem_u, Self::no_custom_opt, |this, _lhs: Reg, rhs: u64| { @@ -2590,8 +2590,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i64_shl(&mut self) -> Self::Output { self.translate_shift::( Instruction::i64_shl, - Instruction::i64_shl_imm, - Instruction::i64_shl_imm16_rev, + Instruction::i64_shl_by, + Instruction::i64_shl_imm16, TypedVal::i64_shl, Self::no_custom_opt, ) @@ -2600,8 +2600,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i64_shr_s(&mut self) -> Self::Output { self.translate_shift( Instruction::i64_shr_s, - Instruction::i64_shr_s_imm, - Instruction::i64_shr_s_imm16_rev, + Instruction::i64_shr_s_by, + Instruction::i64_shr_s_imm16, TypedVal::i64_shr_s, |this, lhs: i64, _rhs: Reg| { if lhs == -1 { @@ -2617,8 +2617,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i64_shr_u(&mut self) -> Self::Output { self.translate_shift::( Instruction::i64_shr_u, - Instruction::i64_shr_u_imm, - Instruction::i64_shr_u_imm16_rev, + Instruction::i64_shr_u_by, + Instruction::i64_shr_u_imm16, TypedVal::i64_shr_u, Self::no_custom_opt, ) @@ -2627,8 +2627,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i64_rotl(&mut self) -> Self::Output { self.translate_shift( Instruction::i64_rotl, - Instruction::i64_rotl_imm, - Instruction::i64_rotl_imm16_rev, + Instruction::i64_rotl_by, + Instruction::i64_rotl_imm16, TypedVal::i64_rotl, |this, lhs: i64, _rhs: Reg| { if lhs == -1 { @@ -2644,8 +2644,8 @@ impl<'a> VisitOperator<'a> for FuncTranslator { fn visit_i64_rotr(&mut self) -> Self::Output { self.translate_shift( Instruction::i64_rotr, - Instruction::i64_rotr_imm, - Instruction::i64_rotr_imm16_rev, + Instruction::i64_rotr_by, + Instruction::i64_rotr_imm16, TypedVal::i64_rotr, |this, lhs: i64, _rhs: Reg| { if lhs == -1 {