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FYI: if this project tries to bump to Chisel 7, which now includes default layers, there will be problems with how the FMATester.scala generates Verilog here:
With default layers always being there, then doing this may create an invalid single-file Verilog file that has `include directives pointing at directories/files which don't exist.
This can either be fixed by changing the ChiselStage invocation to include -enable-layers arguments that specialize away the default layers or this invocation could be changed to use one-file-per-module output and changing the Verilator invocation to properly setup +incdir pointing at the output directory.
The text was updated successfully, but these errors were encountered:
FYI: if this project tries to bump to Chisel 7, which now includes default layers, there will be problems with how the FMATester.scala generates Verilog here:
berkeley-hardfloat/hardfloat/tests/src/FMATester.scala
Line 61 in 26f00d0
With default layers always being there, then doing this may create an invalid single-file Verilog file that has
`include
directives pointing at directories/files which don't exist.This can either be fixed by changing the ChiselStage invocation to include
-enable-layers
arguments that specialize away the default layers or this invocation could be changed to use one-file-per-module output and changing the Verilator invocation to properly setup+incdir
pointing at the output directory.The text was updated successfully, but these errors were encountered: