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fix: ftdi_write_data, ftdi_set_bitmode, not used bits must be set to 1 #8
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@tmbinc Current --- a/src/io_ftdi.c
+++ b/src/io_ftdi.c
@@ -15,6 +15,7 @@
#define PORT_TMS 0x08
#define PORT_MISC 0x90
#define IO_OUTPUT (PORT_MISC|PORT_TCK|PORT_TDI|PORT_TMS)
+#define IO_MASK 0xF0
#define IO_DEFAULT_OUT (0xe0) /* Found to work best for some FTDI implementations */
@@ -131,7 +132,7 @@
}
ftdi_set_bitmode(&ftdi, 0xFF, BITMODE_CBUS);
- res = ftdi_set_bitmode(&ftdi, IO_OUTPUT, BITMODE_SYNCBB);
+ res = ftdi_set_bitmode(&ftdi, IO_MASK | IO_OUTPUT, BITMODE_SYNCBB);
if (res < 0)
{
@@ -226,6 +227,7 @@
v |= PORT_TMS;
if (TDI[i/8] & (1<<(i&7)))
v |= PORT_TDI;
+ v |= IO_MASK;
buffer[i * 2 + 0] = v;
buffer[i * 2 + 1] = v | PORT_TCK;
} |
I can confirm that the version from the above diff works with an Arty A7 100, but the version in the repo does not. |
@davidchisnall @SuibianP thanks for testing the change. I unfortunately don't have a board that requires this so I can't test it. What the change essentially is doing is to configure more pins as output (
This should be equivalent to the following change:
@davidchisnall any chance you can see if this is indeed equivalent or whether I messed up something in my head? Unfortunately, Sheet #10 in the arty schematics (https://digilent.com/reference/_media/programmable-logic/arty-a7/arty-a7-e2-sch.pdf), which contains the relevant circuit ("USB PROG/UART") is "intentionally left blank", and I couldn't find the relevant snippet in any other official schematics. The risk is that we're driving an IO pin that is an input. But honestly that risk is already there for the other bits, so I'm tempted to merge this if it solves a problem. Best action is probably to make this dynamic per config/command line, as it's really board-specific. E.g. mithro's
where 0x88 is the initial output value (our "IO_DEFAULT_OUT"), and 0x8b the default direction ("IO_OUTPUT"). Is the issue that we're driving bit 4 low, whereas it is floating and should be left floating or driven high? Would |
Thanks (hi @tmbinc , it's been a while!), that also works for me. |
(Hi as well!) Thank you so much for testing! To clarify - did you test PORT_MISC=0xF0/IO_DEFAULT_OUT=0xF0 (the diff above) or also PORT_MISC=0x80 DEFAULT_OUT=0x80 (or 0x8B, shouldn't matter here), i.e. the |
I tested your diff, not the arty cfg change. I can do the latter this morning. |
Hi,
I was testing your code with the following setup and it did not work.
Vivado did connect to xvcd server but it did not recognize the FPGA. Vivado error:
I connected scope to JTAG TDI pin and it stayed high for the whole time. Although the TDI (from verbose) was saying that it did set TDI to some value. verbose TDO was 1 all the time.
I applied the following fix to io_ftdi.c:
When using ftdi_write_data, buf must have top 4 bits set to 1 and you must not mask those same bit out when using ftdi_set_bitmode.
With the above fix, I am now able to program FPGA and connect to it with chipscope with Vivado.
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