Misaligned fetch bit must be excluded for RVC

[as-sc]

https://github.com/riscv/riscv-compliance/blob/8dac5e5d3d498eaf576611ce69c2307968cf96e3/riscv-test-env/p/riscv_test.h#L159

This is the same as riscv/riscv-test-env#12

[allenjbaum]

I don't see why it "must" be excluded; if misaligned fetch isn't possible, then either the mdeleg bit is rdonly-0, or the exception never occurs so the fact that you've delegated it is harmless. Do you disagree with this?

[pdonahue-ventana]

I somehow didn't see this so I filed a duplicate of this the other day:
riscv/riscv-test-env#17

I don't see why it "must" be excluded; if misaligned fetch isn't possible, then either the mdeleg bit is rdonly-0, or the exception never occurs so the fact that you've delegated it is harmless. Do you disagree with this?

I think that the original issue description here was unnecessarily terse. The problem is that the reset code is self-checking and fails if mdeleg[0] is read-only (which you say should be allowable). Much more discussion is in my duplicate issue.

[neelgala]

the new tests from imperas now use a different header file: riscv_tests_macros.h which doesnt impose such reset vectors. Also privilege tests checking traps would probably have specific handlers described within the tests.

[neelgala]

closing this for now. Feel free to open if you disagree. Also this is fixed in RISCOF as well.