diff --git a/CHANGELOG.md b/CHANGELOG.md index e423d1ac9..855e62b19 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -13,6 +13,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. - `axi_lite_to_apb`: Make pipeline registers on request and response path optional (can be enabled with the new `PipelineRequest` and `PipelineResponse` `parameter`s), and disable those pipeline registers by default. +- `axi_xbar`: Flatten and update parameter and ports according to (#153). Add inline documentation. + - Remove `doc/axi_xbar.md`. + - Move `doc/svg/axi_xbar.svg` and `doc/axi_xbar.png` to `docs/`. ### Fixed diff --git a/doc/axi_xbar.md b/doc/axi_xbar.md deleted file mode 100644 index 98770c533..000000000 --- a/doc/axi_xbar.md +++ /dev/null @@ -1,108 +0,0 @@ -# AXI4+ATOP Fully-Connected Crossbar - -`axi_xbar` is a fully-connected crossbar that implements the full AXI4 specification plus atomic operations (ATOPs) from AXI5. - - -## Design Overview - -`axi_xbar` is a fully-connected crossbar, which means that each master module that is connected to a *slave port* for of the crossbar has direct wires to all slave modules that are connected to the *master ports* of the crossbar. -A block-diagram of the crossbar is shown below: - -![Block-diagram showing the design of the full AXI4 Crossbar.](axi_xbar.png "Block-diagram showing the design of the full AXI4 Crossbar.") - -The crossbar has a configurable number of slave and master ports. - -The ID width of the master ports is wider than that of the slave ports. The additional ID bits are used by the internal multiplexers to route responses. The ID width of the master ports must be `AxiIdWidthSlvPorts + $clog_2(NoSlvPorts)`. - - -## Address Map - -One address map is shared by all master ports. The *address map* contains an arbitrary number of rules (but at least one). Each *rule* maps one address range to one master port. Multiple rules can map to the same master port. The address ranges of two rules may overlap: in case two address ranges overlap, the rule at the higher (more significant) position in the address map prevails. - -Each address range includes the start address but does **not** include the end address. That is, an address *matches* an address range if and only if -``` - addr >= start_addr && addr < end_addr -``` -The start address must be less than or equal to the end address. - -The address map can be defined and changed at run time (it is an input signal to the crossbar). However, the address map must not be changed while any AW or AR channel of any slave port is valid. - - -## Decode Errors and Default Slave Port - -Each slave port has its own internal *decode error slave* module. If the address of a transaction does not match any rule, the transaction is routed to that decode error slave module. That module absorbs each transaction and responds with a decode error (with the proper number of beats). The data of each read response beat is `32'hBADCAB1E` (zero-extended or truncated to match the data width). - -Each slave port can have a default master port. If the default master port is enabled for a slave port, any address on that slave port that does not match any rule is routed to the default master port instead of the decode error slave. The default master port can be enabled and changed at run time (it is an input signal to the crossbar), and the same restrictions as for the address map apply. - - -## Configuration - -The crossbar is configured through the `Cfg` parameter with a `axi_pkg::xbar_cfg_t` struct. That struct has the following fields: - -| Name | Type | Definition | -|:---------------------|:-------------------|:-----------| -| `NoSlvPorts` | `int unsigned` | The number of AXI slave ports of the crossbar (in other words, how many AXI master modules can be attached). | -| `NoMstPorts` | `int unsigned` | The number of AXI master ports of the crossbar (in other words, how many AXI slave modules can be attached). | -| `MaxMstTrans` | `int unsigned` | Each slave port can have at most this many transactions [in flight](../doc#in-flight). | -| `MaxSlvTrans` | `int unsigned` | Each master port can have at most this many transactions per ID [in flight](../doc#in-flight). | -| `FallThrough` | `bit` | Routing decisions on the AW channel fall through to the W channel. Enabling this allows the crossbar to accept a W beat in the same cycle as the corresponding AW beat, but it increases the combinatorial path of the W channel with logic from the AW channel. | -| `LatencyMode` | `enum logic [9:0]` | Latency on the individual channels, defined in detail in section *Pipelining and Latency* below. | -| `AxiIdWidthSlvPorts` | `int unsigned` | The AXI ID width of the slave ports. | -| `AxiIdUsedSlvPorts` | `int unsigned` | The number of slave port ID bits (starting at the least significant) the crossbar uses to determine the uniqueness of an AXI ID (see section *Ordering and Stalls* below). This value has to be less or equal than `AxiIdWidthSlvPorts`. | -| `AxiAddrWidth` | `int unsigned` | The AXI address width. | -| `AxiDataWidth` | `int unsigned` | The AXI data width. | -| `NoAddrRules` | `int unsigned` | The number of address map rules. | - -The other parameters are types to define the ports of the crossbar. The `*_chan_t` and `*_req_t`/`*_resp_t` types must be bound in accordance to the configuration with the `AXI_TYPEDEF` macros defined in `axi/typedef.svh`. The `rule_t` type must be bound to an address decoding rule with the same address width as in the configuration, and `axi_pkg` contains definitions for 64- and 32-bit addresses. - -### Pipelining and Latency - -The `LatencyMode` parameter allows to insert spill registers after each channel (AW, W, B, AR, and R) of each master port (i.e., each multiplexer) and before each channel of each slave port (i.e., each demultiplexer). Spill registers cut combinatorial paths, so this parameter reduces the length of combinatorial paths through the crossbar. - -Some common configurations are given in the `xbar_latency_e` `enum`. The recommended configuration (`CUT_ALL_AX`) is to have a latency of 2 on the AW and AR channels because these channels have the most combinatorial logic on them. Additionally, `FallThrough` should be set to `0` to prevent logic on the AW channel from extending combinatorial paths on the W channel. However, it is possible to run the crossbar in a fully combinatorial configuration by setting `LatencyMode` to `NO_LATENCY` and `FallThrough` to `1`. - -If two crossbars are connected in both directions, meaning both have one of their master ports connected to a slave port of the other, the `LatencyMode` of both crossbars must be set to either `CUT_SLV_PORTS`, `CUT_MST_PORTS`, or `CUT_ALL_PORTS`. Any other latency mode will lead to timing loops on the uncut channels between the two crossbars. The latency mode of the two crossbars does not have to be identical. - - -## Ports - -| Name | Description | -|:------------------------|:------------| -| `clk_i` | Clock to which all other signals (except `rst_ni`) are synchronous. | -| `rst_ni` | Reset, asynchronous, active-low. | -| `test_i` | Test mode enable (active-high). | -| `slv_ports_*` | Array of slave ports of the crossbar. The array index of each port is the index of the slave port. This index will be prepended to all requests at one of the master ports. | -| `mst_ports_*` | Array of master ports of the crossbar. The array index of each port is the index of the master port. | -| `addr_map_i` | Address map of the crossbar (see section *Address Map* above). | -| `en_default_mst_port_i` | One bit per slave port that defines whether the default master port is active for that slave port (see section *Decode Errors and Default Slave Port* above). | -| `default_mst_port_i` | One master port index per slave port that defines the default master port for that slave port (if active). | - - -## Ordering and Stalls - -When one slave port receives two transactions with the same ID and direction (i.e., both read or both write) but targeting two different master ports, it will not accept the second transaction until the first has completed. During this time, the crossbar stalls the AR or AW channel of that slave port. To determine whether two transactions have the same ID, the `AxiIdUsedSlvPorts` least-significant bits are compared. That parameter can be set to the full `AxiIdWidthSlvPorts` to avoid false ID conflicts, or it can be set to a lower value to reduce area and delay at the cost of more false conflicts. - -The reason for this ordering constraint is that AXI transactions with the same ID and direction must remain ordered. If this crossbar would forward both transactions described above, the second master port could get a response before the first one, and the crossbar would have to reorder the responses before returning them on the master port. However, for efficiency reasons, this crossbar does not have reorder buffers. - - -## Verification Methodology - -This module has been verified with a directed random verification testbench, described and implemented in `test/tb_axi_xbar.sv`. - - -## Design Rationale for No Pipelining Inside Crossbar - -Inserting spill registers between demuxers and muxers seems attractive to further reduce the length of combinatorial paths in the crossbar. However, this can lead to deadlocks in the W channel where two different muxes at the master ports would circular wait on two different demuxes (TODO). In fact, spill registers between the switching modules causes all four deadlock criteria to be met. Recall that the criteria are: - -1. Mutual Exclusion -2. Hold and Wait -3. No Preemption -4. Circular Wait - -The first criterion is given by the nature of a multiplexer on the W channel: all W beats have to arrive in the same order as the AW beats regardless of the ID at the slave module. Thus, the different master ports of the multiplexer exclude each other because the order is given by the arbitration tree of the AW channel. - -The second and third criterion are inherent to the AXI protocol: For (2), the valid signal has to be held high until the ready signal goes high. For (3), AXI does not allow interleaving of W beats and requires W bursts to be in the same order as AW beats. - -The fourth criterion is thus the only one that can be broken to prevent deadlocks. However, inserting a spill register between a master port of the demultiplexer and a slave port of the multiplexer can lead to a circular dependency inside the W FIFOs. This comes from the particular way the round robin arbiter from the AW channel in the multiplexer defines its priorities. It is constructed in a way by giving each of its slave ports an increasing priority and then comparing pairwise down till a winner is chosen. When the winner gets transferred, the priority state is advanced by one position, preventing starvation. - -The problem can be shown with an example. Assume an arbitration tree with 10 inputs. Two requests want to be served in the same clock cycle. The one with the higher priority wins and the priority state advances. In the next cycle again the same two inputs have a request waiting. Again it is possible that the same port as last time wins as the priority shifted only one position further. This can lead in conjunction with the other arbitration trees in the other muxes of the crossbar to the circular dependencies inside the FIFOs. Removing the spill register between the demultiplexer and multiplexer forces the switching decision into the W FIFOs in the same clock cycle. This leads to a strict ordering of the switching decision, thus preventing the circular wait. diff --git a/doc/axi_xbar.png b/docs/axi_xbar.png similarity index 100% rename from doc/axi_xbar.png rename to docs/axi_xbar.png diff --git a/doc/svg/axi_xbar.svg b/docs/svg/axi_xbar.svg similarity index 100% rename from doc/svg/axi_xbar.svg rename to docs/svg/axi_xbar.svg diff --git a/scripts/run_vsim.sh b/scripts/run_vsim.sh index 3c2bd76b7..7546e8d3f 100755 --- a/scripts/run_vsim.sh +++ b/scripts/run_vsim.sh @@ -103,6 +103,26 @@ exec_test() { done done ;; + axi_xbar) + for GEN_ATOP in 0 1; do + for NUM_MST in 1 6; do + for NUM_SLV in 2 9; do + for MST_ID_USE in 3 5; do + MST_ID=5 + for DATA_WIDTH in 64 256; do + call_vsim tb_axi_xbar -t 1ns -voptargs="+acc" \ + -gTbNumMasters=$NUM_MST \ + -gTbNumSlaves=$NUM_SLV \ + -gTbAxiIdWidthMasters=$MST_ID \ + -gTbAxiIdUsed=$MST_ID_USE \ + -gTbAxiDataWidth=$DATA_WIDTH \ + -gTbEnableAtops=$GEN_ATOP + done + done + done + done + done + ;; *) call_vsim tb_$1 -t 1ns -coverage -voptargs="+acc +cover=bcesfx" ;; diff --git a/src/axi_pkg.sv b/src/axi_pkg.sv index 712e4ca34..6e0335ab6 100644 --- a/src/axi_pkg.sv +++ b/src/axi_pkg.sv @@ -393,16 +393,39 @@ package axi_pkg; /// Configuration for `axi_xbar`. typedef struct packed { + /// Number of slave ports of the crossbar. + /// This many master modules are connected to it. int unsigned NoSlvPorts; + /// Number of master ports of the crossbar. + /// This many slave modules are connected to it. int unsigned NoMstPorts; + /// Maximum number of open transactions each master connected to the crossbar can have in + /// flight at the same time. int unsigned MaxMstTrans; + /// Maximum number of open transactions each slave connected to the crossbar can have in + /// flight at the same time. int unsigned MaxSlvTrans; + /// Determine if the internal FIFOs of the crossbar are instantiated in fallthrough mode. + /// 0: No fallthrough + /// 1: Fallthrough bit FallThrough; + /// The Latency mode of the xbar. This determines if the channels on the ports have + /// a spill register instantiated. + /// Example configurations are provided with the enum `xbar_latency_e`. xbar_latency_e LatencyMode; + /// AXI ID width of the salve ports. The ID width of the master ports is determined + /// Automatically. See `axi_mux` for details. int unsigned AxiIdWidthSlvPorts; + /// The used ID portion to determine if a different salve is used for the same ID. + /// See `axi_demux` for details. int unsigned AxiIdUsedSlvPorts; + /// AXI4+ATOP address field width. int unsigned AxiAddrWidth; + /// AXI4+ATOP data field width. int unsigned AxiDataWidth; + /// The number of address rules defined for routing of the transactions. + /// Each master port can have multiple rules, should have however at least one. + /// If a transaction can not be routed the xbar will answer with an `axi_pkg::RESP_DECERR`. int unsigned NoAddrRules; } xbar_cfg_t; diff --git a/src/axi_xbar.sv b/src/axi_xbar.sv index ae1e6ecad..71ef29a82 100644 --- a/src/axi_xbar.sv +++ b/src/axi_xbar.sv @@ -13,64 +13,308 @@ // - Andreas Kurth // - Florian Zaruba -// axi_xbar: Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. -// See `doc/axi_xbar.md` for the documentation, including the definition of parameters and ports. +`include "axi/typedef.svh" + +/// Fully-connected crossbar that implements AXI4 plus atomic operations (ATOPs) from AXI5 (E1.1). +/// +/// +/// # Design Overview +/// +/// `axi_xbar` is a fully-connected crossbar, which means that each master module that is connected +/// to a *slave port* for of the crossbar has direct wires to all slave modules that are connected +/// to the *master ports* of the crossbar. +/// A block-diagram of the crossbar is shown below: +/// +/// ![Block-diagram showing the design of the full AXI4 Crossbar.](axi_xbar.png +/// "Block-diagram showing the design of the full AXI4 Crossbar.") +/// +/// The crossbar has a configurable number of slave and master ports. +/// +/// The ID width of the master ports is **wider** than that of the slave ports. The additional ID +/// bits are used by the internal multiplexers to route responses. The ID width of the master ports +/// must be `AxiIdWidthSlvPorts + $clog_2(NoSlvPorts)`. +/// +/// +/// # Address Map +/// +/// One address map is shared by all master ports. The *address map* contains an arbitrary number +/// of rules (but at least one). Each *rule* maps one address range to one master port. Multiple +/// rules can map to the same master port. The address ranges of two rules may overlap: in case two +/// address ranges overlap, the rule at the higher (more significant) position in the address map +/// prevails. +/// +/// Each address range includes the start address but does **not** include the end address. +/// That is, an address *matches* an address range if and only if +/// ``` +/// addr >= start_addr && addr < end_addr +/// ``` +/// The start address must be less than or equal to the end address. +/// +/// The address map can be defined and changed at run time (it is an input signal to the crossbar). +/// However, the address map must not be changed while any AW or AR channel of any slave port is +/// valid. +/// +/// [`addr_decode`](https://github.com/pulp-platform/common_cells/blob/master/src/addr_decode.sv) +/// module is used for decoding the address map. +/// +/// +/// # Decode Errors and Default Slave Port +/// +/// Each slave port has its own internal *decode error slave* module. If the address of a +/// transaction does not match any rule, the transaction is routed to that decode error slave +/// module. That module absorbs each transaction and responds with a decode error (with the proper +/// number of beats). The data of each read response beat is `32'hBADCAB1E` (zero-extended or +/// truncated to match the data width). +/// +/// Each slave port can have a default master port. If the default master port is enabled for a +/// slave port, any address on that slave port that does not match any rule is routed to the default +/// master port instead of the decode error slave. The default master port can be enabled and +/// changed at run time (it is an input signal to the crossbar), and the same restrictions as for +/// the address map apply. +/// +/// +/// # Ordering and Stalls +/// +/// When one slave port receives two transactions with the same ID and direction (i.e., both read or +/// both write) but targeting two different master ports, it will not accept the second transaction +/// until the first has completed. During this time, the crossbar stalls the AR or AW channel of +/// that slave port. To determine whether two transactions have the same ID, the +/// `AxiIdUsedSlvPorts` least-significant bits are compared. That parameter can be set to the full +/// `AxiIdWidthSlvPorts` to avoid false ID conflicts, or it can be set to a lower value to reduce +/// area and delay at the cost of more false conflicts. +/// +/// The reason for this ordering constraint is that AXI transactions with the same ID and direction +/// must remain ordered. If this crossbar would forward both transactions described above, the +/// second master port could get a response before the first one, and the crossbar would have to +/// reorder the responses before returning them on the master port. However, for efficiency +/// reasons, this crossbar does not have reorder buffers. +/// +/// +/// # Verification Methodology +/// +/// This module has been verified with a directed random verification testbench, described and +/// implemented in [`tb_axi_xbar`](module.tb_axi_xbar) and +/// [`tb_axi_xbar_pkg`](package.tb_axi_xbar_pkg). +/// +/// +/// # Design Rationale for No Pipelining Inside Crossbar +/// +/// Inserting spill registers between [`axi_demux`](module.axi_demux) and +/// [`axi_mux`](module.axi_mux) seems attractive to further reduce the length of combinatorial paths +/// in the crossbar. However, this can lead to deadlocks in the W channel where two different +/// [`axi_mux`](module.axi_mux) at the master ports would circular wait on two different +/// [`axi_demux`](module.axi_demux). In fact, spill registers between the switching modules causes +/// all four deadlock criteria to be met. Recall that the criteria are: +/// +/// 1. Mutual Exclusion +/// 2. Hold and Wait +/// 3. No Preemption +/// 4. Circular Wait +/// +/// The first criterion is given by the nature of a multiplexer on the W channel: all W beats have +/// to arrive in the same order as the AW beats regardless of the ID at the slave module. Thus, the +/// different master ports of the multiplexer exclude each other because the order is given by the +/// arbitration tree of the AW channel. +/// +/// The second and third criterion are inherent to the AXI protocol: For (2), the valid signal has +/// to be held high until the ready signal goes high. For (3), AXI does not allow interleaving of +/// W beats and requires W bursts to be in the same order as AW beats. +/// +/// The fourth criterion is thus the only one that can be broken to prevent deadlocks. However, +/// inserting a spill register between a master port of the [`axi_demux`](module.axi_demux) and a +/// slave port of the [`axi_mux`](module.axi_mux) can lead to a circular dependency inside the +/// W FIFOs. This comes from the particular way the round robin arbiter from the AW channel in the +/// multiplexer defines its priorities. It is constructed in a way by giving each of its slave +/// ports an increasing priority and then comparing pairwise down till a winner is chosen. When the +/// winner gets transferred, the priority state is advanced by one position, preventing starvation. +/// +/// The problem can be shown with an example. Assume an arbitration tree with 10 inputs. Two +/// requests want to be served in the same clock cycle. The one with the higher priority wins and +/// the priority state advances. In the next cycle again the same two inputs have a request +/// waiting. Again it is possible that the same port as last time wins as the priority shifted only +/// one position further. This can lead in conjunction with the other arbitration trees in the +/// other muxes of the crossbar to the circular dependencies inside the FIFOs. Removing the spill +/// register between the demultiplexer and multiplexer forces the switching decision into the +/// W FIFOs in the same clock cycle. This leads to a strict ordering of the switching decision, +/// thus preventing the circular wait. +/// module axi_xbar #( - parameter axi_pkg::xbar_cfg_t Cfg = '0, - parameter bit ATOPs = 1'b1, - parameter type slv_aw_chan_t = logic, - parameter type mst_aw_chan_t = logic, - parameter type w_chan_t = logic, - parameter type slv_b_chan_t = logic, - parameter type mst_b_chan_t = logic, - parameter type slv_ar_chan_t = logic, - parameter type mst_ar_chan_t = logic, - parameter type slv_r_chan_t = logic, - parameter type mst_r_chan_t = logic, - parameter type slv_req_t = logic, - parameter type slv_resp_t = logic, - parameter type mst_req_t = logic, - parameter type mst_resp_t = logic, - parameter type rule_t = axi_pkg::xbar_rule_64_t + /// The number of AXI slave ports of the crossbar. + /// (In other words, how many AXI master modules can be attached). + parameter int unsigned NumSlvPorts = 32'd0, + /// The number of AXI master ports of the crossbar. + /// (In other words, how many AXI slave modules can be attached). + parameter int unsigned NumMstPorts = 32'd0, + /// AXI ID width of the slave ports. + /// + /// This parameter also determines the corresponding value for `MstPortIdWidth` . + /// Routing of responses is done by extending the ID by the index of the slave port witch accepted + /// the transaction. See [`axi_mux`](module.axi_mux) for details. + parameter int unsigned SlvPortIdWidth = 32'd0, + /// The number of slave port ID bits (starting at the least significant) the crossbar uses to + /// determine the uniqueness of an AXI ID (see section *Ordering and Stalls* above). + /// + /// This value *must* follow `SlvPortIdWidth >= SlvPortIdWidthUsed && SlvPortIdWidthUsed > 0`. + /// + /// Setting this to small values leads to less area, however on an increased stalling rate + /// due to ID collisions. + parameter int unsigned SlvPortIdWidthUsed = 32'd0, + /// AXI4+ATOP address field width. + parameter int unsigned AddrWidth = 32'd0, + /// AXI4+ATOP data field width. + parameter int unsigned DataWidth = 32'd0, + /// AXI4+ATOP user field width. + parameter int unsigned UserWidth = 32'd0, + /// Maximum number of open transactions each slave port of the crossbar can have + /// [in flight](doc/#in-flight) at the same time. + parameter int unsigned SlvPortMaxTxns = 32'd0, + /// Maximum number of open transactions each master port the crossbar can have + /// [in flight](../doc#in-flight) per ID at the same time. + parameter int unsigned MstPortMaxTxns = 32'd0, + /// Routing decisions on the AW channel fall through to the W channel. Enabling this allows the + /// crossbar to accept a W beat in the same cycle as the corresponding AW beat, but it increases + /// the combinatorial path of the W channel with logic from the AW channel. + /// + /// Setting this to `0` prevents logic on the AW channel from extending into the W channel. + /// + /// 0: No fallthrough + /// 1: Fallthrough + parameter bit FallThrough = 32'd1, + /// The `LatencyMode` parameter allows to insert spill registers after each channel + /// (AW, W, B, AR, and R) of each master port (i.e., each [`axi_mux`](module.axi_mux)) and before + /// each channel of each slave port (i.e., each [`axi_demux`](module.axi_demux)). + /// Spill registers cut combinatorial paths, so this parameter reduces the length of combinatorial + /// paths through the crossbar. + /// + /// Some common configurations are given in the [`xbar_latency_e` `enum`](package.axi_pkg). + /// The recommended configuration (`axi_pkg::CUT_ALL_AX`) is to have a latency of 2 on the AW and + /// AR channels because these channels have the most combinatorial logic on them. + /// Additionally, `FallThrough` should be set to `0` to prevent logic on the AW channel from + /// extending combinatorial paths on the W channel. However, it is possible to run the crossbar + /// in a fully combinatorial configuration by setting `LatencyMode` to `NO_LATENCY` and + /// `FallThrough` to `1`. + /// + /// If two crossbars are connected in both directions, meaning both have one of their master ports + /// connected to a slave port of the other, the `LatencyMode` of both crossbars must be set to + /// either `CUT_SLV_PORTS`, `CUT_MST_PORTS`, or `CUT_ALL_PORTS`. Any other latency mode will lead + /// to timing loops on the uncut channels between the two crossbars. The latency mode of the two + /// crossbars does not have to be identical. + parameter axi_pkg::xbar_latency_e LatencyMode = axi_pkg::CUT_ALL_AX, + /// The number of address rules defined for routing of the transactions. + /// Each master port can have multiple rules, should have however at least one or be the + /// *default master port* of at least one slave port. + /// If a transaction can not be routed the xbar will answer with an `axi_pkg::RESP_DECERR`. + parameter int unsigned NumAddrRules = 32'd0, + /// Enable atomic operations support. + parameter bit EnableAtops = 1'b1, + /// AXI4+ATOP request struct type for a single slave port. + parameter type slv_port_axi_req_t = logic, + /// AXI4+ATOP response struct type for a single slave port. + parameter type slv_port_axi_rsp_t = logic, + /// AXI4+ATOP request struct type for a single master port. + parameter type mst_port_axi_req_t = logic, + /// AXI4+ATOP response struct type for a single master port. + parameter type mst_port_axi_rsp_t = logic, + /// Address rule type for the address decoders from `common_cells:addr_decode`. + /// + /// Example types are provided in [`axi_pkg`](package.axi_pkg). + /// + /// Required struct fields: + /// + /// ```systemverilog + /// typedef struct packed { + /// int unsigned idx; + /// axi_addr_t start_addr; + /// axi_addr_t end_addr; + /// } rule_t; + /// ``` + parameter type rule_t = axi_pkg::xbar_rule_64_t, + /// Dependent parameter, do **not** override! + /// Width of the index specifying a master port. + parameter int unsigned DefaultMstPortIdxWidth = cf_math_pkg::idx_width(NumMstPorts), + /// Dependent parameter, do **not** override! + /// Type of index for a default master port. + parameter type default_mst_port_idx_t = logic [DefaultMstPortIdxWidth-1:0] ) ( - input logic clk_i, - input logic rst_ni, - input logic test_i, - input slv_req_t [Cfg.NoSlvPorts-1:0] slv_ports_req_i, - output slv_resp_t [Cfg.NoSlvPorts-1:0] slv_ports_resp_o, - output mst_req_t [Cfg.NoMstPorts-1:0] mst_ports_req_o, - input mst_resp_t [Cfg.NoMstPorts-1:0] mst_ports_resp_i, - input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, - input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, - input logic [Cfg.NoSlvPorts-1:0][$clog2(Cfg.NoMstPorts)-1:0] default_mst_port_i + /// Clock, rising edge triggered. + /// + /// All other signals (except `rst_ni`) are synchronous to this signal. + input logic clk_i, + /// Asynchronous reset, active low. + input logic rst_ni, + /// Testmode enable, active high. + input logic test_i, + /// AXI4+ATOP requests to the slave ports. + input slv_port_axi_req_t [NumSlvPorts-1:0] slv_ports_req_i, + /// AXI4+ATOP responses of the slave ports. + output slv_port_axi_rsp_t [NumSlvPorts-1:0] slv_ports_rsp_o, + /// AXI4+ATOP requests of the master ports. + output mst_port_axi_req_t [NumMstPorts-1:0] mst_ports_req_o, + /// AXI4+ATOP responses to the master ports. + input mst_port_axi_rsp_t [NumMstPorts-1:0] mst_ports_rsp_i, + /// Address map array input for the crossbar. This map is global for the whole module. + /// It is used for routing the transactions to the respective master ports. + /// Each master port can have multiple different rules. + input rule_t [NumAddrRules-1:0] addr_map_i, + /// Enables a default master port for each slave port. When this is enabled unmapped + /// transactions get issued at the master port given by `default_mst_port_i`. + /// Each bit index corresponds to the index of a master port and is ordered little-endian (downto). + /// + /// When not used, tie to `'0`. + input logic [NumSlvPorts-1:0] en_default_mst_port_i, + /// For each slave port the default index where the transaction should be routed, if + /// for this slave port the default index functionality is enabled by setting the + /// bit `en_default_mst_ports_i[slave_port_idx]` to `1'b1`. + /// + /// When not used, tie to `'0`. + input default_mst_port_idx_t [NumSlvPorts-1:0] default_mst_ports_i ); - typedef logic [Cfg.AxiAddrWidth-1:0] addr_t; - // to account for the decoding error slave - typedef logic [$clog2(Cfg.NoMstPorts + 1)-1:0] mst_port_idx_t; + // Internal type definitions for the AXI4+ATOP channels. + localparam int unsigned MstPortIdWidth = SlvPortIdWidth + unsigned'($clog2(NumSlvPorts)); + localparam int unsigned StrbWidth = DataWidth / 32'd8; + typedef logic [SlvPortIdWidth -1:0] slv_port_axi_id_t; + typedef logic [MstPortIdWidth -1:0] mst_port_axi_id_t; + typedef logic [AddrWidth -1:0] axi_addr_t; + typedef logic [DataWidth -1:0] axi_data_t; + typedef logic [StrbWidth -1:0] axi_strb_t; + typedef logic [UserWidth -1:0] axi_user_t; - // signals from the axi_demuxes, one index more for decode error - slv_req_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_reqs; - slv_resp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts:0] slv_resps; + `AXI_TYPEDEF_AW_CHAN_T(slv_port_axi_aw_t, axi_addr_t, slv_port_axi_id_t, axi_user_t) + `AXI_TYPEDEF_AW_CHAN_T(mst_port_axi_aw_t, axi_addr_t, mst_port_axi_id_t, axi_user_t) + `AXI_TYPEDEF_W_CHAN_T(axi_w_t, axi_data_t, axi_strb_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_port_axi_b_t, slv_port_axi_id_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_port_axi_b_t, mst_port_axi_id_t, axi_user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_port_axi_ar_t, axi_addr_t, slv_port_axi_id_t, axi_user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_port_axi_ar_t, axi_addr_t, mst_port_axi_id_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_port_axi_r_t, axi_data_t, slv_port_axi_id_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_port_axi_r_t, axi_data_t, mst_port_axi_id_t, axi_user_t) - // workaround for issue #133 (problem with vsim 10.6c) - localparam int unsigned cfg_NoMstPorts = Cfg.NoMstPorts; + // Account for the decoding error slave in the `axi_demux` select width. + // The `axi_demux` on a slave port always has one more master port that the number of master ports + // of the `axi_xbar`. + localparam int unsigned InternalSelectIdxWidth = cf_math_pkg::idx_width(NumMstPorts + 32'd1); + typedef logic [InternalSelectIdxWidth-1:0] internal_select_idx_t; + + // signals from the axi_demuxes, one index more for decode error + slv_port_axi_req_t [NumSlvPorts-1:0][NumMstPorts:0] slv_reqs; + slv_port_axi_rsp_t [NumSlvPorts-1:0][NumMstPorts:0] slv_rsps; // signals into the axi_muxes, are of type slave as the multiplexer extends the ID - slv_req_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_reqs; - slv_resp_t [Cfg.NoMstPorts-1:0][Cfg.NoSlvPorts-1:0] mst_resps; + slv_port_axi_req_t [NumMstPorts-1:0][NumSlvPorts-1:0] mst_reqs; + slv_port_axi_rsp_t [NumMstPorts-1:0][NumSlvPorts-1:0] mst_rsps; - for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_slv_port_demux - logic [$clog2(Cfg.NoMstPorts)-1:0] dec_aw, dec_ar; - mst_port_idx_t slv_aw_select, slv_ar_select; - logic dec_aw_valid, dec_aw_error; - logic dec_ar_valid, dec_ar_error; + for (genvar i = 0; unsigned'(i) < NumSlvPorts; i++) begin : gen_slv_port_demux + default_mst_port_idx_t dec_aw, dec_ar; + internal_select_idx_t slv_aw_select, slv_ar_select; + logic dec_aw_valid, dec_aw_error; + logic dec_ar_valid, dec_ar_error; addr_decode #( - .NoIndices ( Cfg.NoMstPorts ), - .NoRules ( Cfg.NoAddrRules ), - .addr_t ( addr_t ), - .rule_t ( rule_t ) + .NoIndices ( NumMstPorts ), + .NoRules ( NumAddrRules ), + .addr_t ( axi_addr_t ), + .rule_t ( rule_t ) ) i_axi_aw_decode ( .addr_i ( slv_ports_req_i[i].aw.addr ), .addr_map_i ( addr_map_i ), @@ -78,14 +322,14 @@ module axi_xbar #( .dec_valid_o ( dec_aw_valid ), .dec_error_o ( dec_aw_error ), .en_default_idx_i ( en_default_mst_port_i[i] ), - .default_idx_i ( default_mst_port_i[i] ) + .default_idx_i ( default_mst_ports_i[i] ) ); addr_decode #( - .NoIndices ( Cfg.NoMstPorts ), - .addr_t ( addr_t ), - .NoRules ( Cfg.NoAddrRules ), - .rule_t ( rule_t ) + .NoIndices ( NumMstPorts ), + .NoRules ( NumAddrRules ), + .addr_t ( axi_addr_t ), + .rule_t ( rule_t ) ) i_axi_ar_decode ( .addr_i ( slv_ports_req_i[i].ar.addr ), .addr_map_i ( addr_map_i ), @@ -93,13 +337,13 @@ module axi_xbar #( .dec_valid_o ( dec_ar_valid ), .dec_error_o ( dec_ar_error ), .en_default_idx_i ( en_default_mst_port_i[i] ), - .default_idx_i ( default_mst_port_i[i] ) + .default_idx_i ( default_mst_ports_i[i] ) ); assign slv_aw_select = (dec_aw_error) ? - mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(dec_aw); + internal_select_idx_t'(NumMstPorts) : internal_select_idx_t'(dec_aw); assign slv_ar_select = (dec_ar_error) ? - mst_port_idx_t'(Cfg.NoMstPorts) : mst_port_idx_t'(dec_ar); + internal_select_idx_t'(NumMstPorts) : internal_select_idx_t'(dec_ar); // make sure that the default slave does not get changed, if there is an unserved Ax // pragma translate_off @@ -107,117 +351,117 @@ module axi_xbar #( `ifndef XSIM default disable iff (~rst_ni); default_aw_mst_port_en: assert property( - @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) + @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_rsp_o[i].aw_ready) |=> $stable(en_default_mst_port_i[i])) else $fatal (1, $sformatf("It is not allowed to change the default mst port\ enable, when there is an unserved Aw beat. Slave Port: %0d", i)); default_aw_mst_port: assert property( - @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_resp_o[i].aw_ready) - |=> $stable(default_mst_port_i[i])) + @(posedge clk_i) (slv_ports_req_i[i].aw_valid && !slv_ports_rsp_o[i].aw_ready) + |=> $stable(default_mst_ports_i[i])) else $fatal (1, $sformatf("It is not allowed to change the default mst port\ when there is an unserved Aw beat. Slave Port: %0d", i)); default_ar_mst_port_en: assert property( - @(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_resp_o[i].ar_ready) + @(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_rsp_o[i].ar_ready) |=> $stable(en_default_mst_port_i[i])) else $fatal (1, $sformatf("It is not allowed to change the enable, when\ there is an unserved Ar beat. Slave Port: %0d", i)); default_ar_mst_port: assert property( - @(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_resp_o[i].ar_ready) - |=> $stable(default_mst_port_i[i])) + @(posedge clk_i) (slv_ports_req_i[i].ar_valid && !slv_ports_rsp_o[i].ar_ready) + |=> $stable(default_mst_ports_i[i])) else $fatal (1, $sformatf("It is not allowed to change the default mst port\ when there is an unserved Ar beat. Slave Port: %0d", i)); `endif `endif // pragma translate_on axi_demux #( - .AxiIdWidth ( Cfg.AxiIdWidthSlvPorts ), // ID Width - .aw_chan_t ( slv_aw_chan_t ), // AW Channel Type - .w_chan_t ( w_chan_t ), // W Channel Type - .b_chan_t ( slv_b_chan_t ), // B Channel Type - .ar_chan_t ( slv_ar_chan_t ), // AR Channel Type - .r_chan_t ( slv_r_chan_t ), // R Channel Type - .req_t ( slv_req_t ), - .resp_t ( slv_resp_t ), - .NoMstPorts ( Cfg.NoMstPorts + 1 ), - .MaxTrans ( Cfg.MaxMstTrans ), - .AxiLookBits ( Cfg.AxiIdUsedSlvPorts ), - .FallThrough ( Cfg.FallThrough ), - .SpillAw ( Cfg.LatencyMode[9] ), - .SpillW ( Cfg.LatencyMode[8] ), - .SpillB ( Cfg.LatencyMode[7] ), - .SpillAr ( Cfg.LatencyMode[6] ), - .SpillR ( Cfg.LatencyMode[5] ) + .AxiIdWidth ( SlvPortIdWidth ), // ID Width + .aw_chan_t ( slv_port_axi_aw_t ), // AW Channel Type + .w_chan_t ( axi_w_t ), // W Channel Type + .b_chan_t ( slv_port_axi_b_t ), // B Channel Type + .ar_chan_t ( slv_port_axi_ar_t ), // AR Channel Type + .r_chan_t ( slv_port_axi_r_t ), // R Channel Type + .req_t ( slv_port_axi_req_t ), + .resp_t ( slv_port_axi_rsp_t ), + .NoMstPorts ( NumMstPorts + 32'd1 ), + .MaxTrans ( SlvPortMaxTxns ), + .AxiLookBits ( SlvPortIdWidthUsed ), + .FallThrough ( FallThrough ), + .SpillAw ( LatencyMode[9] ), + .SpillW ( LatencyMode[8] ), + .SpillB ( LatencyMode[7] ), + .SpillAr ( LatencyMode[6] ), + .SpillR ( LatencyMode[5] ) ) i_axi_demux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low .test_i, // Testmode enable - .slv_req_i ( slv_ports_req_i[i] ), - .slv_aw_select_i ( slv_aw_select ), - .slv_ar_select_i ( slv_ar_select ), - .slv_resp_o ( slv_ports_resp_o[i] ), - .mst_reqs_o ( slv_reqs[i] ), - .mst_resps_i ( slv_resps[i] ) + .slv_req_i ( slv_ports_req_i[i] ), + .slv_aw_select_i ( slv_aw_select ), + .slv_ar_select_i ( slv_ar_select ), + .slv_resp_o ( slv_ports_rsp_o[i] ), + .mst_reqs_o ( slv_reqs[i] ), + .mst_resps_i ( slv_rsps[i] ) ); axi_err_slv #( - .AxiIdWidth ( Cfg.AxiIdWidthSlvPorts ), - .req_t ( slv_req_t ), - .resp_t ( slv_resp_t ), - .Resp ( axi_pkg::RESP_DECERR ), - .ATOPs ( ATOPs ), - .MaxTrans ( 4 ) // Transactions terminate at this slave, so minimize - // resource consumption by accepting only a few - // transactions at a time. + .AxiIdWidth ( SlvPortIdWidth ), + .req_t ( slv_port_axi_req_t ), + .resp_t ( slv_port_axi_rsp_t ), + .Resp ( axi_pkg::RESP_DECERR ), + .ATOPs ( EnableAtops ), + .MaxTrans ( 32'd4 ) // Transactions terminate at this slave, so minimize + // resource consumption by accepting only a few + // transactions at a time. ) i_axi_err_slv ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low .test_i, // Testmode enable // slave port - .slv_req_i ( slv_reqs[i][Cfg.NoMstPorts] ), - .slv_resp_o ( slv_resps[i][cfg_NoMstPorts] ) + .slv_req_i ( slv_reqs[i][NumMstPorts] ), + .slv_resp_o ( slv_rsps[i][NumMstPorts] ) ); end // cross all channels - for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_xbar_slv_cross - for (genvar j = 0; j < Cfg.NoMstPorts; j++) begin : gen_xbar_mst_cross - assign mst_reqs[j][i] = slv_reqs[i][j]; - assign slv_resps[i][j] = mst_resps[j][i]; + for (genvar i = 0; unsigned'(i) < NumSlvPorts; i++) begin : gen_xbar_slv_cross + for (genvar j = 0; unsigned'(j) < NumMstPorts; j++) begin : gen_xbar_mst_cross + assign mst_reqs[j][i] = slv_reqs[i][j]; + assign slv_rsps[i][j] = mst_rsps[j][i]; end end - for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_mst_port_mux + for (genvar i = 0; unsigned'(i) < NumMstPorts; i++) begin : gen_mst_port_mux axi_mux #( - .SlvAxiIDWidth ( Cfg.AxiIdWidthSlvPorts ), // ID width of the slave ports - .slv_aw_chan_t ( slv_aw_chan_t ), // AW Channel Type, slave ports - .mst_aw_chan_t ( mst_aw_chan_t ), // AW Channel Type, master port - .w_chan_t ( w_chan_t ), // W Channel Type, all ports - .slv_b_chan_t ( slv_b_chan_t ), // B Channel Type, slave ports - .mst_b_chan_t ( mst_b_chan_t ), // B Channel Type, master port - .slv_ar_chan_t ( slv_ar_chan_t ), // AR Channel Type, slave ports - .mst_ar_chan_t ( mst_ar_chan_t ), // AR Channel Type, master port - .slv_r_chan_t ( slv_r_chan_t ), // R Channel Type, slave ports - .mst_r_chan_t ( mst_r_chan_t ), // R Channel Type, master port - .slv_req_t ( slv_req_t ), - .slv_resp_t ( slv_resp_t ), - .mst_req_t ( mst_req_t ), - .mst_resp_t ( mst_resp_t ), - .NoSlvPorts ( Cfg.NoSlvPorts ), // Number of Masters for the module - .MaxWTrans ( Cfg.MaxSlvTrans ), - .FallThrough ( Cfg.FallThrough ), - .SpillAw ( Cfg.LatencyMode[4] ), - .SpillW ( Cfg.LatencyMode[3] ), - .SpillB ( Cfg.LatencyMode[2] ), - .SpillAr ( Cfg.LatencyMode[1] ), - .SpillR ( Cfg.LatencyMode[0] ) + .SlvAxiIDWidth ( SlvPortIdWidth ), // ID width of the slave ports + .slv_aw_chan_t ( slv_port_axi_aw_t ), // AW Channel Type, slave ports + .mst_aw_chan_t ( mst_port_axi_aw_t ), // AW Channel Type, master port + .w_chan_t ( axi_w_t ), // W Channel Type, all ports + .slv_b_chan_t ( slv_port_axi_b_t ), // B Channel Type, slave ports + .mst_b_chan_t ( mst_port_axi_b_t ), // B Channel Type, master port + .slv_ar_chan_t ( slv_port_axi_ar_t ), // AR Channel Type, slave ports + .mst_ar_chan_t ( mst_port_axi_ar_t ), // AR Channel Type, master port + .slv_r_chan_t ( slv_port_axi_r_t ), // R Channel Type, slave ports + .mst_r_chan_t ( mst_port_axi_r_t ), // R Channel Type, master port + .slv_req_t ( slv_port_axi_req_t ), + .slv_resp_t ( slv_port_axi_rsp_t ), + .mst_req_t ( mst_port_axi_req_t ), + .mst_resp_t ( mst_port_axi_rsp_t ), + .NoSlvPorts ( NumSlvPorts ), // Number of Masters for the module + .MaxWTrans ( MstPortMaxTxns ), + .FallThrough ( FallThrough ), + .SpillAw ( LatencyMode[4] ), + .SpillW ( LatencyMode[3] ), + .SpillB ( LatencyMode[2] ), + .SpillAr ( LatencyMode[1] ), + .SpillR ( LatencyMode[0] ) ) i_axi_mux ( .clk_i, // Clock .rst_ni, // Asynchronous reset active low .test_i, // Test Mode enable - .slv_reqs_i ( mst_reqs[i] ), - .slv_resps_o ( mst_resps[i] ), - .mst_req_o ( mst_ports_req_o[i] ), - .mst_resp_i ( mst_ports_resp_i[i] ) + .slv_reqs_i ( mst_reqs[i] ), + .slv_resps_o ( mst_rsps[i] ), + .mst_req_o ( mst_ports_req_o[i] ), + .mst_resp_i ( mst_ports_rsp_i[i] ) ); end @@ -225,10 +469,10 @@ module axi_xbar #( `ifndef VERILATOR `ifndef XSIM initial begin : check_params - id_slv_req_ports: assert ($bits(slv_ports_req_i[0].aw.id ) == Cfg.AxiIdWidthSlvPorts) else - $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); - id_slv_resp_ports: assert ($bits(slv_ports_resp_o[0].r.id) == Cfg.AxiIdWidthSlvPorts) else - $fatal(1, $sformatf("Slv_req and aw_chan id width not equal.")); + id_slv_req_ports: assert ($bits(slv_ports_req_i[0].aw.id) == SlvPortIdWidth) else + $fatal(1, $sformatf("slv_ports_req_i.aw.id and SlvPortIdWidth not equal.")); + id_slv_rsp_ports: assert ($bits(slv_ports_rsp_o[0].r.id) == SlvPortIdWidth) else + $fatal(1, $sformatf("slv_ports_rsp_o.r.id and SlvPortIdWidth not equal.")); end `endif `endif @@ -236,88 +480,113 @@ module axi_xbar #( endmodule `include "axi/assign.svh" -`include "axi/typedef.svh" +/// This is the interface wrapper for `axi_xbar`. Ports and parameters are analog to `axi_xbar`, +/// see [`axi_xbar` documentation](module.axi_xbar). +/// The AXI4+ATOP master and slave ports are structured here as interfaces. +/// +/// The indexing of the master and slave port interface arrays is big-endian. module axi_xbar_intf #( - parameter int unsigned AXI_USER_WIDTH = 0, - parameter axi_pkg::xbar_cfg_t Cfg = '0, - parameter type rule_t = axi_pkg::xbar_rule_64_t + parameter int unsigned NumSlvPorts = 32'd0, + parameter int unsigned NumMstPorts = 32'd0, + parameter int unsigned SlvPortIdWidth = 32'd0, + parameter int unsigned SlvPortIdWidthUsed = 32'd0, + parameter int unsigned AddrWidth = 32'd0, + parameter int unsigned DataWidth = 32'd0, + parameter int unsigned UserWidth = 32'd0, + parameter int unsigned SlvPortMaxTxns = 32'd0, + parameter int unsigned MstPortMaxTxns = 32'd0, + parameter bit FallThrough = 32'd1, + parameter axi_pkg::xbar_latency_e LatencyMode = axi_pkg::CUT_ALL_AX, + parameter int unsigned NumAddrRules = 32'd0, + parameter bit EnableAtops = 1'b1, + parameter type rule_t = axi_pkg::xbar_rule_64_t, + /// Dependent parameter, do **not** override! + parameter int unsigned DefaultMstPortIdxWidth = cf_math_pkg::idx_width(NumMstPorts), + /// Dependent parameter, do **not**parameter override! + parameter type default_mst_port_idx_t = logic [DefaultMstPortIdxWidth-1:0] ) ( - input logic clk_i, - input logic rst_ni, - input logic test_i, - AXI_BUS.Slave slv_ports [Cfg.NoSlvPorts-1:0], - AXI_BUS.Master mst_ports [Cfg.NoMstPorts-1:0], - input rule_t [Cfg.NoAddrRules-1:0] addr_map_i, - input logic [Cfg.NoSlvPorts-1:0] en_default_mst_port_i, - input logic [Cfg.NoSlvPorts-1:0][$clog2(Cfg.NoMstPorts)-1:0] default_mst_port_i + input logic clk_i, + input logic rst_ni, + input logic test_i, + /// Unpacked, big-endian (upto) array of slave port interfaces. + AXI_BUS.Slave slv_ports[NumSlvPorts], + /// Unpacked, big-endian (upto) array of master port interfaces. + AXI_BUS.Master mst_ports[NumMstPorts], + input rule_t [NumAddrRules-1:0] addr_map_i, + input logic [NumSlvPorts -1:0] en_default_mst_port_i, + input default_mst_port_idx_t [NumSlvPorts -1:0] default_mst_ports_i ); - localparam int unsigned AxiIdWidthMstPorts = Cfg.AxiIdWidthSlvPorts + $clog2(Cfg.NoSlvPorts); + // Internal type definitions for the AXI4+ATOP channels. + localparam int unsigned MstPortIdWidth = SlvPortIdWidth + unsigned'($clog2(NumSlvPorts)); + localparam int unsigned StrbWidth = DataWidth / 32'd8; + typedef logic [SlvPortIdWidth -1:0] slv_port_axi_id_t; + typedef logic [MstPortIdWidth -1:0] mst_port_axi_id_t; + typedef logic [AddrWidth -1:0] axi_addr_t; + typedef logic [DataWidth -1:0] axi_data_t; + typedef logic [StrbWidth -1:0] axi_strb_t; + typedef logic [UserWidth -1:0] axi_user_t; - typedef logic [AxiIdWidthMstPorts -1:0] id_mst_t; - typedef logic [Cfg.AxiIdWidthSlvPorts -1:0] id_slv_t; - typedef logic [Cfg.AxiAddrWidth -1:0] addr_t; - typedef logic [Cfg.AxiDataWidth -1:0] data_t; - typedef logic [Cfg.AxiDataWidth/8 -1:0] strb_t; - typedef logic [AXI_USER_WIDTH -1:0] user_t; + `AXI_TYPEDEF_AW_CHAN_T(slv_port_axi_aw_t, axi_addr_t, slv_port_axi_id_t, axi_user_t) + `AXI_TYPEDEF_AW_CHAN_T(mst_port_axi_aw_t, axi_addr_t, mst_port_axi_id_t, axi_user_t) + `AXI_TYPEDEF_W_CHAN_T(axi_w_t, axi_data_t, axi_strb_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(slv_port_axi_b_t, slv_port_axi_id_t, axi_user_t) + `AXI_TYPEDEF_B_CHAN_T(mst_port_axi_b_t, mst_port_axi_id_t, axi_user_t) + `AXI_TYPEDEF_AR_CHAN_T(slv_port_axi_ar_t, axi_addr_t, slv_port_axi_id_t, axi_user_t) + `AXI_TYPEDEF_AR_CHAN_T(mst_port_axi_ar_t, axi_addr_t, mst_port_axi_id_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(slv_port_axi_r_t, axi_data_t, slv_port_axi_id_t, axi_user_t) + `AXI_TYPEDEF_R_CHAN_T(mst_port_axi_r_t, axi_data_t, mst_port_axi_id_t, axi_user_t) - `AXI_TYPEDEF_AW_CHAN_T(mst_aw_chan_t, addr_t, id_mst_t, user_t) - `AXI_TYPEDEF_AW_CHAN_T(slv_aw_chan_t, addr_t, id_slv_t, user_t) - `AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(mst_b_chan_t, id_mst_t, user_t) - `AXI_TYPEDEF_B_CHAN_T(slv_b_chan_t, id_slv_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(mst_ar_chan_t, addr_t, id_mst_t, user_t) - `AXI_TYPEDEF_AR_CHAN_T(slv_ar_chan_t, addr_t, id_slv_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(mst_r_chan_t, data_t, id_mst_t, user_t) - `AXI_TYPEDEF_R_CHAN_T(slv_r_chan_t, data_t, id_slv_t, user_t) - `AXI_TYPEDEF_REQ_T(mst_req_t, mst_aw_chan_t, w_chan_t, mst_ar_chan_t) - `AXI_TYPEDEF_REQ_T(slv_req_t, slv_aw_chan_t, w_chan_t, slv_ar_chan_t) - `AXI_TYPEDEF_RESP_T(mst_resp_t, mst_b_chan_t, mst_r_chan_t) - `AXI_TYPEDEF_RESP_T(slv_resp_t, slv_b_chan_t, slv_r_chan_t) + `AXI_TYPEDEF_REQ_T(slv_port_axi_req_t, slv_port_axi_aw_t, axi_w_t, slv_port_axi_ar_t) + `AXI_TYPEDEF_REQ_T(mst_port_axi_req_t, mst_port_axi_aw_t, axi_w_t, mst_port_axi_ar_t) + `AXI_TYPEDEF_RESP_T(slv_port_axi_rsp_t, slv_port_axi_b_t, slv_port_axi_r_t) + `AXI_TYPEDEF_RESP_T(mst_port_axi_rsp_t, mst_port_axi_b_t, mst_port_axi_r_t) - mst_req_t [Cfg.NoMstPorts-1:0] mst_reqs; - mst_resp_t [Cfg.NoMstPorts-1:0] mst_resps; - slv_req_t [Cfg.NoSlvPorts-1:0] slv_reqs; - slv_resp_t [Cfg.NoSlvPorts-1:0] slv_resps; + slv_port_axi_req_t [NumSlvPorts-1:0] slv_reqs; + slv_port_axi_rsp_t [NumSlvPorts-1:0] slv_rsps; + mst_port_axi_req_t [NumMstPorts-1:0] mst_reqs; + mst_port_axi_rsp_t [NumMstPorts-1:0] mst_rsps; - for (genvar i = 0; i < Cfg.NoMstPorts; i++) begin : gen_assign_mst - `AXI_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i]) - `AXI_ASSIGN_TO_RESP(mst_resps[i], mst_ports[i]) + for (genvar i = 0; unsigned'(i) < NumSlvPorts; i++) begin : gen_assign_slv + `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i]) + `AXI_ASSIGN_FROM_RESP(slv_ports[i], slv_rsps[i]) end - for (genvar i = 0; i < Cfg.NoSlvPorts; i++) begin : gen_assign_slv - `AXI_ASSIGN_TO_REQ(slv_reqs[i], slv_ports[i]) - `AXI_ASSIGN_FROM_RESP(slv_ports[i], slv_resps[i]) + for (genvar i = 0; unsigned'(i) < NumMstPorts; i++) begin : gen_assign_mst + `AXI_ASSIGN_FROM_REQ(mst_ports[i], mst_reqs[i]) + `AXI_ASSIGN_TO_RESP(mst_rsps[i], mst_ports[i]) end axi_xbar #( - .Cfg (Cfg), - .slv_aw_chan_t ( slv_aw_chan_t ), - .mst_aw_chan_t ( mst_aw_chan_t ), - .w_chan_t ( w_chan_t ), - .slv_b_chan_t ( slv_b_chan_t ), - .mst_b_chan_t ( mst_b_chan_t ), - .slv_ar_chan_t ( slv_ar_chan_t ), - .mst_ar_chan_t ( mst_ar_chan_t ), - .slv_r_chan_t ( slv_r_chan_t ), - .mst_r_chan_t ( mst_r_chan_t ), - .slv_req_t ( slv_req_t ), - .slv_resp_t ( slv_resp_t ), - .mst_req_t ( mst_req_t ), - .mst_resp_t ( mst_resp_t ), - .rule_t ( rule_t ) + .NumSlvPorts ( NumSlvPorts ), + .NumMstPorts ( NumMstPorts ), + .SlvPortIdWidth ( SlvPortIdWidth ), + .SlvPortIdWidthUsed ( SlvPortIdWidthUsed ), + .AddrWidth ( AddrWidth ), + .DataWidth ( DataWidth ), + .UserWidth ( UserWidth ), + .SlvPortMaxTxns ( SlvPortMaxTxns ), + .MstPortMaxTxns ( MstPortMaxTxns ), + .FallThrough ( FallThrough ), + .LatencyMode ( LatencyMode ), + .NumAddrRules ( NumAddrRules ), + .EnableAtops ( EnableAtops ), + .slv_port_axi_req_t ( slv_port_axi_req_t ), + .slv_port_axi_rsp_t ( slv_port_axi_rsp_t ), + .mst_port_axi_req_t ( mst_port_axi_req_t ), + .mst_port_axi_rsp_t ( mst_port_axi_rsp_t ), + .rule_t ( rule_t ) ) i_xbar ( .clk_i, .rst_ni, .test_i, - .slv_ports_req_i (slv_reqs ), - .slv_ports_resp_o (slv_resps), - .mst_ports_req_o (mst_reqs ), - .mst_ports_resp_i (mst_resps), + .slv_ports_req_i ( slv_reqs ), + .slv_ports_rsp_o ( slv_rsps ), + .mst_ports_req_o ( mst_reqs ), + .mst_ports_rsp_i ( mst_rsps ), .addr_map_i, .en_default_mst_port_i, - .default_mst_port_i + .default_mst_ports_i ); - endmodule diff --git a/test/tb_axi_xbar.sv b/test/tb_axi_xbar.sv index d5ab6cc0c..8699664b6 100644 --- a/test/tb_axi_xbar.sv +++ b/test/tb_axi_xbar.sv @@ -22,49 +22,54 @@ `include "axi/typedef.svh" `include "axi/assign.svh" -module tb_axi_xbar; - // Dut parameters - localparam int unsigned NoMasters = 6; // How many Axi Masters there are - localparam int unsigned NoSlaves = 8; // How many Axi Slaves there are - // Random master no Transactions - localparam int unsigned NoWrites = 1000; // How many writes per master - localparam int unsigned NoReads = 1000; // How many reads per master - // Random Master Atomics - localparam bit EnAtop = 1'b1; - // timing parameters +/// Testbench for the module `axi_xbar`. +module tb_axi_xbar #( + /// Number of AXI masters connected to the xbar. (Number of slave ports) + parameter int unsigned TbNumMasters = 32'd6, + /// Number of AXI slaves connected to the xbar. (Number of master ports) + parameter int unsigned TbNumSlaves = 32'd8, + /// Number of write transactions per master. + parameter int unsigned TbNumWrites = 32'd100, + /// Number of read transactions per master. + parameter int unsigned TbNumReads = 32'd100, + /// AXI4+ATOP ID wisth of the masters connected to the slave ports of the DUT. + /// The ID width of the salves is calulated depending on the xbar configuration. + parameter int unsigned TbAxiIdWidthMasters = 32'd5, + /// The used ID width of the DUT. + /// Has to be `TbAxiIdWidthMasters >= TbAxiIdUsed`. + parameter int unsigned TbAxiIdUsed = 32'd3, + /// Data width of the AXI channels. + parameter int unsigned TbAxiDataWidth = 32'd64, + /// Eanable ATOP generation + parameter bit TbEnableAtops = 1'b1 +); + + // TB timing parameters localparam time CyclTime = 10ns; localparam time ApplTime = 2ns; localparam time TestTime = 8ns; - // axi configuration - localparam int unsigned AxiIdWidthMasters = 4; - localparam int unsigned AxiIdUsed = 3; // Has to be <= AxiIdWidthMasters - localparam int unsigned AxiIdWidthSlaves = AxiIdWidthMasters + $clog2(NoMasters); - localparam int unsigned AxiAddrWidth = 32; // Axi Address Width - localparam int unsigned AxiDataWidth = 64; // Axi Data Width - localparam int unsigned AxiStrbWidth = AxiDataWidth / 8; - localparam int unsigned AxiUserWidth = 5; - // in the bench can change this variables which are set here freely - localparam axi_pkg::xbar_cfg_t xbar_cfg = '{ - NoSlvPorts: NoMasters, - NoMstPorts: NoSlaves, - MaxMstTrans: 10, - MaxSlvTrans: 6, - FallThrough: 1'b0, - LatencyMode: axi_pkg::CUT_ALL_AX, - AxiIdWidthSlvPorts: AxiIdWidthMasters, - AxiIdUsedSlvPorts: AxiIdUsed, - AxiAddrWidth: AxiAddrWidth, - AxiDataWidth: AxiDataWidth, - NoAddrRules: 8 - }; - typedef logic [AxiIdWidthMasters-1:0] id_mst_t; - typedef logic [AxiIdWidthSlaves-1:0] id_slv_t; - typedef logic [AxiAddrWidth-1:0] addr_t; - typedef axi_pkg::xbar_rule_32_t rule_t; // Has to be the same width as axi addr - typedef logic [AxiDataWidth-1:0] data_t; - typedef logic [AxiStrbWidth-1:0] strb_t; - typedef logic [AxiUserWidth-1:0] user_t; + // AXI configuration which is automatically derived. + localparam int unsigned TbAxiIdWidthSlaves = TbAxiIdWidthMasters + $clog2(TbNumMasters); + localparam int unsigned TbAxiAddrWidth = 32'd32; + localparam int unsigned TbAxiStrbWidth = TbAxiDataWidth / 8; + localparam int unsigned TbAxiUserWidth = 32'd5; + // In the bench can change these variables which are set here freely, + // Set all XBAR parameter here, even if they do not change per default. + // Makes sure that they are properly propageted through the interface wrapper. + localparam int unsigned TbSlvPortMaxTxns = 32'd10; + localparam int unsigned TbMstPortMaxTxns = 32'd6; + localparam int unsigned TbFallThrough = 1'b0; + localparam int unsigned TbLatencyMode = axi_pkg::NO_LATENCY; + localparam int unsigned TbNumAddrRules = TbNumSlaves; + + typedef logic [TbAxiIdWidthMasters-1:0] id_mst_t; + typedef logic [TbAxiIdWidthSlaves-1:0] id_slv_t; + typedef logic [TbAxiAddrWidth-1:0] addr_t; + typedef axi_pkg::xbar_rule_32_t tb_addr_rule_t; // Has to be the same width as axi addr + typedef logic [TbAxiDataWidth-1:0] data_t; + typedef logic [TbAxiStrbWidth-1:0] strb_t; + typedef logic [TbAxiUserWidth-1:0] user_t; `AXI_TYPEDEF_AW_CHAN_T(aw_chan_mst_t, addr_t, id_mst_t, user_t) `AXI_TYPEDEF_AW_CHAN_T(aw_chan_slv_t, addr_t, id_slv_t, user_t) @@ -82,40 +87,43 @@ module tb_axi_xbar; `AXI_TYPEDEF_REQ_T(slv_req_t, aw_chan_slv_t, w_chan_t, ar_chan_slv_t) `AXI_TYPEDEF_RESP_T(slv_resp_t, b_chan_slv_t, r_chan_slv_t) - localparam rule_t [xbar_cfg.NoAddrRules-1:0] AddrMap = '{ - '{idx: 32'd7, start_addr: 32'h0001_0000, end_addr: 32'h0001_1000}, - '{idx: 32'd6, start_addr: 32'h0000_9000, end_addr: 32'h0001_0000}, - '{idx: 32'd5, start_addr: 32'h0000_8000, end_addr: 32'h0000_9000}, - '{idx: 32'd4, start_addr: 32'h0000_7000, end_addr: 32'h0000_8000}, - '{idx: 32'd3, start_addr: 32'h0000_6300, end_addr: 32'h0000_7000}, - '{idx: 32'd2, start_addr: 32'h0000_4000, end_addr: 32'h0000_6300}, - '{idx: 32'd1, start_addr: 32'h0000_3000, end_addr: 32'h0000_4000}, - '{idx: 32'd0, start_addr: 32'h0000_0000, end_addr: 32'h0000_3000} - }; + // Each slave has its own address range: + localparam tb_addr_rule_t [TbNumAddrRules-1:0] AddrMap = addr_map_gen(); + + function tb_addr_rule_t [TbNumAddrRules-1:0] addr_map_gen (); + for (int unsigned i = 0; i < TbNumAddrRules; i++) begin + addr_map_gen[i] = tb_addr_rule_t'{ + idx: unsigned'(i), + start_addr: i * 32'h0000_2000, + end_addr: (i+1) * 32'h0000_2000, + default: '0 + }; + end + endfunction typedef axi_test::axi_rand_master #( // AXI interface parameters - .AW ( AxiAddrWidth ), - .DW ( AxiDataWidth ), - .IW ( AxiIdWidthMasters ), - .UW ( AxiUserWidth ), + .AW ( TbAxiAddrWidth ), + .DW ( TbAxiDataWidth ), + .IW ( TbAxiIdWidthMasters ), + .UW ( TbAxiUserWidth ), // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ), + .TA ( ApplTime ), + .TT ( TestTime ), // Maximum number of read and write transactions in flight - .MAX_READ_TXNS ( 20 ), - .MAX_WRITE_TXNS ( 20 ), - .AXI_ATOPS ( EnAtop ) + .MAX_READ_TXNS ( 20 ), + .MAX_WRITE_TXNS ( 20 ), + .AXI_ATOPS ( TbEnableAtops ) ) axi_rand_master_t; typedef axi_test::axi_rand_slave #( // AXI interface parameters - .AW ( AxiAddrWidth ), - .DW ( AxiDataWidth ), - .IW ( AxiIdWidthSlaves ), - .UW ( AxiUserWidth ), + .AW ( TbAxiAddrWidth ), + .DW ( TbAxiDataWidth ), + .IW ( TbAxiIdWidthSlaves ), + .UW ( TbAxiUserWidth ), // Stimuli application and test time - .TA ( ApplTime ), - .TT ( TestTime ) + .TA ( ApplTime ), + .TT ( TestTime ) ) axi_rand_slave_t; // ------------- @@ -124,87 +132,89 @@ module tb_axi_xbar; logic clk; // DUT signals logic rst_n; - logic [NoMasters-1:0] end_of_sim; + logic [TbNumMasters-1:0] end_of_sim; // master structs - mst_req_t [NoMasters-1:0] masters_req; - mst_resp_t [NoMasters-1:0] masters_resp; + mst_req_t [TbNumMasters-1:0] masters_req; + mst_resp_t [TbNumMasters-1:0] masters_resp; // slave structs - slv_req_t [NoSlaves-1:0] slaves_req; - slv_resp_t [NoSlaves-1:0] slaves_resp; + slv_req_t [TbNumSlaves-1:0] slaves_req; + slv_resp_t [TbNumSlaves-1:0] slaves_resp; // ------------------------------- // AXI Interfaces // ------------------------------- AXI_BUS #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthMasters ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) master [NoMasters-1:0] (); + .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( TbAxiIdWidthMasters ), + .AXI_USER_WIDTH ( TbAxiUserWidth ) + ) master [TbNumMasters] (); AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthMasters ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) master_dv [NoMasters-1:0] (clk); + .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( TbAxiIdWidthMasters ), + .AXI_USER_WIDTH ( TbAxiUserWidth ) + ) master_dv [TbNumMasters] (clk); AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthMasters ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) master_monitor_dv [NoMasters-1:0] (clk); - for (genvar i = 0; i < NoMasters; i++) begin : gen_conn_dv_masters + .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( TbAxiIdWidthMasters ), + .AXI_USER_WIDTH ( TbAxiUserWidth ) + ) master_monitor_dv [TbNumMasters] (clk); + for (genvar i = 0; unsigned'(i) < TbNumMasters; i++) begin : gen_conn_dv_masters `AXI_ASSIGN (master[i], master_dv[i]) + `AXI_ASSIGN_MONITOR(master_monitor_dv[i], master[i]) `AXI_ASSIGN_TO_REQ(masters_req[i], master[i]) - `AXI_ASSIGN_FROM_RESP(master[i], masters_resp[i]) + `AXI_ASSIGN_TO_RESP(masters_resp[i], master[i]) end AXI_BUS #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthSlaves ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) slave [NoSlaves-1:0] (); + .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( TbAxiIdWidthSlaves ), + .AXI_USER_WIDTH ( TbAxiUserWidth ) + ) slave [TbNumSlaves] (); AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthSlaves ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) slave_dv [NoSlaves-1:0](clk); + .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( TbAxiIdWidthSlaves ), + .AXI_USER_WIDTH ( TbAxiUserWidth ) + ) slave_dv [TbNumSlaves](clk); AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthSlaves ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) slave_monitor_dv [NoSlaves-1:0](clk); - for (genvar i = 0; i < NoSlaves; i++) begin : gen_conn_dv_slaves + .AXI_ADDR_WIDTH ( TbAxiAddrWidth ), + .AXI_DATA_WIDTH ( TbAxiDataWidth ), + .AXI_ID_WIDTH ( TbAxiIdWidthSlaves ), + .AXI_USER_WIDTH ( TbAxiUserWidth ) + ) slave_monitor_dv [TbNumSlaves](clk); + for (genvar i = 0; unsigned'(i) < TbNumSlaves; i++) begin : gen_conn_dv_slaves `AXI_ASSIGN(slave_dv[i], slave[i]) - `AXI_ASSIGN_FROM_REQ(slave[i], slaves_req[i]) + `AXI_ASSIGN_MONITOR(slave_monitor_dv[i], slave[i]) + `AXI_ASSIGN_TO_REQ(slaves_req[i], slave[i]) `AXI_ASSIGN_TO_RESP(slaves_resp[i], slave[i]) end // ------------------------------- // AXI Rand Masters and Slaves // ------------------------------- // Masters control simulation run time - for (genvar i = 0; i < NoMasters; i++) begin : gen_rand_master - static axi_rand_master_t axi_rand_master = new ( master_dv[i] ); + for (genvar i = 0; unsigned'(i) < TbNumMasters; i++) begin : gen_rand_master initial begin + static axi_rand_master_t axi_rand_master = new ( master_dv[i] ); end_of_sim[i] <= 1'b0; axi_rand_master.add_memory_region(AddrMap[0].start_addr, - AddrMap[xbar_cfg.NoAddrRules-1].end_addr, + AddrMap[TbNumAddrRules-1].end_addr, axi_pkg::DEVICE_NONBUFFERABLE); axi_rand_master.reset(); @(posedge rst_n); - axi_rand_master.run(NoReads, NoWrites); + axi_rand_master.run(TbNumReads, TbNumWrites); end_of_sim[i] <= 1'b1; end end - for (genvar i = 0; i < NoSlaves; i++) begin : gen_rand_slave - static axi_rand_slave_t axi_rand_slave = new( slave_dv[i] ); + for (genvar i = 0; unsigned'(i) < TbNumSlaves; i++) begin : gen_rand_slave initial begin + static axi_rand_slave_t axi_rand_slave = new( slave_dv[i] ); axi_rand_slave.reset(); @(posedge rst_n); axi_rand_slave.run(); @@ -213,23 +223,23 @@ module tb_axi_xbar; initial begin : proc_monitor static tb_axi_xbar_pkg::axi_xbar_monitor #( - .AxiAddrWidth ( AxiAddrWidth ), - .AxiDataWidth ( AxiDataWidth ), - .AxiIdWidthMasters ( AxiIdWidthMasters ), - .AxiIdWidthSlaves ( AxiIdWidthSlaves ), - .AxiUserWidth ( AxiUserWidth ), - .NoMasters ( NoMasters ), - .NoSlaves ( NoSlaves ), - .NoAddrRules ( xbar_cfg.NoAddrRules ), - .rule_t ( rule_t ), - .AddrMap ( AddrMap ), - .TimeTest ( TestTime ) + .AddrWidth ( TbAxiAddrWidth ), + .DataWidth ( TbAxiDataWidth ), + .SlvPortIdWidth ( TbAxiIdWidthMasters ), + .MstPortIdWidth ( TbAxiIdWidthSlaves ), + .UserWidth ( TbAxiUserWidth ), + .NumSlvPorts ( TbNumMasters ), + .NumMstPorts ( TbNumSlaves ), + .NumAddrRules ( TbNumAddrRules ), + .rule_t ( tb_addr_rule_t ), + .AddrMap ( AddrMap ), + .TestTime ( TestTime ) ) monitor = new( master_monitor_dv, slave_monitor_dv ); fork monitor.run(); do begin #TestTime; - if(end_of_sim == '1) begin + if (end_of_sim == '1) begin monitor.print_result(); $stop(); end @@ -252,37 +262,34 @@ module tb_axi_xbar; //----------------------------------- // DUT //----------------------------------- - axi_xbar #( - .Cfg ( xbar_cfg ), - .slv_aw_chan_t( aw_chan_mst_t ), - .mst_aw_chan_t( aw_chan_slv_t ), - .w_chan_t ( w_chan_t ), - .slv_b_chan_t ( b_chan_mst_t ), - .mst_b_chan_t ( b_chan_slv_t ), - .slv_ar_chan_t( ar_chan_mst_t ), - .mst_ar_chan_t( ar_chan_slv_t ), - .slv_r_chan_t ( r_chan_mst_t ), - .mst_r_chan_t ( r_chan_slv_t ), - .slv_req_t ( mst_req_t ), - .slv_resp_t ( mst_resp_t ), - .mst_req_t ( slv_req_t ), - .mst_resp_t ( slv_resp_t ), - .rule_t (rule_t ) + axi_xbar_intf #( + .NumSlvPorts ( TbNumMasters ), + .NumMstPorts ( TbNumSlaves ), + .SlvPortIdWidth ( TbAxiIdWidthMasters ), + .SlvPortIdWidthUsed ( TbAxiIdUsed ), + .AddrWidth ( TbAxiAddrWidth ), + .DataWidth ( TbAxiDataWidth ), + .UserWidth ( TbAxiUserWidth ), + .SlvPortMaxTxns ( TbSlvPortMaxTxns ), + .MstPortMaxTxns ( TbMstPortMaxTxns ), + .FallThrough ( TbFallThrough ), + .LatencyMode ( TbLatencyMode ), + .NumAddrRules ( TbNumAddrRules ), + .EnableAtops ( TbEnableAtops ), + .rule_t ( tb_addr_rule_t ) ) i_xbar_dut ( - .clk_i ( clk ), - .rst_ni ( rst_n ), - .test_i ( 1'b0 ), - .slv_ports_req_i ( masters_req ), - .slv_ports_resp_o ( masters_resp ), - .mst_ports_req_o ( slaves_req ), - .mst_ports_resp_i ( slaves_resp ), - .addr_map_i ( AddrMap ), - .en_default_mst_port_i ( '0 ), - .default_mst_port_i ( '0 ) + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_i ( 1'b0 ), + .slv_ports ( master ), + .mst_ports ( slave ), + .addr_map_i ( AddrMap ), + .en_default_mst_port_i ( '0 ), + .default_mst_ports_i ( '0 ) ); // logger for master modules - for (genvar i = 0; i < NoMasters; i++) begin : gen_master_logger + for (genvar i = 0; unsigned'(i) < TbNumMasters; i++) begin : gen_master_logger axi_chan_logger #( .TestTime ( TestTime ), // Time after clock, where sampling happens .LoggerName( $sformatf("axi_logger_master_%0d", i)), @@ -318,7 +325,7 @@ module tb_axi_xbar; ); end // logger for slave modules - for (genvar i = 0; i < NoSlaves; i++) begin : gen_slave_logger + for (genvar i = 0; unsigned'(i) < TbNumSlaves; i++) begin : gen_slave_logger axi_chan_logger #( .TestTime ( TestTime ), // Time after clock, where sampling happens .LoggerName( $sformatf("axi_logger_slave_%0d",i)), @@ -353,100 +360,4 @@ module tb_axi_xbar; .r_ready_i ( slaves_req[i].r_ready ) ); end - - - for (genvar i = 0; i < NoMasters; i++) begin : gen_connect_master_monitor - assign master_monitor_dv[i].aw_id = master[i].aw_id ; - assign master_monitor_dv[i].aw_addr = master[i].aw_addr ; - assign master_monitor_dv[i].aw_len = master[i].aw_len ; - assign master_monitor_dv[i].aw_size = master[i].aw_size ; - assign master_monitor_dv[i].aw_burst = master[i].aw_burst ; - assign master_monitor_dv[i].aw_lock = master[i].aw_lock ; - assign master_monitor_dv[i].aw_cache = master[i].aw_cache ; - assign master_monitor_dv[i].aw_prot = master[i].aw_prot ; - assign master_monitor_dv[i].aw_qos = master[i].aw_qos ; - assign master_monitor_dv[i].aw_region = master[i].aw_region; - assign master_monitor_dv[i].aw_atop = master[i].aw_atop ; - assign master_monitor_dv[i].aw_user = master[i].aw_user ; - assign master_monitor_dv[i].aw_valid = master[i].aw_valid ; - assign master_monitor_dv[i].aw_ready = master[i].aw_ready ; - assign master_monitor_dv[i].w_data = master[i].w_data ; - assign master_monitor_dv[i].w_strb = master[i].w_strb ; - assign master_monitor_dv[i].w_last = master[i].w_last ; - assign master_monitor_dv[i].w_user = master[i].w_user ; - assign master_monitor_dv[i].w_valid = master[i].w_valid ; - assign master_monitor_dv[i].w_ready = master[i].w_ready ; - assign master_monitor_dv[i].b_id = master[i].b_id ; - assign master_monitor_dv[i].b_resp = master[i].b_resp ; - assign master_monitor_dv[i].b_user = master[i].b_user ; - assign master_monitor_dv[i].b_valid = master[i].b_valid ; - assign master_monitor_dv[i].b_ready = master[i].b_ready ; - assign master_monitor_dv[i].ar_id = master[i].ar_id ; - assign master_monitor_dv[i].ar_addr = master[i].ar_addr ; - assign master_monitor_dv[i].ar_len = master[i].ar_len ; - assign master_monitor_dv[i].ar_size = master[i].ar_size ; - assign master_monitor_dv[i].ar_burst = master[i].ar_burst ; - assign master_monitor_dv[i].ar_lock = master[i].ar_lock ; - assign master_monitor_dv[i].ar_cache = master[i].ar_cache ; - assign master_monitor_dv[i].ar_prot = master[i].ar_prot ; - assign master_monitor_dv[i].ar_qos = master[i].ar_qos ; - assign master_monitor_dv[i].ar_region = master[i].ar_region; - assign master_monitor_dv[i].ar_user = master[i].ar_user ; - assign master_monitor_dv[i].ar_valid = master[i].ar_valid ; - assign master_monitor_dv[i].ar_ready = master[i].ar_ready ; - assign master_monitor_dv[i].r_id = master[i].r_id ; - assign master_monitor_dv[i].r_data = master[i].r_data ; - assign master_monitor_dv[i].r_resp = master[i].r_resp ; - assign master_monitor_dv[i].r_last = master[i].r_last ; - assign master_monitor_dv[i].r_user = master[i].r_user ; - assign master_monitor_dv[i].r_valid = master[i].r_valid ; - assign master_monitor_dv[i].r_ready = master[i].r_ready ; - end - for (genvar i = 0; i < NoSlaves; i++) begin : gen_connect_slave_monitor - assign slave_monitor_dv[i].aw_id = slave[i].aw_id ; - assign slave_monitor_dv[i].aw_addr = slave[i].aw_addr ; - assign slave_monitor_dv[i].aw_len = slave[i].aw_len ; - assign slave_monitor_dv[i].aw_size = slave[i].aw_size ; - assign slave_monitor_dv[i].aw_burst = slave[i].aw_burst ; - assign slave_monitor_dv[i].aw_lock = slave[i].aw_lock ; - assign slave_monitor_dv[i].aw_cache = slave[i].aw_cache ; - assign slave_monitor_dv[i].aw_prot = slave[i].aw_prot ; - assign slave_monitor_dv[i].aw_qos = slave[i].aw_qos ; - assign slave_monitor_dv[i].aw_region = slave[i].aw_region; - assign slave_monitor_dv[i].aw_atop = slave[i].aw_atop ; - assign slave_monitor_dv[i].aw_user = slave[i].aw_user ; - assign slave_monitor_dv[i].aw_valid = slave[i].aw_valid ; - assign slave_monitor_dv[i].aw_ready = slave[i].aw_ready ; - assign slave_monitor_dv[i].w_data = slave[i].w_data ; - assign slave_monitor_dv[i].w_strb = slave[i].w_strb ; - assign slave_monitor_dv[i].w_last = slave[i].w_last ; - assign slave_monitor_dv[i].w_user = slave[i].w_user ; - assign slave_monitor_dv[i].w_valid = slave[i].w_valid ; - assign slave_monitor_dv[i].w_ready = slave[i].w_ready ; - assign slave_monitor_dv[i].b_id = slave[i].b_id ; - assign slave_monitor_dv[i].b_resp = slave[i].b_resp ; - assign slave_monitor_dv[i].b_user = slave[i].b_user ; - assign slave_monitor_dv[i].b_valid = slave[i].b_valid ; - assign slave_monitor_dv[i].b_ready = slave[i].b_ready ; - assign slave_monitor_dv[i].ar_id = slave[i].ar_id ; - assign slave_monitor_dv[i].ar_addr = slave[i].ar_addr ; - assign slave_monitor_dv[i].ar_len = slave[i].ar_len ; - assign slave_monitor_dv[i].ar_size = slave[i].ar_size ; - assign slave_monitor_dv[i].ar_burst = slave[i].ar_burst ; - assign slave_monitor_dv[i].ar_lock = slave[i].ar_lock ; - assign slave_monitor_dv[i].ar_cache = slave[i].ar_cache ; - assign slave_monitor_dv[i].ar_prot = slave[i].ar_prot ; - assign slave_monitor_dv[i].ar_qos = slave[i].ar_qos ; - assign slave_monitor_dv[i].ar_region = slave[i].ar_region; - assign slave_monitor_dv[i].ar_user = slave[i].ar_user ; - assign slave_monitor_dv[i].ar_valid = slave[i].ar_valid ; - assign slave_monitor_dv[i].ar_ready = slave[i].ar_ready ; - assign slave_monitor_dv[i].r_id = slave[i].r_id ; - assign slave_monitor_dv[i].r_data = slave[i].r_data ; - assign slave_monitor_dv[i].r_resp = slave[i].r_resp ; - assign slave_monitor_dv[i].r_last = slave[i].r_last ; - assign slave_monitor_dv[i].r_user = slave[i].r_user ; - assign slave_monitor_dv[i].r_valid = slave[i].r_valid ; - assign slave_monitor_dv[i].r_ready = slave[i].r_ready ; - end -endmodule +endmodule : tb_axi_xbar diff --git a/test/tb_axi_xbar_pkg.sv b/test/tb_axi_xbar_pkg.sv index d46a09515..26dd08856 100644 --- a/test/tb_axi_xbar_pkg.sv +++ b/test/tb_axi_xbar_pkg.sv @@ -19,81 +19,81 @@ package tb_axi_xbar_pkg; class axi_xbar_monitor #( - parameter int unsigned AxiAddrWidth, - parameter int unsigned AxiDataWidth, - parameter int unsigned AxiIdWidthMasters, - parameter int unsigned AxiIdWidthSlaves, - parameter int unsigned AxiUserWidth, - parameter int unsigned NoMasters, - parameter int unsigned NoSlaves, - parameter int unsigned NoAddrRules, + parameter int unsigned AddrWidth, + parameter int unsigned DataWidth, + parameter int unsigned SlvPortIdWidth, + parameter int unsigned MstPortIdWidth, + parameter int unsigned UserWidth, + parameter int unsigned NumSlvPorts, + parameter int unsigned NumMstPorts, + parameter int unsigned NumAddrRules, parameter type rule_t, - parameter rule_t [NoAddrRules-1:0] AddrMap, + parameter rule_t [NumAddrRules-1:0] AddrMap, // Stimuli application and test time - parameter time TimeTest + parameter time TestTime ); - typedef logic [AxiIdWidthMasters-1:0] mst_axi_id_t; - typedef logic [AxiIdWidthSlaves-1:0] slv_axi_id_t; - typedef logic [AxiAddrWidth-1:0] axi_addr_t; + typedef logic [SlvPortIdWidth-1:0] slv_port_axi_id_t; + typedef logic [MstPortIdWidth-1:0] mst_port_axi_id_t; + typedef logic [AddrWidth-1:0] axi_addr_t; - typedef logic [$clog2(NoMasters)-1:0] idx_mst_t; - typedef int unsigned idx_slv_t; // from rule_t + typedef logic [$clog2(NumSlvPorts)-1:0] idx_mst_t; // Index of conected master + typedef int unsigned idx_slv_t; // Connected salve index from rule_t typedef struct packed { - mst_axi_id_t mst_axi_id; - logic last; + slv_port_axi_id_t mst_axi_id; + logic last; } master_exp_t; typedef struct packed { - slv_axi_id_t slv_axi_id; - axi_addr_t slv_axi_addr; - axi_pkg::len_t slv_axi_len; + mst_port_axi_id_t slv_axi_id; + axi_addr_t slv_axi_addr; + axi_pkg::len_t slv_axi_len; } exp_ax_t; typedef struct packed { - slv_axi_id_t slv_axi_id; - logic last; + mst_port_axi_id_t slv_axi_id; + logic last; } slave_exp_t; typedef rand_id_queue_pkg::rand_id_queue #( - .data_t ( master_exp_t ), - .ID_WIDTH ( AxiIdWidthMasters ) + .data_t ( master_exp_t ), + .ID_WIDTH ( SlvPortIdWidth ) ) master_exp_queue_t; typedef rand_id_queue_pkg::rand_id_queue #( - .data_t ( exp_ax_t ), - .ID_WIDTH ( AxiIdWidthSlaves ) + .data_t ( exp_ax_t ), + .ID_WIDTH ( MstPortIdWidth ) ) ax_queue_t; typedef rand_id_queue_pkg::rand_id_queue #( - .data_t ( slave_exp_t ), - .ID_WIDTH ( AxiIdWidthSlaves ) + .data_t ( slave_exp_t ), + .ID_WIDTH ( MstPortIdWidth ) ) slave_exp_queue_t; //----------------------------------------- // Monitoring virtual interfaces //----------------------------------------- virtual AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthMasters ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) masters_axi [NoMasters-1:0]; + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( SlvPortIdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) slv_ports[NumSlvPorts]; virtual AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthSlaves ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) slaves_axi [NoSlaves-1:0]; + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( MstPortIdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) mst_ports[NumMstPorts]; //----------------------------------------- // Queues and FIFOs to hold the expected ids //----------------------------------------- // Write transactions - ax_queue_t exp_aw_queue [NoSlaves-1:0]; - slave_exp_t exp_w_fifo [NoSlaves-1:0][$]; - slave_exp_t act_w_fifo [NoSlaves-1:0][$]; - master_exp_queue_t exp_b_queue [NoMasters-1:0]; + ax_queue_t exp_aw_queue [NumMstPorts-1:0]; + slave_exp_t exp_w_fifo [NumMstPorts-1:0][$]; + slave_exp_t act_w_fifo [NumMstPorts-1:0][$]; + master_exp_queue_t exp_b_queue [NumSlvPorts-1:0]; // Read transactions - ax_queue_t exp_ar_queue [NoSlaves-1:0]; - master_exp_queue_t exp_r_queue [NoMasters-1:0]; + ax_queue_t exp_ar_queue [NumMstPorts-1:0]; + master_exp_queue_t exp_r_queue [NumSlvPorts-1:0]; //----------------------------------------- // Bookkeeping @@ -108,29 +108,29 @@ package tb_axi_xbar_pkg; //----------------------------------------- function new( virtual AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthMasters ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) axi_masters_vif [NoMasters-1:0], + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( SlvPortIdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) slv_ports_vif[NumSlvPorts], virtual AXI_BUS_DV #( - .AXI_ADDR_WIDTH ( AxiAddrWidth ), - .AXI_DATA_WIDTH ( AxiDataWidth ), - .AXI_ID_WIDTH ( AxiIdWidthSlaves ), - .AXI_USER_WIDTH ( AxiUserWidth ) - ) axi_slaves_vif [NoSlaves-1:0] + .AXI_ADDR_WIDTH ( AddrWidth ), + .AXI_DATA_WIDTH ( DataWidth ), + .AXI_ID_WIDTH ( MstPortIdWidth ), + .AXI_USER_WIDTH ( UserWidth ) + ) mst_ports_vif[NumMstPorts] ); begin - this.masters_axi = axi_masters_vif; - this.slaves_axi = axi_slaves_vif; + this.slv_ports = slv_ports_vif; + this.mst_ports = mst_ports_vif; this.tests_expected = 0; this.tests_conducted = 0; this.tests_failed = 0; - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumSlvPorts; i++) begin this.exp_b_queue[i] = new; this.exp_r_queue[i] = new; end - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumMstPorts; i++) begin this.exp_aw_queue[i] = new; this.exp_ar_queue[i] = new; end @@ -140,12 +140,12 @@ package tb_axi_xbar_pkg; // when start the testing task cycle_start; - #TimeTest; + #TestTime; endtask // when is cycle finished task cycle_end; - @(posedge masters_axi[0].clk_i); + @(posedge slv_ports[0].clk_i); endtask // This task monitors a slave ports of the crossbar. Every time an AW beat is seen @@ -155,50 +155,50 @@ package tb_axi_xbar_pkg; task automatic monitor_mst_aw(input int unsigned i); idx_slv_t to_slave_idx; exp_ax_t exp_aw; - slv_axi_id_t exp_aw_id; + mst_port_axi_id_t exp_aw_id; bit decerr; master_exp_t exp_b; - if (masters_axi[i].aw_valid && masters_axi[i].aw_ready) begin + if (slv_ports[i].aw_valid && slv_ports[i].aw_ready) begin // check if it should go to a decerror decerr = 1'b1; - for (int unsigned j = 0; j < NoAddrRules; j++) begin - if ((masters_axi[i].aw_addr >= AddrMap[j].start_addr) && - (masters_axi[i].aw_addr < AddrMap[j].end_addr)) begin + for (int unsigned j = 0; j < NumAddrRules; j++) begin + if ((slv_ports[i].aw_addr >= AddrMap[j].start_addr) && + (slv_ports[i].aw_addr < AddrMap[j].end_addr)) begin to_slave_idx = idx_slv_t'(AddrMap[j].idx); decerr = 1'b0; end end // send the exp aw beat down into the queue of the slave when no decerror if (!decerr) begin - exp_aw_id = {idx_mst_t'(i), masters_axi[i].aw_id}; + exp_aw_id = {idx_mst_t'(i), slv_ports[i].aw_id}; // $display("Test exp aw_id: %b",exp_aw_id); exp_aw = '{slv_axi_id: exp_aw_id, - slv_axi_addr: masters_axi[i].aw_addr, - slv_axi_len: masters_axi[i].aw_len }; + slv_axi_addr: slv_ports[i].aw_addr, + slv_axi_len: slv_ports[i].aw_len }; this.exp_aw_queue[to_slave_idx].push(exp_aw_id, exp_aw); incr_expected_tests(3); $display("%0tns > Master %0d: AW to Slave %0d: Axi ID: %b", - $time, i, to_slave_idx, masters_axi[i].aw_id); + $time, i, to_slave_idx, slv_ports[i].aw_id); end else begin $display("%0tns > Master %0d: AW to Decerror: Axi ID: %b", - $time, i, to_slave_idx, masters_axi[i].aw_id); + $time, i, to_slave_idx, slv_ports[i].aw_id); end // populate the expected b queue anyway - exp_b = '{mst_axi_id: masters_axi[i].aw_id, last: 1'b1}; - this.exp_b_queue[i].push(masters_axi[i].aw_id, exp_b); + exp_b = '{mst_axi_id: slv_ports[i].aw_id, last: 1'b1}; + this.exp_b_queue[i].push(slv_ports[i].aw_id, exp_b); incr_expected_tests(1); $display(" Expect B response."); // inject expected r beats on this id, if it is an atop - if(masters_axi[i].aw_atop[5]) begin + if(slv_ports[i].aw_atop[5]) begin // push the required r beats into the right fifo (reuse the exp_b variable) - $display(" Expect R response, len: %0d.", masters_axi[i].aw_len); - for (int unsigned j = 0; j <= masters_axi[i].aw_len; j++) begin - exp_b = (j == masters_axi[i].aw_len) ? - '{mst_axi_id: masters_axi[i].aw_id, last: 1'b1} : - '{mst_axi_id: masters_axi[i].aw_id, last: 1'b0}; - this.exp_r_queue[i].push(masters_axi[i].aw_id, exp_b); + $display(" Expect R response, len: %0d.", slv_ports[i].aw_len); + for (int unsigned j = 0; j <= slv_ports[i].aw_len; j++) begin + exp_b = (j == slv_ports[i].aw_len) ? + '{mst_axi_id: slv_ports[i].aw_id, last: 1'b1} : + '{mst_axi_id: slv_ports[i].aw_id, last: 1'b0}; + this.exp_r_queue[i].push(slv_ports[i].aw_id, exp_b); incr_expected_tests(1); end end @@ -212,34 +212,34 @@ package tb_axi_xbar_pkg; exp_ax_t exp_aw; slave_exp_t exp_slv_w; // $display("%0t > Was triggered: aw_valid %b, aw_ready: %b", - // $time(), slaves_axi[i].aw_valid, slaves_axi[i].aw_ready); - if (slaves_axi[i].aw_valid && slaves_axi[i].aw_ready) begin + // $time(), mst_ports[i].aw_valid, mst_ports[i].aw_ready); + if (mst_ports[i].aw_valid && mst_ports[i].aw_ready) begin // test if the aw beat was expected - exp_aw = this.exp_aw_queue[i].pop_id(slaves_axi[i].aw_id); + exp_aw = this.exp_aw_queue[i].pop_id(mst_ports[i].aw_id); $display("%0tns > Slave %0d: AW Axi ID: %b", - $time, i, slaves_axi[i].aw_id); - if (exp_aw.slv_axi_id != slaves_axi[i].aw_id) begin + $time, i, mst_ports[i].aw_id); + if (exp_aw.slv_axi_id != mst_ports[i].aw_id) begin incr_failed_tests(1); - $warning("Slave %0d: Unexpected AW with ID: %b", i, slaves_axi[i].aw_id); + $error("Slave %0d: Unexpected AW with ID: %b", i, mst_ports[i].aw_id); end - if (exp_aw.slv_axi_addr != slaves_axi[i].aw_addr) begin + if (exp_aw.slv_axi_addr != mst_ports[i].aw_addr) begin incr_failed_tests(1); - $warning("Slave %0d: Unexpected AW with ID: %b and ADDR: %h, exp: %h", - i, slaves_axi[i].aw_id, slaves_axi[i].aw_addr, exp_aw.slv_axi_addr); + $error("Slave %0d: Unexpected AW with ID: %b and ADDR: %h, exp: %h", + i, mst_ports[i].aw_id, mst_ports[i].aw_addr, exp_aw.slv_axi_addr); end - if (exp_aw.slv_axi_len != slaves_axi[i].aw_len) begin + if (exp_aw.slv_axi_len != mst_ports[i].aw_len) begin incr_failed_tests(1); - $warning("Slave %0d: Unexpected AW with ID: %b and LEN: %h, exp: %h", - i, slaves_axi[i].aw_id, slaves_axi[i].aw_len, exp_aw.slv_axi_len); + $error("Slave %0d: Unexpected AW with ID: %b and LEN: %h, exp: %h", + i, mst_ports[i].aw_id, mst_ports[i].aw_len, exp_aw.slv_axi_len); end incr_conducted_tests(3); // push the required w beats into the right fifo - incr_expected_tests(slaves_axi[i].aw_len + 1); - for (int unsigned j = 0; j <= slaves_axi[i].aw_len; j++) begin - exp_slv_w = (j == slaves_axi[i].aw_len) ? - '{slv_axi_id: slaves_axi[i].aw_id, last: 1'b1} : - '{slv_axi_id: slaves_axi[i].aw_id, last: 1'b0}; + incr_expected_tests(mst_ports[i].aw_len + 1); + for (int unsigned j = 0; j <= mst_ports[i].aw_len; j++) begin + exp_slv_w = (j == mst_ports[i].aw_len) ? + '{slv_axi_id: mst_ports[i].aw_id, last: 1'b1} : + '{slv_axi_id: mst_ports[i].aw_id, last: 1'b0}; this.exp_w_fifo[i].push_back(exp_slv_w); end end @@ -248,9 +248,9 @@ package tb_axi_xbar_pkg; // This task just pushes every W beat that gets sent on a master port in its respective fifo. task automatic monitor_slv_w(input int unsigned i); slave_exp_t act_slv_w; - if (slaves_axi[i].w_valid && slaves_axi[i].w_ready) begin - // $display("%0t > W beat on Slave %0d, last flag: %b", $time, i, slaves_axi[i].w_last); - act_slv_w = '{last: slaves_axi[i].w_last , default:'0}; + if (mst_ports[i].w_valid && mst_ports[i].w_ready) begin + // $display("%0t > W beat on Slave %0d, last flag: %b", $time, i, mst_ports[i].w_last); + act_slv_w = '{last: mst_ports[i].w_last , default:'0}; this.act_w_fifo[i].push_back(act_slv_w); end endtask : monitor_slv_w @@ -268,7 +268,7 @@ package tb_axi_xbar_pkg; incr_conducted_tests(1); if(exp_w.last != act_w.last) begin incr_failed_tests(1); - $warning("Slave %d: unexpected W beat last flag %b, expected: %b.", + $error("Slave %d: unexpected W beat last flag %b, expected: %b.", i, act_w.last, exp_w.last); end end @@ -277,20 +277,20 @@ package tb_axi_xbar_pkg; // This task checks if a B response is allowed on a slave port of the crossbar. task automatic monitor_mst_b(input int unsigned i); master_exp_t exp_b; - mst_axi_id_t axi_b_id; - if (masters_axi[i].b_valid && masters_axi[i].b_ready) begin + slv_port_axi_id_t axi_b_id; + if (slv_ports[i].b_valid && slv_ports[i].b_ready) begin incr_conducted_tests(1); - axi_b_id = masters_axi[i].b_id; + axi_b_id = slv_ports[i].b_id; $display("%0tns > Master %0d: Got last B with id: %b", $time, i, axi_b_id); if (this.exp_b_queue[i].empty()) begin incr_failed_tests(1); - $warning("Master %d: unexpected B beat with ID: %b detected!", i, axi_b_id); + $error("Master %d: unexpected B beat with ID: %b detected!", i, axi_b_id); end else begin exp_b = this.exp_b_queue[i].pop_id(axi_b_id); if (axi_b_id != exp_b.mst_axi_id) begin incr_failed_tests(1); - $warning("Master: %d got unexpected B with ID: %b", i, axi_b_id); + $error("Master: %d got unexpected B with ID: %b", i, axi_b_id); end end end @@ -301,25 +301,25 @@ package tb_axi_xbar_pkg; // Emphasis on the last flag. We will detect reordering, if the last flags do not match, // as each `random` burst tend to have a different length. task automatic monitor_mst_ar(input int unsigned i); - mst_axi_id_t mst_axi_id; + slv_port_axi_id_t mst_axi_id; axi_addr_t mst_axi_addr; axi_pkg::len_t mst_axi_len; idx_slv_t exp_slv_idx; - slv_axi_id_t exp_slv_axi_id; + mst_port_axi_id_t exp_slv_axi_id; exp_ax_t exp_slv_ar; master_exp_t exp_mst_r; logic exp_decerr; - if (masters_axi[i].ar_valid && masters_axi[i].ar_ready) begin + if (slv_ports[i].ar_valid && slv_ports[i].ar_ready) begin exp_decerr = 1'b1; - mst_axi_id = masters_axi[i].ar_id; - mst_axi_addr = masters_axi[i].ar_addr; - mst_axi_len = masters_axi[i].ar_len; + mst_axi_id = slv_ports[i].ar_id; + mst_axi_addr = slv_ports[i].ar_addr; + mst_axi_len = slv_ports[i].ar_len; exp_slv_axi_id = {idx_mst_t'(i), mst_axi_id}; exp_slv_idx = '0; - for (int unsigned j = 0; j < NoAddrRules; j++) begin + for (int unsigned j = 0; j < NumAddrRules; j++) begin if ((mst_axi_addr >= AddrMap[j].start_addr) && (mst_axi_addr < AddrMap[j].end_addr)) begin exp_slv_idx = AddrMap[j].idx; exp_decerr = 1'b0; @@ -340,7 +340,7 @@ package tb_axi_xbar_pkg; incr_expected_tests(1); end // push the required r beats into the right fifo - $display(" Expect R response, len: %0d.", masters_axi[i].ar_len); + $display(" Expect R response, len: %0d.", slv_ports[i].ar_len); for (int unsigned j = 0; j <= mst_axi_len; j++) begin exp_mst_r = (j == mst_axi_len) ? '{mst_axi_id: mst_axi_id, last: 1'b1} : '{mst_axi_id: mst_axi_id, last: 1'b0}; @@ -354,10 +354,10 @@ package tb_axi_xbar_pkg; // expected. task automatic monitor_slv_ar(input int unsigned i); exp_ax_t exp_slv_ar; - slv_axi_id_t slv_axi_id; - if (slaves_axi[i].ar_valid && slaves_axi[i].ar_ready) begin + mst_port_axi_id_t slv_axi_id; + if (mst_ports[i].ar_valid && mst_ports[i].ar_ready) begin incr_conducted_tests(1); - slv_axi_id = slaves_axi[i].ar_id; + slv_axi_id = mst_ports[i].ar_id; if (this.exp_ar_queue[i].empty()) begin incr_failed_tests(1); end else begin @@ -366,7 +366,7 @@ package tb_axi_xbar_pkg; $display("%0tns > Slave %0d: AR Axi ID: %b", $time, i, slv_axi_id); if (exp_slv_ar.slv_axi_id != slv_axi_id) begin incr_failed_tests(1); - $warning("Slave %d: Unexpected AR with ID: %b", i, slv_axi_id); + $error("Slave %d: Unexpected AR with ID: %b", i, slv_axi_id); end end end @@ -376,28 +376,28 @@ package tb_axi_xbar_pkg; // which are determined by the sequence of previously sent AR vectors. task automatic monitor_mst_r(input int unsigned i); master_exp_t exp_mst_r; - mst_axi_id_t mst_axi_r_id; + slv_port_axi_id_t mst_axi_r_id; logic mst_axi_r_last; - if (masters_axi[i].r_valid && masters_axi[i].r_ready) begin + if (slv_ports[i].r_valid && slv_ports[i].r_ready) begin incr_conducted_tests(1); - mst_axi_r_id = masters_axi[i].r_id; - mst_axi_r_last = masters_axi[i].r_last; + mst_axi_r_id = slv_ports[i].r_id; + mst_axi_r_last = slv_ports[i].r_last; if (mst_axi_r_last) begin $display("%0tns > Master %0d: Got last R with id: %b", $time, i, mst_axi_r_id); end if (this.exp_r_queue[i].empty()) begin incr_failed_tests(1); - $warning("Master %d: unexpected R beat with ID: %b detected!", i, mst_axi_r_id); + $error("Master %d: unexpected R beat with ID: %b detected!", i, mst_axi_r_id); end else begin exp_mst_r = this.exp_r_queue[i].pop_id(mst_axi_r_id); if (mst_axi_r_id != exp_mst_r.mst_axi_id) begin incr_failed_tests(1); - $warning("Master: %d got unexpected R with ID: %b", i, mst_axi_r_id); + $error("Master: %d got unexpected R with ID: %b", i, mst_axi_r_id); end if (mst_axi_r_last != exp_mst_r.last) begin incr_failed_tests(1); - $warning("Master: %d got unexpected R with ID: %b and last flag: %b", + $error("Master: %d got unexpected R with ID: %b and last flag: %b", i, mst_axi_r_id, mst_axi_r_last); end end @@ -436,48 +436,48 @@ package tb_axi_xbar_pkg; // execute all processes that put something into the queues PushMon: fork proc_mst_aw: begin - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumSlvPorts; i++) begin monitor_mst_aw(i); end end proc_mst_ar: begin - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumSlvPorts; i++) begin monitor_mst_ar(i); end end join : PushMon // this one pops and pushes something proc_slv_aw: begin - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumMstPorts; i++) begin monitor_slv_aw(i); end end proc_slv_w: begin - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumMstPorts; i++) begin monitor_slv_w(i); end end // These only pop somethong from the queses PopMon: fork proc_mst_b: begin - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumSlvPorts; i++) begin monitor_mst_b(i); end end proc_slv_ar: begin - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumMstPorts; i++) begin monitor_slv_ar(i); end end proc_mst_r: begin - for (int unsigned i = 0; i < NoMasters; i++) begin + for (int unsigned i = 0; i < NumSlvPorts; i++) begin monitor_mst_r(i); end end join : PopMon // check the slave W fifos last proc_check_slv_w: begin - for (int unsigned i = 0; i < NoSlaves; i++) begin + for (int unsigned i = 0; i < NumMstPorts; i++) begin check_slv_w(i); end end