From c94b1fb35b2f04adb9279a9103105756e84e96dd Mon Sep 17 00:00:00 2001
From: Michael Rogenmoser <michael@rogenmoser.us>
Date: Mon, 10 Apr 2023 23:35:10 +0200
Subject: [PATCH] change port naming in line with style guide

---
 doc/svg/axi_lite_mux.svg           |   2 +-
 src/axi_atop_filter.sv             | 132 +++++++--------
 src/axi_burst_splitter.sv          |  96 +++++------
 src/axi_cut.sv                     |  84 +++++-----
 src/axi_delayer.sv                 |  76 ++++-----
 src/axi_demux.sv                   |  78 ++++-----
 src/axi_dw_converter.sv            |  36 ++---
 src/axi_dw_downsizer.sv            | 100 ++++++------
 src/axi_dw_upsizer.sv              |  88 +++++-----
 src/axi_err_sbr.sv                 |  18 +--
 src/axi_fifo.sv                    |  80 +++++-----
 src/axi_from_mem.sv                |   4 +-
 src/axi_id_remap.sv                | 248 ++++++++++++++---------------
 src/axi_id_serialize.sv            |  86 +++++-----
 src/axi_isolate.sv                 | 124 +++++++--------
 src/axi_iw_converter.sv            | 104 ++++++------
 src/axi_lfsr.sv                    |   8 +-
 src/axi_lite_demux.sv              |  72 ++++-----
 src/axi_lite_mailbox.sv            |  76 ++++-----
 src/axi_lite_mux.sv                |  68 ++++----
 src/axi_lite_to_axi.sv             |  22 +--
 src/axi_lite_xbar.sv               |  16 +-
 src/axi_modify_address.sv          |  74 ++++-----
 src/axi_multicut.sv                |  44 ++---
 src/axi_mux.sv                     |  84 +++++-----
 src/axi_rw_join.sv                 |  34 ++--
 src/axi_rw_split.sv                |  34 ++--
 src/axi_serializer.sv              |  94 +++++------
 src/axi_to_axi_lite.sv             | 118 +++++++-------
 src/axi_to_mem_banked.sv           |   4 +-
 src/axi_to_mem_split.sv            |   4 +-
 src/axi_xbar.sv                    |  24 +--
 src/axi_xp.sv                      |  28 ++--
 test/tb_axi_bus_compare.sv         |   8 +-
 test/tb_axi_fifo.wave.do           |  32 ++--
 test/tb_axi_serializer.wave.do     |   4 +-
 test/tb_axi_subordinate_compare.sv |   8 +-
 37 files changed, 1106 insertions(+), 1106 deletions(-)

diff --git a/doc/svg/axi_lite_mux.svg b/doc/svg/axi_lite_mux.svg
index e3d610b86..523c50760 100644
--- a/doc/svg/axi_lite_mux.svg
+++ b/doc/svg/axi_lite_mux.svg
@@ -2956,7 +2956,7 @@
          x="30.112265"
          y="286.17563"
          style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:3.88055563px;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Bold';text-align:center;writing-mode:lr-tb;text-anchor:middle;fill:#0000ff;fill-opacity:1;stroke-width:0.26458332"
-         id="tspan1345-5">mgr_req_o</tspan></text>
+         id="tspan1345-5">mgr_port_req_o</tspan></text>
     <text
        xml:space="preserve"
        style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:3.88055563px;line-height:1.10000002;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Bold';text-align:center;letter-spacing:0px;word-spacing:0px;writing-mode:lr-tb;text-anchor:middle;display:inline;fill:#0000ff;fill-opacity:1;stroke:none;stroke-width:0.26458332;filter:url(#filter8341-4)"
diff --git a/src/axi_atop_filter.sv b/src/axi_atop_filter.sv
index 369636593..84d60c30e 100644
--- a/src/axi_atop_filter.sv
+++ b/src/axi_atop_filter.sv
@@ -49,13 +49,13 @@ module axi_atop_filter #(
   /// Asynchronous reset, active low
   input  logic     rst_ni,
   /// Subordinate port request
-  input  axi_req_t sbr_req_i,
+  input  axi_req_t sbr_port_req_i,
   /// Subordinate port response
-  output axi_rsp_t sbr_rsp_o,
+  output axi_rsp_t sbr_port_rsp_o,
   /// Manager port request
-  output axi_req_t mgr_req_o,
+  output axi_req_t mgr_port_req_o,
   /// Manager port response
-  input  axi_rsp_t mgr_rsp_i
+  input  axi_rsp_t mgr_port_rsp_i
 );
 
   // Minimum counter width is 2 to detect underflows.
@@ -100,14 +100,14 @@ module axi_atop_filter #(
   always_comb begin
     // Defaults:
     // Disable AW and W handshakes.
-    mgr_req_o.aw_valid = 1'b0;
-    sbr_rsp_o.aw_ready = 1'b0;
-    mgr_req_o.w_valid  = 1'b0;
-    sbr_rsp_o.w_ready  = 1'b0;
+    mgr_port_req_o.aw_valid = 1'b0;
+    sbr_port_rsp_o.aw_ready = 1'b0;
+    mgr_port_req_o.w_valid  = 1'b0;
+    sbr_port_rsp_o.w_ready  = 1'b0;
     // Feed write responses through.
-    mgr_req_o.b_ready  = sbr_req_i.b_ready;
-    sbr_rsp_o.b_valid  = mgr_rsp_i.b_valid;
-    sbr_rsp_o.b        = mgr_rsp_i.b;
+    mgr_port_req_o.b_ready  = sbr_port_req_i.b_ready;
+    sbr_port_rsp_o.b_valid  = mgr_port_rsp_i.b_valid;
+    sbr_port_rsp_o.b        = mgr_port_rsp_i.b;
     // Keep ID stored for B and R response.
     id_d = id_q;
     // Do not push R response commands.
@@ -119,26 +119,26 @@ module axi_atop_filter #(
       W_FEEDTHROUGH: begin
         // Feed AW channel through if the maximum number of outstanding bursts is not reached.
         if (complete_w_without_aw_downstream || (w_cnt_q.cnt < MaxWriteTxns)) begin
-          mgr_req_o.aw_valid = sbr_req_i.aw_valid;
-          sbr_rsp_o.aw_ready = mgr_rsp_i.aw_ready;
+          mgr_port_req_o.aw_valid = sbr_port_req_i.aw_valid;
+          sbr_port_rsp_o.aw_ready = mgr_port_rsp_i.aw_ready;
         end
         // Feed W channel through if ..
         if (aw_without_complete_w_downstream // .. downstream is missing W bursts ..
             // .. or a new non-ATOP AW is being applied and there is not already a complete W burst
             // downstream (to prevent underflows of w_cnt).
-            || ((sbr_req_i.aw_valid && sbr_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE)
+            || ((sbr_port_req_i.aw_valid && sbr_port_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE)
                 && !complete_w_without_aw_downstream)
         ) begin
-          mgr_req_o.w_valid = sbr_req_i.w_valid;
-          sbr_rsp_o.w_ready = mgr_rsp_i.w_ready;
+          mgr_port_req_o.w_valid = sbr_port_req_i.w_valid;
+          sbr_port_rsp_o.w_ready = mgr_port_rsp_i.w_ready;
         end
         // Filter out AWs that are atomic operations.
-        if (sbr_req_i.aw_valid && sbr_req_i.aw.atop[5:4] != axi_pkg::ATOP_NONE) begin
-          mgr_req_o.aw_valid = 1'b0; // Do not let AW pass to manager port.
-          sbr_rsp_o.aw_ready = 1'b1; // Absorb AW on subordinate port.
-          id_d = sbr_req_i.aw.id; // Store ID for B response.
+        if (sbr_port_req_i.aw_valid && sbr_port_req_i.aw.atop[5:4] != axi_pkg::ATOP_NONE) begin
+          mgr_port_req_o.aw_valid = 1'b0; // Do not let AW pass to manager port.
+          sbr_port_rsp_o.aw_ready = 1'b1; // Absorb AW on subordinate port.
+          id_d = sbr_port_req_i.aw.id; // Store ID for B response.
           // Some atomic operations require a response on the R channel.
-          if (sbr_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin
+          if (sbr_port_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin
             // Push R response command.  We do not have to wait for the ready of the register
             // because we know it is ready: we are its only manager and will wait for the register to
             // be emptied before going back to the `W_FEEDTHROUGH` state.
@@ -149,13 +149,13 @@ module axi_atop_filter #(
             w_state_d = BLOCK_AW;
           // If downstream is not missing W beats, absorb the W beats for this atomic AW.
           end else begin
-            mgr_req_o.w_valid  = 1'b0; // Do not let W beats pass to manager port.
-            sbr_rsp_o.w_ready = 1'b1; // Absorb W beats on subordinate port.
-            if (sbr_req_i.w_valid && sbr_req_i.w.last) begin
+            mgr_port_req_o.w_valid  = 1'b0; // Do not let W beats pass to manager port.
+            sbr_port_rsp_o.w_ready = 1'b1; // Absorb W beats on subordinate port.
+            if (sbr_port_req_i.w_valid && sbr_port_req_i.w.last) begin
               // If the W beat is valid and the last, proceed by injecting the B response.
               // However, if there is a non-handshaked B on our response port, we must let that
               // complete first.
-              if (sbr_rsp_o.b_valid && !sbr_req_i.b_ready) begin
+              if (sbr_port_rsp_o.b_valid && !sbr_port_req_i.b_ready) begin
                 w_state_d = HOLD_B;
               end else begin
                 w_state_d = INJECT_B;
@@ -171,14 +171,14 @@ module axi_atop_filter #(
       BLOCK_AW: begin
         // Feed W channel through to let outstanding bursts complete.
         if (aw_without_complete_w_downstream) begin
-          mgr_req_o.w_valid = sbr_req_i.w_valid;
-          sbr_rsp_o.w_ready = mgr_rsp_i.w_ready;
+          mgr_port_req_o.w_valid = sbr_port_req_i.w_valid;
+          sbr_port_rsp_o.w_ready = mgr_port_rsp_i.w_ready;
         end else begin
           // If there are no more outstanding W bursts, start absorbing the next W burst.
-          sbr_rsp_o.w_ready = 1'b1;
-          if (sbr_req_i.w_valid && sbr_req_i.w.last) begin
+          sbr_port_rsp_o.w_ready = 1'b1;
+          if (sbr_port_req_i.w_valid && sbr_port_req_i.w.last) begin
             // If the W beat is valid and the last, proceed by injecting the B response.
-            if (sbr_rsp_o.b_valid && !sbr_req_i.b_ready) begin
+            if (sbr_port_rsp_o.b_valid && !sbr_port_req_i.b_ready) begin
               w_state_d = HOLD_B;
             end else begin
               w_state_d = INJECT_B;
@@ -192,9 +192,9 @@ module axi_atop_filter #(
 
       ABSORB_W: begin
         // Absorb all W beats of the current burst.
-        sbr_rsp_o.w_ready = 1'b1;
-        if (sbr_req_i.w_valid && sbr_req_i.w.last) begin
-          if (sbr_rsp_o.b_valid && !sbr_req_i.b_ready) begin
+        sbr_port_rsp_o.w_ready = 1'b1;
+        if (sbr_port_req_i.w_valid && sbr_port_req_i.w.last) begin
+          if (sbr_port_rsp_o.b_valid && !sbr_port_req_i.b_ready) begin
             w_state_d = HOLD_B;
           end else begin
             w_state_d = INJECT_B;
@@ -204,22 +204,22 @@ module axi_atop_filter #(
 
       HOLD_B: begin
         // Proceed with injection of B response upon handshake.
-        if (sbr_rsp_o.b_valid && sbr_req_i.b_ready) begin
+        if (sbr_port_rsp_o.b_valid && sbr_port_req_i.b_ready) begin
           w_state_d = INJECT_B;
         end
       end
 
       INJECT_B: begin
         // Pause forwarding of B response.
-        mgr_req_o.b_ready = 1'b0;
+        mgr_port_req_o.b_ready = 1'b0;
         // Inject error response instead.  Since the B channel has an ID and the atomic burst we are
         // replying to is guaranteed to be the only burst with this ID in flight, we do not have to
         // observe any ordering and can immediately inject on the B channel.
-        sbr_rsp_o.b = '0;
-        sbr_rsp_o.b.id = id_q;
-        sbr_rsp_o.b.resp = axi_pkg::RESP_SLVERR;
-        sbr_rsp_o.b_valid = 1'b1;
-        if (sbr_req_i.b_ready) begin
+        sbr_port_rsp_o.b = '0;
+        sbr_port_rsp_o.b.id = id_q;
+        sbr_port_rsp_o.b.resp = axi_pkg::RESP_SLVERR;
+        sbr_port_rsp_o.b_valid = 1'b1;
+        if (sbr_port_req_i.b_ready) begin
           // If not all beats of the R response have been injected, wait for them. Otherwise, return
           // to `W_FEEDTHROUGH`.
           if (r_resp_cmd_pop_valid && !r_resp_cmd_pop_ready) begin
@@ -246,18 +246,18 @@ module axi_atop_filter #(
   // Feed-through of the AW and W vectors, make sure that downstream aw.atop is always zero
   always_comb begin
     // overwrite the atop signal
-    mgr_req_o.aw      = sbr_req_i.aw;
-    mgr_req_o.aw.atop = '0;
+    mgr_port_req_o.aw      = sbr_port_req_i.aw;
+    mgr_port_req_o.aw.atop = '0;
   end
-  assign mgr_req_o.w = sbr_req_i.w;
+  assign mgr_port_req_o.w = sbr_port_req_i.w;
 
   // Manage R channel.
   always_comb begin
     // Defaults:
     // Feed read responses through.
-    sbr_rsp_o.r       = mgr_rsp_i.r;
-    sbr_rsp_o.r_valid = mgr_rsp_i.r_valid;
-    mgr_req_o.r_ready = sbr_req_i.r_ready;
+    sbr_port_rsp_o.r       = mgr_port_rsp_i.r;
+    sbr_port_rsp_o.r_valid = mgr_port_rsp_i.r_valid;
+    mgr_port_req_o.r_ready = sbr_port_req_i.r_ready;
     // Do not pop R response command.
     r_resp_cmd_pop_ready = 1'b0;
     // Keep the current value of the beats counter.
@@ -267,7 +267,7 @@ module axi_atop_filter #(
 
     unique case (r_state_q)
       R_FEEDTHROUGH: begin
-        if (mgr_rsp_i.r_valid && !sbr_req_i.r_ready) begin
+        if (mgr_port_rsp_i.r_valid && !sbr_port_req_i.r_ready) begin
           r_state_d = R_HOLD;
         end else if (r_resp_cmd_pop_valid) begin
           // Upon a command to inject an R response, immediately proceed with doing so because there
@@ -279,14 +279,14 @@ module axi_atop_filter #(
       end
 
       INJECT_R: begin
-        mgr_req_o.r_ready = 1'b0;
-        sbr_rsp_o.r       = '0;
-        sbr_rsp_o.r.id    = id_q;
-        sbr_rsp_o.r.resp  = axi_pkg::RESP_SLVERR;
-        sbr_rsp_o.r.last  = (r_beats_q == '0);
-        sbr_rsp_o.r_valid = 1'b1;
-        if (sbr_req_i.r_ready) begin
-          if (sbr_rsp_o.r.last) begin
+        mgr_port_req_o.r_ready = 1'b0;
+        sbr_port_rsp_o.r       = '0;
+        sbr_port_rsp_o.r.id    = id_q;
+        sbr_port_rsp_o.r.resp  = axi_pkg::RESP_SLVERR;
+        sbr_port_rsp_o.r.last  = (r_beats_q == '0);
+        sbr_port_rsp_o.r_valid = 1'b1;
+        if (sbr_port_req_i.r_ready) begin
+          if (sbr_port_rsp_o.r.last) begin
             r_resp_cmd_pop_ready = 1'b1;
             r_state_d = R_FEEDTHROUGH;
           end else begin
@@ -296,7 +296,7 @@ module axi_atop_filter #(
       end
 
       R_HOLD: begin
-        if (mgr_rsp_i.r_valid && sbr_req_i.r_ready) begin
+        if (mgr_port_rsp_i.r_valid && sbr_port_req_i.r_ready) begin
           r_state_d = R_FEEDTHROUGH;
         end
       end
@@ -305,17 +305,17 @@ module axi_atop_filter #(
     endcase
   end
   // Feed all signals on AR through.
-  assign mgr_req_o.ar       = sbr_req_i.ar;
-  assign mgr_req_o.ar_valid = sbr_req_i.ar_valid;
-  assign sbr_rsp_o.ar_ready = mgr_rsp_i.ar_ready;
+  assign mgr_port_req_o.ar       = sbr_port_req_i.ar;
+  assign mgr_port_req_o.ar_valid = sbr_port_req_i.ar_valid;
+  assign sbr_port_rsp_o.ar_ready = mgr_port_rsp_i.ar_ready;
 
   // Keep track of outstanding downstream write bursts and responses.
   always_comb begin
     w_cnt_d = w_cnt_q;
-    if (mgr_req_o.aw_valid && mgr_rsp_i.aw_ready) begin
+    if (mgr_port_req_o.aw_valid && mgr_port_rsp_i.aw_ready) begin
       w_cnt_d.cnt += 1;
     end
-    if (mgr_req_o.w_valid && mgr_rsp_i.w_ready && mgr_req_o.w.last) begin
+    if (mgr_port_req_o.w_valid && mgr_port_rsp_i.w_ready && mgr_port_req_o.w.last) begin
       w_cnt_d.cnt -= 1;
     end
     if (w_cnt_q.underflow && (w_cnt_d.cnt == '0)) begin
@@ -355,7 +355,7 @@ module axi_atop_filter #(
     .ready_i    (r_resp_cmd_pop_ready),
     .data_o     (r_resp_cmd_pop)
   );
-  assign r_resp_cmd_push.len = sbr_req_i.aw.len;
+  assign r_resp_cmd_push.len = sbr_port_req_i.aw.len;
 
 // pragma translate_off
 `ifndef VERILATOR
@@ -427,10 +427,10 @@ module axi_atop_filter_intf #(
   ) i_axi_atop_filter (
     .clk_i,
     .rst_ni,
-    .sbr_req_i ( sbr_req ),
-    .sbr_rsp_o ( sbr_rsp ),
-    .mgr_req_o ( mgr_req ),
-    .mgr_rsp_i ( mgr_rsp )
+    .sbr_port_req_i ( sbr_req ),
+    .sbr_port_rsp_o ( sbr_rsp ),
+    .mgr_port_req_o ( mgr_req ),
+    .mgr_port_rsp_i ( mgr_rsp )
   );
 // pragma translate_off
 `ifndef VERILATOR
diff --git a/src/axi_burst_splitter.sv b/src/axi_burst_splitter.sv
index 45045459e..b16b91739 100644
--- a/src/axi_burst_splitter.sv
+++ b/src/axi_burst_splitter.sv
@@ -42,12 +42,12 @@ module axi_burst_splitter #(
   input  logic     rst_ni,
 
   // Input / Subordinate Port
-  input  axi_req_t sbr_req_i,
-  output axi_rsp_t sbr_rsp_o,
+  input  axi_req_t sbr_port_req_i,
+  output axi_rsp_t sbr_port_rsp_o,
 
   // Output / Manager Port
-  output axi_req_t mgr_req_o,
-  input  axi_rsp_t mgr_rsp_i
+  output axi_req_t mgr_port_req_o,
+  input  axi_rsp_t mgr_port_rsp_i
 );
 
   typedef logic [AddrWidth-1:0]   addr_t;
@@ -87,10 +87,10 @@ module axi_burst_splitter #(
     .clk_i,
     .rst_ni,
     .test_i           ( 1'b0                        ),
-    .sbr_req_i,
+    .sbr_port_req_i,
     .sbr_aw_select_i  ( sel_aw_unsupported          ),
     .sbr_ar_select_i  ( sel_ar_unsupported          ),
-    .sbr_rsp_o,
+    .sbr_port_rsp_o,
     .mgr_reqs_o       ( {unsupported_req, act_req}  ),
     .mgr_rsps_i       ( {unsupported_rsp, act_rsp}  )
   );
@@ -111,10 +111,10 @@ module axi_burst_splitter #(
     // All other transactions are supported.
     return 1'b1;
   endfunction
-  assign sel_aw_unsupported = ~txn_supported(sbr_req_i.aw.atop, sbr_req_i.aw.burst,
-                                              sbr_req_i.aw.cache, sbr_req_i.aw.len);
-  assign sel_ar_unsupported = ~txn_supported('0, sbr_req_i.ar.burst,
-                                              sbr_req_i.ar.cache, sbr_req_i.ar.len);
+  assign sel_aw_unsupported = ~txn_supported(sbr_port_req_i.aw.atop, sbr_port_req_i.aw.burst,
+                                              sbr_port_req_i.aw.cache, sbr_port_req_i.aw.len);
+  assign sel_ar_unsupported = ~txn_supported('0, sbr_port_req_i.ar.burst,
+                                              sbr_port_req_i.ar.cache, sbr_port_req_i.ar.len);
   // Respond to unsupported transactions with subordinate errors.
   axi_err_sbr #(
     .IdWidth    ( IdWidth               ),
@@ -127,8 +127,8 @@ module axi_burst_splitter #(
     .clk_i,
     .rst_ni,
     .test_i    ( 1'b0             ),
-    .sbr_req_i ( unsupported_req  ),
-    .sbr_rsp_o ( unsupported_rsp  )
+    .sbr_port_req_i ( unsupported_req  ),
+    .sbr_port_rsp_o ( unsupported_rsp  )
   );
 
   // --------------------------------------------------
@@ -146,12 +146,12 @@ module axi_burst_splitter #(
     .ax_i           ( act_req.aw          ),
     .ax_valid_i     ( act_req.aw_valid    ),
     .ax_ready_o     ( act_rsp.aw_ready    ),
-    .ax_o           ( mgr_req_o.aw        ),
-    .ax_valid_o     ( mgr_req_o.aw_valid  ),
-    .ax_ready_i     ( mgr_rsp_i.aw_ready  ),
-    .cnt_id_i       ( mgr_rsp_i.b.id      ),
+    .ax_o           ( mgr_port_req_o.aw        ),
+    .ax_valid_o     ( mgr_port_req_o.aw_valid  ),
+    .ax_ready_i     ( mgr_port_rsp_i.aw_ready  ),
+    .cnt_id_i       ( mgr_port_rsp_i.b.id      ),
     .cnt_len_o      ( w_cnt_len           ),
-    .cnt_set_err_i  ( mgr_rsp_i.b.resp[1] ),
+    .cnt_set_err_i  ( mgr_port_rsp_i.b.resp[1] ),
     .cnt_err_o      ( w_cnt_err           ),
     .cnt_dec_i      ( w_cnt_dec           ),
     .cnt_req_i      ( w_cnt_req           ),
@@ -163,11 +163,11 @@ module axi_burst_splitter #(
   // --------------------------------------------------
   // Feed through, except `last`, which is always set.
   always_comb begin
-    mgr_req_o.w        = act_req.w;
-    mgr_req_o.w.last   = 1'b1;        // overwrite last flag
+    mgr_port_req_o.w        = act_req.w;
+    mgr_port_req_o.w.last   = 1'b1;        // overwrite last flag
   end
-  assign mgr_req_o.w_valid  = act_req.w_valid;
-  assign act_rsp.w_ready    = mgr_rsp_i.w_ready;
+  assign mgr_port_req_o.w_valid  = act_req.w_valid;
+  assign act_rsp.w_ready    = mgr_port_rsp_i.w_ready;
 
   // --------------------------------------------------
   // B Channel
@@ -176,7 +176,7 @@ module axi_burst_splitter #(
   enum logic {BReady, BWait} b_state_d, b_state_q;
   logic b_err_d, b_err_q;
   always_comb begin
-    mgr_req_o.b_ready = 1'b0;
+    mgr_port_req_o.b_ready = 1'b0;
     act_rsp.b         = '0;
     act_rsp.b_valid   = 1'b0;
     w_cnt_dec         = 1'b0;
@@ -186,37 +186,37 @@ module axi_burst_splitter #(
 
     unique case (b_state_q)
       BReady: begin
-        if (mgr_rsp_i.b_valid) begin
+        if (mgr_port_rsp_i.b_valid) begin
           w_cnt_req = 1'b1;
           if (w_cnt_gnt) begin
             if (w_cnt_len == 8'd0) begin
-              act_rsp.b = mgr_rsp_i.b;
+              act_rsp.b = mgr_port_rsp_i.b;
               if (w_cnt_err) begin
                 act_rsp.b.resp = axi_pkg::RESP_SLVERR;
               end
               act_rsp.b_valid  = 1'b1;
               w_cnt_dec         = 1'b1;
               if (act_req.b_ready) begin
-                mgr_req_o.b_ready = 1'b1;
+                mgr_port_req_o.b_ready = 1'b1;
               end else begin
                 b_state_d = BWait;
                 b_err_d   = w_cnt_err;
               end
             end else begin
-              mgr_req_o.b_ready = 1'b1;
+              mgr_port_req_o.b_ready = 1'b1;
               w_cnt_dec         = 1'b1;
             end
           end
         end
       end
       BWait: begin
-        act_rsp.b = mgr_rsp_i.b;
+        act_rsp.b = mgr_port_rsp_i.b;
         if (b_err_q) begin
           act_rsp.b.resp = axi_pkg::RESP_SLVERR;
         end
         act_rsp.b_valid  = 1'b1;
-        if (mgr_rsp_i.b_valid && act_req.b_ready) begin
-          mgr_req_o.b_ready = 1'b1;
+        if (mgr_port_rsp_i.b_valid && act_req.b_ready) begin
+          mgr_port_req_o.b_ready = 1'b1;
           b_state_d         = BReady;
         end
       end
@@ -240,10 +240,10 @@ module axi_burst_splitter #(
     .ax_i           ( act_req.ar         ),
     .ax_valid_i     ( act_req.ar_valid   ),
     .ax_ready_o     ( act_rsp.ar_ready   ),
-    .ax_o           ( mgr_req_o.ar       ),
-    .ax_valid_o     ( mgr_req_o.ar_valid ),
-    .ax_ready_i     ( mgr_rsp_i.ar_ready ),
-    .cnt_id_i       ( mgr_rsp_i.r.id     ),
+    .ax_o           ( mgr_port_req_o.ar       ),
+    .ax_valid_o     ( mgr_port_req_o.ar_valid ),
+    .ax_ready_i     ( mgr_port_rsp_i.ar_ready ),
+    .cnt_id_i       ( mgr_port_rsp_i.r.id     ),
     .cnt_len_o      ( r_cnt_len          ),
     .cnt_set_err_i  ( 1'b0               ),
     .cnt_err_o      (                    ),
@@ -263,8 +263,8 @@ module axi_burst_splitter #(
     r_cnt_req         = 1'b0;
     r_last_d          = r_last_q;
     r_state_d         = r_state_q;
-    mgr_req_o.r_ready = 1'b0;
-    act_rsp.r         = mgr_rsp_i.r;
+    mgr_port_req_o.r_ready = 1'b0;
+    act_rsp.r         = mgr_port_rsp_i.r;
     act_rsp.r.last    = 1'b0;
     act_rsp.r_valid   = 1'b0;
 
@@ -272,7 +272,7 @@ module axi_burst_splitter #(
       RFeedthrough: begin
         // If downstream has an R beat and the R counters can give us the remaining length of
         // that burst, ...
-        if (mgr_rsp_i.r_valid) begin
+        if (mgr_port_rsp_i.r_valid) begin
           r_cnt_req = 1'b1;
           if (r_cnt_gnt) begin
             r_last_d = (r_cnt_len == 8'd0);
@@ -283,7 +283,7 @@ module axi_burst_splitter #(
             act_rsp.r_valid  = 1'b1;
             if (act_req.r_ready) begin
               // Acknowledge downstream.
-              mgr_req_o.r_ready = 1'b1;
+              mgr_port_req_o.r_ready = 1'b1;
             end else begin
               // Wait for upstream to become ready.
               r_state_d = RWait;
@@ -293,9 +293,9 @@ module axi_burst_splitter #(
       end
       RWait: begin
         act_rsp.r.last   = r_last_q;
-        act_rsp.r_valid  = mgr_rsp_i.r_valid;
-        if (mgr_rsp_i.r_valid && act_req.r_ready) begin
-          mgr_req_o.r_ready = 1'b1;
+        act_rsp.r_valid  = mgr_port_rsp_i.r_valid;
+        if (mgr_port_rsp_i.r_valid && act_req.r_ready) begin
+          mgr_port_req_o.r_ready = 1'b1;
           r_state_d         = RFeedthrough;
         end
       end
@@ -318,20 +318,20 @@ module axi_burst_splitter #(
   // pragma translate_off
   default disable iff (!rst_ni);
   // Inputs
-  assume property (@(posedge clk_i) sbr_req_i.aw_valid |->
-      txn_supported(sbr_req_i.aw.atop, sbr_req_i.aw.burst, sbr_req_i.aw.cache, sbr_req_i.aw.len)
+  assume property (@(posedge clk_i) sbr_port_req_i.aw_valid |->
+      txn_supported(sbr_port_req_i.aw.atop, sbr_port_req_i.aw.burst, sbr_port_req_i.aw.cache, sbr_port_req_i.aw.len)
     ) else $warning("Unsupported AW transaction received, returning subordinate error!");
-  assume property (@(posedge clk_i) sbr_req_i.ar_valid |->
-      txn_supported('0, sbr_req_i.ar.burst, sbr_req_i.ar.cache, sbr_req_i.ar.len)
+  assume property (@(posedge clk_i) sbr_port_req_i.ar_valid |->
+      txn_supported('0, sbr_port_req_i.ar.burst, sbr_port_req_i.ar.cache, sbr_port_req_i.ar.len)
     ) else $warning("Unsupported AR transaction received, returning subordinate error!");
-  assume property (@(posedge clk_i) sbr_req_i.aw_valid |->
-      sbr_req_i.aw.atop == '0 || sbr_req_i.aw.atop[5:4] == axi_pkg::ATOP_ATOMICSTORE
+  assume property (@(posedge clk_i) sbr_port_req_i.aw_valid |->
+      sbr_port_req_i.aw.atop == '0 || sbr_port_req_i.aw.atop[5:4] == axi_pkg::ATOP_ATOMICSTORE
     ) else $fatal(1, "Unsupported ATOP that gives rise to a R response received,\
                       cannot respond in protocol-compliant manner!");
   // Outputs
-  assert property (@(posedge clk_i) mgr_req_o.aw_valid |-> mgr_req_o.aw.len == '0)
+  assert property (@(posedge clk_i) mgr_port_req_o.aw_valid |-> mgr_port_req_o.aw.len == '0)
     else $fatal(1, "AW burst longer than a single beat emitted!");
-  assert property (@(posedge clk_i) mgr_req_o.ar_valid |-> mgr_req_o.ar.len == '0)
+  assert property (@(posedge clk_i) mgr_port_req_o.ar_valid |-> mgr_port_req_o.ar.len == '0)
     else $fatal(1, "AR burst longer than a single beat emitted!");
   // pragma translate_on
   `endif
diff --git a/src/axi_cut.sv b/src/axi_cut.sv
index 0f1c5cc7f..66e691f9c 100644
--- a/src/axi_cut.sv
+++ b/src/axi_cut.sv
@@ -33,11 +33,11 @@ module axi_cut #(
   input logic      clk_i,
   input logic      rst_ni,
   // subordinate port
-  input  axi_req_t sbr_req_i,
-  output axi_rsp_t sbr_rsp_o,
+  input  axi_req_t sbr_port_req_i,
+  output axi_rsp_t sbr_port_rsp_o,
   // manager port
-  output axi_req_t mgr_req_o,
-  input  axi_rsp_t mgr_rsp_i
+  output axi_req_t mgr_port_req_o,
+  input  axi_rsp_t mgr_port_rsp_i
 );
 
   // a spill register for each channel
@@ -47,12 +47,12 @@ module axi_cut #(
   ) i_reg_aw (
     .clk_i   ( clk_i              ),
     .rst_ni  ( rst_ni             ),
-    .valid_i ( sbr_req_i.aw_valid ),
-    .ready_o ( sbr_rsp_o.aw_ready ),
-    .data_i  ( sbr_req_i.aw       ),
-    .valid_o ( mgr_req_o.aw_valid ),
-    .ready_i ( mgr_rsp_i.aw_ready ),
-    .data_o  ( mgr_req_o.aw       )
+    .valid_i ( sbr_port_req_i.aw_valid ),
+    .ready_o ( sbr_port_rsp_o.aw_ready ),
+    .data_i  ( sbr_port_req_i.aw       ),
+    .valid_o ( mgr_port_req_o.aw_valid ),
+    .ready_i ( mgr_port_rsp_i.aw_ready ),
+    .data_o  ( mgr_port_req_o.aw       )
   );
 
   spill_register #(
@@ -61,12 +61,12 @@ module axi_cut #(
   ) i_reg_w  (
     .clk_i   ( clk_i             ),
     .rst_ni  ( rst_ni            ),
-    .valid_i ( sbr_req_i.w_valid ),
-    .ready_o ( sbr_rsp_o.w_ready ),
-    .data_i  ( sbr_req_i.w       ),
-    .valid_o ( mgr_req_o.w_valid ),
-    .ready_i ( mgr_rsp_i.w_ready ),
-    .data_o  ( mgr_req_o.w       )
+    .valid_i ( sbr_port_req_i.w_valid ),
+    .ready_o ( sbr_port_rsp_o.w_ready ),
+    .data_i  ( sbr_port_req_i.w       ),
+    .valid_o ( mgr_port_req_o.w_valid ),
+    .ready_i ( mgr_port_rsp_i.w_ready ),
+    .data_o  ( mgr_port_req_o.w       )
   );
 
   spill_register #(
@@ -75,12 +75,12 @@ module axi_cut #(
   ) i_reg_b  (
     .clk_i   ( clk_i             ),
     .rst_ni  ( rst_ni            ),
-    .valid_i ( mgr_rsp_i.b_valid ),
-    .ready_o ( mgr_req_o.b_ready ),
-    .data_i  ( mgr_rsp_i.b       ),
-    .valid_o ( sbr_rsp_o.b_valid ),
-    .ready_i ( sbr_req_i.b_ready ),
-    .data_o  ( sbr_rsp_o.b       )
+    .valid_i ( mgr_port_rsp_i.b_valid ),
+    .ready_o ( mgr_port_req_o.b_ready ),
+    .data_i  ( mgr_port_rsp_i.b       ),
+    .valid_o ( sbr_port_rsp_o.b_valid ),
+    .ready_i ( sbr_port_req_i.b_ready ),
+    .data_o  ( sbr_port_rsp_o.b       )
   );
 
   spill_register #(
@@ -89,12 +89,12 @@ module axi_cut #(
   ) i_reg_ar (
     .clk_i   ( clk_i              ),
     .rst_ni  ( rst_ni             ),
-    .valid_i ( sbr_req_i.ar_valid ),
-    .ready_o ( sbr_rsp_o.ar_ready ),
-    .data_i  ( sbr_req_i.ar       ),
-    .valid_o ( mgr_req_o.ar_valid ),
-    .ready_i ( mgr_rsp_i.ar_ready ),
-    .data_o  ( mgr_req_o.ar       )
+    .valid_i ( sbr_port_req_i.ar_valid ),
+    .ready_o ( sbr_port_rsp_o.ar_ready ),
+    .data_i  ( sbr_port_req_i.ar       ),
+    .valid_o ( mgr_port_req_o.ar_valid ),
+    .ready_i ( mgr_port_rsp_i.ar_ready ),
+    .data_o  ( mgr_port_req_o.ar       )
   );
 
   spill_register #(
@@ -103,12 +103,12 @@ module axi_cut #(
   ) i_reg_r  (
     .clk_i   ( clk_i             ),
     .rst_ni  ( rst_ni            ),
-    .valid_i ( mgr_rsp_i.r_valid ),
-    .ready_o ( mgr_req_o.r_ready ),
-    .data_i  ( mgr_rsp_i.r       ),
-    .valid_o ( sbr_rsp_o.r_valid ),
-    .ready_i ( sbr_req_i.r_ready ),
-    .data_o  ( sbr_rsp_o.r       )
+    .valid_i ( mgr_port_rsp_i.r_valid ),
+    .ready_o ( mgr_port_req_o.r_ready ),
+    .data_i  ( mgr_port_rsp_i.r       ),
+    .valid_o ( sbr_port_rsp_o.r_valid ),
+    .ready_i ( sbr_port_req_i.r_ready ),
+    .data_o  ( sbr_port_rsp_o.r       )
   );
 endmodule
 
@@ -169,10 +169,10 @@ module axi_cut_intf #(
   ) i_axi_cut (
     .clk_i,
     .rst_ni,
-    .sbr_req_i ( sbr_req ),
-    .sbr_rsp_o ( sbr_rsp ),
-    .mgr_req_o ( mgr_req ),
-    .mgr_rsp_i ( mgr_rsp )
+    .sbr_port_req_i ( sbr_req ),
+    .sbr_port_rsp_o ( sbr_rsp ),
+    .mgr_port_req_o ( mgr_req ),
+    .mgr_port_rsp_i ( mgr_rsp )
   );
 
   // Check the invariants.
@@ -243,10 +243,10 @@ module axi_lite_cut_intf #(
   ) i_axi_cut (
     .clk_i,
     .rst_ni,
-    .sbr_req_i ( sbr_req ),
-    .sbr_rsp_o ( sbr_rsp ),
-    .mgr_req_o ( mgr_req ),
-    .mgr_rsp_i ( mgr_rsp )
+    .sbr_port_req_i ( sbr_req ),
+    .sbr_port_rsp_o ( sbr_rsp ),
+    .mgr_port_req_o ( mgr_req ),
+    .mgr_port_rsp_i ( mgr_rsp )
   );
 
   // Check the invariants.
diff --git a/src/axi_delayer.sv b/src/axi_delayer.sv
index 3709dc833..415081faa 100644
--- a/src/axi_delayer.sv
+++ b/src/axi_delayer.sv
@@ -33,11 +33,11 @@ module axi_delayer #(
   input  logic     clk_i,      // Clock
   input  logic     rst_ni,     // Asynchronous reset active low
   // subordinate port
-  input  axi_req_t sbr_req_i,
-  output axi_rsp_t sbr_rsp_o,
+  input  axi_req_t sbr_port_req_i,
+  output axi_rsp_t sbr_port_rsp_o,
   // manager port
-  output axi_req_t mgr_req_o,
-  input  axi_rsp_t mgr_rsp_i
+  output axi_req_t mgr_port_req_o,
+  input  axi_rsp_t mgr_port_rsp_i
 );
   // AW
   stream_delay #(
@@ -47,12 +47,12 @@ module axi_delayer #(
   ) i_stream_delay_aw (
     .clk_i,
     .rst_ni,
-    .payload_i ( sbr_req_i.aw       ),
-    .ready_o   ( sbr_rsp_o.aw_ready ),
-    .valid_i   ( sbr_req_i.aw_valid ),
-    .payload_o ( mgr_req_o.aw       ),
-    .ready_i   ( mgr_rsp_i.aw_ready ),
-    .valid_o   ( mgr_req_o.aw_valid )
+    .payload_i ( sbr_port_req_i.aw       ),
+    .ready_o   ( sbr_port_rsp_o.aw_ready ),
+    .valid_i   ( sbr_port_req_i.aw_valid ),
+    .payload_o ( mgr_port_req_o.aw       ),
+    .ready_i   ( mgr_port_rsp_i.aw_ready ),
+    .valid_o   ( mgr_port_req_o.aw_valid )
   );
 
   // AR
@@ -63,12 +63,12 @@ module axi_delayer #(
   ) i_stream_delay_ar (
     .clk_i,
     .rst_ni,
-    .payload_i ( sbr_req_i.ar       ),
-    .ready_o   ( sbr_rsp_o.ar_ready ),
-    .valid_i   ( sbr_req_i.ar_valid ),
-    .payload_o ( mgr_req_o.ar       ),
-    .ready_i   ( mgr_rsp_i.ar_ready ),
-    .valid_o   ( mgr_req_o.ar_valid )
+    .payload_i ( sbr_port_req_i.ar       ),
+    .ready_o   ( sbr_port_rsp_o.ar_ready ),
+    .valid_i   ( sbr_port_req_i.ar_valid ),
+    .payload_o ( mgr_port_req_o.ar       ),
+    .ready_i   ( mgr_port_rsp_i.ar_ready ),
+    .valid_o   ( mgr_port_req_o.ar_valid )
   );
 
   // W
@@ -79,12 +79,12 @@ module axi_delayer #(
   ) i_stream_delay_w (
     .clk_i,
     .rst_ni,
-    .payload_i ( sbr_req_i.w       ),
-    .ready_o   ( sbr_rsp_o.w_ready ),
-    .valid_i   ( sbr_req_i.w_valid ),
-    .payload_o ( mgr_req_o.w       ),
-    .ready_i   ( mgr_rsp_i.w_ready ),
-    .valid_o   ( mgr_req_o.w_valid )
+    .payload_i ( sbr_port_req_i.w       ),
+    .ready_o   ( sbr_port_rsp_o.w_ready ),
+    .valid_i   ( sbr_port_req_i.w_valid ),
+    .payload_o ( mgr_port_req_o.w       ),
+    .ready_i   ( mgr_port_rsp_i.w_ready ),
+    .valid_o   ( mgr_port_req_o.w_valid )
   );
 
   // B
@@ -95,12 +95,12 @@ module axi_delayer #(
   ) i_stream_delay_b (
     .clk_i,
     .rst_ni,
-    .payload_i ( mgr_rsp_i.b       ),
-    .ready_o   ( mgr_req_o.b_ready ),
-    .valid_i   ( mgr_rsp_i.b_valid ),
-    .payload_o ( sbr_rsp_o.b       ),
-    .ready_i   ( sbr_req_i.b_ready ),
-    .valid_o   ( sbr_rsp_o.b_valid )
+    .payload_i ( mgr_port_rsp_i.b       ),
+    .ready_o   ( mgr_port_req_o.b_ready ),
+    .valid_i   ( mgr_port_rsp_i.b_valid ),
+    .payload_o ( sbr_port_rsp_o.b       ),
+    .ready_i   ( sbr_port_req_i.b_ready ),
+    .valid_o   ( sbr_port_rsp_o.b_valid )
   );
 
   // R
@@ -111,12 +111,12 @@ module axi_delayer #(
   ) i_stream_delay_r (
     .clk_i,
     .rst_ni,
-    .payload_i ( mgr_rsp_i.r       ),
-    .ready_o   ( mgr_req_o.r_ready ),
-    .valid_i   ( mgr_rsp_i.r_valid ),
-    .payload_o ( sbr_rsp_o.r       ),
-    .ready_i   ( sbr_req_i.r_ready ),
-    .valid_o   ( sbr_rsp_o.r_valid )
+    .payload_i ( mgr_port_rsp_i.r       ),
+    .ready_o   ( mgr_port_req_o.r_ready ),
+    .valid_i   ( mgr_port_rsp_i.r_valid ),
+    .payload_o ( sbr_port_rsp_o.r       ),
+    .ready_i   ( sbr_port_req_i.r_ready ),
+    .valid_o   ( sbr_port_rsp_o.r_valid )
   );
 endmodule
 
@@ -179,10 +179,10 @@ module axi_delayer_intf #(
   ) i_axi_delayer (
     .clk_i,   // Clock
     .rst_ni,  // Asynchronous reset active low
-    .sbr_req_i ( sbr_req ),
-    .sbr_rsp_o ( sbr_rsp ),
-    .mgr_req_o ( mgr_req ),
-    .mgr_rsp_i ( mgr_rsp )
+    .sbr_port_req_i ( sbr_req ),
+    .sbr_port_rsp_o ( sbr_rsp ),
+    .mgr_port_req_o ( mgr_req ),
+    .mgr_port_rsp_i ( mgr_rsp )
   );
 
 // pragma translate_off
diff --git a/src/axi_demux.sv b/src/axi_demux.sv
index a4d7f4f95..6346f0340 100644
--- a/src/axi_demux.sv
+++ b/src/axi_demux.sv
@@ -64,10 +64,10 @@ module axi_demux #(
   input  logic                          rst_ni,
   input  logic                          test_i,
   // Subordinate Port
-  input  axi_req_t                      sbr_req_i,
+  input  axi_req_t                      sbr_port_req_i,
   input  select_t                       sbr_aw_select_i,
   input  select_t                       sbr_ar_select_i,
-  output axi_rsp_t                      sbr_rsp_o,
+  output axi_rsp_t                      sbr_port_rsp_o,
   // Manager Ports
   output axi_req_t    [NumMgrPorts-1:0] mgr_reqs_o,
   input  axi_rsp_t    [NumMgrPorts-1:0] mgr_rsps_i
@@ -85,9 +85,9 @@ module axi_demux #(
     ) i_aw_spill_reg (
       .clk_i   ( clk_i                   ),
       .rst_ni  ( rst_ni                  ),
-      .valid_i ( sbr_req_i.aw_valid      ),
-      .ready_o ( sbr_rsp_o.aw_ready      ),
-      .data_i  ( sbr_req_i.aw            ),
+      .valid_i ( sbr_port_req_i.aw_valid      ),
+      .ready_o ( sbr_port_rsp_o.aw_ready      ),
+      .data_i  ( sbr_port_req_i.aw            ),
       .valid_o ( mgr_reqs_o[0].aw_valid  ),
       .ready_i ( mgr_rsps_i[0].aw_ready  ),
       .data_o  ( mgr_reqs_o[0].aw        )
@@ -98,9 +98,9 @@ module axi_demux #(
     ) i_w_spill_reg (
       .clk_i   ( clk_i                  ),
       .rst_ni  ( rst_ni                 ),
-      .valid_i ( sbr_req_i.w_valid      ),
-      .ready_o ( sbr_rsp_o.w_ready      ),
-      .data_i  ( sbr_req_i.w            ),
+      .valid_i ( sbr_port_req_i.w_valid      ),
+      .ready_o ( sbr_port_rsp_o.w_ready      ),
+      .data_i  ( sbr_port_req_i.w            ),
       .valid_o ( mgr_reqs_o[0].w_valid  ),
       .ready_i ( mgr_rsps_i[0].w_ready  ),
       .data_o  ( mgr_reqs_o[0].w        )
@@ -114,9 +114,9 @@ module axi_demux #(
       .valid_i ( mgr_rsps_i[0].b_valid ),
       .ready_o ( mgr_reqs_o[0].b_ready ),
       .data_i  ( mgr_rsps_i[0].b       ),
-      .valid_o ( sbr_rsp_o.b_valid     ),
-      .ready_i ( sbr_req_i.b_ready     ),
-      .data_o  ( sbr_rsp_o.b           )
+      .valid_o ( sbr_port_rsp_o.b_valid     ),
+      .ready_i ( sbr_port_req_i.b_ready     ),
+      .data_o  ( sbr_port_rsp_o.b           )
     );
     spill_register #(
       .T       ( ar_chan_t  ),
@@ -124,9 +124,9 @@ module axi_demux #(
     ) i_ar_spill_reg (
       .clk_i   ( clk_i                   ),
       .rst_ni  ( rst_ni                  ),
-      .valid_i ( sbr_req_i.ar_valid      ),
-      .ready_o ( sbr_rsp_o.ar_ready      ),
-      .data_i  ( sbr_req_i.ar            ),
+      .valid_i ( sbr_port_req_i.ar_valid      ),
+      .ready_o ( sbr_port_rsp_o.ar_ready      ),
+      .data_i  ( sbr_port_req_i.ar            ),
       .valid_o ( mgr_reqs_o[0].ar_valid  ),
       .ready_i ( mgr_rsps_i[0].ar_ready  ),
       .data_o  ( mgr_reqs_o[0].ar        )
@@ -140,9 +140,9 @@ module axi_demux #(
       .valid_i ( mgr_rsps_i[0].r_valid ),
       .ready_o ( mgr_reqs_o[0].r_ready ),
       .data_i  ( mgr_rsps_i[0].r       ),
-      .valid_o ( sbr_rsp_o.r_valid     ),
-      .ready_i ( sbr_req_i.r_ready     ),
-      .data_o  ( sbr_rsp_o.r           )
+      .valid_o ( sbr_port_rsp_o.r_valid     ),
+      .ready_i ( sbr_port_req_i.r_ready     ),
+      .data_o  ( sbr_port_rsp_o.r           )
     );
 
   // other non degenerate cases
@@ -232,9 +232,9 @@ module axi_demux #(
     ) i_aw_channel_spill_reg (
       .clk_i   ( clk_i              ),
       .rst_ni  ( rst_ni             ),
-      .valid_i ( sbr_req_i.aw_valid ),
+      .valid_i ( sbr_port_req_i.aw_valid ),
       .ready_o ( sbr_aw_ready_chan  ),
-      .data_i  ( sbr_req_i.aw       ),
+      .data_i  ( sbr_port_req_i.aw       ),
       .valid_o ( sbr_aw_valid_chan  ),
       .ready_i ( sbr_aw_ready       ),
       .data_o  ( sbr_aw_chan        )
@@ -245,14 +245,14 @@ module axi_demux #(
     ) i_aw_select_spill_reg (
       .clk_i   ( clk_i              ),
       .rst_ni  ( rst_ni             ),
-      .valid_i ( sbr_req_i.aw_valid ),
+      .valid_i ( sbr_port_req_i.aw_valid ),
       .ready_o ( sbr_aw_ready_sel   ),
       .data_i  ( sbr_aw_select_i    ),
       .valid_o ( sbr_aw_valid_sel   ),
       .ready_i ( sbr_aw_ready       ),
       .data_o  ( sbr_aw_select      )
     );
-    assign sbr_rsp_o.aw_ready = sbr_aw_ready_chan & sbr_aw_ready_sel;
+    assign sbr_port_rsp_o.aw_ready = sbr_aw_ready_chan & sbr_aw_ready_sel;
     assign sbr_aw_valid = sbr_aw_valid_chan & sbr_aw_valid_sel;
 
     // Control of the AW handshake
@@ -382,9 +382,9 @@ module axi_demux #(
     ) i_w_spill_reg(
       .clk_i   ( clk_i             ),
       .rst_ni  ( rst_ni            ),
-      .valid_i ( sbr_req_i.w_valid ),
-      .ready_o ( sbr_rsp_o.w_ready ),
-      .data_i  ( sbr_req_i.w       ),
+      .valid_i ( sbr_port_req_i.w_valid ),
+      .ready_o ( sbr_port_rsp_o.w_ready ),
+      .data_i  ( sbr_port_req_i.w       ),
       .valid_o ( sbr_w_valid       ),
       .ready_i ( sbr_w_ready       ),
       .data_o  ( sbr_w_chan        )
@@ -403,9 +403,9 @@ module axi_demux #(
       .valid_i ( sbr_b_valid       ),
       .ready_o ( sbr_b_ready       ),
       .data_i  ( sbr_b_chan        ),
-      .valid_o ( sbr_rsp_o.b_valid ),
-      .ready_i ( sbr_req_i.b_ready ),
-      .data_o  ( sbr_rsp_o.b       )
+      .valid_o ( sbr_port_rsp_o.b_valid ),
+      .ready_i ( sbr_port_req_i.b_ready ),
+      .data_o  ( sbr_port_rsp_o.b       )
     );
 
     // Arbitration of the different B responses
@@ -439,9 +439,9 @@ module axi_demux #(
     ) i_ar_chan_spill_reg (
       .clk_i   ( clk_i              ),
       .rst_ni  ( rst_ni             ),
-      .valid_i ( sbr_req_i.ar_valid ),
+      .valid_i ( sbr_port_req_i.ar_valid ),
       .ready_o ( sbr_ar_ready_chan  ),
-      .data_i  ( sbr_req_i.ar       ),
+      .data_i  ( sbr_port_req_i.ar       ),
       .valid_o ( ar_valid_chan      ),
       .ready_i ( sbr_ar_ready       ),
       .data_o  ( sbr_ar_chan        )
@@ -452,14 +452,14 @@ module axi_demux #(
     ) i_ar_sel_spill_reg (
       .clk_i   ( clk_i              ),
       .rst_ni  ( rst_ni             ),
-      .valid_i ( sbr_req_i.ar_valid ),
+      .valid_i ( sbr_port_req_i.ar_valid ),
       .ready_o ( sbr_ar_ready_sel   ),
       .data_i  ( sbr_ar_select_i    ),
       .valid_o ( ar_valid_sel       ),
       .ready_i ( sbr_ar_ready       ),
       .data_o  ( sbr_ar_select      )
     );
-    assign sbr_rsp_o.ar_ready = sbr_ar_ready_chan & sbr_ar_ready_sel;
+    assign sbr_port_rsp_o.ar_ready = sbr_ar_ready_chan & sbr_ar_ready_sel;
     assign sbr_ar_valid = ar_valid_chan & ar_valid_sel;
 
     // control of the AR handshake
@@ -555,9 +555,9 @@ module axi_demux #(
       .valid_i ( sbr_r_valid       ),
       .ready_o ( sbr_r_ready       ),
       .data_i  ( sbr_r_chan        ),
-      .valid_o ( sbr_rsp_o.r_valid ),
-      .ready_i ( sbr_req_i.r_ready ),
-      .data_o  ( sbr_rsp_o.r       )
+      .valid_o ( sbr_port_rsp_o.r_valid ),
+      .ready_i ( sbr_port_req_i.r_ready ),
+      .data_o  ( sbr_port_rsp_o.r       )
     );
 
     // Arbitration of the different r responses
@@ -642,11 +642,11 @@ module axi_demux #(
         $fatal(1, "IdBits has to be equal or smaller than IdWidth.");
     end
     default disable iff (!rst_ni);
-    aw_select: assume property( @(posedge clk_i) (sbr_req_i.aw_valid |->
+    aw_select: assume property( @(posedge clk_i) (sbr_port_req_i.aw_valid |->
                                                  (sbr_aw_select_i < NumMgrPorts))) else
       $fatal(1, "sbr_aw_select_i is %d: AW has selected a subordinate that is not defined.\
                  NumMgrPorts: %d", sbr_aw_select_i, NumMgrPorts);
-    ar_select: assume property( @(posedge clk_i) (sbr_req_i.ar_valid |->
+    ar_select: assume property( @(posedge clk_i) (sbr_port_req_i.ar_valid |->
                                                  (sbr_ar_select_i < NumMgrPorts))) else
       $fatal(1, "sbr_ar_select_i is %d: AR has selected a subordinate that is not defined.\
                  NumMgrPorts: %d", sbr_ar_select_i, NumMgrPorts);
@@ -676,7 +676,7 @@ module axi_demux #(
     w_underflow: assert property( @(posedge clk_i)
         ((w_open == '0) && (w_cnt_up ^ w_cnt_down) |-> !w_cnt_down)) else
         $fatal(1, "W counter underflowed!");
-    `ASSUME(NoAtopAllowed, !AtopSupport && sbr_req_i.aw_valid |-> sbr_req_i.aw.atop == '0)
+    `ASSUME(NoAtopAllowed, !AtopSupport && sbr_port_req_i.aw_valid |-> sbr_port_req_i.aw.atop == '0)
 `endif
 `endif
 // pragma translate_on
@@ -885,10 +885,10 @@ module axi_demux_intf #(
     .rst_ni,  // Asynchronous reset active low
     .test_i,  // Testmode enable
     // subordinate port
-    .sbr_req_i       ( sbr_req         ),
+    .sbr_port_req_i       ( sbr_req         ),
     .sbr_aw_select_i ( sbr_aw_select_i ),
     .sbr_ar_select_i ( sbr_ar_select_i ),
-    .sbr_rsp_o       ( sbr_rsp         ),
+    .sbr_port_rsp_o       ( sbr_rsp         ),
     // manager port
     .mgr_reqs_o      ( mgr_req         ),
     .mgr_rsps_i      ( mgr_rsp         )
diff --git a/src/axi_dw_converter.sv b/src/axi_dw_converter.sv
index bf70ae9a4..4de0bf79c 100644
--- a/src/axi_dw_converter.sv
+++ b/src/axi_dw_converter.sv
@@ -36,16 +36,16 @@ module axi_dw_converter #(
     input  logic              clk_i,
     input  logic              rst_ni,
     // Subordinate interface
-    input  sbr_port_axi_req_t sbr_req_i,
-    output sbr_port_axi_rsp_t sbr_rsp_o,
+    input  sbr_port_axi_req_t sbr_port_req_i,
+    output sbr_port_axi_rsp_t sbr_port_rsp_o,
     // Manager interface
-    output mgr_port_axi_req_t mgr_req_o,
-    input  mgr_port_axi_rsp_t mgr_rsp_i
+    output mgr_port_axi_req_t mgr_port_req_o,
+    input  mgr_port_axi_rsp_t mgr_port_rsp_i
   );
 
   if (MgrPortDataWidth == SbrPortDataWidth) begin: gen_no_dw_conversion
-    assign mgr_req_o = sbr_req_i ;
-    assign sbr_rsp_o = mgr_rsp_i;
+    assign mgr_port_req_o = sbr_port_req_i ;
+    assign sbr_port_rsp_o = mgr_port_rsp_i;
   end : gen_no_dw_conversion
 
   if (MgrPortDataWidth > SbrPortDataWidth) begin: gen_dw_upsize
@@ -70,11 +70,11 @@ module axi_dw_converter #(
       .clk_i     (clk_i    ),
       .rst_ni    (rst_ni   ),
       // Subordinate interface
-      .sbr_req_i (sbr_req_i),
-      .sbr_rsp_o (sbr_rsp_o),
+      .sbr_port_req_i (sbr_port_req_i),
+      .sbr_port_rsp_o (sbr_port_rsp_o),
       // Manager interface
-      .mgr_req_o (mgr_req_o),
-      .mgr_rsp_i (mgr_rsp_i)
+      .mgr_port_req_o (mgr_port_req_o),
+      .mgr_port_rsp_i (mgr_port_rsp_i)
     );
   end : gen_dw_upsize
 
@@ -100,11 +100,11 @@ module axi_dw_converter #(
       .clk_i     (clk_i    ),
       .rst_ni    (rst_ni   ),
       // Subordinate interface
-      .sbr_req_i (sbr_req_i),
-      .sbr_rsp_o (sbr_rsp_o),
+      .sbr_port_req_i (sbr_port_req_i),
+      .sbr_port_rsp_o (sbr_port_rsp_o),
       // Manager interface
-      .mgr_req_o (mgr_req_o),
-      .mgr_rsp_i (mgr_rsp_i)
+      .mgr_port_req_o (mgr_port_req_o),
+      .mgr_port_rsp_i (mgr_port_rsp_i)
     );
   end : gen_dw_downsize
 
@@ -180,11 +180,11 @@ module axi_dw_converter_intf #(
     .clk_i      ( clk_i    ),
     .rst_ni     ( rst_ni   ),
     // subordinate port
-    .sbr_req_i  ( sbr_req  ),
-    .sbr_rsp_o ( sbr_rsp ),
+    .sbr_port_req_i  ( sbr_req  ),
+    .sbr_port_rsp_o ( sbr_rsp ),
     // manager port
-    .mgr_req_o  ( mgr_req  ),
-    .mgr_rsp_i ( mgr_rsp )
+    .mgr_port_req_o  ( mgr_req  ),
+    .mgr_port_rsp_i ( mgr_rsp )
   );
 
 endmodule : axi_dw_converter_intf
diff --git a/src/axi_dw_downsizer.sv b/src/axi_dw_downsizer.sv
index 98b54ff97..21930cc00 100644
--- a/src/axi_dw_downsizer.sv
+++ b/src/axi_dw_downsizer.sv
@@ -40,11 +40,11 @@ module axi_dw_downsizer #(
     input  logic              clk_i,
     input  logic              rst_ni,
     // Subordinate interface
-    input  sbr_port_axi_req_t sbr_req_i,
-    output sbr_port_axi_rsp_t sbr_rsp_o,
+    input  sbr_port_axi_req_t sbr_port_req_i,
+    output sbr_port_axi_rsp_t sbr_port_rsp_o,
     // Manager interface
-    output mgr_port_axi_req_t mgr_req_o,
-    input  mgr_port_axi_rsp_t mgr_rsp_i
+    output mgr_port_axi_req_t mgr_port_req_o,
+    input  mgr_port_axi_rsp_t mgr_port_rsp_i
   );
 
   /*****************
@@ -110,9 +110,9 @@ module axi_dw_downsizer #(
     .req_i  (sbr_r_valid_tran ),
     .gnt_o  (sbr_r_ready_tran ),
     .data_i (sbr_r_tran       ),
-    .gnt_i  (sbr_req_i.r_ready),
-    .req_o  (sbr_rsp_o.r_valid),
-    .data_o (sbr_rsp_o.r      ),
+    .gnt_i  (sbr_port_req_i.r_ready),
+    .req_o  (sbr_port_rsp_o.r_valid),
+    .data_o (sbr_port_rsp_o.r      ),
     .idx_o  (/* Unused */     )
   );
 
@@ -143,9 +143,9 @@ module axi_dw_downsizer #(
     .rst_ni  (rst_ni                                     ),
     .flush_i (1'b0                                       ),
     .rr_i    ('0                                         ),
-    .req_i   ({inject_aw_into_ar_req, sbr_req_i.ar_valid}),
-    .gnt_o   ({inject_aw_into_ar_gnt, sbr_rsp_o.ar_ready}),
-    .data_i  ({sbr_req_i.aw.id, sbr_req_i.ar.id}         ),
+    .req_i   ({inject_aw_into_ar_req, sbr_port_req_i.ar_valid}),
+    .gnt_o   ({inject_aw_into_ar_gnt, sbr_port_rsp_o.ar_ready}),
+    .data_i  ({sbr_port_req_i.aw.id, sbr_port_req_i.ar.id}         ),
     .req_o   (arb_sbr_ar_req                             ),
     .gnt_i   (arb_sbr_ar_gnt                             ),
     .data_o  (arb_sbr_ar_id                              ),
@@ -194,8 +194,8 @@ module axi_dw_downsizer #(
     .clk_i    (clk_i      ),
     .rst_ni   (rst_ni     ),
     .test_i   (1'b0       ),
-    .sbr_req_i(axi_err_req),
-    .sbr_rsp_o(axi_err_rsp)
+    .sbr_port_req_i(axi_err_req),
+    .sbr_port_rsp_o(axi_err_rsp)
   );
 
   /***********
@@ -225,12 +225,12 @@ module axi_dw_downsizer #(
     .clk_i          (clk_i                      ),
     .rst_ni         (rst_ni                     ),
     .test_i         (1'b0                       ),
-    .mgr_reqs_o     ({axi_err_req, mgr_req_o}   ),
-    .mgr_rsps_i     ({axi_err_rsp, mgr_rsp_i}   ),
+    .mgr_reqs_o     ({axi_err_req, mgr_port_req_o}   ),
+    .mgr_rsps_i     ({axi_err_rsp, mgr_port_rsp_i}   ),
     .sbr_ar_select_i(mgr_req_ar_err[mgr_req_idx]),
     .sbr_aw_select_i(mgr_req_aw_err             ),
-    .sbr_req_i      (mgr_req                    ),
-    .sbr_rsp_o      (mgr_rsp                    )
+    .sbr_port_req_i      (mgr_req                    ),
+    .sbr_port_rsp_o      (mgr_rsp                    )
   );
 
   /**********
@@ -397,10 +397,10 @@ module axi_dw_downsizer #(
               r_state_d = R_PASSTHROUGH;
 
               // Save beat
-              r_req_d.ar           = sbr_req_i.ar     ;
+              r_req_d.ar           = sbr_port_req_i.ar     ;
               r_req_d.ar_valid     = 1'b1             ;
-              r_req_d.burst_len    = sbr_req_i.ar.len ;
-              r_req_d.orig_ar_size = sbr_req_i.ar.size;
+              r_req_d.burst_len    = sbr_port_req_i.ar.len ;
+              r_req_d.orig_ar_size = sbr_port_req_i.ar.size;
               r_req_d.injected_aw  = 1'b0             ;
 
               case (r_req_d.ar.burst)
@@ -679,7 +679,7 @@ module axi_dw_downsizer #(
     // AW Channel
     mgr_req.aw          = w_req_q.aw      ;
     mgr_req.aw_valid    = w_req_q.aw_valid;
-    sbr_rsp_o.aw_ready = '0               ;
+    sbr_port_rsp_o.aw_ready = '0               ;
 
     // Throw an error.
     mgr_req_aw_err = w_req_q.aw_throw_error;
@@ -687,7 +687,7 @@ module axi_dw_downsizer #(
     // W Channel
     mgr_req.w         = '0;
     mgr_req.w_valid   = '0;
-    sbr_rsp_o.w_ready = '0;
+    sbr_port_rsp_o.w_ready = '0;
 
     // Initialize w_data
     w_data = '0;
@@ -697,21 +697,21 @@ module axi_dw_downsizer #(
       // Merge response of this burst with prior one according to precedence rules.
       w_req_d.burst_resp = axi_pkg::resp_precedence(w_req_q.burst_resp, mgr_rsp.b.resp);
     end
-    sbr_rsp_o.b      = mgr_rsp.b         ;
-    sbr_rsp_o.b.resp = w_req_d.burst_resp;
+    sbr_port_rsp_o.b      = mgr_rsp.b         ;
+    sbr_port_rsp_o.b.resp = w_req_d.burst_resp;
 
     // Each write transaction might trigger several B beats on the manager (narrow) side.
     // Only forward the last B beat of each transaction.
     if (forward_b_beat_o) begin
-      sbr_rsp_o.b_valid = mgr_rsp.b_valid ;
-      mgr_req.b_ready   = sbr_req_i.b_ready;
+      sbr_port_rsp_o.b_valid = mgr_rsp.b_valid ;
+      mgr_req.b_ready   = sbr_port_req_i.b_ready;
 
       // Got an ack on the B channel. Pop transaction.
       if (mgr_req.b_ready && mgr_rsp.b_valid)
         forward_b_beat_pop = 1'b1;
     end else begin
       // Otherwise, just acknowlegde the B beats
-      sbr_rsp_o.b_valid  = 1'b0           ;
+      sbr_port_rsp_o.b_valid  = 1'b0           ;
       mgr_req.b_ready    = 1'b1           ;
       forward_b_beat_pop = mgr_rsp.b_valid;
     end
@@ -726,22 +726,22 @@ module axi_dw_downsizer #(
       W_PASSTHROUGH, W_INCR_DOWNSIZE, W_SPLIT_INCR_DOWNSIZE: begin
         // Request was accepted
         if (!w_req_q.aw_valid)
-          if (sbr_req_i.w_valid) begin
+          if (sbr_port_req_i.w_valid) begin
             automatic addr_t mgr_port_offset = MgrPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(MgrPortStrbWidth)-1:0];
             automatic addr_t sbr_port_offset = SbrPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(SbrPortStrbWidth)-1:0];
 
             // Valid output
             mgr_req.w_valid = 1'b1               ;
             mgr_req.w.last  = w_req_q.aw.len == 0;
-            mgr_req.w.user  = sbr_req_i.w.user   ;
+            mgr_req.w.user  = sbr_port_req_i.w.user   ;
 
             // Lane steering
             for (int b = 0; b < SbrPortStrbWidth; b++)
               if ((b >= sbr_port_offset) &&
                   (b - sbr_port_offset < (1 << w_req_q.orig_aw_size)) &&
                   (b + mgr_port_offset - sbr_port_offset < MgrPortStrbWidth)) begin
-                w_data[b + mgr_port_offset - sbr_port_offset]         = sbr_req_i.w.data[8*b +: 8];
-                mgr_req.w.strb[b + mgr_port_offset - sbr_port_offset] = sbr_req_i.w.strb[b]       ;
+                w_data[b + mgr_port_offset - sbr_port_offset]         = sbr_port_req_i.w.data[8*b +: 8];
+                mgr_req.w.strb[b + mgr_port_offset - sbr_port_offset] = sbr_port_req_i.w.strb[b]       ;
               end
             mgr_req.w.data = w_data;
           end
@@ -762,11 +762,11 @@ module axi_dw_downsizer #(
 
           case (w_state_q)
             W_PASSTHROUGH:
-              sbr_rsp_o.w_ready = 1'b1;
+              sbr_port_rsp_o.w_ready = 1'b1;
 
             W_INCR_DOWNSIZE, W_SPLIT_INCR_DOWNSIZE:
               if (w_req_q.burst_len == 0 || (aligned_addr(w_req_d.aw.addr, w_req_q.orig_aw_size) != aligned_addr(w_req_q.aw.addr, w_req_q.orig_aw_size)))
-                sbr_rsp_o.w_ready = 1'b1;
+                sbr_port_rsp_o.w_ready = 1'b1;
           endcase
 
           // Trigger another burst request, if needed
@@ -800,35 +800,35 @@ module axi_dw_downsizer #(
       w_req_d.burst_resp     = axi_pkg::RESP_OKAY;
 
       if (!forward_b_beat_full) begin
-        if (sbr_req_i.aw_valid && sbr_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin // ATOP with an R response
+        if (sbr_port_req_i.aw_valid && sbr_port_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin // ATOP with an R response
           inject_aw_into_ar_req = 1'b1                 ;
-          sbr_rsp_o.aw_ready   = inject_aw_into_ar_gnt;
+          sbr_port_rsp_o.aw_ready   = inject_aw_into_ar_gnt;
         end else begin // Regular AW
-          sbr_rsp_o.aw_ready = 1'b1;
+          sbr_port_rsp_o.aw_ready = 1'b1;
         end
 
         // New write request
-        if (sbr_req_i.aw_valid && sbr_rsp_o.aw_ready) begin
+        if (sbr_port_req_i.aw_valid && sbr_port_rsp_o.aw_ready) begin
           // Default state
           w_state_d = W_PASSTHROUGH;
 
           // Save beat
-          w_req_d.aw            = sbr_req_i.aw      ;
+          w_req_d.aw            = sbr_port_req_i.aw      ;
           w_req_d.aw_valid      = 1'b1              ;
-          w_req_d.burst_len     = sbr_req_i.aw.len  ;
-          w_req_d.orig_aw_len   = sbr_req_i.aw.len  ;
-          w_req_d.orig_aw_size  = sbr_req_i.aw.size ;
-          w_req_d.orig_aw_burst = sbr_req_i.aw.burst;
+          w_req_d.burst_len     = sbr_port_req_i.aw.len  ;
+          w_req_d.orig_aw_len   = sbr_port_req_i.aw.len  ;
+          w_req_d.orig_aw_size  = sbr_port_req_i.aw.size ;
+          w_req_d.orig_aw_burst = sbr_port_req_i.aw.burst;
 
-          case (sbr_req_i.aw.burst)
+          case (sbr_port_req_i.aw.burst)
             axi_pkg::BURST_INCR: begin
               // Evaluate downsize ratio
-              automatic addr_t size_mask  = (1 << sbr_req_i.aw.size) - 1                                        ;
-              automatic addr_t conv_ratio = ((1 << sbr_req_i.aw.size) + MgrPortStrbWidth - 1) / MgrPortStrbWidth;
+              automatic addr_t size_mask  = (1 << sbr_port_req_i.aw.size) - 1                                        ;
+              automatic addr_t conv_ratio = ((1 << sbr_port_req_i.aw.size) + MgrPortStrbWidth - 1) / MgrPortStrbWidth;
 
               // Evaluate output burst length
-              automatic addr_t align_adj = (sbr_req_i.aw.addr & size_mask & ~MgrPortByteMask) / MgrPortStrbWidth;
-              w_req_d.burst_len          = (sbr_req_i.aw.len + 1) * conv_ratio - align_adj - 1                  ;
+              automatic addr_t align_adj = (sbr_port_req_i.aw.addr & size_mask & ~MgrPortByteMask) / MgrPortStrbWidth;
+              w_req_d.burst_len          = (sbr_port_req_i.aw.len + 1) * conv_ratio - align_adj - 1                  ;
 
               if (conv_ratio != 1) begin
                 w_req_d.aw.size = MgrPortMaxSize;
@@ -845,13 +845,13 @@ module axi_dw_downsizer #(
 
             axi_pkg::BURST_FIXED: begin
               // Single transaction
-              if (sbr_req_i.aw.len == '0) begin
+              if (sbr_port_req_i.aw.len == '0) begin
                 // Evaluate downsize ratio
-                automatic addr_t size_mask  = (1 << sbr_req_i.aw.size) - 1                                        ;
-                automatic addr_t conv_ratio = ((1 << sbr_req_i.aw.size) + MgrPortStrbWidth - 1) / MgrPortStrbWidth;
+                automatic addr_t size_mask  = (1 << sbr_port_req_i.aw.size) - 1                                        ;
+                automatic addr_t conv_ratio = ((1 << sbr_port_req_i.aw.size) + MgrPortStrbWidth - 1) / MgrPortStrbWidth;
 
                 // Evaluate output burst length
-                automatic addr_t align_adj = (sbr_req_i.aw.addr & size_mask & ~MgrPortByteMask) / MgrPortStrbWidth;
+                automatic addr_t align_adj = (sbr_port_req_i.aw.addr & size_mask & ~MgrPortByteMask) / MgrPortStrbWidth;
                 w_req_d.burst_len          = (conv_ratio >= align_adj + 1) ? (conv_ratio - align_adj - 1) : 0;
 
                 if (conv_ratio != 1) begin
diff --git a/src/axi_dw_upsizer.sv b/src/axi_dw_upsizer.sv
index 8ebf7fa49..665d02b36 100644
--- a/src/axi_dw_upsizer.sv
+++ b/src/axi_dw_upsizer.sv
@@ -39,11 +39,11 @@ module axi_dw_upsizer #(
     input  logic              clk_i,
     input  logic              rst_ni,
     // Subordinate interface
-    input  sbr_port_axi_req_t sbr_req_i,
-    output sbr_port_axi_rsp_t sbr_rsp_o,
+    input  sbr_port_axi_req_t sbr_port_req_i,
+    output sbr_port_axi_rsp_t sbr_port_rsp_o,
     // Manager interface
-    output mgr_port_axi_req_t mgr_req_o,
-    input  mgr_port_axi_rsp_t mgr_rsp_i
+    output mgr_port_axi_req_t mgr_port_req_o,
+    input  mgr_port_axi_rsp_t mgr_port_rsp_i
   );
 
   /*****************
@@ -107,9 +107,9 @@ module axi_dw_upsizer #(
     .req_i  (sbr_r_valid_tran ),
     .gnt_o  (sbr_r_ready_tran ),
     .data_i (sbr_r_tran       ),
-    .gnt_i  (sbr_req_i.r_ready),
-    .req_o  (sbr_rsp_o.r_valid),
-    .data_o (sbr_rsp_o.r      ),
+    .gnt_i  (sbr_port_req_i.r_ready),
+    .req_o  (sbr_port_rsp_o.r_valid),
+    .data_o (sbr_port_rsp_o.r      ),
     .idx_o  (/* Unused */     )
   );
 
@@ -140,9 +140,9 @@ module axi_dw_upsizer #(
     .rst_ni (rst_ni                                     ),
     .flush_i(1'b0                                       ),
     .rr_i   ('0                                         ),
-    .req_i  ({inject_aw_into_ar_req, sbr_req_i.ar_valid}),
-    .gnt_o  ({inject_aw_into_ar_gnt, sbr_rsp_o.ar_ready}),
-    .data_i ({sbr_req_i.aw.id, sbr_req_i.ar.id}         ),
+    .req_i  ({inject_aw_into_ar_req, sbr_port_req_i.ar_valid}),
+    .gnt_o  ({inject_aw_into_ar_gnt, sbr_port_rsp_o.ar_ready}),
+    .data_i ({sbr_port_req_i.aw.id, sbr_port_req_i.ar.id}         ),
     .req_o  (arb_sbr_ar_req                             ),
     .gnt_i  (arb_sbr_ar_gnt                             ),
     .data_o (arb_sbr_ar_id                              ),
@@ -191,8 +191,8 @@ module axi_dw_upsizer #(
     .clk_i    (clk_i      ),
     .rst_ni   (rst_ni     ),
     .test_i   (1'b0       ),
-    .sbr_req_i(axi_err_req),
-    .sbr_rsp_o(axi_err_rsp)
+    .sbr_port_req_i(axi_err_req),
+    .sbr_port_rsp_o(axi_err_rsp)
   );
 
   /***********
@@ -222,12 +222,12 @@ module axi_dw_upsizer #(
     .clk_i          (clk_i                      ),
     .rst_ni         (rst_ni                     ),
     .test_i         (1'b0                       ),
-    .mgr_reqs_o     ({axi_err_req, mgr_req_o}   ),
-    .mgr_rsps_i     ({axi_err_rsp, mgr_rsp_i}   ),
+    .mgr_reqs_o     ({axi_err_req, mgr_port_req_o}   ),
+    .mgr_rsps_i     ({axi_err_rsp, mgr_port_rsp_i}   ),
     .sbr_ar_select_i(mgr_req_ar_err[mgr_req_idx]),
     .sbr_aw_select_i(mgr_req_aw_err             ),
-    .sbr_req_i      (mgr_req                    ),
-    .sbr_rsp_o      (mgr_rsp                    )
+    .sbr_port_req_i      (mgr_req                    ),
+    .sbr_port_rsp_o      (mgr_rsp                    )
   );
 
   /**********
@@ -376,10 +376,10 @@ module axi_dw_upsizer #(
               r_state_d = R_PASSTHROUGH;
 
               // Save beat
-              r_req_d.ar           = sbr_req_i.ar     ;
+              r_req_d.ar           = sbr_port_req_i.ar     ;
               r_req_d.ar_valid     = 1'b1             ;
-              r_req_d.burst_len    = sbr_req_i.ar.len ;
-              r_req_d.orig_ar_size = sbr_req_i.ar.size;
+              r_req_d.burst_len    = sbr_port_req_i.ar.len ;
+              r_req_d.orig_ar_size = sbr_port_req_i.ar.size;
 
               case (r_req_d.ar.burst)
                 axi_pkg::BURST_INCR: begin
@@ -561,7 +561,7 @@ module axi_dw_upsizer #(
     // AW Channel
     mgr_req.aw         = w_req_q.aw      ;
     mgr_req.aw_valid   = w_req_q.aw_valid;
-    sbr_rsp_o.aw_ready = '0              ;
+    sbr_port_rsp_o.aw_ready = '0              ;
 
     // Throw an error.
     mgr_req_aw_err = w_req_q.aw_throw_error;
@@ -569,15 +569,15 @@ module axi_dw_upsizer #(
     // W Channel
     mgr_req.w         = w_req_q.w      ;
     mgr_req.w_valid   = w_req_q.w_valid;
-    sbr_rsp_o.w_ready = '0             ;
+    sbr_port_rsp_o.w_ready = '0             ;
 
     // Initialize w_data
     w_data = w_req_q.w.data;
 
     // B Channel (No latency)
-    sbr_rsp_o.b       = mgr_rsp.b        ;
-    sbr_rsp_o.b_valid = mgr_rsp.b_valid  ;
-    mgr_req.b_ready   = sbr_req_i.b_ready;
+    sbr_port_rsp_o.b       = mgr_rsp.b        ;
+    sbr_port_rsp_o.b_valid = mgr_rsp.b_valid  ;
+    mgr_req.b_ready   = sbr_port_req_i.b_ready;
 
     // Got a grant on the AW channel
     if (mgr_req.aw_valid && mgr_rsp.aw_ready) begin
@@ -597,9 +597,9 @@ module axi_dw_upsizer #(
         // Request was accepted
         if (!w_req_q.aw_valid) begin
           // Ready if downstream interface is idle, or if it is ready
-          sbr_rsp_o.w_ready = ~mgr_req.w_valid || mgr_rsp.w_ready;
+          sbr_port_rsp_o.w_ready = ~mgr_req.w_valid || mgr_rsp.w_ready;
 
-          if (sbr_req_i.w_valid && sbr_rsp_o.w_ready) begin
+          if (sbr_port_req_i.w_valid && sbr_port_rsp_o.w_ready) begin
             automatic addr_t mgr_port_offset = MgrPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(MgrPortStrbWidth)-1:0];
             automatic addr_t sbr_port_offset = SbrPortStrbWidth == 1 ? '0 : w_req_q.aw.addr[idx_width(SbrPortStrbWidth)-1:0];
 
@@ -608,14 +608,14 @@ module axi_dw_upsizer #(
               if ((b >= mgr_port_offset) &&
                   (b - mgr_port_offset < (1 << w_req_q.orig_aw_size)) &&
                   (b + sbr_port_offset - mgr_port_offset < SbrPortStrbWidth)) begin
-                w_data[b]         = sbr_req_i.w.data[8*(b + sbr_port_offset - mgr_port_offset) +: 8];
-                w_req_d.w.strb[b] = sbr_req_i.w.strb[b + sbr_port_offset - mgr_port_offset]         ;
+                w_data[b]         = sbr_port_req_i.w.data[8*(b + sbr_port_offset - mgr_port_offset) +: 8];
+                w_req_d.w.strb[b] = sbr_port_req_i.w.strb[b + sbr_port_offset - mgr_port_offset]         ;
               end
 
             w_req_d.burst_len = w_req_q.burst_len - 1   ;
             w_req_d.w.data    = w_data                  ;
             w_req_d.w.last    = (w_req_q.burst_len == 0);
-            w_req_d.w.user    = sbr_req_i.w.user        ;
+            w_req_d.w.user    = sbr_port_req_i.w.user        ;
 
             case (w_req_q.aw.burst)
               axi_pkg::BURST_INCR: begin
@@ -641,7 +641,7 @@ module axi_dw_upsizer #(
 
         if (mgr_req.w_valid && mgr_rsp.w_ready)
           if (w_req_q.burst_len == '1) begin
-            sbr_rsp_o.w_ready = 1'b0  ;
+            sbr_port_rsp_o.w_ready = 1'b0  ;
             w_state_d          = W_IDLE;
           end
       end
@@ -656,35 +656,35 @@ module axi_dw_upsizer #(
       w_req_d.w              = '0  ;
       w_req_d.w_valid        = 1'b0;
 
-      if (sbr_req_i.aw_valid && sbr_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin // ATOP with an R response
+      if (sbr_port_req_i.aw_valid && sbr_port_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin // ATOP with an R response
         inject_aw_into_ar_req = 1'b1                 ;
-        sbr_rsp_o.aw_ready   = inject_aw_into_ar_gnt;
+        sbr_port_rsp_o.aw_ready   = inject_aw_into_ar_gnt;
       end else begin // Regular AW
-        sbr_rsp_o.aw_ready = 1'b1;
+        sbr_port_rsp_o.aw_ready = 1'b1;
       end
 
       // New write request
-      if (sbr_req_i.aw_valid & sbr_rsp_o.aw_ready) begin
+      if (sbr_port_req_i.aw_valid & sbr_port_rsp_o.aw_ready) begin
         // Default state
         w_state_d = W_PASSTHROUGH;
 
         // Save beat
-        w_req_d.aw       = sbr_req_i.aw;
+        w_req_d.aw       = sbr_port_req_i.aw;
         w_req_d.aw_valid = 1'b1        ;
 
-        w_req_d.burst_len    = sbr_req_i.aw.len ;
-        w_req_d.orig_aw_size = sbr_req_i.aw.size;
+        w_req_d.burst_len    = sbr_port_req_i.aw.len ;
+        w_req_d.orig_aw_size = sbr_port_req_i.aw.size;
 
-        case (sbr_req_i.aw.burst)
+        case (sbr_port_req_i.aw.burst)
           axi_pkg::BURST_INCR: begin
             // Modifiable transaction
-            if (modifiable(sbr_req_i.aw.cache))
+            if (modifiable(sbr_port_req_i.aw.cache))
               // No need to upsize single-beat transactions.
-              if (sbr_req_i.aw.len != '0) begin
+              if (sbr_port_req_i.aw.len != '0) begin
                 // Evaluate output burst length
-                automatic addr_t start_addr = aligned_addr(sbr_req_i.aw.addr, MgrPortMaxSize);
-                automatic addr_t end_addr   = aligned_addr(beat_addr(sbr_req_i.aw.addr,
-                    sbr_req_i.aw.size, sbr_req_i.aw.len, sbr_req_i.aw.burst, sbr_req_i.aw.len),
+                automatic addr_t start_addr = aligned_addr(sbr_port_req_i.aw.addr, MgrPortMaxSize);
+                automatic addr_t end_addr   = aligned_addr(beat_addr(sbr_port_req_i.aw.addr,
+                    sbr_port_req_i.aw.size, sbr_port_req_i.aw.len, sbr_port_req_i.aw.burst, sbr_port_req_i.aw.len),
                     MgrPortMaxSize);
 
                 w_req_d.aw.len  = (end_addr - start_addr) >> MgrPortMaxSize;
@@ -704,7 +704,7 @@ module axi_dw_upsizer #(
             w_req_d.aw_throw_error = 1'b1         ;
 
             // ... but might if this is a single-beat transaction
-            if (sbr_req_i.aw.len == '0)
+            if (sbr_port_req_i.aw.len == '0)
               w_req_d.aw_throw_error = 1'b0;
           end
         endcase
diff --git a/src/axi_err_sbr.sv b/src/axi_err_sbr.sv
index 0fca3acc4..4ee5c0da7 100644
--- a/src/axi_err_sbr.sv
+++ b/src/axi_err_sbr.sv
@@ -30,8 +30,8 @@ module axi_err_sbr #(
   input  logic     rst_ni,  // Asynchronous reset active low
   input  logic     test_i,  // Testmode enable
   // subordinate port
-  input  axi_req_t sbr_req_i,
-  output axi_rsp_t sbr_rsp_o
+  input  axi_req_t sbr_port_req_i,
+  output axi_rsp_t sbr_port_rsp_o
 );
   typedef logic [IdWidth-1:0] id_t;
   typedef struct packed {
@@ -51,14 +51,14 @@ module axi_err_sbr #(
     ) i_atop_filter (
       .clk_i,
       .rst_ni,
-      .sbr_req_i ( sbr_req_i  ),
-      .sbr_rsp_o ( sbr_rsp_o  ),
-      .mgr_req_o ( err_req    ),
-      .mgr_rsp_i ( err_rsp    )
+      .sbr_port_req_i ( sbr_port_req_i  ),
+      .sbr_port_rsp_o ( sbr_port_rsp_o  ),
+      .mgr_port_req_o ( err_req    ),
+      .mgr_port_rsp_i ( err_rsp    )
     );
   end else begin
-    assign err_req    = sbr_req_i;
-    assign sbr_rsp_o = err_rsp;
+    assign err_req    = sbr_port_req_i;
+    assign sbr_port_rsp_o = err_rsp;
   end
 
   // w fifo
@@ -251,7 +251,7 @@ module axi_err_sbr #(
   end
   default disable iff (!rst_ni);
   if (!ATOPs) begin : gen_assert_atops_unsupported
-    assume property( @(posedge clk_i) (sbr_req_i.aw_valid |-> sbr_req_i.aw.atop == '0)) else
+    assume property( @(posedge clk_i) (sbr_port_req_i.aw_valid |-> sbr_port_req_i.aw.atop == '0)) else
      $fatal(1, "Got ATOP but not configured to support ATOPs!");
   end
   `endif
diff --git a/src/axi_fifo.sv b/src/axi_fifo.sv
index cb1481fc4..c291ed59c 100644
--- a/src/axi_fifo.sv
+++ b/src/axi_fifo.sv
@@ -35,32 +35,32 @@ module axi_fifo #(
     input  logic     rst_ni,  // Asynchronous reset active low
     input  logic     test_i,
     // subordinate port
-    input  axi_req_t sbr_req_i,
-    output axi_rsp_t sbr_rsp_o,
+    input  axi_req_t sbr_port_req_i,
+    output axi_rsp_t sbr_port_rsp_o,
     // manager port
-    output axi_req_t mgr_req_o,
-    input  axi_rsp_t mgr_rsp_i
+    output axi_req_t mgr_port_req_o,
+    input  axi_rsp_t mgr_port_rsp_i
 );
 
   if (Depth == '0) begin : gen_no_fifo
     // degenerate case, connect input to output
-    assign mgr_req_o = sbr_req_i;
-    assign sbr_rsp_o = mgr_rsp_i;
+    assign mgr_port_req_o = sbr_port_req_i;
+    assign sbr_port_rsp_o = mgr_port_rsp_i;
   end else begin : gen_axi_fifo
     logic aw_fifo_empty, ar_fifo_empty, w_fifo_empty, r_fifo_empty, b_fifo_empty;
     logic aw_fifo_full, ar_fifo_full, w_fifo_full, r_fifo_full, b_fifo_full;
 
-    assign mgr_req_o.aw_valid = ~aw_fifo_empty;
-    assign mgr_req_o.ar_valid = ~ar_fifo_empty;
-    assign mgr_req_o.w_valid  = ~w_fifo_empty;
-    assign sbr_rsp_o.r_valid  = ~r_fifo_empty;
-    assign sbr_rsp_o.b_valid  = ~b_fifo_empty;
+    assign mgr_port_req_o.aw_valid = ~aw_fifo_empty;
+    assign mgr_port_req_o.ar_valid = ~ar_fifo_empty;
+    assign mgr_port_req_o.w_valid  = ~w_fifo_empty;
+    assign sbr_port_rsp_o.r_valid  = ~r_fifo_empty;
+    assign sbr_port_rsp_o.b_valid  = ~b_fifo_empty;
 
-    assign sbr_rsp_o.aw_ready = ~aw_fifo_full;
-    assign sbr_rsp_o.ar_ready = ~ar_fifo_full;
-    assign sbr_rsp_o.w_ready  = ~w_fifo_full;
-    assign mgr_req_o.r_ready  = ~r_fifo_full;
-    assign mgr_req_o.b_ready  = ~b_fifo_full;
+    assign sbr_port_rsp_o.aw_ready = ~aw_fifo_full;
+    assign sbr_port_rsp_o.ar_ready = ~ar_fifo_full;
+    assign sbr_port_rsp_o.w_ready  = ~w_fifo_full;
+    assign mgr_port_req_o.r_ready  = ~r_fifo_full;
+    assign mgr_port_req_o.b_ready  = ~b_fifo_full;
 
     // A FiFo for each channel
     fifo_v3 #(
@@ -75,10 +75,10 @@ module axi_fifo #(
         .full_o    (aw_fifo_full),
         .empty_o   (aw_fifo_empty),
         .usage_o   (),
-        .data_i    (sbr_req_i.aw),
-        .push_i    (sbr_req_i.aw_valid && sbr_rsp_o.aw_ready),
-        .data_o    (mgr_req_o.aw),
-        .pop_i     (mgr_req_o.aw_valid && mgr_rsp_i.aw_ready)
+        .data_i    (sbr_port_req_i.aw),
+        .push_i    (sbr_port_req_i.aw_valid && sbr_port_rsp_o.aw_ready),
+        .data_o    (mgr_port_req_o.aw),
+        .pop_i     (mgr_port_req_o.aw_valid && mgr_port_rsp_i.aw_ready)
     );
     fifo_v3 #(
         .dtype(ar_chan_t),
@@ -92,10 +92,10 @@ module axi_fifo #(
         .full_o    (ar_fifo_full),
         .empty_o   (ar_fifo_empty),
         .usage_o   (),
-        .data_i    (sbr_req_i.ar),
-        .push_i    (sbr_req_i.ar_valid && sbr_rsp_o.ar_ready),
-        .data_o    (mgr_req_o.ar),
-        .pop_i     (mgr_req_o.ar_valid && mgr_rsp_i.ar_ready)
+        .data_i    (sbr_port_req_i.ar),
+        .push_i    (sbr_port_req_i.ar_valid && sbr_port_rsp_o.ar_ready),
+        .data_o    (mgr_port_req_o.ar),
+        .pop_i     (mgr_port_req_o.ar_valid && mgr_port_rsp_i.ar_ready)
     );
     fifo_v3 #(
         .dtype(w_chan_t),
@@ -109,10 +109,10 @@ module axi_fifo #(
         .full_o    (w_fifo_full),
         .empty_o   (w_fifo_empty),
         .usage_o   (),
-        .data_i    (sbr_req_i.w),
-        .push_i    (sbr_req_i.w_valid && sbr_rsp_o.w_ready),
-        .data_o    (mgr_req_o.w),
-        .pop_i     (mgr_req_o.w_valid && mgr_rsp_i.w_ready)
+        .data_i    (sbr_port_req_i.w),
+        .push_i    (sbr_port_req_i.w_valid && sbr_port_rsp_o.w_ready),
+        .data_o    (mgr_port_req_o.w),
+        .pop_i     (mgr_port_req_o.w_valid && mgr_port_rsp_i.w_ready)
     );
     fifo_v3 #(
         .dtype(r_chan_t),
@@ -126,10 +126,10 @@ module axi_fifo #(
         .full_o    (r_fifo_full),
         .empty_o   (r_fifo_empty),
         .usage_o   (),
-        .data_i    (mgr_rsp_i.r),
-        .push_i    (mgr_rsp_i.r_valid && mgr_req_o.r_ready),
-        .data_o    (sbr_rsp_o.r),
-        .pop_i     (sbr_rsp_o.r_valid && sbr_req_i.r_ready)
+        .data_i    (mgr_port_rsp_i.r),
+        .push_i    (mgr_port_rsp_i.r_valid && mgr_port_req_o.r_ready),
+        .data_o    (sbr_port_rsp_o.r),
+        .pop_i     (sbr_port_rsp_o.r_valid && sbr_port_req_i.r_ready)
     );
     fifo_v3 #(
         .dtype(b_chan_t),
@@ -143,10 +143,10 @@ module axi_fifo #(
         .full_o    (b_fifo_full),
         .empty_o   (b_fifo_empty),
         .usage_o   (),
-        .data_i    (mgr_rsp_i.b),
-        .push_i    (mgr_rsp_i.b_valid && mgr_req_o.b_ready),
-        .data_o    (sbr_rsp_o.b),
-        .pop_i     (sbr_rsp_o.b_valid && sbr_req_i.b_ready)
+        .data_i    (mgr_port_rsp_i.b),
+        .push_i    (mgr_port_rsp_i.b_valid && mgr_port_req_o.b_ready),
+        .data_o    (sbr_port_rsp_o.b),
+        .pop_i     (sbr_port_rsp_o.b_valid && sbr_port_req_i.b_ready)
     );
   end
 
@@ -216,10 +216,10 @@ module axi_fifo_intf #(
       .clk_i,
       .rst_ni,
       .test_i,
-      .sbr_req_i (sbr_req),
-      .sbr_rsp_o(sbr_rsp),
-      .mgr_req_o (mgr_req),
-      .mgr_rsp_i(mgr_rsp)
+      .sbr_port_req_i (sbr_req),
+      .sbr_port_rsp_o(sbr_rsp),
+      .mgr_port_req_o (mgr_req),
+      .mgr_port_rsp_i(mgr_rsp)
   );
 
   // Check the invariants.
diff --git a/src/axi_from_mem.sv b/src/axi_from_mem.sv
index 3681d319b..1e85419f0 100644
--- a/src/axi_from_mem.sv
+++ b/src/axi_from_mem.sv
@@ -117,8 +117,8 @@ module axi_from_mem #(
     .sbr_rsp_lite_o ( axi_lite_rsp    ),
     .sbr_aw_cache_i,
     .sbr_ar_cache_i,
-    .mgr_req_o      ( axi_req_o       ),
-    .mgr_rsp_i      ( axi_rsp_i       )
+    .mgr_port_req_o      ( axi_req_o       ),
+    .mgr_port_rsp_i      ( axi_rsp_i       )
   );
 
 endmodule
diff --git a/src/axi_id_remap.sv b/src/axi_id_remap.sv
index 72185c56e..c336ba597 100644
--- a/src/axi_id_remap.sv
+++ b/src/axi_id_remap.sv
@@ -77,54 +77,54 @@ module axi_id_remap #(
   /// Asynchronous reset, active low
   input  logic              rst_ni,
   /// Subordinate port request
-  input  sbr_port_axi_req_t sbr_req_i,
+  input  sbr_port_axi_req_t sbr_port_req_i,
   /// Subordinate port response
-  output sbr_port_axi_rsp_t sbr_rsp_o,
+  output sbr_port_axi_rsp_t sbr_port_rsp_o,
   /// Manager port request
-  output mgr_port_axi_req_t mgr_req_o,
+  output mgr_port_axi_req_t mgr_port_req_o,
   /// Manager port response
-  input  mgr_port_axi_rsp_t mgr_rsp_i
+  input  mgr_port_axi_rsp_t mgr_port_rsp_i
 );
 
   // Feed all signals that are not ID or flow control of AW and AR through.
-  assign mgr_req_o.aw.addr   = sbr_req_i.aw.addr;
-  assign mgr_req_o.aw.len    = sbr_req_i.aw.len;
-  assign mgr_req_o.aw.size   = sbr_req_i.aw.size;
-  assign mgr_req_o.aw.burst  = sbr_req_i.aw.burst;
-  assign mgr_req_o.aw.lock   = sbr_req_i.aw.lock;
-  assign mgr_req_o.aw.cache  = sbr_req_i.aw.cache;
-  assign mgr_req_o.aw.prot   = sbr_req_i.aw.prot;
-  assign mgr_req_o.aw.qos    = sbr_req_i.aw.qos;
-  assign mgr_req_o.aw.region = sbr_req_i.aw.region;
-  assign mgr_req_o.aw.atop   = sbr_req_i.aw.atop;
-  assign mgr_req_o.aw.user   = sbr_req_i.aw.user;
-
-  assign mgr_req_o.w         = sbr_req_i.w;
-  assign mgr_req_o.w_valid   = sbr_req_i.w_valid;
-  assign sbr_rsp_o.w_ready   = mgr_rsp_i.w_ready;
-
-  assign sbr_rsp_o.b.resp    = mgr_rsp_i.b.resp;
-  assign sbr_rsp_o.b.user    = mgr_rsp_i.b.user;
-  assign sbr_rsp_o.b_valid   = mgr_rsp_i.b_valid;
-  assign mgr_req_o.b_ready   = sbr_req_i.b_ready;
-
-  assign mgr_req_o.ar.addr   = sbr_req_i.ar.addr;
-  assign mgr_req_o.ar.len    = sbr_req_i.ar.len;
-  assign mgr_req_o.ar.size   = sbr_req_i.ar.size;
-  assign mgr_req_o.ar.burst  = sbr_req_i.ar.burst;
-  assign mgr_req_o.ar.lock   = sbr_req_i.ar.lock;
-  assign mgr_req_o.ar.cache  = sbr_req_i.ar.cache;
-  assign mgr_req_o.ar.prot   = sbr_req_i.ar.prot;
-  assign mgr_req_o.ar.qos    = sbr_req_i.ar.qos;
-  assign mgr_req_o.ar.region = sbr_req_i.ar.region;
-  assign mgr_req_o.ar.user   = sbr_req_i.ar.user;
-
-  assign sbr_rsp_o.r.data    = mgr_rsp_i.r.data;
-  assign sbr_rsp_o.r.resp    = mgr_rsp_i.r.resp;
-  assign sbr_rsp_o.r.last    = mgr_rsp_i.r.last;
-  assign sbr_rsp_o.r.user    = mgr_rsp_i.r.user;
-  assign sbr_rsp_o.r_valid   = mgr_rsp_i.r_valid;
-  assign mgr_req_o.r_ready   = sbr_req_i.r_ready;
+  assign mgr_port_req_o.aw.addr   = sbr_port_req_i.aw.addr;
+  assign mgr_port_req_o.aw.len    = sbr_port_req_i.aw.len;
+  assign mgr_port_req_o.aw.size   = sbr_port_req_i.aw.size;
+  assign mgr_port_req_o.aw.burst  = sbr_port_req_i.aw.burst;
+  assign mgr_port_req_o.aw.lock   = sbr_port_req_i.aw.lock;
+  assign mgr_port_req_o.aw.cache  = sbr_port_req_i.aw.cache;
+  assign mgr_port_req_o.aw.prot   = sbr_port_req_i.aw.prot;
+  assign mgr_port_req_o.aw.qos    = sbr_port_req_i.aw.qos;
+  assign mgr_port_req_o.aw.region = sbr_port_req_i.aw.region;
+  assign mgr_port_req_o.aw.atop   = sbr_port_req_i.aw.atop;
+  assign mgr_port_req_o.aw.user   = sbr_port_req_i.aw.user;
+
+  assign mgr_port_req_o.w         = sbr_port_req_i.w;
+  assign mgr_port_req_o.w_valid   = sbr_port_req_i.w_valid;
+  assign sbr_port_rsp_o.w_ready   = mgr_port_rsp_i.w_ready;
+
+  assign sbr_port_rsp_o.b.resp    = mgr_port_rsp_i.b.resp;
+  assign sbr_port_rsp_o.b.user    = mgr_port_rsp_i.b.user;
+  assign sbr_port_rsp_o.b_valid   = mgr_port_rsp_i.b_valid;
+  assign mgr_port_req_o.b_ready   = sbr_port_req_i.b_ready;
+
+  assign mgr_port_req_o.ar.addr   = sbr_port_req_i.ar.addr;
+  assign mgr_port_req_o.ar.len    = sbr_port_req_i.ar.len;
+  assign mgr_port_req_o.ar.size   = sbr_port_req_i.ar.size;
+  assign mgr_port_req_o.ar.burst  = sbr_port_req_i.ar.burst;
+  assign mgr_port_req_o.ar.lock   = sbr_port_req_i.ar.lock;
+  assign mgr_port_req_o.ar.cache  = sbr_port_req_i.ar.cache;
+  assign mgr_port_req_o.ar.prot   = sbr_port_req_i.ar.prot;
+  assign mgr_port_req_o.ar.qos    = sbr_port_req_i.ar.qos;
+  assign mgr_port_req_o.ar.region = sbr_port_req_i.ar.region;
+  assign mgr_port_req_o.ar.user   = sbr_port_req_i.ar.user;
+
+  assign sbr_port_rsp_o.r.data    = mgr_port_rsp_i.r.data;
+  assign sbr_port_rsp_o.r.resp    = mgr_port_rsp_i.r.resp;
+  assign sbr_port_rsp_o.r.last    = mgr_port_rsp_i.r.last;
+  assign sbr_port_rsp_o.r.user    = mgr_port_rsp_i.r.user;
+  assign sbr_port_rsp_o.r_valid   = mgr_port_rsp_i.r_valid;
+  assign mgr_port_req_o.r_ready   = sbr_port_req_i.r_ready;
 
 
   // Remap tables keep track of in-flight bursts and their input and output IDs.
@@ -153,15 +153,15 @@ module axi_id_remap #(
     .free_oup_id_o   ( wr_free_oup_id                         ),
     .full_o          ( wr_full                                ),
     .push_i          ( wr_push                                ),
-    .push_inp_id_i   ( sbr_req_i.aw.id                        ),
+    .push_inp_id_i   ( sbr_port_req_i.aw.id                        ),
     .push_oup_id_i   ( wr_push_oup_id                         ),
-    .exists_inp_id_i ( sbr_req_i.aw.id                        ),
+    .exists_inp_id_i ( sbr_port_req_i.aw.id                        ),
     .exists_o        ( wr_exists                              ),
     .exists_oup_id_o ( wr_exists_id                           ),
     .exists_full_o   ( wr_exists_full                         ),
-    .pop_i           ( sbr_rsp_o.b_valid && sbr_req_i.b_ready ),
-    .pop_oup_id_i    ( mgr_rsp_i.b.id[IdxWidth-1:0]           ),
-    .pop_inp_id_o    ( sbr_rsp_o.b.id                         )
+    .pop_i           ( sbr_port_rsp_o.b_valid && sbr_port_req_i.b_ready ),
+    .pop_oup_id_i    ( mgr_port_rsp_i.b.id[IdxWidth-1:0]           ),
+    .pop_inp_id_o    ( sbr_port_rsp_o.b.id                         )
   );
   axi_id_remap_table #(
     .InpIdWidth     ( SbrPortIdWidth     ),
@@ -176,13 +176,13 @@ module axi_id_remap #(
     .push_i           ( rd_push                                                    ),
     .push_inp_id_i    ( rd_push_inp_id                                             ),
     .push_oup_id_i    ( rd_push_oup_id                                             ),
-    .exists_inp_id_i  ( sbr_req_i.ar.id                                            ),
+    .exists_inp_id_i  ( sbr_port_req_i.ar.id                                            ),
     .exists_o         ( rd_exists                                                  ),
     .exists_oup_id_o  ( rd_exists_id                                               ),
     .exists_full_o    ( rd_exists_full                                             ),
-    .pop_i            ( sbr_rsp_o.r_valid && sbr_req_i.r_ready && sbr_rsp_o.r.last ),
-    .pop_oup_id_i     ( mgr_rsp_i.r.id[IdxWidth-1:0]                               ),
-    .pop_inp_id_o     ( sbr_rsp_o.r.id                                             )
+    .pop_i            ( sbr_port_rsp_o.r_valid && sbr_port_req_i.r_ready && sbr_port_rsp_o.r.last ),
+    .pop_oup_id_i     ( mgr_port_rsp_i.r.id[IdxWidth-1:0]                               ),
+    .pop_inp_id_o     ( sbr_port_rsp_o.r.id                                             )
   );
   assign both_free = wr_free & rd_free;
   lzc #(
@@ -196,8 +196,8 @@ module axi_id_remap #(
 
   // Zero-extend output IDs if the output IDs is are wider than the IDs from the tables.
   localparam ZeroWidth = MgrPortIdWidth - IdxWidth;
-  assign mgr_req_o.ar.id = {{ZeroWidth{1'b0}}, rd_push_oup_id};
-  assign mgr_req_o.aw.id = {{ZeroWidth{1'b0}}, wr_push_oup_id};
+  assign mgr_port_req_o.ar.id = {{ZeroWidth{1'b0}}, rd_push_oup_id};
+  assign mgr_port_req_o.aw.id = {{ZeroWidth{1'b0}}, wr_push_oup_id};
 
   // Handle requests.
   enum logic [1:0] {Ready, HoldAR, HoldAW, HoldAx} state_d, state_q;
@@ -205,12 +205,12 @@ module axi_id_remap #(
         aw_id_d, aw_id_q;
   logic ar_prio_d, ar_prio_q;
   always_comb begin
-    mgr_req_o.aw_valid = 1'b0;
-    sbr_rsp_o.aw_ready = 1'b0;
+    mgr_port_req_o.aw_valid = 1'b0;
+    sbr_port_rsp_o.aw_ready = 1'b0;
     wr_push            = 1'b0;
     wr_push_oup_id     =   '0;
-    mgr_req_o.ar_valid = 1'b0;
-    sbr_rsp_o.ar_ready = 1'b0;
+    mgr_port_req_o.ar_valid = 1'b0;
+    sbr_port_rsp_o.ar_ready = 1'b0;
     rd_push            = 1'b0;
     rd_push_inp_id     =   '0;
     rd_push_oup_id     =   '0;
@@ -222,48 +222,48 @@ module axi_id_remap #(
     unique case (state_q)
       Ready: begin
         // Reads
-        if (sbr_req_i.ar_valid) begin
+        if (sbr_port_req_i.ar_valid) begin
           // If a burst with the same input ID is already in flight or there are free output IDs:
           if ((rd_exists && !rd_exists_full) || (!rd_exists && !rd_full)) begin
             // Determine the output ID: if another in-flight burst had the same input ID, we must
             // reuse its output ID to maintain ordering; else, we assign the next free ID.
-            rd_push_inp_id     = sbr_req_i.ar.id;
+            rd_push_inp_id     = sbr_port_req_i.ar.id;
             rd_push_oup_id     = rd_exists ? rd_exists_id : rd_free_oup_id;
             // Forward the AR and push a new entry to the read table.
-            mgr_req_o.ar_valid = 1'b1;
+            mgr_port_req_o.ar_valid = 1'b1;
             rd_push            = 1'b1;
           end
         end
 
         // Writes
-        if (sbr_req_i.aw_valid) begin
+        if (sbr_port_req_i.aw_valid) begin
           // If this is not an ATOP that gives rise to an R response, we can handle it in isolation
           // on the write direction.
-          if (!sbr_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin
+          if (!sbr_port_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin
             // If a burst with the same input ID is already in flight or there are free output IDs:
             if ((wr_exists && !wr_exists_full) || (!wr_exists && !wr_full)) begin
               // Determine the output ID: if another in-flight burst had the same input ID, we must
               // reuse its output ID to maintain ordering; else, we assign the next free ID.
               wr_push_oup_id     = wr_exists ? wr_exists_id : wr_free_oup_id;
               // Forward the AW and push a new entry to the write table.
-              mgr_req_o.aw_valid = 1'b1;
+              mgr_port_req_o.aw_valid = 1'b1;
               wr_push            = 1'b1;
             end
           // If this is an ATOP that gives rise to an R response, we must remap to an ID that is
           // free on both read and write direction and push also to the read table.
           // Only allowed if AR does not have arbitration priority
-          end else if (!(ar_prio_q && mgr_req_o.ar_valid)) begin
+          end else if (!(ar_prio_q && mgr_port_req_o.ar_valid)) begin
             // Nullify a potential AR at our output.  This is legal in this state.
-            mgr_req_o.ar_valid = 1'b0;
-            sbr_rsp_o.ar_ready = 1'b0;
+            mgr_port_req_o.ar_valid = 1'b0;
+            sbr_port_rsp_o.ar_ready = 1'b0;
             rd_push            = 1'b0;
             if ((|both_free)) begin
               // Use an output ID that is free in both directions.
               wr_push_oup_id = both_free_oup_id;
-              rd_push_inp_id = sbr_req_i.aw.id;
+              rd_push_inp_id = sbr_port_req_i.aw.id;
               rd_push_oup_id = both_free_oup_id;
               // Forward the AW and push a new entry to both tables.
-              mgr_req_o.aw_valid = 1'b1;
+              mgr_port_req_o.aw_valid = 1'b1;
               rd_push            = 1'b1;
               wr_push            = 1'b1;
               // Give AR priority in the next cycle (so ATOPs cannot infinitely preempt ARs).
@@ -273,69 +273,69 @@ module axi_id_remap #(
         end
 
         // Hold AR, AW, or both if they are valid but not yet ready.
-        if (mgr_req_o.ar_valid) begin
-          sbr_rsp_o.ar_ready = mgr_rsp_i.ar_ready;
-          if (!mgr_rsp_i.ar_ready) begin
+        if (mgr_port_req_o.ar_valid) begin
+          sbr_port_rsp_o.ar_ready = mgr_port_rsp_i.ar_ready;
+          if (!mgr_port_rsp_i.ar_ready) begin
             ar_id_d = rd_push_oup_id;
           end
         end
-        if (mgr_req_o.aw_valid) begin
-          sbr_rsp_o.aw_ready = mgr_rsp_i.aw_ready;
-          if (!mgr_rsp_i.aw_ready) begin
+        if (mgr_port_req_o.aw_valid) begin
+          sbr_port_rsp_o.aw_ready = mgr_port_rsp_i.aw_ready;
+          if (!mgr_port_rsp_i.aw_ready) begin
             aw_id_d = wr_push_oup_id;
           end
         end
-        if ({mgr_req_o.ar_valid, mgr_rsp_i.ar_ready,
-             mgr_req_o.aw_valid, mgr_rsp_i.aw_ready} == 4'b1010) begin
+        if ({mgr_port_req_o.ar_valid, mgr_port_rsp_i.ar_ready,
+             mgr_port_req_o.aw_valid, mgr_port_rsp_i.aw_ready} == 4'b1010) begin
           state_d = HoldAx;
-        end else if ({mgr_req_o.ar_valid, mgr_rsp_i.ar_ready} == 2'b10) begin
+        end else if ({mgr_port_req_o.ar_valid, mgr_port_rsp_i.ar_ready} == 2'b10) begin
           state_d = HoldAR;
-        end else if ({mgr_req_o.aw_valid, mgr_rsp_i.aw_ready} == 2'b10) begin
+        end else if ({mgr_port_req_o.aw_valid, mgr_port_rsp_i.aw_ready} == 2'b10) begin
           state_d = HoldAW;
         end else begin
           state_d = Ready;
         end
 
-        if (mgr_req_o.ar_valid && mgr_rsp_i.ar_ready) begin
+        if (mgr_port_req_o.ar_valid && mgr_port_rsp_i.ar_ready) begin
           ar_prio_d = 1'b0; // Reset AR priority, because handshake was successful in this cycle.
         end
       end
 
       HoldAR: begin
-        // Drive `mgr_req_o.ar.id` through `rd_push_oup_id`.
+        // Drive `mgr_port_req_o.ar.id` through `rd_push_oup_id`.
         rd_push_oup_id      = ar_id_q;
-        mgr_req_o.ar_valid  = 1'b1;
-        sbr_rsp_o.ar_ready = mgr_rsp_i.ar_ready;
-        if (mgr_rsp_i.ar_ready) begin
+        mgr_port_req_o.ar_valid  = 1'b1;
+        sbr_port_rsp_o.ar_ready = mgr_port_rsp_i.ar_ready;
+        if (mgr_port_rsp_i.ar_ready) begin
           state_d = Ready;
           ar_prio_d = 1'b0; // Reset AR priority, because handshake was successful in this cycle.
         end
       end
 
       HoldAW: begin
-        // Drive mgr_req_o.aw.id through `wr_push_oup_id`.
+        // Drive mgr_port_req_o.aw.id through `wr_push_oup_id`.
         wr_push_oup_id      = aw_id_q;
-        mgr_req_o.aw_valid  = 1'b1;
-        sbr_rsp_o.aw_ready = mgr_rsp_i.aw_ready;
-        if (mgr_rsp_i.aw_ready) begin
+        mgr_port_req_o.aw_valid  = 1'b1;
+        sbr_port_rsp_o.aw_ready = mgr_port_rsp_i.aw_ready;
+        if (mgr_port_rsp_i.aw_ready) begin
           state_d = Ready;
         end
       end
 
       HoldAx: begin
         rd_push_oup_id     = ar_id_q;
-        mgr_req_o.ar_valid = 1'b1;
-        sbr_rsp_o.ar_ready = mgr_rsp_i.ar_ready;
+        mgr_port_req_o.ar_valid = 1'b1;
+        sbr_port_rsp_o.ar_ready = mgr_port_rsp_i.ar_ready;
         wr_push_oup_id     = aw_id_q;
-        mgr_req_o.aw_valid = 1'b1;
-        sbr_rsp_o.aw_ready = mgr_rsp_i.aw_ready;
-        unique case ({mgr_rsp_i.ar_ready, mgr_rsp_i.aw_ready})
+        mgr_port_req_o.aw_valid = 1'b1;
+        sbr_port_rsp_o.aw_ready = mgr_port_rsp_i.aw_ready;
+        unique case ({mgr_port_rsp_i.ar_ready, mgr_port_rsp_i.aw_ready})
           2'b01:   state_d = HoldAR;
           2'b10:   state_d = HoldAW;
           2'b11:   state_d = Ready;
           default: /*do nothing / stay in this state*/;
         endcase
-        if (mgr_rsp_i.ar_ready) begin
+        if (mgr_port_rsp_i.ar_ready) begin
           ar_prio_d = 1'b0; // Reset AR priority, because handshake was successful in this cycle.
         end
       end
@@ -363,40 +363,40 @@ module axi_id_remap #(
       else $fatal(1, "Parameter SbrPortMaxUniqIds may be at most 2**SbrPortIdWidth!");
     assert (MaxTxnsPerId > 0)
       else $fatal(1, "Parameter MaxTxnsPerId has to be larger than 0!");
-    assert($bits(sbr_req_i.aw.addr) == $bits(mgr_req_o.aw.addr))
+    assert($bits(sbr_port_req_i.aw.addr) == $bits(mgr_port_req_o.aw.addr))
       else $fatal(1, "AXI AW address widths are not equal!");
-    assert($bits(sbr_req_i.w.data) == $bits(mgr_req_o.w.data))
+    assert($bits(sbr_port_req_i.w.data) == $bits(mgr_port_req_o.w.data))
       else $fatal(1, "AXI W data widths are not equal!");
-    assert($bits(sbr_req_i.w.user) == $bits(mgr_req_o.w.user))
+    assert($bits(sbr_port_req_i.w.user) == $bits(mgr_port_req_o.w.user))
       else $fatal(1, "AXI W user widths are not equal!");
-    assert($bits(sbr_req_i.ar.addr) == $bits(mgr_req_o.ar.addr))
+    assert($bits(sbr_port_req_i.ar.addr) == $bits(mgr_port_req_o.ar.addr))
       else $fatal(1, "AXI AR address widths are not equal!");
-    assert($bits(sbr_rsp_o.r.data) == $bits(mgr_rsp_i.r.data))
+    assert($bits(sbr_port_rsp_o.r.data) == $bits(mgr_port_rsp_i.r.data))
       else $fatal(1, "AXI R data widths are not equal!");
-    assert ($bits(sbr_req_i.aw.id) == SbrPortIdWidth);
-    assert ($bits(sbr_rsp_o.b.id) == SbrPortIdWidth);
-    assert ($bits(sbr_req_i.ar.id) == SbrPortIdWidth);
-    assert ($bits(sbr_rsp_o.r.id) == SbrPortIdWidth);
-    assert ($bits(mgr_req_o.aw.id) == MgrPortIdWidth);
-    assert ($bits(mgr_rsp_i.b.id) == MgrPortIdWidth);
-    assert ($bits(mgr_req_o.ar.id) == MgrPortIdWidth);
-    assert ($bits(mgr_rsp_i.r.id) == MgrPortIdWidth);
+    assert ($bits(sbr_port_req_i.aw.id) == SbrPortIdWidth);
+    assert ($bits(sbr_port_rsp_o.b.id) == SbrPortIdWidth);
+    assert ($bits(sbr_port_req_i.ar.id) == SbrPortIdWidth);
+    assert ($bits(sbr_port_rsp_o.r.id) == SbrPortIdWidth);
+    assert ($bits(mgr_port_req_o.aw.id) == MgrPortIdWidth);
+    assert ($bits(mgr_port_rsp_i.b.id) == MgrPortIdWidth);
+    assert ($bits(mgr_port_req_o.ar.id) == MgrPortIdWidth);
+    assert ($bits(mgr_port_rsp_i.r.id) == MgrPortIdWidth);
   end
   default disable iff (!rst_ni);
-  assert property (@(posedge clk_i) sbr_req_i.aw_valid && sbr_rsp_o.aw_ready
-      |-> mgr_req_o.aw_valid && mgr_rsp_i.aw_ready);
-  assert property (@(posedge clk_i) mgr_rsp_i.b_valid && mgr_req_o.b_ready
-      |-> sbr_rsp_o.b_valid && sbr_req_i.b_ready);
-  assert property (@(posedge clk_i) sbr_req_i.ar_valid && sbr_rsp_o.ar_ready
-      |-> mgr_req_o.ar_valid && mgr_rsp_i.ar_ready);
-  assert property (@(posedge clk_i) mgr_rsp_i.r_valid && mgr_req_o.r_ready
-      |-> sbr_rsp_o.r_valid && sbr_req_i.r_ready);
-  assert property (@(posedge clk_i) sbr_rsp_o.r_valid
-      |-> sbr_rsp_o.r.last == mgr_rsp_i.r.last);
-  assert property (@(posedge clk_i) mgr_req_o.ar_valid && !mgr_rsp_i.ar_ready
-      |=> mgr_req_o.ar_valid && $stable(mgr_req_o.ar.id));
-  assert property (@(posedge clk_i) mgr_req_o.aw_valid && !mgr_rsp_i.aw_ready
-      |=> mgr_req_o.aw_valid && $stable(mgr_req_o.aw.id));
+  assert property (@(posedge clk_i) sbr_port_req_i.aw_valid && sbr_port_rsp_o.aw_ready
+      |-> mgr_port_req_o.aw_valid && mgr_port_rsp_i.aw_ready);
+  assert property (@(posedge clk_i) mgr_port_rsp_i.b_valid && mgr_port_req_o.b_ready
+      |-> sbr_port_rsp_o.b_valid && sbr_port_req_i.b_ready);
+  assert property (@(posedge clk_i) sbr_port_req_i.ar_valid && sbr_port_rsp_o.ar_ready
+      |-> mgr_port_req_o.ar_valid && mgr_port_rsp_i.ar_ready);
+  assert property (@(posedge clk_i) mgr_port_rsp_i.r_valid && mgr_port_req_o.r_ready
+      |-> sbr_port_rsp_o.r_valid && sbr_port_req_i.r_ready);
+  assert property (@(posedge clk_i) sbr_port_rsp_o.r_valid
+      |-> sbr_port_rsp_o.r.last == mgr_port_rsp_i.r.last);
+  assert property (@(posedge clk_i) mgr_port_req_o.ar_valid && !mgr_port_rsp_i.ar_ready
+      |=> mgr_port_req_o.ar_valid && $stable(mgr_port_req_o.ar.id));
+  assert property (@(posedge clk_i) mgr_port_req_o.aw_valid && !mgr_port_rsp_i.aw_ready
+      |=> mgr_port_req_o.aw_valid && $stable(mgr_port_req_o.aw.id));
   `endif
   // pragma translate_on
 endmodule
@@ -639,10 +639,10 @@ module axi_id_remap_intf #(
   ) i_axi_id_remap (
     .clk_i,
     .rst_ni,
-    .sbr_req_i ( sbr_req ),
-    .sbr_rsp_o ( sbr_rsp ),
-    .mgr_req_o ( mgr_req ),
-    .mgr_rsp_i ( mgr_rsp )
+    .sbr_port_req_i ( sbr_req ),
+    .sbr_port_rsp_o ( sbr_rsp ),
+    .mgr_port_req_o ( mgr_req ),
+    .mgr_port_rsp_i ( mgr_rsp )
   );
   // pragma translate_off
   `ifndef VERILATOR
diff --git a/src/axi_id_serialize.sv b/src/axi_id_serialize.sv
index d15fa4ef5..54296fd91 100644
--- a/src/axi_id_serialize.sv
+++ b/src/axi_id_serialize.sv
@@ -62,13 +62,13 @@ module axi_id_serialize #(
   /// Asynchronous reset, active low
   input  logic              rst_ni,
   /// Subordinate port request
-  input  sbr_port_axi_req_t sbr_req_i,
+  input  sbr_port_axi_req_t sbr_port_req_i,
   /// Subordinate port response
-  output sbr_port_axi_rsp_t sbr_rsp_o,
+  output sbr_port_axi_rsp_t sbr_port_rsp_o,
   /// Manager port request
-  output mgr_port_axi_req_t mgr_req_o,
+  output mgr_port_axi_req_t mgr_port_req_o,
   /// Manager port response
-  input  mgr_port_axi_rsp_t mgr_rsp_i
+  input  mgr_port_axi_rsp_t mgr_port_rsp_i
 );
 
   /// Number of bits of the subordinate port ID that determine the mapping to the manager port ID
@@ -144,8 +144,8 @@ module axi_id_serialize #(
   `AXI_TYPEDEF_R_CHAN_T(mgr_r_t, data_t, mgr_id_t, user_t)
 
   select_t sbr_aw_select, sbr_ar_select;
-  assign sbr_aw_select = select_t'(sbr_req_i.aw.id % MgrPortMaxUniqIds); // TODO: customizable base
-  assign sbr_ar_select = select_t'(sbr_req_i.ar.id % MgrPortMaxUniqIds);
+  assign sbr_aw_select = select_t'(sbr_port_req_i.aw.id % MgrPortMaxUniqIds); // TODO: customizable base
+  assign sbr_ar_select = select_t'(sbr_port_req_i.ar.id % MgrPortMaxUniqIds);
 
   sbr_port_axi_req_t [MgrPortMaxUniqIds-1:0] to_serializer_reqs;
   sbr_port_axi_rsp_t [MgrPortMaxUniqIds-1:0] to_serializer_rsps;
@@ -172,10 +172,10 @@ module axi_id_serialize #(
     .clk_i,
     .rst_ni,
     .test_i          ( 1'b0               ),
-    .sbr_req_i       ( sbr_req_i          ),
+    .sbr_port_req_i       ( sbr_port_req_i          ),
     .sbr_aw_select_i ( sbr_aw_select      ),
     .sbr_ar_select_i ( sbr_ar_select      ),
-    .sbr_rsp_o       ( sbr_rsp_o          ),
+    .sbr_port_rsp_o       ( sbr_port_rsp_o          ),
     .mgr_reqs_o      ( to_serializer_reqs ),
     .mgr_rsps_i      ( to_serializer_rsps )
   );
@@ -195,10 +195,10 @@ module axi_id_serialize #(
     ) i_axi_serializer (
       .clk_i,
       .rst_ni,
-      .sbr_req_i ( to_serializer_reqs[i]  ),
-      .sbr_rsp_o ( to_serializer_rsps[i]  ),
-      .mgr_req_o ( tmp_serializer_reqs[i] ),
-      .mgr_rsp_i ( tmp_serializer_rsps[i] )
+      .sbr_port_req_i ( to_serializer_reqs[i]  ),
+      .sbr_port_rsp_o ( to_serializer_rsps[i]  ),
+      .mgr_port_req_o ( tmp_serializer_reqs[i] ),
+      .mgr_port_rsp_i ( tmp_serializer_rsps[i] )
     );
     always_comb begin
       `AXI_SET_REQ_STRUCT(from_serializer_reqs[i], tmp_serializer_reqs[i])
@@ -244,19 +244,19 @@ module axi_id_serialize #(
     .test_i     ( 1'b0                  ),
     .sbr_reqs_i ( from_serializer_reqs  ),
     .sbr_rsps_o ( from_serializer_rsps  ),
-    .mgr_req_o  ( axi_mux_req           ),
-    .mgr_rsp_i  ( axi_mux_rsp           )
+    .mgr_port_req_o  ( axi_mux_req           ),
+    .mgr_port_rsp_i  ( axi_mux_rsp           )
   );
 
   // Shift the ID one down if needed, as mux prepends IDs
   if (MuxIdWidth > 32'd1) begin : gen_id_shift
     always_comb begin
-      `AXI_SET_REQ_STRUCT(mgr_req_o, axi_mux_req)
-      mgr_req_o.aw.id = mgr_id_t'(axi_mux_req.aw.id >> 32'd1);
-      mgr_req_o.ar.id = mgr_id_t'(axi_mux_req.ar.id >> 32'd1);
-      `AXI_SET_RSP_STRUCT(axi_mux_rsp, mgr_rsp_i)
-      axi_mux_rsp.b.id = mux_id_t'(mgr_rsp_i.b.id << 32'd1);
-      axi_mux_rsp.r.id = mux_id_t'(mgr_rsp_i.r.id << 32'd1);
+      `AXI_SET_REQ_STRUCT(mgr_port_req_o, axi_mux_req)
+      mgr_port_req_o.aw.id = mgr_id_t'(axi_mux_req.aw.id >> 32'd1);
+      mgr_port_req_o.ar.id = mgr_id_t'(axi_mux_req.ar.id >> 32'd1);
+      `AXI_SET_RSP_STRUCT(axi_mux_rsp, mgr_port_rsp_i)
+      axi_mux_rsp.b.id = mux_id_t'(mgr_port_rsp_i.b.id << 32'd1);
+      axi_mux_rsp.r.id = mux_id_t'(mgr_port_rsp_i.r.id << 32'd1);
     end
   end else begin : gen_no_id_shift
     axi_id_prepend #(
@@ -290,21 +290,21 @@ module axi_id_serialize #(
       .sbr_r_chans_o    ( axi_mux_rsp.r        ),
       .sbr_r_valids_o   ( axi_mux_rsp.r_valid  ),
       .sbr_r_readies_i  ( axi_mux_req.r_ready  ),
-      .mgr_aw_chans_o   ( mgr_req_o.aw         ),
-      .mgr_aw_valids_o  ( mgr_req_o.aw_valid   ),
-      .mgr_aw_readies_i ( mgr_rsp_i.aw_ready   ),
-      .mgr_w_chans_o    ( mgr_req_o.w          ),
-      .mgr_w_valids_o   ( mgr_req_o.w_valid    ),
-      .mgr_w_readies_i  ( mgr_rsp_i.w_ready    ),
-      .mgr_b_chans_i    ( mgr_rsp_i.b          ),
-      .mgr_b_valids_i   ( mgr_rsp_i.b_valid    ),
-      .mgr_b_readies_o  ( mgr_req_o.b_ready    ),
-      .mgr_ar_chans_o   ( mgr_req_o.ar         ),
-      .mgr_ar_valids_o  ( mgr_req_o.ar_valid   ),
-      .mgr_ar_readies_i ( mgr_rsp_i.ar_ready   ),
-      .mgr_r_chans_i    ( mgr_rsp_i.r          ),
-      .mgr_r_valids_i   ( mgr_rsp_i.r_valid    ),
-      .mgr_r_readies_o  ( mgr_req_o.r_ready    )
+      .mgr_aw_chans_o   ( mgr_port_req_o.aw         ),
+      .mgr_aw_valids_o  ( mgr_port_req_o.aw_valid   ),
+      .mgr_aw_readies_i ( mgr_port_rsp_i.aw_ready   ),
+      .mgr_w_chans_o    ( mgr_port_req_o.w          ),
+      .mgr_w_valids_o   ( mgr_port_req_o.w_valid    ),
+      .mgr_w_readies_i  ( mgr_port_rsp_i.w_ready    ),
+      .mgr_b_chans_i    ( mgr_port_rsp_i.b          ),
+      .mgr_b_valids_i   ( mgr_port_rsp_i.b_valid    ),
+      .mgr_b_readies_o  ( mgr_port_req_o.b_ready    ),
+      .mgr_ar_chans_o   ( mgr_port_req_o.ar         ),
+      .mgr_ar_valids_o  ( mgr_port_req_o.ar_valid   ),
+      .mgr_ar_readies_i ( mgr_port_rsp_i.ar_ready   ),
+      .mgr_r_chans_i    ( mgr_port_rsp_i.r          ),
+      .mgr_r_valids_i   ( mgr_port_rsp_i.r_valid    ),
+      .mgr_r_readies_o  ( mgr_port_req_o.r_ready    )
     );
   end
 
@@ -321,13 +321,13 @@ module axi_id_serialize #(
       else $fatal(1, "Parameter MgrPortIdWidth has to be larger than 0!");
     assert(MgrPortIdWidth <= SbrPortIdWidth)
       else $fatal(1, "Downsize implies that MgrPortIdWidth <= SbrPortIdWidth!");
-    assert($bits(sbr_req_i.aw.addr) == $bits(mgr_req_o.aw.addr))
+    assert($bits(sbr_port_req_i.aw.addr) == $bits(mgr_port_req_o.aw.addr))
       else $fatal(1, "AXI AW address widths are not equal!");
-    assert($bits(sbr_req_i.w.data) == $bits(mgr_req_o.w.data))
+    assert($bits(sbr_port_req_i.w.data) == $bits(mgr_port_req_o.w.data))
       else $fatal(1, "AXI W data widths are not equal!");
-    assert($bits(sbr_req_i.ar.addr) == $bits(mgr_req_o.ar.addr))
+    assert($bits(sbr_port_req_i.ar.addr) == $bits(mgr_port_req_o.ar.addr))
       else $fatal(1, "AXI AR address widths are not equal!");
-    assert($bits(sbr_rsp_o.r.data) == $bits(mgr_rsp_i.r.data))
+    assert($bits(sbr_port_rsp_o.r.data) == $bits(mgr_port_rsp_i.r.data))
       else $fatal(1, "AXI R data widths are not equal!");
   end
   `endif
@@ -402,10 +402,10 @@ module axi_id_serialize_intf #(
   ) i_axi_id_serialize (
     .clk_i,
     .rst_ni,
-    .sbr_req_i ( sbr_req ),
-    .sbr_rsp_o ( sbr_rsp ),
-    .mgr_req_o ( mgr_req ),
-    .mgr_rsp_i ( mgr_rsp )
+    .sbr_port_req_i ( sbr_req ),
+    .sbr_port_rsp_o ( sbr_rsp ),
+    .mgr_port_req_o ( mgr_req ),
+    .mgr_port_rsp_i ( mgr_rsp )
   );
 
 // pragma translate_off
diff --git a/src/axi_isolate.sv b/src/axi_isolate.sv
index 358d7acbc..68095e1cc 100644
--- a/src/axi_isolate.sv
+++ b/src/axi_isolate.sv
@@ -26,7 +26,7 @@
 /// The isolation interface has two signals: `isolate_i` and `isolated_o`.  When `isolate_i` is
 /// asserted, all open transactions are gracefully terminated.  When no transactions are in flight
 /// anymore, the `isolated_o` output is asserted.  As long as `isolated_o` is asserted, all output
-/// signals in `mgr_req_o` are silenced to `'0`.  When isolated, new transactions initiated on the
+/// signals in `mgr_port_req_o` are silenced to `'0`.  When isolated, new transactions initiated on the
 /// subordinate port are stalled until the isolation is terminated by deasserting `isolate_i`.
 ///
 /// ## Response
@@ -63,13 +63,13 @@ module axi_isolate #(
   /// Asynchronous reset, active low
   input  logic      rst_ni,
   /// Subordinate port request
-  input  axi_req_t  sbr_req_i,
+  input  axi_req_t  sbr_port_req_i,
   /// Subordinate port response
-  output axi_rsp_t sbr_rsp_o,
+  output axi_rsp_t sbr_port_rsp_o,
   /// Manager port request
-  output axi_req_t  mgr_req_o,
+  output axi_req_t  mgr_port_req_o,
   /// Manager port response
-  input  axi_rsp_t mgr_rsp_i,
+  input  axi_rsp_t mgr_port_rsp_i,
   /// Isolate manager port from subordinate port
   input  logic      isolate_i,
   /// Manager port is isolated from subordinate port
@@ -116,10 +116,10 @@ module axi_isolate #(
       .clk_i,
       .rst_ni,
       .test_i          ( 1'b0       ),
-      .sbr_req_i,
+      .sbr_port_req_i,
       .sbr_aw_select_i ( isolated_o ),
       .sbr_ar_select_i ( isolated_o ),
-      .sbr_rsp_o,
+      .sbr_port_rsp_o,
       .mgr_reqs_o      ( demux_req ),
       .mgr_rsps_i      ( demux_rsp )
     );
@@ -136,12 +136,12 @@ module axi_isolate #(
       .clk_i,
       .rst_ni,
       .test_i    ( 1'b0         ),
-      .sbr_req_i ( demux_req[1] ),
-      .sbr_rsp_o ( demux_rsp[1] )
+      .sbr_port_req_i ( demux_req[1] ),
+      .sbr_port_rsp_o ( demux_rsp[1] )
     );
   end else begin
-    assign demux_req[0] = sbr_req_i;
-    assign sbr_rsp_o = demux_rsp[0];
+    assign demux_req[0] = sbr_port_req_i;
+    assign sbr_port_rsp_o = demux_rsp[0];
   end
 
   axi_isolate_inner #(
@@ -151,10 +151,10 @@ module axi_isolate #(
   ) i_axi_isolate (
     .clk_i,
     .rst_ni,
-    .sbr_req_i ( demux_req[0] ),
-    .sbr_rsp_o ( demux_rsp[0] ),
-    .mgr_req_o,
-    .mgr_rsp_i,
+    .sbr_port_req_i ( demux_req[0] ),
+    .sbr_port_rsp_o ( demux_rsp[0] ),
+    .mgr_port_req_o,
+    .mgr_port_rsp_i,
     .isolate_i,
     .isolated_o
   );
@@ -167,10 +167,10 @@ module axi_isolate_inner #(
 ) (
   input  logic     clk_i,
   input  logic     rst_ni,
-  input  axi_req_t sbr_req_i,
-  output axi_rsp_t sbr_rsp_o,
-  output axi_req_t mgr_req_o,
-  input  axi_rsp_t mgr_rsp_i,
+  input  axi_req_t sbr_port_req_i,
+  output axi_rsp_t sbr_port_rsp_o,
+  output axi_req_t mgr_port_req_o,
+  input  axi_rsp_t mgr_port_rsp_i,
   input  logic     isolate_i,
   output logic     isolated_o
 );
@@ -213,31 +213,31 @@ module axi_isolate_inner #(
     pending_ar_d  = pending_ar_q;
     update_ar_cnt = 1'b0;
     // write counters
-    if (mgr_req_o.aw_valid && (state_aw_q == Normal)) begin
+    if (mgr_port_req_o.aw_valid && (state_aw_q == Normal)) begin
       pending_aw_d++;
       update_aw_cnt   = 1'b1;
       pending_w_d++;
       update_w_cnt    = 1'b1;
       connect_w       = 1'b1;
-      if (mgr_req_o.aw.atop[axi_pkg::ATOP_R_RESP]) begin
+      if (mgr_port_req_o.aw.atop[axi_pkg::ATOP_R_RESP]) begin
         pending_ar_d++; // handle atomic with read response by injecting a count in AR
         update_ar_cnt = 1'b1;
       end
     end
-    if (mgr_req_o.w_valid  && mgr_rsp_i.w_ready && mgr_req_o.w.last) begin
+    if (mgr_port_req_o.w_valid  && mgr_port_rsp_i.w_ready && mgr_port_req_o.w.last) begin
       pending_w_d--;
       update_w_cnt  = 1'b1;
     end
-    if (mgr_rsp_i.b_valid  && mgr_req_o.b_ready) begin
+    if (mgr_port_rsp_i.b_valid  && mgr_port_req_o.b_ready) begin
       pending_aw_d--;
       update_aw_cnt = 1'b1;
     end
     // read counters
-    if (mgr_req_o.ar_valid && (state_ar_q == Normal)) begin
+    if (mgr_port_req_o.ar_valid && (state_ar_q == Normal)) begin
       pending_ar_d++;
       update_ar_cnt = 1'b1;
     end
-    if (mgr_rsp_i.r_valid  && mgr_req_o.r_ready && mgr_rsp_i.r.last) begin
+    if (mgr_port_rsp_i.r_valid  && mgr_port_req_o.r_ready && mgr_port_rsp_i.r.last) begin
       pending_ar_d--;
       update_ar_cnt = 1'b1;
     end
@@ -251,8 +251,8 @@ module axi_isolate_inner #(
     state_ar_d      = state_ar_q;
     update_ar_state = 1'b0;
     // Connect channel per default
-    mgr_req_o       = sbr_req_i;
-    sbr_rsp_o      = mgr_rsp_i;
+    mgr_port_req_o       = sbr_port_req_i;
+    sbr_port_rsp_o      = mgr_port_rsp_i;
 
     /////////////////////////////////////////////////////////////
     // Write transaction
@@ -264,15 +264,15 @@ module axi_isolate_inner #(
         // counter.
         if (pending_aw_q >= cnt_t'(NumPending) || pending_ar_q >= cnt_t'(2*NumPending)
             || (pending_w_q >= cnt_t'(NumPending))) begin
-          mgr_req_o.aw_valid  = 1'b0;
-          sbr_rsp_o.aw_ready = 1'b0;
+          mgr_port_req_o.aw_valid  = 1'b0;
+          sbr_port_rsp_o.aw_ready = 1'b0;
           if (isolate_i) begin
             state_aw_d      = Drain;
             update_aw_state = 1'b1;
           end
         end else begin
           // here the AW handshake is connected normally
-          if (sbr_req_i.aw_valid && !mgr_rsp_i.aw_ready) begin
+          if (sbr_port_req_i.aw_valid && !mgr_port_rsp_i.aw_ready) begin
             state_aw_d      = Hold;
             update_aw_state = 1'b1;
           end else begin
@@ -284,29 +284,29 @@ module axi_isolate_inner #(
         end
       end
       Hold: begin // Hold the valid signal on 1'b1 if there was no transfer
-        mgr_req_o.aw_valid = 1'b1;
+        mgr_port_req_o.aw_valid = 1'b1;
         // aw_ready normal connected
-        if (mgr_rsp_i.aw_ready) begin
+        if (mgr_port_rsp_i.aw_ready) begin
           update_aw_state = 1'b1;
           state_aw_d      = isolate_i ? Drain : Normal;
         end
       end
       Drain: begin // cut the AW channel until counter is zero
-        mgr_req_o.aw       = '0;
-        mgr_req_o.aw_valid = 1'b0;
-        sbr_rsp_o.aw_ready = 1'b0;
+        mgr_port_req_o.aw       = '0;
+        mgr_port_req_o.aw_valid = 1'b0;
+        sbr_port_rsp_o.aw_ready = 1'b0;
         if (pending_aw_q == '0) begin
           state_aw_d      = Isolate;
           update_aw_state = 1'b1;
         end
       end
       Isolate: begin // Cut the signals to the outputs
-        mgr_req_o.aw       = '0;
-        mgr_req_o.aw_valid = 1'b0;
-        sbr_rsp_o.aw_ready = 1'b0;
-        sbr_rsp_o.b        = '0;
-        sbr_rsp_o.b_valid  = 1'b0;
-        mgr_req_o.b_ready  = 1'b0;
+        mgr_port_req_o.aw       = '0;
+        mgr_port_req_o.aw_valid = 1'b0;
+        sbr_port_rsp_o.aw_ready = 1'b0;
+        sbr_port_rsp_o.b        = '0;
+        sbr_port_rsp_o.b_valid  = 1'b0;
+        mgr_port_req_o.b_ready  = 1'b0;
         if (!isolate_i) begin
           state_aw_d      = Normal;
           update_aw_state = 1'b1;
@@ -317,9 +317,9 @@ module axi_isolate_inner #(
 
     // W channel is cut as long the counter is zero and not explicitly unlocked through an AW.
     if ((pending_w_q == '0) && !connect_w ) begin
-      mgr_req_o.w        = '0;
-      mgr_req_o.w_valid  = 1'b0;
-      sbr_rsp_o.w_ready  = 1'b0;
+      mgr_port_req_o.w        = '0;
+      mgr_port_req_o.w_valid  = 1'b0;
+      sbr_port_rsp_o.w_ready  = 1'b0;
     end
 
     /////////////////////////////////////////////////////////////
@@ -329,15 +329,15 @@ module axi_isolate_inner #(
       Normal: begin
         // cut handshake if counter capacity is reached
         if (pending_ar_q >= NumPending) begin
-          mgr_req_o.ar_valid = 1'b0;
-          sbr_rsp_o.ar_ready = 1'b0;
+          mgr_port_req_o.ar_valid = 1'b0;
+          sbr_port_rsp_o.ar_ready = 1'b0;
           if (isolate_i) begin
             state_ar_d      = Drain;
             update_ar_state = 1'b1;
           end
         end else begin
           // here the AR handshake is connected normally
-          if (sbr_req_i.ar_valid && !mgr_rsp_i.ar_ready) begin
+          if (sbr_port_req_i.ar_valid && !mgr_port_rsp_i.ar_ready) begin
             state_ar_d      = Hold;
             update_ar_state = 1'b1;
           end else begin
@@ -349,29 +349,29 @@ module axi_isolate_inner #(
         end
       end
       Hold: begin // Hold the valid signal on 1'b1 if there was no transfer
-        mgr_req_o.ar_valid = 1'b1;
+        mgr_port_req_o.ar_valid = 1'b1;
         // ar_ready normal connected
-        if (mgr_rsp_i.ar_ready) begin
+        if (mgr_port_rsp_i.ar_ready) begin
           update_ar_state = 1'b1;
           state_ar_d      = isolate_i ? Drain : Normal;
         end
       end
       Drain: begin
-        mgr_req_o.ar       = '0;
-        mgr_req_o.ar_valid = 1'b0;
-        sbr_rsp_o.ar_ready = 1'b0;
+        mgr_port_req_o.ar       = '0;
+        mgr_port_req_o.ar_valid = 1'b0;
+        sbr_port_rsp_o.ar_ready = 1'b0;
         if (pending_ar_q == '0) begin
           state_ar_d      = Isolate;
           update_ar_state = 1'b1;
         end
       end
       Isolate: begin
-        mgr_req_o.ar       = '0;
-        mgr_req_o.ar_valid = 1'b0;
-        sbr_rsp_o.ar_ready = 1'b0;
-        sbr_rsp_o.r        = '0;
-        sbr_rsp_o.r_valid  = 1'b0;
-        mgr_req_o.r_ready  = 1'b0;
+        mgr_port_req_o.ar       = '0;
+        mgr_port_req_o.ar_valid = 1'b0;
+        sbr_port_rsp_o.ar_ready = 1'b0;
+        sbr_port_rsp_o.r        = '0;
+        sbr_port_rsp_o.r_valid  = 1'b0;
+        mgr_port_req_o.r_ready  = 1'b0;
         if (!isolate_i) begin
           state_ar_d      = Normal;
           update_ar_state = 1'b1;
@@ -465,10 +465,10 @@ module axi_isolate_intf #(
   ) i_axi_isolate (
     .clk_i,
     .rst_ni,
-    .sbr_req_i ( sbr_req ),
-    .sbr_rsp_o ( sbr_rsp ),
-    .mgr_req_o ( mgr_req ),
-    .mgr_rsp_i ( mgr_rsp ),
+    .sbr_port_req_i ( sbr_req ),
+    .sbr_port_rsp_o ( sbr_rsp ),
+    .mgr_port_req_o ( mgr_req ),
+    .mgr_port_rsp_i ( mgr_rsp ),
     .isolate_i,
     .isolated_o
   );
diff --git a/src/axi_iw_converter.sv b/src/axi_iw_converter.sv
index d510aba06..3e777648e 100644
--- a/src/axi_iw_converter.sv
+++ b/src/axi_iw_converter.sv
@@ -99,13 +99,13 @@ module axi_iw_converter #(
   /// Asynchronous reset, active low
   input  logic              rst_ni,
   /// Subordinate port request
-  input  sbr_port_axi_req_t sbr_req_i,
+  input  sbr_port_axi_req_t sbr_port_req_i,
   /// Subordinate port response
-  output sbr_port_axi_rsp_t sbr_rsp_o,
+  output sbr_port_axi_rsp_t sbr_port_rsp_o,
   /// Manager port request
-  output mgr_port_axi_req_t mgr_req_o,
+  output mgr_port_axi_req_t mgr_port_req_o,
   /// Manager port response
-  input  mgr_port_axi_rsp_t mgr_rsp_i
+  input  mgr_port_axi_rsp_t mgr_port_rsp_i
 );
 
   typedef logic [AddrWidth-1:0]      addr_t;
@@ -138,10 +138,10 @@ module axi_iw_converter #(
       ) i_axi_id_remap (
         .clk_i,
         .rst_ni,
-        .sbr_req_i ( sbr_req_i ),
-        .sbr_rsp_o ( sbr_rsp_o ),
-        .mgr_req_o ( mgr_req_o ),
-        .mgr_rsp_i ( mgr_rsp_i )
+        .sbr_port_req_i ( sbr_port_req_i ),
+        .sbr_port_rsp_o ( sbr_port_rsp_o ),
+        .mgr_port_req_o ( mgr_port_req_o ),
+        .mgr_port_rsp_i ( mgr_port_rsp_i )
       );
     end else begin : gen_serialize
       axi_id_serialize #(
@@ -160,10 +160,10 @@ module axi_iw_converter #(
       ) i_axi_id_serialize (
         .clk_i,
         .rst_ni,
-        .sbr_req_i ( sbr_req_i ),
-        .sbr_rsp_o ( sbr_rsp_o ),
-        .mgr_req_o ( mgr_req_o ),
-        .mgr_rsp_i ( mgr_rsp_i )
+        .sbr_port_req_i ( sbr_port_req_i ),
+        .sbr_port_rsp_o ( sbr_port_rsp_o ),
+        .mgr_port_req_o ( mgr_port_req_o ),
+        .mgr_port_rsp_i ( mgr_port_rsp_i )
       );
       end
   end else if (MgrPortIdWidth > SbrPortIdWidth) begin : gen_upsize
@@ -183,40 +183,40 @@ module axi_iw_converter #(
       .mgr_r_chan_t   ( mgr_r_t         )
     ) i_axi_id_prepend (
       .pre_id_i         ( '0                 ),
-      .sbr_aw_chans_i   ( sbr_req_i.aw       ),
-      .sbr_aw_valids_i  ( sbr_req_i.aw_valid ),
-      .sbr_aw_readies_o ( sbr_rsp_o.aw_ready ),
-      .sbr_w_chans_i    ( sbr_req_i.w        ),
-      .sbr_w_valids_i   ( sbr_req_i.w_valid  ),
-      .sbr_w_readies_o  ( sbr_rsp_o.w_ready  ),
-      .sbr_b_chans_o    ( sbr_rsp_o.b        ),
-      .sbr_b_valids_o   ( sbr_rsp_o.b_valid  ),
-      .sbr_b_readies_i  ( sbr_req_i.b_ready  ),
-      .sbr_ar_chans_i   ( sbr_req_i.ar       ),
-      .sbr_ar_valids_i  ( sbr_req_i.ar_valid ),
-      .sbr_ar_readies_o ( sbr_rsp_o.ar_ready ),
-      .sbr_r_chans_o    ( sbr_rsp_o.r        ),
-      .sbr_r_valids_o   ( sbr_rsp_o.r_valid  ),
-      .sbr_r_readies_i  ( sbr_req_i.r_ready  ),
-      .mgr_aw_chans_o   ( mgr_req_o.aw       ),
-      .mgr_aw_valids_o  ( mgr_req_o.aw_valid ),
-      .mgr_aw_readies_i ( mgr_rsp_i.aw_ready ),
-      .mgr_w_chans_o    ( mgr_req_o.w        ),
-      .mgr_w_valids_o   ( mgr_req_o.w_valid  ),
-      .mgr_w_readies_i  ( mgr_rsp_i.w_ready  ),
-      .mgr_b_chans_i    ( mgr_rsp_i.b        ),
-      .mgr_b_valids_i   ( mgr_rsp_i.b_valid  ),
-      .mgr_b_readies_o  ( mgr_req_o.b_ready  ),
-      .mgr_ar_chans_o   ( mgr_req_o.ar       ),
-      .mgr_ar_valids_o  ( mgr_req_o.ar_valid ),
-      .mgr_ar_readies_i ( mgr_rsp_i.ar_ready ),
-      .mgr_r_chans_i    ( mgr_rsp_i.r        ),
-      .mgr_r_valids_i   ( mgr_rsp_i.r_valid  ),
-      .mgr_r_readies_o  ( mgr_req_o.r_ready  )
+      .sbr_aw_chans_i   ( sbr_port_req_i.aw       ),
+      .sbr_aw_valids_i  ( sbr_port_req_i.aw_valid ),
+      .sbr_aw_readies_o ( sbr_port_rsp_o.aw_ready ),
+      .sbr_w_chans_i    ( sbr_port_req_i.w        ),
+      .sbr_w_valids_i   ( sbr_port_req_i.w_valid  ),
+      .sbr_w_readies_o  ( sbr_port_rsp_o.w_ready  ),
+      .sbr_b_chans_o    ( sbr_port_rsp_o.b        ),
+      .sbr_b_valids_o   ( sbr_port_rsp_o.b_valid  ),
+      .sbr_b_readies_i  ( sbr_port_req_i.b_ready  ),
+      .sbr_ar_chans_i   ( sbr_port_req_i.ar       ),
+      .sbr_ar_valids_i  ( sbr_port_req_i.ar_valid ),
+      .sbr_ar_readies_o ( sbr_port_rsp_o.ar_ready ),
+      .sbr_r_chans_o    ( sbr_port_rsp_o.r        ),
+      .sbr_r_valids_o   ( sbr_port_rsp_o.r_valid  ),
+      .sbr_r_readies_i  ( sbr_port_req_i.r_ready  ),
+      .mgr_aw_chans_o   ( mgr_port_req_o.aw       ),
+      .mgr_aw_valids_o  ( mgr_port_req_o.aw_valid ),
+      .mgr_aw_readies_i ( mgr_port_rsp_i.aw_ready ),
+      .mgr_w_chans_o    ( mgr_port_req_o.w        ),
+      .mgr_w_valids_o   ( mgr_port_req_o.w_valid  ),
+      .mgr_w_readies_i  ( mgr_port_rsp_i.w_ready  ),
+      .mgr_b_chans_i    ( mgr_port_rsp_i.b        ),
+      .mgr_b_valids_i   ( mgr_port_rsp_i.b_valid  ),
+      .mgr_b_readies_o  ( mgr_port_req_o.b_ready  ),
+      .mgr_ar_chans_o   ( mgr_port_req_o.ar       ),
+      .mgr_ar_valids_o  ( mgr_port_req_o.ar_valid ),
+      .mgr_ar_readies_i ( mgr_port_rsp_i.ar_ready ),
+      .mgr_r_chans_i    ( mgr_port_rsp_i.r        ),
+      .mgr_r_valids_i   ( mgr_port_rsp_i.r_valid  ),
+      .mgr_r_readies_o  ( mgr_port_req_o.r_ready  )
     );
   end else begin : gen_passthrough
-    assign mgr_req_o = sbr_req_i;
-    assign sbr_rsp_o = mgr_rsp_i;
+    assign mgr_port_req_o = sbr_port_req_i;
+    assign sbr_port_rsp_o = mgr_port_rsp_i;
   end
 
   // pragma translate_off
@@ -241,13 +241,13 @@ module axi_iw_converter #(
       assert(MgrPortMaxTxnsPerId > 32'd0)
         else $fatal(1, "Parameter MgrPortMaxTxnsPerId has to be larger than 0!");
     end
-    assert($bits(sbr_req_i.aw.addr) == $bits(mgr_req_o.aw.addr))
+    assert($bits(sbr_port_req_i.aw.addr) == $bits(mgr_port_req_o.aw.addr))
       else $fatal(1, "AXI AW address widths are not equal!");
-    assert($bits(sbr_req_i.w.data) == $bits(mgr_req_o.w.data))
+    assert($bits(sbr_port_req_i.w.data) == $bits(mgr_port_req_o.w.data))
       else $fatal(1, "AXI W data widths are not equal!");
-    assert($bits(sbr_req_i.ar.addr) == $bits(mgr_req_o.ar.addr))
+    assert($bits(sbr_port_req_i.ar.addr) == $bits(mgr_port_req_o.ar.addr))
       else $fatal(1, "AXI AR address widths are not equal!");
-    assert($bits(sbr_rsp_o.r.data) == $bits(mgr_rsp_i.r.data))
+    assert($bits(sbr_port_rsp_o.r.data) == $bits(mgr_port_rsp_i.r.data))
       else $fatal(1, "AXI R data widths are not equal!");
   end
   `endif
@@ -328,10 +328,10 @@ module axi_iw_converter_intf #(
   ) i_axi_iw_converter (
     .clk_i,
     .rst_ni,
-    .sbr_req_i ( sbr_req ),
-    .sbr_rsp_o ( sbr_rsp ),
-    .mgr_req_o ( mgr_req ),
-    .mgr_rsp_i ( mgr_rsp )
+    .sbr_port_req_i ( sbr_req ),
+    .sbr_port_rsp_o ( sbr_rsp ),
+    .mgr_port_req_o ( mgr_req ),
+    .mgr_port_rsp_i ( mgr_rsp )
   );
   // pragma translate_off
   `ifndef VERILATOR
diff --git a/src/axi_lfsr.sv b/src/axi_lfsr.sv
index 88164f857..d63dafe4b 100644
--- a/src/axi_lfsr.sv
+++ b/src/axi_lfsr.sv
@@ -94,10 +94,10 @@ module axi_lfsr #(
         .clk_i,
         .rst_ni,
         .test_i    ( testmode_i   ),
-        .sbr_req_i ( req_i        ),
-        .sbr_rsp_o ( rsp_o        ),
-        .mgr_req_o ( axi_lite_req ),
-        .mgr_rsp_i ( axi_lite_rsp )
+        .sbr_port_req_i ( req_i        ),
+        .sbr_port_rsp_o ( rsp_o        ),
+        .mgr_port_req_o ( axi_lite_req ),
+        .mgr_port_rsp_i ( axi_lite_rsp )
     );
 
     axi_lite_lfsr #(
diff --git a/src/axi_lite_demux.sv b/src/axi_lite_demux.sv
index 2a42b8976..58e30866a 100644
--- a/src/axi_lite_demux.sv
+++ b/src/axi_lite_demux.sv
@@ -47,10 +47,10 @@ module axi_lite_demux #(
   input  logic                            rst_ni,
   input  logic                            test_i,
   // subordinate port (AXI4-Lite input), connect manager module here
-  input  axi_lite_req_t                   sbr_req_i,
+  input  axi_lite_req_t                   sbr_port_req_i,
   input  select_t                         sbr_aw_select_i,
   input  select_t                         sbr_ar_select_i,
-  output axi_lite_rsp_t                   sbr_rsp_o,
+  output axi_lite_rsp_t                   sbr_port_rsp_o,
   // manager ports (AXI4-Lite outputs), connect subordinate modules here
   output axi_lite_req_t [NumMgrPorts-1:0] mgr_reqs_o,
   input  axi_lite_rsp_t [NumMgrPorts-1:0] mgr_rsps_i
@@ -76,9 +76,9 @@ module axi_lite_demux #(
     ) i_aw_spill_reg (
       .clk_i   ( clk_i                    ),
       .rst_ni  ( rst_ni                   ),
-      .valid_i ( sbr_req_i.aw_valid       ),
-      .ready_o ( sbr_rsp_o.aw_ready       ),
-      .data_i  ( sbr_req_i.aw             ),
+      .valid_i ( sbr_port_req_i.aw_valid       ),
+      .ready_o ( sbr_port_rsp_o.aw_ready       ),
+      .data_i  ( sbr_port_req_i.aw             ),
       .valid_o ( mgr_reqs_o[0].aw_valid   ),
       .ready_i ( mgr_rsps_i[0].aw_ready   ),
       .data_o  ( mgr_reqs_o[0].aw         )
@@ -89,9 +89,9 @@ module axi_lite_demux #(
     ) i_w_spill_reg (
       .clk_i   ( clk_i                   ),
       .rst_ni  ( rst_ni                  ),
-      .valid_i ( sbr_req_i.w_valid       ),
-      .ready_o ( sbr_rsp_o.w_ready       ),
-      .data_i  ( sbr_req_i.w             ),
+      .valid_i ( sbr_port_req_i.w_valid       ),
+      .ready_o ( sbr_port_rsp_o.w_ready       ),
+      .data_i  ( sbr_port_req_i.w             ),
       .valid_o ( mgr_reqs_o[0].w_valid   ),
       .ready_i ( mgr_rsps_i[0].w_ready   ),
       .data_o  ( mgr_reqs_o[0].w         )
@@ -105,9 +105,9 @@ module axi_lite_demux #(
       .valid_i ( mgr_rsps_i[0].b_valid  ),
       .ready_o ( mgr_reqs_o[0].b_ready  ),
       .data_i  ( mgr_rsps_i[0].b        ),
-      .valid_o ( sbr_rsp_o.b_valid      ),
-      .ready_i ( sbr_req_i.b_ready      ),
-      .data_o  ( sbr_rsp_o.b            )
+      .valid_o ( sbr_port_rsp_o.b_valid      ),
+      .ready_i ( sbr_port_req_i.b_ready      ),
+      .data_o  ( sbr_port_rsp_o.b            )
     );
     spill_register #(
       .T       ( ar_chan_t  ),
@@ -115,9 +115,9 @@ module axi_lite_demux #(
     ) i_ar_spill_reg (
       .clk_i   ( clk_i                    ),
       .rst_ni  ( rst_ni                   ),
-      .valid_i ( sbr_req_i.ar_valid       ),
-      .ready_o ( sbr_rsp_o.ar_ready       ),
-      .data_i  ( sbr_req_i.ar             ),
+      .valid_i ( sbr_port_req_i.ar_valid       ),
+      .ready_o ( sbr_port_rsp_o.ar_ready       ),
+      .data_i  ( sbr_port_req_i.ar             ),
       .valid_o ( mgr_reqs_o[0].ar_valid   ),
       .ready_i ( mgr_rsps_i[0].ar_ready   ),
       .data_o  ( mgr_reqs_o[0].ar         )
@@ -131,9 +131,9 @@ module axi_lite_demux #(
       .valid_i ( mgr_rsps_i[0].r_valid  ),
       .ready_o ( mgr_reqs_o[0].r_ready  ),
       .data_i  ( mgr_rsps_i[0].r        ),
-      .valid_o ( sbr_rsp_o.r_valid      ),
-      .ready_i ( sbr_req_i.r_ready      ),
-      .data_o  ( sbr_rsp_o.r            )
+      .valid_o ( sbr_port_rsp_o.r_valid      ),
+      .ready_i ( sbr_port_req_i.r_ready      ),
+      .data_o  ( sbr_port_rsp_o.r            )
     );
 
   end else begin : gen_demux
@@ -203,15 +203,15 @@ module axi_lite_demux #(
     `endif
     aw_chan_select_flat_t sbr_aw_chan_select_in_flat,
                           sbr_aw_chan_select_out_flat;
-    assign sbr_aw_chan_select_in_flat = {sbr_req_i.aw, sbr_aw_select_i};
+    assign sbr_aw_chan_select_in_flat = {sbr_port_req_i.aw, sbr_aw_select_i};
     spill_register #(
       .T      ( aw_chan_select_flat_t         ),
       .Bypass ( ~SpillAw                      )
     ) i_aw_spill_reg (
       .clk_i   ( clk_i                        ),
       .rst_ni  ( rst_ni                       ),
-      .valid_i ( sbr_req_i.aw_valid           ),
-      .ready_o ( sbr_rsp_o.aw_ready           ),
+      .valid_i ( sbr_port_req_i.aw_valid           ),
+      .ready_o ( sbr_port_rsp_o.aw_ready           ),
       .data_i  ( sbr_aw_chan_select_in_flat   ),
       .valid_o ( sbr_aw_valid                 ),
       .ready_i ( sbr_aw_ready                 ),
@@ -294,9 +294,9 @@ module axi_lite_demux #(
     ) i_w_spill_reg (
       .clk_i   ( clk_i              ),
       .rst_ni  ( rst_ni             ),
-      .valid_i ( sbr_req_i.w_valid  ),
-      .ready_o ( sbr_rsp_o.w_ready  ),
-      .data_i  ( sbr_req_i.w        ),
+      .valid_i ( sbr_port_req_i.w_valid  ),
+      .ready_o ( sbr_port_rsp_o.w_ready  ),
+      .data_i  ( sbr_port_req_i.w        ),
       .valid_o ( sbr_w_valid        ),
       .ready_i ( sbr_w_ready        ),
       .data_o  ( sbr_w_chan         )
@@ -341,9 +341,9 @@ module axi_lite_demux #(
       .valid_i ( sbr_b_valid        ),
       .ready_o ( sbr_b_ready        ),
       .data_i  ( sbr_b_chan         ),
-      .valid_o ( sbr_rsp_o.b_valid  ),
-      .ready_i ( sbr_req_i.b_ready  ),
-      .data_o  ( sbr_rsp_o.b        )
+      .valid_o ( sbr_port_rsp_o.b_valid  ),
+      .ready_i ( sbr_port_req_i.b_ready  ),
+      .data_o  ( sbr_port_rsp_o.b        )
     );
 
     // connect the response if the FIFO has valid data in it
@@ -365,15 +365,15 @@ module axi_lite_demux #(
     `endif
     ar_chan_select_flat_t sbr_ar_chan_select_in_flat,
                           sbr_ar_chan_select_out_flat;
-    assign sbr_ar_chan_select_in_flat = {sbr_req_i.ar, sbr_ar_select_i};
+    assign sbr_ar_chan_select_in_flat = {sbr_port_req_i.ar, sbr_ar_select_i};
     spill_register #(
       .T      ( ar_chan_select_flat_t         ),
       .Bypass ( ~SpillAr                      )
     ) i_ar_spill_reg (
       .clk_i   ( clk_i                        ),
       .rst_ni  ( rst_ni                       ),
-      .valid_i ( sbr_req_i.ar_valid           ),
-      .ready_o ( sbr_rsp_o.ar_ready           ),
+      .valid_i ( sbr_port_req_i.ar_valid           ),
+      .ready_o ( sbr_port_rsp_o.ar_ready           ),
       .data_i  ( sbr_ar_chan_select_in_flat   ),
       .valid_o ( sbr_ar_valid                 ),
       .ready_i ( sbr_ar_ready                 ),
@@ -420,9 +420,9 @@ module axi_lite_demux #(
       .valid_i ( sbr_r_valid        ),
       .ready_o ( sbr_r_ready        ),
       .data_i  ( sbr_r_chan         ),
-      .valid_o ( sbr_rsp_o.r_valid  ),
-      .ready_i ( sbr_req_i.r_ready  ),
-      .data_o  ( sbr_rsp_o.r        )
+      .valid_o ( sbr_port_rsp_o.r_valid  ),
+      .ready_i ( sbr_port_req_i.r_ready  ),
+      .data_o  ( sbr_port_rsp_o.r        )
     );
 
     // connect the response if the FIFO has valid data in it
@@ -443,11 +443,11 @@ module axi_lite_demux #(
     // pragma translate_off
     `ifndef VERILATOR
     default disable iff (!rst_ni);
-    aw_select: assume property( @(posedge clk_i) (sbr_req_i.aw_valid |->
+    aw_select: assume property( @(posedge clk_i) (sbr_port_req_i.aw_valid |->
                                                  (sbr_aw_select_i < NumMgrPorts))) else
       $fatal(1, "sbr_aw_select_i is %d: AW has selected a subordinate that is not defined.\
                  NumMgrPorts: %d", sbr_aw_select_i, NumMgrPorts);
-    ar_select: assume property( @(posedge clk_i) (sbr_req_i.ar_valid |->
+    ar_select: assume property( @(posedge clk_i) (sbr_port_req_i.ar_valid |->
                                                  (sbr_ar_select_i < NumMgrPorts))) else
       $fatal(1, "sbr_ar_select_i is %d: AR has selected a subordinate that is not defined.\
                  NumMgrPorts: %d", sbr_ar_select_i, NumMgrPorts);
@@ -547,10 +547,10 @@ module axi_lite_demux_intf #(
     .rst_ni,
     .test_i,
     // subordinate Port
-    .sbr_req_i       ( sbr_req         ),
+    .sbr_port_req_i       ( sbr_req         ),
     .sbr_aw_select_i ( sbr_aw_select_i ), // must be stable while sbr_aw_valid_i
     .sbr_ar_select_i ( sbr_ar_select_i ), // must be stable while sbr_ar_valid_i
-    .sbr_rsp_o       ( sbr_rsp         ),
+    .sbr_port_rsp_o       ( sbr_rsp         ),
     // mgrer ports
     .mgr_reqs_o      ( mgr_reqs        ),
     .mgr_rsps_i      ( mgr_rsps        )
diff --git a/src/axi_lite_mailbox.sv b/src/axi_lite_mailbox.sv
index 232afa9b4..0535d1385 100644
--- a/src/axi_lite_mailbox.sv
+++ b/src/axi_lite_mailbox.sv
@@ -67,8 +67,8 @@ module axi_lite_mailbox #(
     .clk_i,   // Clock
     .rst_ni,  // Asynchronous reset active low
     // subordinate port
-    .sbr_req_i      ( sbr_reqs_i[0]   ),
-    .sbr_rsp_o      ( sbr_rsps_o[0]   ),
+    .sbr_port_req_i      ( sbr_reqs_i[0]   ),
+    .sbr_port_rsp_o      ( sbr_rsps_o[0]   ),
     .base_addr_i    ( base_addr_i[0]  ), // base address for the subordinate port
     // write FIFO port
     .mbox_w_data_o  ( mbox_w_data[0]  ),
@@ -100,8 +100,8 @@ module axi_lite_mailbox #(
     .clk_i,   // Clock
     .rst_ni,  // Asynchronous reset active low
     // subordinate port
-    .sbr_req_i      ( sbr_reqs_i[1]   ),
-    .sbr_rsp_o      ( sbr_rsps_o[1]   ),
+    .sbr_port_req_i      ( sbr_reqs_i[1]   ),
+    .sbr_port_rsp_o      ( sbr_rsps_o[1]   ),
     .base_addr_i    ( base_addr_i[1]  ), // base address for the subordinate port
     // write FIFO port
     .mbox_w_data_o  ( mbox_w_data[1]  ),
@@ -214,8 +214,8 @@ module axi_lite_mailbox_subordinate #(
   input  logic          clk_i,   // Clock
   input  logic          rst_ni,  // Asynchronous reset active low
   // subordinate port
-  input  axi_lite_req_t sbr_req_i,
-  output axi_lite_rsp_t sbr_rsp_o,
+  input  axi_lite_req_t sbr_port_req_i,
+  output axi_lite_rsp_t sbr_port_rsp_o,
   input  addr_t         base_addr_i, // base address for the subordinate port
   // write FIFO port
   output data_t         mbox_w_data_o,
@@ -300,7 +300,7 @@ module axi_lite_mailbox_subordinate #(
 
   // Mailbox FIFO data assignments
   for (genvar i = 0; i < (DataWidth/8); i++) begin : gen_w_mbox_data
-    assign mbox_w_data_o[i*8+:8] = sbr_req_i.w.strb[i] ? sbr_req_i.w.data[i*8+:8] : '0;
+    assign mbox_w_data_o[i*8+:8] = sbr_port_req_i.w.strb[i] ? sbr_port_req_i.w.data[i*8+:8] : '0;
   end
 
   // combinational mailbox register assignments, for the read only registers
@@ -314,11 +314,11 @@ module axi_lite_mailbox_subordinate #(
 
   always_comb begin
     // subordinate port channel outputs for the AW, W and R channel, other driven from spill register
-    sbr_rsp_o.aw_ready = 1'b0;
-    sbr_rsp_o.w_ready  = 1'b0;
+    sbr_port_rsp_o.aw_ready = 1'b0;
+    sbr_port_rsp_o.w_ready  = 1'b0;
     b_chan             = '{resp: axi_pkg::RESP_SLVERR};
     b_valid            = 1'b0;
-    sbr_rsp_o.ar_ready = 1'b0;
+    sbr_port_rsp_o.ar_ready = 1'b0;
     r_chan             = '{data: '0, resp: axi_pkg::RESP_SLVERR};
     r_valid            = 1'b0;
     // Default assignments for the internal registers
@@ -361,7 +361,7 @@ module axi_lite_mailbox_subordinate #(
     // active state.
 
     // Check if there is a pending read request on the subordinate port.
-    if (sbr_req_i.ar_valid) begin
+    if (sbr_port_req_i.ar_valid) begin
       // set the right read channel output depending on the address decoding
       if (dec_r_valid) begin
         // when decode not valid, send the default subordinateerror
@@ -397,7 +397,7 @@ module axi_lite_mailbox_subordinate #(
       end
       r_valid = 1'b1;
       if (r_ready) begin
-        sbr_rsp_o.ar_ready = 1'b1;
+        sbr_port_rsp_o.ar_ready = 1'b1;
       end
     end // read register
 
@@ -405,7 +405,7 @@ module axi_lite_mailbox_subordinate #(
     // Write registers
     // -------------------------------------------
     // Wait for control and write data to be valid.
-    if (sbr_req_i.aw_valid && sbr_req_i.w_valid) begin
+    if (sbr_port_req_i.aw_valid && sbr_port_req_i.w_valid) begin
       // Can do the handshake here as the b response goes into a spill register with latency one.
       // Without the B spill register, the B channel would violate the AXI stable requirement.
       b_valid = 1'b1;
@@ -429,7 +429,7 @@ module axi_lite_mailbox_subordinate #(
             // ERROR:  read only
             WIRQT:  begin
               for (int unsigned i = 0; i < DataWidth/8; i++) begin
-                wirqt_d[i*8+:8] = sbr_req_i.w.strb[i] ? sbr_req_i.w.data[i*8+:8] : 8'b0000_0000;
+                wirqt_d[i*8+:8] = sbr_port_req_i.w.strb[i] ? sbr_port_req_i.w.data[i*8+:8] : 8'b0000_0000;
               end
               if (wirqt_d >= data_t'(MailboxDepth)) begin
                 // the `-1` is to have the interrupt fireing when the FIFO is comletely full
@@ -440,7 +440,7 @@ module axi_lite_mailbox_subordinate #(
             end
             RIRQT:  begin
               for (int unsigned i = 0; i < DataWidth/8; i++) begin
-                rirqt_d[i*8+:8] = sbr_req_i.w.strb[i] ? sbr_req_i.w.data[i*8+:8] : 8'b0000_0000;
+                rirqt_d[i*8+:8] = sbr_port_req_i.w.strb[i] ? sbr_port_req_i.w.data[i*8+:8] : 8'b0000_0000;
               end
               if (rirqt_d >= data_t'(MailboxDepth)) begin
               // Threshold to maximal value, minus two to prevent overflow in usage
@@ -451,37 +451,37 @@ module axi_lite_mailbox_subordinate #(
             end
             IRQS:   begin
               // Acknowledge and clear the register by asserting the respective one
-              if (sbr_req_i.w.strb[0]) begin
+              if (sbr_port_req_i.w.strb[0]) begin
                 // *_d signal is set in the beginning of this process, prevent accidental
                 // overwrite of not acknowledged irq
-                irqs_d[2]   = sbr_req_i.w.data[2] ? 1'b0 : irqs_d[2]; // Error irq status
-                irqs_d[1]   = sbr_req_i.w.data[1] ? 1'b0 : irqs_d[1]; // Read  irq status
-                irqs_d[0]   = sbr_req_i.w.data[0] ? 1'b0 : irqs_d[0]; // Write irq status
+                irqs_d[2]   = sbr_port_req_i.w.data[2] ? 1'b0 : irqs_d[2]; // Error irq status
+                irqs_d[1]   = sbr_port_req_i.w.data[1] ? 1'b0 : irqs_d[1]; // Read  irq status
+                irqs_d[0]   = sbr_port_req_i.w.data[0] ? 1'b0 : irqs_d[0]; // Write irq status
                 clear_irq_o = 1'b1;
                 update_regs = 1'b1;
               end
               b_chan = '{resp: axi_pkg::RESP_OKAY};
             end
             IRQEN:  begin
-              if (sbr_req_i.w.strb[0]) begin
-                irqen_d[2:0]  = sbr_req_i.w.data[2:0]; // set the irq enable bits
+              if (sbr_port_req_i.w.strb[0]) begin
+                irqen_d[2:0]  = sbr_port_req_i.w.data[2:0]; // set the irq enable bits
                 update_regs = 1'b1;
               end
               b_chan = '{resp: axi_pkg::RESP_OKAY};
             end
             // IRQP: read only
             CTRL:   begin
-              if (sbr_req_i.w.strb[0]) begin
-                mbox_r_flush_o = sbr_req_i.w.data[1]; // Flush read  FIFO
-                mbox_w_flush_o = sbr_req_i.w.data[0]; // Flush write FIFO
+              if (sbr_port_req_i.w.strb[0]) begin
+                mbox_r_flush_o = sbr_port_req_i.w.data[1]; // Flush read  FIFO
+                mbox_w_flush_o = sbr_port_req_i.w.data[0]; // Flush write FIFO
               end
               b_chan = '{resp: axi_pkg::RESP_OKAY};
             end
             default : /* use default b_chan */;
           endcase
         end
-        sbr_rsp_o.aw_ready = 1'b1;
-        sbr_rsp_o.w_ready  = 1'b1;
+        sbr_port_rsp_o.aw_ready = 1'b1;
+        sbr_port_rsp_o.w_ready  = 1'b1;
       end // if (b_ready): Does not violate AXI spec, because the ready comes from an internal
           // spill register and does not propagate the ready from the b channel.
     end // write register
@@ -495,7 +495,7 @@ module axi_lite_mailbox_subordinate #(
     .addr_t   ( addr_t  ),
     .rule_t   ( rule_t  )
   ) i_waddr_decode (
-    .addr_i           ( sbr_req_i.aw.addr ),
+    .addr_i           ( sbr_port_req_i.aw.addr ),
     .addr_map_i       ( addr_map          ),
     .idx_o            ( w_reg_idx         ),
     .dec_valid_o      ( dec_w_valid       ),
@@ -511,9 +511,9 @@ module axi_lite_mailbox_subordinate #(
     .valid_i ( b_valid           ),
     .ready_o ( b_ready           ),
     .data_i  ( b_chan            ),
-    .valid_o ( sbr_rsp_o.b_valid ),
-    .ready_i ( sbr_req_i.b_ready ),
-    .data_o  ( sbr_rsp_o.b       )
+    .valid_o ( sbr_port_rsp_o.b_valid ),
+    .ready_i ( sbr_port_req_i.b_ready ),
+    .data_o  ( sbr_port_rsp_o.b       )
   );
   addr_decode #(
     .NoIndices( NumRegs ),
@@ -521,7 +521,7 @@ module axi_lite_mailbox_subordinate #(
     .addr_t   ( addr_t  ),
     .rule_t   ( rule_t  )
   ) i_raddr_decode (
-    .addr_i           ( sbr_req_i.ar.addr ),
+    .addr_i           ( sbr_port_req_i.ar.addr ),
     .addr_map_i       ( addr_map          ),
     .idx_o            ( r_reg_idx         ),
     .dec_valid_o      ( dec_r_valid       ),
@@ -537,17 +537,17 @@ module axi_lite_mailbox_subordinate #(
     .valid_i ( r_valid           ),
     .ready_o ( r_ready           ),
     .data_i  ( r_chan            ),
-    .valid_o ( sbr_rsp_o.r_valid ),
-    .ready_i ( sbr_req_i.r_ready ),
-    .data_o  ( sbr_rsp_o.r       )
+    .valid_o ( sbr_port_rsp_o.r_valid ),
+    .ready_i ( sbr_port_req_i.r_ready ),
+    .data_o  ( sbr_port_rsp_o.r       )
   );
   // pragma translate_off
   `ifndef VERILATOR
   initial begin : proc_check_params
-    assert (AddrWidth == $bits(sbr_req_i.aw.addr)) else $fatal(1, "AW AddrWidth mismatch");
-    assert (DataWidth == $bits(sbr_req_i.w.data))  else $fatal(1, " W DataWidth mismatch");
-    assert (AddrWidth == $bits(sbr_req_i.ar.addr)) else $fatal(1, "AR AddrWidth mismatch");
-    assert (DataWidth == $bits(sbr_rsp_o.r.data))  else $fatal(1, " R DataWidth mismatch");
+    assert (AddrWidth == $bits(sbr_port_req_i.aw.addr)) else $fatal(1, "AW AddrWidth mismatch");
+    assert (DataWidth == $bits(sbr_port_req_i.w.data))  else $fatal(1, " W DataWidth mismatch");
+    assert (AddrWidth == $bits(sbr_port_req_i.ar.addr)) else $fatal(1, "AR AddrWidth mismatch");
+    assert (DataWidth == $bits(sbr_port_rsp_o.r.data))  else $fatal(1, " R DataWidth mismatch");
   end
   `endif
   // pragma translate_on
diff --git a/src/axi_lite_mux.sv b/src/axi_lite_mux.sv
index 3f87b80c9..299d04e0d 100644
--- a/src/axi_lite_mux.sv
+++ b/src/axi_lite_mux.sv
@@ -49,8 +49,8 @@ module axi_lite_mux #(
   input  axi_lite_req_t [NumSbrPorts-1:0] sbr_reqs_i,
   output axi_lite_rsp_t [NumSbrPorts-1:0] sbr_rsps_o,
   // manager port (AXI4-Lite output), connect subordinate module here
-  output axi_lite_req_t                   mgr_req_o,
-  input  axi_lite_rsp_t                   mgr_rsp_i
+  output axi_lite_req_t                   mgr_port_req_o,
+  input  axi_lite_rsp_t                   mgr_port_rsp_i
 );
   // pass through if only one subordinate port
   if (NumSbrPorts == 32'h1) begin : gen_no_mux
@@ -63,9 +63,9 @@ module axi_lite_mux #(
       .valid_i ( sbr_reqs_i[0].aw_valid   ),
       .ready_o ( sbr_rsps_o[0].aw_ready   ),
       .data_i  ( sbr_reqs_i[0].aw         ),
-      .valid_o ( mgr_req_o.aw_valid       ),
-      .ready_i ( mgr_rsp_i.aw_ready       ),
-      .data_o  ( mgr_req_o.aw             )
+      .valid_o ( mgr_port_req_o.aw_valid       ),
+      .ready_i ( mgr_port_rsp_i.aw_ready       ),
+      .data_o  ( mgr_port_req_o.aw             )
     );
     spill_register #(
       .T       ( w_chan_t ),
@@ -76,9 +76,9 @@ module axi_lite_mux #(
       .valid_i ( sbr_reqs_i[0].w_valid   ),
       .ready_o ( sbr_rsps_o[0].w_ready   ),
       .data_i  ( sbr_reqs_i[0].w         ),
-      .valid_o ( mgr_req_o.w_valid       ),
-      .ready_i ( mgr_rsp_i.w_ready       ),
-      .data_o  ( mgr_req_o.w             )
+      .valid_o ( mgr_port_req_o.w_valid       ),
+      .ready_i ( mgr_port_rsp_i.w_ready       ),
+      .data_o  ( mgr_port_req_o.w             )
     );
     spill_register #(
       .T       ( b_chan_t ),
@@ -86,9 +86,9 @@ module axi_lite_mux #(
     ) i_b_spill_reg (
       .clk_i   ( clk_i                 ),
       .rst_ni  ( rst_ni                ),
-      .valid_i ( mgr_rsp_i.b_valid     ),
-      .ready_o ( mgr_req_o.b_ready     ),
-      .data_i  ( mgr_rsp_i.b           ),
+      .valid_i ( mgr_port_rsp_i.b_valid     ),
+      .ready_o ( mgr_port_req_o.b_ready     ),
+      .data_i  ( mgr_port_rsp_i.b           ),
       .valid_o ( sbr_rsps_o[0].b_valid ),
       .ready_i ( sbr_reqs_i[0].b_ready ),
       .data_o  ( sbr_rsps_o[0].b       )
@@ -102,9 +102,9 @@ module axi_lite_mux #(
       .valid_i ( sbr_reqs_i[0].ar_valid   ),
       .ready_o ( sbr_rsps_o[0].ar_ready   ),
       .data_i  ( sbr_reqs_i[0].ar         ),
-      .valid_o ( mgr_req_o.ar_valid       ),
-      .ready_i ( mgr_rsp_i.ar_ready       ),
-      .data_o  ( mgr_req_o.ar             )
+      .valid_o ( mgr_port_req_o.ar_valid       ),
+      .ready_i ( mgr_port_rsp_i.ar_ready       ),
+      .data_o  ( mgr_port_req_o.ar             )
     );
     spill_register #(
       .T       ( r_chan_t ),
@@ -112,9 +112,9 @@ module axi_lite_mux #(
     ) i_r_spill_reg (
       .clk_i   ( clk_i                 ),
       .rst_ni  ( rst_ni                ),
-      .valid_i ( mgr_rsp_i.r_valid     ),
-      .ready_o ( mgr_req_o.r_ready     ),
-      .data_i  ( mgr_rsp_i.r           ),
+      .valid_i ( mgr_port_rsp_i.r_valid     ),
+      .ready_o ( mgr_port_req_o.r_ready     ),
+      .data_i  ( mgr_port_rsp_i.r           ),
       .valid_o ( sbr_rsps_o[0].r_valid ),
       .ready_i ( sbr_reqs_i[0].r_ready ),
       .data_o  ( sbr_rsps_o[0].r       )
@@ -274,9 +274,9 @@ module axi_lite_mux #(
       .valid_i ( mgr_aw_valid        ),
       .ready_o ( mgr_aw_ready        ),
       .data_i  ( mgr_aw_chan         ),
-      .valid_o ( mgr_req_o.aw_valid  ),
-      .ready_i ( mgr_rsp_i.aw_ready  ),
-      .data_o  ( mgr_req_o.aw        )
+      .valid_o ( mgr_port_req_o.aw_valid  ),
+      .ready_i ( mgr_port_rsp_i.aw_ready  ),
+      .data_o  ( mgr_port_req_o.aw        )
     );
 
     //--------------------------------------
@@ -318,9 +318,9 @@ module axi_lite_mux #(
       .valid_i ( mgr_w_valid        ),
       .ready_o ( mgr_w_ready        ),
       .data_i  ( mgr_w_chan         ),
-      .valid_o ( mgr_req_o.w_valid  ),
-      .ready_i ( mgr_rsp_i.w_ready  ),
-      .data_o  ( mgr_req_o.w        )
+      .valid_o ( mgr_port_req_o.w_valid  ),
+      .ready_i ( mgr_port_rsp_i.w_ready  ),
+      .data_o  ( mgr_port_req_o.w        )
     );
 
     //--------------------------------------
@@ -340,9 +340,9 @@ module axi_lite_mux #(
     ) i_b_spill_reg (
       .clk_i   ( clk_i             ),
       .rst_ni  ( rst_ni            ),
-      .valid_i ( mgr_rsp_i.b_valid ),
-      .ready_o ( mgr_req_o.b_ready ),
-      .data_i  ( mgr_rsp_i.b       ),
+      .valid_i ( mgr_port_rsp_i.b_valid ),
+      .ready_o ( mgr_port_req_o.b_ready ),
+      .data_i  ( mgr_port_rsp_i.b       ),
       .valid_o ( mgr_b_valid       ),
       .ready_i ( mgr_b_ready       ),
       .data_o  ( mgr_b_chan        )
@@ -409,9 +409,9 @@ module axi_lite_mux #(
       .valid_i ( mgr_ar_valid        ),
       .ready_o ( mgr_ar_ready        ),
       .data_i  ( mgr_ar_chan         ),
-      .valid_o ( mgr_req_o.ar_valid  ),
-      .ready_i ( mgr_rsp_i.ar_ready  ),
-      .data_o  ( mgr_req_o.ar        )
+      .valid_o ( mgr_port_req_o.ar_valid  ),
+      .ready_i ( mgr_port_rsp_i.ar_ready  ),
+      .data_o  ( mgr_port_req_o.ar        )
     );
 
     //--------------------------------------
@@ -431,9 +431,9 @@ module axi_lite_mux #(
     ) i_r_spill_reg (
       .clk_i   ( clk_i             ),
       .rst_ni  ( rst_ni            ),
-      .valid_i ( mgr_rsp_i.r_valid ),
-      .ready_o ( mgr_req_o.r_ready ),
-      .data_i  ( mgr_rsp_i.r       ),
+      .valid_i ( mgr_port_rsp_i.r_valid ),
+      .ready_o ( mgr_port_req_o.r_ready ),
+      .data_i  ( mgr_port_rsp_i.r       ),
       .valid_o ( mgr_r_valid       ),
       .ready_i ( mgr_r_ready       ),
       .data_o  ( mgr_r_chan        )
@@ -524,8 +524,8 @@ module axi_lite_mux_intf #(
     .test_i, // Test Mode enable
     .sbr_reqs_i ( sbr_reqs ),
     .sbr_rsps_o ( sbr_rsps ),
-    .mgr_req_o  ( mgr_req  ),
-    .mgr_rsp_i  ( mgr_rsp  )
+    .mgr_port_req_o  ( mgr_req  ),
+    .mgr_port_rsp_i  ( mgr_rsp  )
   );
 
   // pragma translate_off
diff --git a/src/axi_lite_to_axi.sv b/src/axi_lite_to_axi.sv
index f7061efcc..ccfaaf487 100644
--- a/src/axi_lite_to_axi.sv
+++ b/src/axi_lite_to_axi.sv
@@ -30,13 +30,13 @@ module axi_lite_to_axi #(
   input  axi_pkg::cache_t sbr_aw_cache_i,
   input  axi_pkg::cache_t sbr_ar_cache_i,
   // Manager AXI port
-  output axi_req_t        mgr_req_o,
-  input  axi_rsp_t        mgr_rsp_i
+  output axi_req_t        mgr_port_req_o,
+  input  axi_rsp_t        mgr_port_rsp_i
 );
   localparam int unsigned Size = axi_pkg::size_t'($unsigned($clog2(DataWidth/8)));
 
   // request assign
-  assign mgr_req_o = '{
+  assign mgr_port_req_o = '{
     aw: '{
       addr:  sbr_req_lite_i.aw.addr,
       prot:  sbr_req_lite_i.aw.prot,
@@ -68,20 +68,20 @@ module axi_lite_to_axi #(
   };
   // response assign
   assign sbr_rsp_lite_o = '{
-    aw_ready: mgr_rsp_i.aw_ready,
-    w_ready:  mgr_rsp_i.w_ready,
+    aw_ready: mgr_port_rsp_i.aw_ready,
+    w_ready:  mgr_port_rsp_i.w_ready,
     b: '{
-      resp: mgr_rsp_i.b.resp,
+      resp: mgr_port_rsp_i.b.resp,
       default: '0
     },
-    b_valid:  mgr_rsp_i.b_valid,
-    ar_ready: mgr_rsp_i.ar_ready,
+    b_valid:  mgr_port_rsp_i.b_valid,
+    ar_ready: mgr_port_rsp_i.ar_ready,
     r: '{
-      data: mgr_rsp_i.r.data,
-      resp: mgr_rsp_i.r.resp,
+      data: mgr_port_rsp_i.r.data,
+      resp: mgr_port_rsp_i.r.resp,
       default: '0
     },
-    r_valid: mgr_rsp_i.r_valid,
+    r_valid: mgr_port_rsp_i.r_valid,
     default: '0
   };
 
diff --git a/src/axi_lite_xbar.sv b/src/axi_lite_xbar.sv
index b53f89674..08780423a 100644
--- a/src/axi_lite_xbar.sv
+++ b/src/axi_lite_xbar.sv
@@ -157,10 +157,10 @@ module axi_lite_xbar #(
       .clk_i,   // Clock
       .rst_ni,  // Asynchronous reset active low
       .test_i,  // Testmode enable
-      .sbr_req_i       ( sbr_ports_req_i[i] ),
+      .sbr_port_req_i       ( sbr_ports_req_i[i] ),
       .sbr_aw_select_i ( sbr_aw_select      ),
       .sbr_ar_select_i ( sbr_ar_select      ),
-      .sbr_rsp_o       ( sbr_ports_rsp_o[i] ),
+      .sbr_port_rsp_o       ( sbr_ports_rsp_o[i] ),
       .mgr_reqs_o      ( sbr_reqs[i]        ),
       .mgr_rsps_i      ( sbr_rsps[i]        )
     );
@@ -178,8 +178,8 @@ module axi_lite_xbar #(
       .sbr_rsp_lite_o ( sbr_rsps[i][Cfg.NumMgrPorts] ),
       .sbr_aw_cache_i ( 4'd0                         ),
       .sbr_ar_cache_i ( 4'd0                         ),
-      .mgr_req_o      ( decerr_req                   ),
-      .mgr_rsp_i      ( decerr_rsp                   )
+      .mgr_port_req_o      ( decerr_req                   ),
+      .mgr_port_rsp_i      ( decerr_rsp                   )
     );
 
     axi_err_sbr #(
@@ -195,8 +195,8 @@ module axi_lite_xbar #(
       .rst_ni    ( rst_ni     ),  // Asynchronous reset active low
       .test_i    ( test_i     ),  // Testmode enable
       // subordinate port
-      .sbr_req_i ( decerr_req ),
-      .sbr_rsp_o ( decerr_rsp )
+      .sbr_port_req_i ( decerr_req ),
+      .sbr_port_rsp_o ( decerr_rsp )
     );
   end
 
@@ -231,8 +231,8 @@ module axi_lite_xbar #(
       .test_i, // Test Mode enable
       .sbr_reqs_i ( mgr_reqs[i]        ),
       .sbr_rsps_o ( mgr_rsps[i]        ),
-      .mgr_req_o  ( mgr_ports_req_o[i] ),
-      .mgr_rsp_i  ( mgr_ports_rsp_i[i] )
+      .mgr_port_req_o  ( mgr_ports_req_o[i] ),
+      .mgr_port_rsp_i  ( mgr_ports_rsp_i[i] )
     );
   end
 endmodule
diff --git a/src/axi_modify_address.sv b/src/axi_modify_address.sv
index ac6c1cba3..6b0ce4e8a 100644
--- a/src/axi_modify_address.sv
+++ b/src/axi_modify_address.sv
@@ -26,59 +26,59 @@ module axi_modify_address #(
   parameter type axi_rsp_t = logic
 ) (
   /// Subordinate port request
-  input  sbr_port_axi_req_t  sbr_req_i,
+  input  sbr_port_axi_req_t  sbr_port_req_i,
   /// Subordinate port response
-  output axi_rsp_t sbr_rsp_o,
+  output axi_rsp_t sbr_port_rsp_o,
   /// AW address on manager port; must remain stable while an AW handshake is pending.
   input  mgr_addr_t mgr_aw_addr_i,
   /// AR address on manager port; must remain stable while an AR handshake is pending.
   input  mgr_addr_t mgr_ar_addr_i,
   /// Manager port request
-  output mgr_port_axi_req_t  mgr_req_o,
+  output mgr_port_axi_req_t  mgr_port_req_o,
   /// Manager port response
-  input  axi_rsp_t mgr_rsp_i
+  input  axi_rsp_t mgr_port_rsp_i
 );
 
-  assign mgr_req_o = '{
+  assign mgr_port_req_o = '{
     aw: '{
-      id:     sbr_req_i.aw.id,
+      id:     sbr_port_req_i.aw.id,
       addr:   mgr_aw_addr_i,
-      len:    sbr_req_i.aw.len,
-      size:   sbr_req_i.aw.size,
-      burst:  sbr_req_i.aw.burst,
-      lock:   sbr_req_i.aw.lock,
-      cache:  sbr_req_i.aw.cache,
-      prot:   sbr_req_i.aw.prot,
-      qos:    sbr_req_i.aw.qos,
-      region: sbr_req_i.aw.region,
-      atop:   sbr_req_i.aw.atop,
-      user:   sbr_req_i.aw.user,
+      len:    sbr_port_req_i.aw.len,
+      size:   sbr_port_req_i.aw.size,
+      burst:  sbr_port_req_i.aw.burst,
+      lock:   sbr_port_req_i.aw.lock,
+      cache:  sbr_port_req_i.aw.cache,
+      prot:   sbr_port_req_i.aw.prot,
+      qos:    sbr_port_req_i.aw.qos,
+      region: sbr_port_req_i.aw.region,
+      atop:   sbr_port_req_i.aw.atop,
+      user:   sbr_port_req_i.aw.user,
       default: '0
     },
-    aw_valid: sbr_req_i.aw_valid,
-    w:        sbr_req_i.w,
-    w_valid:  sbr_req_i.w_valid,
-    b_ready:  sbr_req_i.b_ready,
+    aw_valid: sbr_port_req_i.aw_valid,
+    w:        sbr_port_req_i.w,
+    w_valid:  sbr_port_req_i.w_valid,
+    b_ready:  sbr_port_req_i.b_ready,
     ar: '{
-      id:     sbr_req_i.ar.id,
+      id:     sbr_port_req_i.ar.id,
       addr:   mgr_ar_addr_i,
-      len:    sbr_req_i.ar.len,
-      size:   sbr_req_i.ar.size,
-      burst:  sbr_req_i.ar.burst,
-      lock:   sbr_req_i.ar.lock,
-      cache:  sbr_req_i.ar.cache,
-      prot:   sbr_req_i.ar.prot,
-      qos:    sbr_req_i.ar.qos,
-      region: sbr_req_i.ar.region,
-      user:   sbr_req_i.ar.user,
+      len:    sbr_port_req_i.ar.len,
+      size:   sbr_port_req_i.ar.size,
+      burst:  sbr_port_req_i.ar.burst,
+      lock:   sbr_port_req_i.ar.lock,
+      cache:  sbr_port_req_i.ar.cache,
+      prot:   sbr_port_req_i.ar.prot,
+      qos:    sbr_port_req_i.ar.qos,
+      region: sbr_port_req_i.ar.region,
+      user:   sbr_port_req_i.ar.user,
       default: '0
     },
-    ar_valid: sbr_req_i.ar_valid,
-    r_ready:  sbr_req_i.r_ready,
+    ar_valid: sbr_port_req_i.ar_valid,
+    r_ready:  sbr_port_req_i.r_ready,
     default: '0
   };
 
-  assign sbr_rsp_o = mgr_rsp_i;
+  assign sbr_port_rsp_o = mgr_port_rsp_i;
 endmodule
 
 
@@ -143,10 +143,10 @@ module axi_modify_address_intf #(
     .mgr_port_axi_req_t ( mgr_port_axi_req_t ),
     .axi_rsp_t          ( axi_rsp_t          )
   ) i_axi_modify_address (
-    .sbr_req_i    ( sbr_req ),
-    .sbr_rsp_o    ( sbr_rsp ),
-    .mgr_req_o    ( mgr_req ),
-    .mgr_rsp_i    ( mgr_rsp ),
+    .sbr_port_req_i    ( sbr_req ),
+    .sbr_port_rsp_o    ( sbr_rsp ),
+    .mgr_port_req_o    ( mgr_req ),
+    .mgr_port_rsp_i    ( mgr_rsp ),
     .mgr_aw_addr_i,
     .mgr_ar_addr_i
   );
diff --git a/src/axi_multicut.sv b/src/axi_multicut.sv
index e6f6cec9c..962b0628e 100644
--- a/src/axi_multicut.sv
+++ b/src/axi_multicut.sv
@@ -33,25 +33,25 @@ module axi_multicut #(
   input  logic     clk_i,   // Clock
   input  logic     rst_ni,  // Asynchronous reset active low
   // subordinate port
-  input  axi_req_t sbr_req_i,
-  output axi_rsp_t sbr_rsp_o,
+  input  axi_req_t sbr_port_req_i,
+  output axi_rsp_t sbr_port_rsp_o,
   // manager port
-  output axi_req_t mgr_req_o,
-  input  axi_rsp_t mgr_rsp_i
+  output axi_req_t mgr_port_req_o,
+  input  axi_rsp_t mgr_port_rsp_i
 );
 
   if (NumCuts == '0) begin : gen_no_cut
     // degenerate case, connect input to output
-    assign mgr_req_o = sbr_req_i;
-    assign sbr_rsp_o = mgr_rsp_i;
+    assign mgr_port_req_o = sbr_port_req_i;
+    assign sbr_port_rsp_o = mgr_port_rsp_i;
   end else begin : gen_axi_cut
     // instantiate all needed cuts
     axi_req_t [NumCuts:0] cut_req;
     axi_rsp_t [NumCuts:0] cut_rsp;
 
     // connect subordinate to the lowest index
-    assign cut_req[0] = sbr_req_i;
-    assign sbr_rsp_o  = cut_rsp[0];
+    assign cut_req[0] = sbr_port_req_i;
+    assign sbr_port_rsp_o  = cut_rsp[0];
 
     // AXI cuts
     for (genvar i = 0; i < NumCuts; i++) begin : gen_axi_cuts
@@ -67,16 +67,16 @@ module axi_multicut #(
       ) i_cut (
         .clk_i,
         .rst_ni,
-        .sbr_req_i ( cut_req[i]   ),
-        .sbr_rsp_o ( cut_rsp[i]   ),
-        .mgr_req_o ( cut_req[i+1] ),
-        .mgr_rsp_i ( cut_rsp[i+1] )
+        .sbr_port_req_i ( cut_req[i]   ),
+        .sbr_port_rsp_o ( cut_rsp[i]   ),
+        .mgr_port_req_o ( cut_req[i+1] ),
+        .mgr_port_rsp_i ( cut_rsp[i+1] )
       );
     end
 
     // connect manager to the highest index
-    assign mgr_req_o        = cut_req[NumCuts];
-    assign cut_rsp[NumCuts] = mgr_rsp_i;
+    assign mgr_port_req_o        = cut_req[NumCuts];
+    assign cut_rsp[NumCuts] = mgr_port_rsp_i;
   end
 
   // Check the invariants
@@ -141,10 +141,10 @@ module axi_multicut_intf #(
   ) i_axi_multicut (
     .clk_i,
     .rst_ni,
-    .sbr_req_i ( sbr_req ),
-    .sbr_rsp_o ( sbr_rsp ),
-    .mgr_req_o ( mgr_req ),
-    .mgr_rsp_i ( mgr_rsp )
+    .sbr_port_req_i ( sbr_req ),
+    .sbr_port_rsp_o ( sbr_rsp ),
+    .mgr_port_req_o ( mgr_req ),
+    .mgr_port_rsp_i ( mgr_rsp )
   );
 
   // Check the invariants.
@@ -215,10 +215,10 @@ module axi_lite_multicut_intf #(
   ) i_axi_multicut (
     .clk_i,
     .rst_ni,
-    .sbr_req_i ( sbr_req ),
-    .sbr_rsp_o ( sbr_rsp ),
-    .mgr_req_o ( mgr_req ),
-    .mgr_rsp_i ( mgr_rsp )
+    .sbr_port_req_i ( sbr_req ),
+    .sbr_port_rsp_o ( sbr_rsp ),
+    .mgr_port_req_o ( mgr_req ),
+    .mgr_port_rsp_i ( mgr_rsp )
   );
 
   // Check the invariants.
diff --git a/src/axi_mux.sv b/src/axi_mux.sv
index 843fa28c1..bca47ce5e 100644
--- a/src/axi_mux.sv
+++ b/src/axi_mux.sv
@@ -61,8 +61,8 @@ module axi_mux #(
   input  sbr_port_axi_req_t [NumSbrPorts-1:0] sbr_reqs_i,
   output sbr_port_axi_rsp_t [NumSbrPorts-1:0] sbr_rsps_o,
   // manager port (AXI outputs), connect subordinate modules here
-  output mgr_port_axi_req_t                   mgr_req_o,
-  input  mgr_port_axi_rsp_t                   mgr_rsp_i
+  output mgr_port_axi_req_t                   mgr_port_req_o,
+  input  mgr_port_axi_rsp_t                   mgr_port_rsp_i
 );
 
   localparam int unsigned MgrIdxBits = $clog2(NumSbrPorts);
@@ -79,9 +79,9 @@ module axi_mux #(
       .valid_i ( sbr_reqs_i[0].aw_valid   ),
       .ready_o ( sbr_rsps_o[0].aw_ready   ),
       .data_i  ( sbr_reqs_i[0].aw         ),
-      .valid_o ( mgr_req_o.aw_valid       ),
-      .ready_i ( mgr_rsp_i.aw_ready       ),
-      .data_o  ( mgr_req_o.aw             )
+      .valid_o ( mgr_port_req_o.aw_valid       ),
+      .ready_i ( mgr_port_rsp_i.aw_ready       ),
+      .data_o  ( mgr_port_req_o.aw             )
     );
     spill_register #(
       .T       ( w_chan_t ),
@@ -92,9 +92,9 @@ module axi_mux #(
       .valid_i ( sbr_reqs_i[0].w_valid   ),
       .ready_o ( sbr_rsps_o[0].w_ready   ),
       .data_i  ( sbr_reqs_i[0].w         ),
-      .valid_o ( mgr_req_o.w_valid       ),
-      .ready_i ( mgr_rsp_i.w_ready       ),
-      .data_o  ( mgr_req_o.w             )
+      .valid_o ( mgr_port_req_o.w_valid       ),
+      .ready_i ( mgr_port_rsp_i.w_ready       ),
+      .data_o  ( mgr_port_req_o.w             )
     );
     spill_register #(
       .T       ( mgr_b_chan_t ),
@@ -102,9 +102,9 @@ module axi_mux #(
     ) i_b_spill_reg (
       .clk_i   ( clk_i                  ),
       .rst_ni  ( rst_ni                 ),
-      .valid_i ( mgr_rsp_i.b_valid      ),
-      .ready_o ( mgr_req_o.b_ready      ),
-      .data_i  ( mgr_rsp_i.b            ),
+      .valid_i ( mgr_port_rsp_i.b_valid      ),
+      .ready_o ( mgr_port_req_o.b_ready      ),
+      .data_i  ( mgr_port_rsp_i.b            ),
       .valid_o ( sbr_rsps_o[0].b_valid  ),
       .ready_i ( sbr_reqs_i[0].b_ready  ),
       .data_o  ( sbr_rsps_o[0].b        )
@@ -118,9 +118,9 @@ module axi_mux #(
       .valid_i ( sbr_reqs_i[0].ar_valid   ),
       .ready_o ( sbr_rsps_o[0].ar_ready   ),
       .data_i  ( sbr_reqs_i[0].ar         ),
-      .valid_o ( mgr_req_o.ar_valid       ),
-      .ready_i ( mgr_rsp_i.ar_ready       ),
-      .data_o  ( mgr_req_o.ar             )
+      .valid_o ( mgr_port_req_o.ar_valid       ),
+      .ready_i ( mgr_port_rsp_i.ar_ready       ),
+      .data_o  ( mgr_port_req_o.ar             )
     );
     spill_register #(
       .T       ( mgr_r_chan_t ),
@@ -128,9 +128,9 @@ module axi_mux #(
     ) i_r_spill_reg (
       .clk_i   ( clk_i                  ),
       .rst_ni  ( rst_ni                 ),
-      .valid_i ( mgr_rsp_i.r_valid      ),
-      .ready_o ( mgr_req_o.r_ready      ),
-      .data_i  ( mgr_rsp_i.r            ),
+      .valid_i ( mgr_port_rsp_i.r_valid      ),
+      .ready_o ( mgr_port_req_o.r_ready      ),
+      .data_i  ( mgr_port_rsp_i.r            ),
       .valid_o ( sbr_rsps_o[0].r_valid  ),
       .ready_i ( sbr_reqs_i[0].r_ready  ),
       .data_o  ( sbr_rsps_o[0].r        )
@@ -141,10 +141,10 @@ module axi_mux #(
     `ASSERT_INIT(CorrectIdWidthSbrB, $bits(sbr_rsps_o[0].b.id) == SbrIDWidth)
     `ASSERT_INIT(CorrectIdWidthSbrAr, $bits(sbr_reqs_i[0].ar.id) == SbrIDWidth)
     `ASSERT_INIT(CorrectIdWidthSbrR, $bits(sbr_rsps_o[0].r.id) == SbrIDWidth)
-    `ASSERT_INIT(CorrectIdWidthMgrAw, $bits(mgr_req_o.aw.id) == SbrIDWidth)
-    `ASSERT_INIT(CorrectIdWidthMgrB, $bits(mgr_rsp_i.b.id) == SbrIDWidth)
-    `ASSERT_INIT(CorrectIdWidthMgrAr, $bits(mgr_req_o.ar.id) == SbrIDWidth)
-    `ASSERT_INIT(CorrectIdWidthMgrR, $bits(mgr_rsp_i.r.id) == SbrIDWidth)
+    `ASSERT_INIT(CorrectIdWidthMgrAw, $bits(mgr_port_req_o.aw.id) == SbrIDWidth)
+    `ASSERT_INIT(CorrectIdWidthMgrB, $bits(mgr_port_rsp_i.b.id) == SbrIDWidth)
+    `ASSERT_INIT(CorrectIdWidthMgrAr, $bits(mgr_port_req_o.ar.id) == SbrIDWidth)
+    `ASSERT_INIT(CorrectIdWidthMgrR, $bits(mgr_port_rsp_i.r.id) == SbrIDWidth)
 // pragma translate_on
 
   // other non degenerate cases
@@ -341,9 +341,9 @@ module axi_mux #(
       .valid_i ( mgr_aw_valid        ),
       .ready_o ( mgr_aw_ready        ),
       .data_i  ( mgr_aw_chan         ),
-      .valid_o ( mgr_req_o.aw_valid  ),
-      .ready_i ( mgr_rsp_i.aw_ready ),
-      .data_o  ( mgr_req_o.aw        )
+      .valid_o ( mgr_port_req_o.aw_valid  ),
+      .ready_i ( mgr_port_rsp_i.aw_ready ),
+      .data_o  ( mgr_port_req_o.aw        )
     );
 
     //--------------------------------------
@@ -375,9 +375,9 @@ module axi_mux #(
       .valid_i ( mgr_w_valid        ),
       .ready_o ( mgr_w_ready        ),
       .data_i  ( mgr_w_chan         ),
-      .valid_o ( mgr_req_o.w_valid  ),
-      .ready_i ( mgr_rsp_i.w_ready  ),
-      .data_o  ( mgr_req_o.w        )
+      .valid_o ( mgr_port_req_o.w_valid  ),
+      .ready_i ( mgr_port_rsp_i.w_ready  ),
+      .data_o  ( mgr_port_req_o.w        )
     );
 
     //--------------------------------------
@@ -395,9 +395,9 @@ module axi_mux #(
     ) i_b_spill_reg (
       .clk_i   ( clk_i                      ),
       .rst_ni  ( rst_ni                     ),
-      .valid_i ( mgr_rsp_i.b_valid          ),
-      .ready_o ( mgr_req_o.b_ready          ),
-      .data_i  ( mgr_rsp_i.b                ),
+      .valid_i ( mgr_port_rsp_i.b_valid          ),
+      .ready_o ( mgr_port_req_o.b_ready          ),
+      .data_i  ( mgr_port_rsp_i.b                ),
       .valid_o ( mgr_b_valid                ),
       .ready_i ( sbr_b_readies[switch_b_id] ),
       .data_o  ( mgr_b_chan                 )
@@ -434,9 +434,9 @@ module axi_mux #(
       .valid_i ( ar_valid            ),
       .ready_o ( ar_ready            ),
       .data_i  ( mgr_ar_chan         ),
-      .valid_o ( mgr_req_o.ar_valid  ),
-      .ready_i ( mgr_rsp_i.ar_ready  ),
-      .data_o  ( mgr_req_o.ar        )
+      .valid_o ( mgr_port_req_o.ar_valid  ),
+      .ready_i ( mgr_port_rsp_i.ar_ready  ),
+      .data_o  ( mgr_port_req_o.ar        )
     );
 
     //--------------------------------------
@@ -454,9 +454,9 @@ module axi_mux #(
     ) i_r_spill_reg (
       .clk_i   ( clk_i                      ),
       .rst_ni  ( rst_ni                     ),
-      .valid_i ( mgr_rsp_i.r_valid          ),
-      .ready_o ( mgr_req_o.r_ready          ),
-      .data_i  ( mgr_rsp_i.r                ),
+      .valid_i ( mgr_port_rsp_i.r_valid          ),
+      .ready_o ( mgr_port_req_o.r_ready          ),
+      .data_i  ( mgr_port_rsp_i.r                ),
       .valid_o ( mgr_r_valid                ),
       .ready_i ( sbr_r_readies[switch_r_id] ),
       .data_o  ( mgr_r_chan                 )
@@ -481,13 +481,13 @@ module axi_mux #(
       else $fatal(1, "ID width of B channel of subordinate ports does not match parameter!");
     assert ($unsigned($bits(sbr_rsps_o[0].r.id)) == SbrIDWidth)
       else $fatal(1, "ID width of R channel of subordinate ports does not match parameter!");
-    assert ($unsigned($bits(mgr_req_o.aw.id)) == MgrIDWidth)
+    assert ($unsigned($bits(mgr_port_req_o.aw.id)) == MgrIDWidth)
       else $fatal(1, "ID width of AW channel of manager port is wrong!");
-    assert ($unsigned($bits(mgr_req_o.ar.id)) == MgrIDWidth)
+    assert ($unsigned($bits(mgr_port_req_o.ar.id)) == MgrIDWidth)
       else $fatal(1, "ID width of AR channel of manager port is wrong!");
-    assert ($unsigned($bits(mgr_rsp_i.b.id)) == MgrIDWidth)
+    assert ($unsigned($bits(mgr_port_rsp_i.b.id)) == MgrIDWidth)
       else $fatal(1, "ID width of B channel of manager port is wrong!");
-    assert ($unsigned($bits(mgr_rsp_i.r.id)) == MgrIDWidth)
+    assert ($unsigned($bits(mgr_port_rsp_i.r.id)) == MgrIDWidth)
       else $fatal(1, "ID width of R channel of manager port is wrong!");
   end
 `endif
@@ -592,7 +592,7 @@ module axi_mux_intf #(
     .test_i     ( test_i   ), // Test Mode enable
     .sbr_reqs_i ( sbr_reqs ),
     .sbr_rsps_o ( sbr_rsps ),
-    .mgr_req_o  ( mgr_req  ),
-    .mgr_rsp_i  ( mgr_rsp  )
+    .mgr_port_req_o  ( mgr_req  ),
+    .mgr_port_rsp_i  ( mgr_rsp  )
   );
 endmodule
diff --git a/src/axi_rw_join.sv b/src/axi_rw_join.sv
index 0370171b4..53c18ca89 100644
--- a/src/axi_rw_join.sv
+++ b/src/axi_rw_join.sv
@@ -34,8 +34,8 @@ module axi_rw_join #(
   output axi_rsp_t sbr_write_rsp_o,
 
   // Read / Write Manager
-  output axi_req_t mgr_req_o,
-  input  axi_rsp_t mgr_rsp_i
+  output axi_req_t mgr_port_req_o,
+  input  axi_rsp_t mgr_port_rsp_i
 );
 
   //--------------------------------------
@@ -43,8 +43,8 @@ module axi_rw_join #(
   //--------------------------------------
 
   // Assign Read Structs
-  `AXI_ASSIGN_AR_STRUCT ( mgr_req_o.ar      , sbr_read_req_i.ar  )
-  `AXI_ASSIGN_R_STRUCT  ( sbr_read_rsp_o.r  , mgr_rsp_i.r        )
+  `AXI_ASSIGN_AR_STRUCT ( mgr_port_req_o.ar      , sbr_read_req_i.ar  )
+  `AXI_ASSIGN_R_STRUCT  ( sbr_read_rsp_o.r  , mgr_port_rsp_i.r        )
 
   // Read B channel data
   assign sbr_read_rsp_o.b         = '0;
@@ -55,12 +55,12 @@ module axi_rw_join #(
   //--------------------------------------
 
   // Read AR channel handshake
-  assign mgr_req_o.ar_valid       = sbr_read_req_i.ar_valid;
-  assign sbr_read_rsp_o.ar_ready  = mgr_rsp_i.ar_ready;
+  assign mgr_port_req_o.ar_valid       = sbr_read_req_i.ar_valid;
+  assign sbr_read_rsp_o.ar_ready  = mgr_port_rsp_i.ar_ready;
 
   // Read R channel handshake
-  assign sbr_read_rsp_o.r_valid   = mgr_rsp_i.r_valid;
-  assign mgr_req_o.r_ready        = sbr_read_req_i.r_ready;
+  assign sbr_read_rsp_o.r_valid   = mgr_port_rsp_i.r_valid;
+  assign mgr_port_req_o.r_ready        = sbr_read_req_i.r_ready;
 
   // Read AW, W and B handshake
   assign sbr_read_rsp_o.aw_ready  = 1'b0;
@@ -76,9 +76,9 @@ module axi_rw_join #(
   //--------------------------------------
 
   // Assign Write Structs
-  `AXI_ASSIGN_AW_STRUCT ( mgr_req_o.aw      , sbr_write_req_i.aw )
-  `AXI_ASSIGN_W_STRUCT  ( mgr_req_o.w       , sbr_write_req_i.w  )
-  `AXI_ASSIGN_B_STRUCT  ( sbr_write_rsp_o.b , mgr_rsp_i.b        )
+  `AXI_ASSIGN_AW_STRUCT ( mgr_port_req_o.aw      , sbr_write_req_i.aw )
+  `AXI_ASSIGN_W_STRUCT  ( mgr_port_req_o.w       , sbr_write_req_i.w  )
+  `AXI_ASSIGN_B_STRUCT  ( sbr_write_rsp_o.b , mgr_port_rsp_i.b        )
 
   // Write R channel data
   assign sbr_write_rsp_o.r        = '0;
@@ -96,15 +96,15 @@ module axi_rw_join #(
   `ASSERT_NEVER(sbr_write_req_ar_valid, sbr_write_req_i.ar_valid, clk_i, !rst_ni)
 
   // Write AW channel handshake
-  assign mgr_req_o.aw_valid       = sbr_write_req_i.aw_valid;
-  assign sbr_write_rsp_o.aw_ready = mgr_rsp_i.aw_ready;
+  assign mgr_port_req_o.aw_valid       = sbr_write_req_i.aw_valid;
+  assign sbr_write_rsp_o.aw_ready = mgr_port_rsp_i.aw_ready;
 
   // Write W channel handshake
-  assign mgr_req_o.w_valid        = sbr_write_req_i.w_valid;
-  assign sbr_write_rsp_o.w_ready  = mgr_rsp_i.w_ready;
+  assign mgr_port_req_o.w_valid        = sbr_write_req_i.w_valid;
+  assign sbr_write_rsp_o.w_ready  = mgr_port_rsp_i.w_ready;
 
   // Write B channel handshake
-  assign sbr_write_rsp_o.b_valid  = mgr_rsp_i.b_valid;
-  assign mgr_req_o.b_ready        = sbr_write_req_i.b_ready;
+  assign sbr_write_rsp_o.b_valid  = mgr_port_rsp_i.b_valid;
+  assign mgr_port_req_o.b_ready        = sbr_write_req_i.b_ready;
 
 endmodule : axi_rw_join
diff --git a/src/axi_rw_split.sv b/src/axi_rw_split.sv
index 7d15ae616..1f7e735e7 100644
--- a/src/axi_rw_split.sv
+++ b/src/axi_rw_split.sv
@@ -26,8 +26,8 @@ module axi_rw_split #(
   input  logic      clk_i,
   input  logic      rst_ni,
   // Read / Write Subordinate
-  input  axi_req_t sbr_req_i,
-  output axi_rsp_t sbr_rsp_o,
+  input  axi_req_t sbr_port_req_i,
+  output axi_rsp_t sbr_port_rsp_o,
 
   // Read Manager
   output axi_req_t mgr_read_req_o,
@@ -43,8 +43,8 @@ module axi_rw_split #(
   //--------------------------------------
 
   // Assign Read channel structs
-  `AXI_ASSIGN_AR_STRUCT ( mgr_read_req_o.ar  , sbr_req_i.ar      )
-  `AXI_ASSIGN_R_STRUCT  ( sbr_rsp_o.r        , mgr_read_rsp_i.r  )
+  `AXI_ASSIGN_AR_STRUCT ( mgr_read_req_o.ar  , sbr_port_req_i.ar      )
+  `AXI_ASSIGN_R_STRUCT  ( sbr_port_rsp_o.r        , mgr_read_rsp_i.r  )
 
   // Read AW and W channel data
   assign mgr_read_req_o.aw        = '0;
@@ -56,12 +56,12 @@ module axi_rw_split #(
   //--------------------------------------
 
   // Read AR channel handshake
-  assign mgr_read_req_o.ar_valid  = sbr_req_i.ar_valid;
-  assign sbr_rsp_o.ar_ready       = mgr_read_rsp_i.ar_ready;
+  assign mgr_read_req_o.ar_valid  = sbr_port_req_i.ar_valid;
+  assign sbr_port_rsp_o.ar_ready       = mgr_read_rsp_i.ar_ready;
 
   // Read R channel handshake
-  assign sbr_rsp_o.r_valid        = mgr_read_rsp_i.r_valid;
-  assign mgr_read_req_o.r_ready   = sbr_req_i.r_ready;
+  assign sbr_port_rsp_o.r_valid        = mgr_read_rsp_i.r_valid;
+  assign mgr_read_req_o.r_ready   = sbr_port_req_i.r_ready;
 
   // Read AW, W and B handshake
   assign mgr_read_req_o.aw_valid  = 1'b0;
@@ -77,9 +77,9 @@ module axi_rw_split #(
   //--------------------------------------
 
   // Assign Write channel structs
-  `AXI_ASSIGN_AW_STRUCT ( mgr_write_req_o.aw , sbr_req_i.aw      )
-  `AXI_ASSIGN_W_STRUCT  ( mgr_write_req_o.w  , sbr_req_i.w       )
-  `AXI_ASSIGN_B_STRUCT  ( sbr_rsp_o.b        , mgr_write_rsp_i.b )
+  `AXI_ASSIGN_AW_STRUCT ( mgr_write_req_o.aw , sbr_port_req_i.aw      )
+  `AXI_ASSIGN_W_STRUCT  ( mgr_write_req_o.w  , sbr_port_req_i.w       )
+  `AXI_ASSIGN_B_STRUCT  ( sbr_port_rsp_o.b        , mgr_write_rsp_i.b )
 
   // Write AR channel data
   assign mgr_write_req_o.ar       = '0;
@@ -97,15 +97,15 @@ module axi_rw_split #(
   `ASSERT_NEVER(mgr_read_rsp_r_valid, mgr_read_rsp_i.r_valid, clk_i, !rst_ni)
 
   // Write AW channel handshake
-  assign mgr_write_req_o.aw_valid = sbr_req_i.aw_valid;
-  assign sbr_rsp_o.aw_ready       = mgr_write_rsp_i.aw_ready;
+  assign mgr_write_req_o.aw_valid = sbr_port_req_i.aw_valid;
+  assign sbr_port_rsp_o.aw_ready       = mgr_write_rsp_i.aw_ready;
 
   // Write W channel handshake
-  assign mgr_write_req_o.w_valid  = sbr_req_i.w_valid;
-  assign sbr_rsp_o.w_ready        = mgr_write_rsp_i.w_ready;
+  assign mgr_write_req_o.w_valid  = sbr_port_req_i.w_valid;
+  assign sbr_port_rsp_o.w_ready        = mgr_write_rsp_i.w_ready;
 
   // Write B channel handshake
-  assign sbr_rsp_o.b_valid        = mgr_write_rsp_i.b_valid;
-  assign mgr_write_req_o.b_ready  = sbr_req_i.b_ready;
+  assign sbr_port_rsp_o.b_valid        = mgr_write_rsp_i.b_valid;
+  assign mgr_write_req_o.b_ready  = sbr_port_req_i.b_ready;
 
 endmodule : axi_rw_split
diff --git a/src/axi_serializer.sv b/src/axi_serializer.sv
index a3ce5edcd..5b0647a19 100644
--- a/src/axi_serializer.sv
+++ b/src/axi_serializer.sv
@@ -36,13 +36,13 @@ module axi_serializer #(
   /// Asynchronous reset, active low
   input  logic     rst_ni,
   /// Subordinate port request
-  input  axi_req_t sbr_req_i,
+  input  axi_req_t sbr_port_req_i,
   /// Subordinate port response
-  output axi_rsp_t sbr_rsp_o,
+  output axi_rsp_t sbr_port_rsp_o,
   /// Manager port request
-  output axi_req_t mgr_req_o,
+  output axi_req_t mgr_port_req_o,
   /// Manager port response
-  input  axi_rsp_t mgr_rsp_i
+  input  axi_rsp_t mgr_port_rsp_i
 );
 
   typedef logic [IdWidth-1:0] id_t;
@@ -65,23 +65,23 @@ module axi_serializer #(
     wr_fifo_push = 1'b0;
 
     // Default, connect the channels
-    mgr_req_o = sbr_req_i;
-    sbr_rsp_o = mgr_rsp_i;
+    mgr_port_req_o = sbr_port_req_i;
+    sbr_port_rsp_o = mgr_port_rsp_i;
 
     // Serialize transactions -> tie downstream IDs to zero.
-    mgr_req_o.aw.id = '0;
-    mgr_req_o.ar.id = '0;
+    mgr_port_req_o.aw.id = '0;
+    mgr_port_req_o.ar.id = '0;
 
     // Reflect upstream ID in response.
-    ar_id          = sbr_req_i.ar.id;
-    sbr_rsp_o.b.id = b_id;
-    sbr_rsp_o.r.id = r_id;
+    ar_id          = sbr_port_req_i.ar.id;
+    sbr_port_rsp_o.b.id = b_id;
+    sbr_port_rsp_o.r.id = r_id;
 
     // Default, cut the AW/AR handshaking
-    mgr_req_o.ar_valid = 1'b0;
-    sbr_rsp_o.ar_ready = 1'b0;
-    mgr_req_o.aw_valid = 1'b0;
-    sbr_rsp_o.aw_ready = 1'b0;
+    mgr_port_req_o.ar_valid = 1'b0;
+    sbr_port_rsp_o.ar_ready = 1'b0;
+    mgr_port_req_o.aw_valid = 1'b0;
+    sbr_port_rsp_o.aw_ready = 1'b0;
 
     unique case (state_q)
       AtopIdle, AtopExecute: begin
@@ -98,20 +98,20 @@ module axi_serializer #(
         // response has been transmitted.
         if ((state_q == AtopIdle) || (state_d == AtopIdle)) begin
           // Gate AR handshake with ready output of Read FIFO.
-          mgr_req_o.ar_valid = sbr_req_i.ar_valid & ~rd_fifo_full;
-          sbr_rsp_o.ar_ready = mgr_rsp_i.ar_ready & ~rd_fifo_full;
-          rd_fifo_push       = mgr_req_o.ar_valid & mgr_rsp_i.ar_ready;
-          if (sbr_req_i.aw_valid) begin
-            if (sbr_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE) begin
+          mgr_port_req_o.ar_valid = sbr_port_req_i.ar_valid & ~rd_fifo_full;
+          sbr_port_rsp_o.ar_ready = mgr_port_rsp_i.ar_ready & ~rd_fifo_full;
+          rd_fifo_push       = mgr_port_req_o.ar_valid & mgr_port_rsp_i.ar_ready;
+          if (sbr_port_req_i.aw_valid) begin
+            if (sbr_port_req_i.aw.atop[5:4] == axi_pkg::ATOP_NONE) begin
               // Normal operation
               // Gate AW handshake with ready output of Write FIFO.
-              mgr_req_o.aw_valid = ~wr_fifo_full;
-              sbr_rsp_o.aw_ready = mgr_rsp_i.aw_ready & ~wr_fifo_full;
-              wr_fifo_push       = mgr_req_o.aw_valid  & mgr_rsp_i.aw_ready;
+              mgr_port_req_o.aw_valid = ~wr_fifo_full;
+              sbr_port_rsp_o.aw_ready = mgr_port_rsp_i.aw_ready & ~wr_fifo_full;
+              wr_fifo_push       = mgr_port_req_o.aw_valid  & mgr_port_rsp_i.aw_ready;
             end else begin
               // Atomic Operation received, go to drain state, when both channels are ready
               // Wait for finished or no AR beat
-              if (!mgr_req_o.ar_valid || (mgr_req_o.ar_valid && mgr_rsp_i.ar_ready)) begin
+              if (!mgr_port_req_o.ar_valid || (mgr_port_req_o.ar_valid && mgr_port_rsp_i.ar_ready)) begin
                 state_d = AtopDrain;
               end
             end
@@ -121,15 +121,15 @@ module axi_serializer #(
       AtopDrain: begin
         // Send the ATOP AW when the last open transaction terminates
         if (wr_fifo_empty && rd_fifo_empty) begin
-          mgr_req_o.aw_valid = 1'b1;
-          sbr_rsp_o.aw_ready = mgr_rsp_i.aw_ready;
-          wr_fifo_push       = mgr_rsp_i.aw_ready;
-          if (sbr_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin
+          mgr_port_req_o.aw_valid = 1'b1;
+          sbr_port_rsp_o.aw_ready = mgr_port_rsp_i.aw_ready;
+          wr_fifo_push       = mgr_port_rsp_i.aw_ready;
+          if (sbr_port_req_i.aw.atop[axi_pkg::ATOP_R_RESP]) begin
             // Overwrite the read ID with the one from AW
-            ar_id        = sbr_req_i.aw.id;
-            rd_fifo_push = mgr_rsp_i.aw_ready;
+            ar_id        = sbr_port_req_i.aw.id;
+            rd_fifo_push = mgr_port_rsp_i.aw_ready;
           end
-          if (mgr_rsp_i.aw_ready) begin
+          if (mgr_port_rsp_i.aw_ready) begin
             state_d = AtopExecute;
           end
         end
@@ -138,12 +138,12 @@ module axi_serializer #(
     endcase
 
     // Gate B handshake with empty flag output of Write FIFO.
-    sbr_rsp_o.b_valid = mgr_rsp_i.b_valid & ~wr_fifo_empty;
-    mgr_req_o.b_ready = sbr_req_i.b_ready & ~wr_fifo_empty;
+    sbr_port_rsp_o.b_valid = mgr_port_rsp_i.b_valid & ~wr_fifo_empty;
+    mgr_port_req_o.b_ready = sbr_port_req_i.b_ready & ~wr_fifo_empty;
 
     // Gate R handshake with empty flag output of Read FIFO.
-    sbr_rsp_o.r_valid = mgr_rsp_i.r_valid & ~rd_fifo_empty;
-    mgr_req_o.r_ready = sbr_req_i.r_ready & ~rd_fifo_empty;
+    sbr_port_rsp_o.r_valid = mgr_port_rsp_i.r_valid & ~rd_fifo_empty;
+    mgr_port_req_o.r_ready = sbr_port_req_i.r_ready & ~rd_fifo_empty;
   end
 
   fifo_v3 #(
@@ -164,7 +164,7 @@ module axi_serializer #(
     .usage_o    ( /*not used*/  )
   );
   // Assign as this condition is needed in FSM
-  assign rd_fifo_pop = sbr_rsp_o.r_valid & sbr_req_i.r_ready & sbr_rsp_o.r.last;
+  assign rd_fifo_pop = sbr_port_rsp_o.r_valid & sbr_port_req_i.r_ready & sbr_port_rsp_o.r.last;
 
   fifo_v3 #(
     .FALL_THROUGH ( 1'b0         ),
@@ -175,7 +175,7 @@ module axi_serializer #(
     .rst_ni,
     .flush_i    ( 1'b0            ),
     .testmode_i ( 1'b0            ),
-    .data_i     ( sbr_req_i.aw.id ),
+    .data_i     ( sbr_port_req_i.aw.id ),
     .push_i     ( wr_fifo_push    ),
     .full_o     ( wr_fifo_full    ),
     .data_o     ( b_id            ),
@@ -184,7 +184,7 @@ module axi_serializer #(
     .usage_o    ( /*not used*/    )
   );
   // Assign as this condition is needed in FSM
-  assign wr_fifo_pop = sbr_rsp_o.b_valid & sbr_req_i.b_ready;
+  assign wr_fifo_pop = sbr_port_rsp_o.b_valid & sbr_port_req_i.b_ready;
 
   `FFARN(state_q, state_d, AtopIdle, clk_i, rst_ni)
 
@@ -199,19 +199,19 @@ module axi_serializer #(
   end
   default disable iff (~rst_ni);
   aw_lost : assert property( @(posedge clk_i)
-      (sbr_req_i.aw_valid & sbr_rsp_o.aw_ready |-> mgr_req_o.aw_valid & mgr_rsp_i.aw_ready))
+      (sbr_port_req_i.aw_valid & sbr_port_rsp_o.aw_ready |-> mgr_port_req_o.aw_valid & mgr_port_rsp_i.aw_ready))
     else $error("AW beat lost.");
   w_lost  : assert property( @(posedge clk_i)
-      (sbr_req_i.w_valid & sbr_rsp_o.w_ready |-> mgr_req_o.w_valid & mgr_rsp_i.w_ready))
+      (sbr_port_req_i.w_valid & sbr_port_rsp_o.w_ready |-> mgr_port_req_o.w_valid & mgr_port_rsp_i.w_ready))
     else $error("W beat lost.");
   b_lost  : assert property( @(posedge clk_i)
-      (mgr_rsp_i.b_valid & mgr_req_o.b_ready |-> sbr_rsp_o.b_valid & sbr_req_i.b_ready))
+      (mgr_port_rsp_i.b_valid & mgr_port_req_o.b_ready |-> sbr_port_rsp_o.b_valid & sbr_port_req_i.b_ready))
     else $error("B beat lost.");
   ar_lost : assert property( @(posedge clk_i)
-      (sbr_req_i.ar_valid & sbr_rsp_o.ar_ready |-> mgr_req_o.ar_valid & mgr_rsp_i.ar_ready))
+      (sbr_port_req_i.ar_valid & sbr_port_rsp_o.ar_ready |-> mgr_port_req_o.ar_valid & mgr_port_rsp_i.ar_ready))
     else $error("AR beat lost.");
   r_lost :  assert property( @(posedge clk_i)
-      (mgr_rsp_i.r_valid & mgr_req_o.r_ready |-> sbr_rsp_o.r_valid & sbr_req_i.r_ready))
+      (mgr_port_rsp_i.r_valid & mgr_port_req_o.r_ready |-> sbr_port_rsp_o.r_valid & sbr_port_req_i.r_ready))
     else $error("R beat lost.");
 `endif
 // pragma translate_on
@@ -272,10 +272,10 @@ module axi_serializer_intf #(
   ) i_axi_serializer (
     .clk_i,
     .rst_ni,
-    .sbr_req_i ( sbr_req ),
-    .sbr_rsp_o ( sbr_rsp ),
-    .mgr_req_o ( mgr_req ),
-    .mgr_rsp_i ( mgr_rsp )
+    .sbr_port_req_i ( sbr_req ),
+    .sbr_port_rsp_o ( sbr_rsp ),
+    .mgr_port_req_o ( mgr_req ),
+    .mgr_port_rsp_i ( mgr_rsp )
   );
 
 // pragma translate_off
diff --git a/src/axi_to_axi_lite.sv b/src/axi_to_axi_lite.sv
index d0de1a38f..671df4ad7 100644
--- a/src/axi_to_axi_lite.sv
+++ b/src/axi_to_axi_lite.sv
@@ -32,11 +32,11 @@ module axi_to_axi_lite #(
   input  logic          rst_ni,   // Asynchronous reset active low
   input  logic          test_i,   // Testmode enable
   // subordinate port full AXI4+ATOP
-  input  axi_req_t      sbr_req_i,
-  output axi_rsp_t      sbr_rsp_o,
+  input  axi_req_t      sbr_port_req_i,
+  output axi_rsp_t      sbr_port_rsp_o,
   // manager port AXI4-Lite
-  output axi_lite_req_t mgr_req_o,
-  input  axi_lite_rsp_t mgr_rsp_i
+  output axi_lite_req_t mgr_port_req_o,
+  input  axi_lite_rsp_t mgr_port_rsp_i
 );
   // full bus declarations
   axi_req_t filtered_req, splitted_req;
@@ -51,10 +51,10 @@ module axi_to_axi_lite #(
   ) i_axi_atop_filter(
     .clk_i     ( clk_i        ),
     .rst_ni    ( rst_ni       ),
-    .sbr_req_i ( sbr_req_i    ),
-    .sbr_rsp_o ( sbr_rsp_o    ),
-    .mgr_req_o ( filtered_req ),
-    .mgr_rsp_i ( filtered_rsp )
+    .sbr_port_req_i ( sbr_port_req_i    ),
+    .sbr_port_rsp_o ( sbr_port_rsp_o    ),
+    .mgr_port_req_o ( filtered_req ),
+    .mgr_port_rsp_i ( filtered_rsp )
   );
 
   // burst splitter so that the id reflect module has no burst accessing it
@@ -70,10 +70,10 @@ module axi_to_axi_lite #(
   ) i_axi_burst_splitter (
     .clk_i     ( clk_i        ),
     .rst_ni    ( rst_ni       ),
-    .sbr_req_i ( filtered_req ),
-    .sbr_rsp_o ( filtered_rsp ),
-    .mgr_req_o ( splitted_req ),
-    .mgr_rsp_i ( splitted_rsp )
+    .sbr_port_req_i ( filtered_req ),
+    .sbr_port_rsp_o ( filtered_rsp ),
+    .mgr_port_req_o ( splitted_req ),
+    .mgr_port_rsp_i ( splitted_rsp )
   );
 
   // ID reflect module handles the conversion from the full AXI to AXI lite on the wireing
@@ -90,10 +90,10 @@ module axi_to_axi_lite #(
     .clk_i     ( clk_i        ),
     .rst_ni    ( rst_ni       ),
     .test_i    ( test_i       ),
-    .sbr_req_i ( splitted_req ),
-    .sbr_rsp_o ( splitted_rsp ),
-    .mgr_req_o ( mgr_req_o    ),
-    .mgr_rsp_i ( mgr_rsp_i    )
+    .sbr_port_req_i ( splitted_req ),
+    .sbr_port_rsp_o ( splitted_rsp ),
+    .mgr_port_req_o ( mgr_port_req_o    ),
+    .mgr_port_rsp_i ( mgr_port_rsp_i    )
   );
 
   // Assertions, check params
@@ -127,11 +127,11 @@ module axi_to_axi_lite_id_reflect #(
   input  logic          rst_ni,   // Asynchronous reset active low
   input  logic          test_i,   // Testmode enable
   // subordinate port full AXI
-  input  axi_req_t      sbr_req_i,
-  output axi_rsp_t      sbr_rsp_o,
+  input  axi_req_t      sbr_port_req_i,
+  output axi_rsp_t      sbr_port_rsp_o,
   // manager port AXI LITE
-  output axi_lite_req_t mgr_req_o,
-  input  axi_lite_rsp_t mgr_rsp_i
+  output axi_lite_req_t mgr_port_req_o,
+  input  axi_lite_rsp_t mgr_port_rsp_i
 );
   typedef logic [IdWidth-1:0] id_t;
 
@@ -139,30 +139,30 @@ module axi_to_axi_lite_id_reflect #(
   logic aw_full, aw_empty, aw_push, aw_pop, ar_full, ar_empty, ar_push, ar_pop;
   id_t  aw_reflect_id, ar_reflect_id;
 
-  assign sbr_rsp_o = '{
-    aw_ready: mgr_rsp_i.aw_ready & ~aw_full,
-    w_ready:  mgr_rsp_i.w_ready,
+  assign sbr_port_rsp_o = '{
+    aw_ready: mgr_port_rsp_i.aw_ready & ~aw_full,
+    w_ready:  mgr_port_rsp_i.w_ready,
     b: '{
       id:       aw_reflect_id,
-      resp:     mgr_rsp_i.b.resp,
+      resp:     mgr_port_rsp_i.b.resp,
       default:  '0
     },
-    b_valid:  mgr_rsp_i.b_valid  & ~aw_empty,
-    ar_ready: mgr_rsp_i.ar_ready & ~ar_full,
+    b_valid:  mgr_port_rsp_i.b_valid  & ~aw_empty,
+    ar_ready: mgr_port_rsp_i.ar_ready & ~ar_full,
     r: '{
       id:       ar_reflect_id,
-      data:     mgr_rsp_i.r.data,
-      resp:     mgr_rsp_i.r.resp,
+      data:     mgr_port_rsp_i.r.data,
+      resp:     mgr_port_rsp_i.r.resp,
       last:     1'b1,
       default:  '0
     },
-    r_valid: mgr_rsp_i.r_valid & ~ar_empty,
+    r_valid: mgr_port_rsp_i.r_valid & ~ar_empty,
     default: '0
   };
 
   // Write ID reflection
-  assign aw_push = mgr_req_o.aw_valid & sbr_rsp_o.aw_ready;
-  assign aw_pop  = sbr_rsp_o.b_valid & mgr_req_o.b_ready;
+  assign aw_push = mgr_port_req_o.aw_valid & sbr_port_rsp_o.aw_ready;
+  assign aw_pop  = sbr_port_rsp_o.b_valid & mgr_port_req_o.b_ready;
   fifo_v3 #(
     .FALL_THROUGH ( FallThrough  ),
     .DEPTH        ( MaxWriteTxns ),
@@ -175,15 +175,15 @@ module axi_to_axi_lite_id_reflect #(
     .full_o    ( aw_full         ),
     .empty_o   ( aw_empty        ),
     .usage_o   ( /*not used*/    ),
-    .data_i    ( sbr_req_i.aw.id ),
+    .data_i    ( sbr_port_req_i.aw.id ),
     .push_i    ( aw_push         ),
     .data_o    ( aw_reflect_id   ),
     .pop_i     ( aw_pop          )
   );
 
   // Read ID reflection
-  assign ar_push = mgr_req_o.ar_valid & sbr_rsp_o.ar_ready;
-  assign ar_pop  = sbr_rsp_o.r_valid & mgr_req_o.r_ready;
+  assign ar_push = mgr_port_req_o.ar_valid & sbr_port_rsp_o.ar_ready;
+  assign ar_pop  = sbr_port_rsp_o.r_valid & mgr_port_req_o.r_ready;
   fifo_v3 #(
     .FALL_THROUGH ( FallThrough ),
     .DEPTH        ( MaxReadTxns ),
@@ -196,30 +196,30 @@ module axi_to_axi_lite_id_reflect #(
     .full_o    ( ar_full         ),
     .empty_o   ( ar_empty        ),
     .usage_o   ( /*not used*/    ),
-    .data_i    ( sbr_req_i.ar.id ),
+    .data_i    ( sbr_port_req_i.ar.id ),
     .push_i    ( ar_push         ),
     .data_o    ( ar_reflect_id   ),
     .pop_i     ( ar_pop          )
   );
 
-  assign mgr_req_o = '{
+  assign mgr_port_req_o = '{
     aw: '{
-      addr: sbr_req_i.aw.addr,
-      prot: sbr_req_i.aw.prot
+      addr: sbr_port_req_i.aw.addr,
+      prot: sbr_port_req_i.aw.prot
     },
-    aw_valid: sbr_req_i.aw_valid & ~aw_full,
+    aw_valid: sbr_port_req_i.aw_valid & ~aw_full,
     w: '{
-      data: sbr_req_i.w.data,
-      strb: sbr_req_i.w.strb
+      data: sbr_port_req_i.w.data,
+      strb: sbr_port_req_i.w.strb
     },
-    w_valid:  sbr_req_i.w_valid,
-    b_ready:  sbr_req_i.b_ready & ~aw_empty,
+    w_valid:  sbr_port_req_i.w_valid,
+    b_ready:  sbr_port_req_i.b_ready & ~aw_empty,
     ar: '{
-      addr: sbr_req_i.ar.addr,
-      prot: sbr_req_i.ar.prot
+      addr: sbr_port_req_i.ar.addr,
+      prot: sbr_port_req_i.ar.prot
     },
-    ar_valid: sbr_req_i.ar_valid & ~ar_full,
-    r_ready:  sbr_req_i.r_ready  & ~ar_empty,
+    ar_valid: sbr_port_req_i.ar_valid & ~ar_full,
+    r_ready:  sbr_port_req_i.r_ready  & ~ar_empty,
     default:  '0
   };
 
@@ -227,17 +227,17 @@ module axi_to_axi_lite_id_reflect #(
   // pragma translate_off
   `ifndef VERILATOR
   aw_atop: assume property( @(posedge clk_i) disable iff (~rst_ni)
-                        sbr_req_i.aw_valid |-> (sbr_req_i.aw.atop == '0)) else
-    $fatal(1, "Module does not support atomics. Value observed: %0b", sbr_req_i.aw.atop);
+                        sbr_port_req_i.aw_valid |-> (sbr_port_req_i.aw.atop == '0)) else
+    $fatal(1, "Module does not support atomics. Value observed: %0b", sbr_port_req_i.aw.atop);
   aw_axi_len: assume property( @(posedge clk_i) disable iff (~rst_ni)
-                        sbr_req_i.aw_valid |-> (sbr_req_i.aw.len == '0)) else
-    $fatal(1, "AW request length has to be zero. Value observed: %0b", sbr_req_i.aw.len);
+                        sbr_port_req_i.aw_valid |-> (sbr_port_req_i.aw.len == '0)) else
+    $fatal(1, "AW request length has to be zero. Value observed: %0b", sbr_port_req_i.aw.len);
   w_axi_last: assume property( @(posedge clk_i) disable iff (~rst_ni)
-                        sbr_req_i.w_valid |-> (sbr_req_i.w.last == 1'b1)) else
-    $fatal(1, "W last signal has to be one. Value observed: %0b", sbr_req_i.w.last);
+                        sbr_port_req_i.w_valid |-> (sbr_port_req_i.w.last == 1'b1)) else
+    $fatal(1, "W last signal has to be one. Value observed: %0b", sbr_port_req_i.w.last);
   ar_axi_len: assume property( @(posedge clk_i) disable iff (~rst_ni)
-                        sbr_req_i.ar_valid |-> (sbr_req_i.ar.len == '0)) else
-    $fatal(1, "AR request length has to be zero. Value observed: %0b", sbr_req_i.ar.len);
+                        sbr_port_req_i.ar_valid |-> (sbr_port_req_i.ar.len == '0)) else
+    $fatal(1, "AR request length has to be zero. Value observed: %0b", sbr_port_req_i.ar.len);
   `endif
   // pragma translate_on
 endmodule
@@ -313,10 +313,10 @@ module axi_to_axi_lite_intf #(
     .rst_ni    ( rst_ni     ),
     .test_i    ( testmode_i ),
     // subordinate port full AXI4+ATOP
-    .sbr_req_i ( full_req   ),
-    .sbr_rsp_o ( full_rsp   ),
+    .sbr_port_req_i ( full_req   ),
+    .sbr_port_rsp_o ( full_rsp   ),
     // manager port AXI4-Lite
-    .mgr_req_o ( lite_req   ),
-    .mgr_rsp_i ( lite_rsp   )
+    .mgr_port_req_o ( lite_req   ),
+    .mgr_port_rsp_i ( lite_rsp   )
   );
 endmodule
diff --git a/src/axi_to_mem_banked.sv b/src/axi_to_mem_banked.sv
index ac2b56eb0..93a633ca1 100644
--- a/src/axi_to_mem_banked.sv
+++ b/src/axi_to_mem_banked.sv
@@ -160,10 +160,10 @@ module axi_to_mem_banked #(
     .clk_i,
     .rst_ni,
     .test_i,
-    .sbr_req_i       ( axi_req_i    ),
+    .sbr_port_req_i       ( axi_req_i    ),
     .sbr_aw_select_i ( WriteAccess  ),
     .sbr_ar_select_i ( ReadAccess   ),
-    .sbr_rsp_o       ( axi_rsp_o    ),
+    .sbr_port_rsp_o       ( axi_rsp_o    ),
     .mgr_reqs_o      ( mem_axi_reqs ),
     .mgr_rsps_i      ( mem_axi_rsps )
   );
diff --git a/src/axi_to_mem_split.sv b/src/axi_to_mem_split.sv
index a6b6483f5..0cf60cac8 100644
--- a/src/axi_to_mem_split.sv
+++ b/src/axi_to_mem_split.sv
@@ -87,8 +87,8 @@ module axi_to_mem_split #(
   ) i_axi_rw_split (
     .clk_i,
     .rst_ni,
-    .sbr_req_i       ( axi_req_i       ),
-    .sbr_rsp_o       ( axi_rsp_o       ),
+    .sbr_port_req_i       ( axi_req_i       ),
+    .sbr_port_rsp_o       ( axi_rsp_o       ),
     .mgr_read_req_o  ( axi_read_req    ),
     .mgr_read_rsp_i  ( axi_read_rsp    ),
     .mgr_write_req_o ( axi_write_req   ),
diff --git a/src/axi_xbar.sv b/src/axi_xbar.sv
index 371ce1355..aabd3a4eb 100644
--- a/src/axi_xbar.sv
+++ b/src/axi_xbar.sv
@@ -217,10 +217,10 @@ import cf_math_pkg::idx_width;
       .clk_i,   // Clock
       .rst_ni,  // Asynchronous reset active low
       .test_i,  // Testmode enable
-      .sbr_req_i       ( sbr_ports_req_i[i] ),
+      .sbr_port_req_i       ( sbr_ports_req_i[i] ),
       .sbr_aw_select_i ( sbr_aw_select      ),
       .sbr_ar_select_i ( sbr_ar_select      ),
-      .sbr_rsp_o       ( sbr_ports_rsp_o[i] ),
+      .sbr_port_rsp_o       ( sbr_ports_rsp_o[i] ),
       .mgr_reqs_o      ( sbr_reqs[i]        ),
       .mgr_rsps_i      ( sbr_rsps[i]        )
     );
@@ -239,8 +239,8 @@ import cf_math_pkg::idx_width;
       .rst_ni,  // Asynchronous reset active low
       .test_i,  // Testmode enable
       // subordinate port
-      .sbr_req_i ( sbr_reqs[i][Cfg.NumMgrPorts]  ),
-      .sbr_rsp_o ( sbr_rsps[i][cfg_NumMgrPorts]  )
+      .sbr_port_req_i ( sbr_reqs[i][Cfg.NumMgrPorts]  ),
+      .sbr_port_rsp_o ( sbr_rsps[i][cfg_NumMgrPorts]  )
     );
   end
 
@@ -260,10 +260,10 @@ import cf_math_pkg::idx_width;
         ) i_axi_multicut_xbar_pipeline (
           .clk_i,
           .rst_ni,
-          .sbr_req_i ( sbr_reqs[i][j] ),
-          .sbr_rsp_o ( sbr_rsps[i][j] ),
-          .mgr_req_o ( mgr_reqs[j][i] ),
-          .mgr_rsp_i ( mgr_rsps[j][i] )
+          .sbr_port_req_i ( sbr_reqs[i][j] ),
+          .sbr_port_rsp_o ( sbr_rsps[i][j] ),
+          .mgr_port_req_o ( mgr_reqs[j][i] ),
+          .mgr_port_rsp_i ( mgr_rsps[j][i] )
         );
 
       end else begin : gen_no_connection
@@ -279,8 +279,8 @@ import cf_math_pkg::idx_width;
           .clk_i,
           .rst_ni,
           .test_i,
-          .sbr_req_i ( sbr_reqs[i][j] ),
-          .sbr_rsp_o ( sbr_rsps[i][j] )
+          .sbr_port_req_i ( sbr_reqs[i][j] ),
+          .sbr_port_rsp_o ( sbr_rsps[i][j] )
         );
       end
     end
@@ -316,8 +316,8 @@ import cf_math_pkg::idx_width;
       .test_i,  // Test Mode enable
       .sbr_reqs_i ( mgr_reqs[i]        ),
       .sbr_rsps_o ( mgr_rsps[i]        ),
-      .mgr_req_o  ( mgr_ports_req_o[i] ),
-      .mgr_rsp_i  ( mgr_ports_rsp_i[i] )
+      .mgr_port_req_o  ( mgr_ports_req_o[i] ),
+      .mgr_port_rsp_i  ( mgr_ports_rsp_i[i] )
     );
   end
 
diff --git a/src/axi_xp.sv b/src/axi_xp.sv
index c3fa5238a..05efcf78d 100644
--- a/src/axi_xp.sv
+++ b/src/axi_xp.sv
@@ -87,13 +87,13 @@ module axi_xp #(
   /// Test mode enable
   input  logic                         test_en_i,
   /// Subordinate ports request
-  input  axi_req_t [NumSbrPorts-1:0]   sbr_req_i,
+  input  axi_req_t [NumSbrPorts-1:0]   sbr_port_req_i,
   /// Subordinate ports response
-  output axi_rsp_t [NumSbrPorts-1:0]   sbr_rsp_o,
+  output axi_rsp_t [NumSbrPorts-1:0]   sbr_port_rsp_o,
   /// Manager ports request
-  output axi_req_t [NumMgrPorts-1:0]   mgr_req_o,
+  output axi_req_t [NumMgrPorts-1:0]   mgr_port_req_o,
   /// Manager ports response
-  input  axi_rsp_t [NumMgrPorts-1:0]   mgr_rsp_i,
+  input  axi_rsp_t [NumMgrPorts-1:0]   mgr_port_rsp_i,
   /// Address map for transferring transactions from subordinate to manager ports
   input  rule_t    [NumAddrRules-1:0]  addr_map_i
 );
@@ -136,8 +136,8 @@ module axi_xp #(
     .clk_i,
     .rst_ni,
     .test_i                 ( test_en_i                               ),
-    .sbr_ports_req_i        ( sbr_req_i                               ),
-    .sbr_ports_rsp_o        ( sbr_rsp_o                               ),
+    .sbr_ports_req_i        ( sbr_port_req_i                               ),
+    .sbr_ports_rsp_o        ( sbr_port_rsp_o                               ),
     .mgr_ports_req_o        ( xbar_req                                ),
     .mgr_ports_rsp_i        ( xbar_rsp                                ),
     .addr_map_i,
@@ -158,10 +158,10 @@ module axi_xp #(
     ) i_axi_id_remap (
       .clk_i,
       .rst_ni,
-      .sbr_req_i ( xbar_req[i]  ),
-      .sbr_rsp_o ( xbar_rsp[i]  ),
-      .mgr_req_o ( mgr_req_o[i] ),
-      .mgr_rsp_i ( mgr_rsp_i[i] )
+      .sbr_port_req_i ( xbar_req[i]  ),
+      .sbr_port_rsp_o ( xbar_rsp[i]  ),
+      .mgr_port_req_o ( mgr_port_req_o[i] ),
+      .mgr_port_rsp_i ( mgr_port_rsp_i[i] )
     );
   end
 
@@ -246,10 +246,10 @@ import cf_math_pkg::idx_width;
     .clk_i,
     .rst_ni,
     .test_en_i,
-    .sbr_req_i (sbr_reqs),
-    .sbr_rsp_o (sbr_rsps),
-    .mgr_req_o (mgr_reqs),
-    .mgr_rsp_i (mgr_rsps),
+    .sbr_port_req_i (sbr_reqs),
+    .sbr_port_rsp_o (sbr_rsps),
+    .mgr_port_req_o (mgr_reqs),
+    .mgr_port_rsp_i (mgr_rsps),
     .addr_map_i
   );
 
diff --git a/test/tb_axi_bus_compare.sv b/test/tb_axi_bus_compare.sv
index 30ec7eb62..e5586349d 100644
--- a/test/tb_axi_bus_compare.sv
+++ b/test/tb_axi_bus_compare.sv
@@ -209,10 +209,10 @@ module tb_axi_bus_compare #(
   ) i_axi_multicut (
     .clk_i     ( clk           ),
     .rst_ni    ( rst_n         ),
-    .sbr_req_i ( axi_req_b_out ),
-    .sbr_rsp_o ( axi_rsp_b_out ),
-    .mgr_req_o ( axi_req_b_dly ),
-    .mgr_rsp_i ( axi_rsp_b_dly )
+    .sbr_port_req_i ( axi_req_b_out ),
+    .sbr_port_rsp_o ( axi_rsp_b_out ),
+    .mgr_port_req_o ( axi_req_b_dly ),
+    .mgr_port_rsp_i ( axi_rsp_b_dly )
   );
 
   axi_sim_mem #(
diff --git a/test/tb_axi_fifo.wave.do b/test/tb_axi_fifo.wave.do
index d5155c412..9e56c9b05 100644
--- a/test/tb_axi_fifo.wave.do
+++ b/test/tb_axi_fifo.wave.do
@@ -151,35 +151,35 @@ add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi
 add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/data_o
 add wave -noupdate -expand -group {R FiFo} /tb_axi_fifo/i_dut/i_axi_fifo/gen_axi_fifo/i_r_fifo/pop_i
 add wave -noupdate -divider {DUT Ports}
-add wave -noupdate -expand -group {DUT sbr AW} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.aw_valid
+add wave -noupdate -expand -group {DUT sbr AW} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_port_req_i.aw_valid
 add wave -noupdate -expand -group {DUT sbr AW} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_resp_o.aw_ready
-add wave -noupdate -expand -group {DUT sbr AW} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.aw
-add wave -noupdate -expand -group {DUT sbr W} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.w
-add wave -noupdate -expand -group {DUT sbr W} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.w_valid
+add wave -noupdate -expand -group {DUT sbr AW} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_port_req_i.aw
+add wave -noupdate -expand -group {DUT sbr W} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_port_req_i.w
+add wave -noupdate -expand -group {DUT sbr W} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_port_req_i.w_valid
 add wave -noupdate -expand -group {DUT sbr W} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_resp_o.w_ready
 add wave -noupdate -expand -group {DUT sbr B} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_resp_o.b_valid
-add wave -noupdate -expand -group {DUT sbr B} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.b_ready
+add wave -noupdate -expand -group {DUT sbr B} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_port_req_i.b_ready
 add wave -noupdate -expand -group {DUT sbr B} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_resp_o.b
-add wave -noupdate -expand -group {DUT sbr AR} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.ar_valid
+add wave -noupdate -expand -group {DUT sbr AR} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_port_req_i.ar_valid
 add wave -noupdate -expand -group {DUT sbr AR} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_resp_o.ar_ready
-add wave -noupdate -expand -group {DUT sbr AR} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.ar
+add wave -noupdate -expand -group {DUT sbr AR} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_port_req_i.ar
 add wave -noupdate -expand -group {DUT sbr R} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_resp_o.r_valid
-add wave -noupdate -expand -group {DUT sbr R} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_req_i.r_ready
+add wave -noupdate -expand -group {DUT sbr R} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_port_req_i.r_ready
 add wave -noupdate -expand -group {DUT sbr R} /tb_axi_fifo/i_dut/i_axi_fifo/sbr_resp_o.r
-add wave -noupdate -expand -group {DUT mgr AW} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.aw_valid
+add wave -noupdate -expand -group {DUT mgr AW} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_port_req_o.aw_valid
 add wave -noupdate -expand -group {DUT mgr AW} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_resp_i.aw_ready
-add wave -noupdate -expand -group {DUT mgr AW} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.aw
-add wave -noupdate -expand -group {DUT mgr W} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.w
-add wave -noupdate -expand -group {DUT mgr W} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.w_valid
+add wave -noupdate -expand -group {DUT mgr AW} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_port_req_o.aw
+add wave -noupdate -expand -group {DUT mgr W} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_port_req_o.w
+add wave -noupdate -expand -group {DUT mgr W} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_port_req_o.w_valid
 add wave -noupdate -expand -group {DUT mgr W} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_resp_i.w_ready
 add wave -noupdate -expand -group {DUT mgr B} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_resp_i.b_valid
-add wave -noupdate -expand -group {DUT mgr B} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.b_ready
+add wave -noupdate -expand -group {DUT mgr B} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_port_req_o.b_ready
 add wave -noupdate -expand -group {DUT mgr B} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_resp_i.b
-add wave -noupdate -expand -group {DUT mgr AR} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.ar_valid
+add wave -noupdate -expand -group {DUT mgr AR} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_port_req_o.ar_valid
 add wave -noupdate -expand -group {DUT mgr AR} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_resp_i.ar_ready
-add wave -noupdate -expand -group {DUT mgr AR} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.ar
+add wave -noupdate -expand -group {DUT mgr AR} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_port_req_o.ar
 add wave -noupdate -expand -group {DUT mgr R} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_resp_i.r_valid
-add wave -noupdate -expand -group {DUT mgr R} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_req_o.r_ready
+add wave -noupdate -expand -group {DUT mgr R} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_port_req_o.r_ready
 add wave -noupdate -expand -group {DUT mgr R} /tb_axi_fifo/i_dut/i_axi_fifo/mgr_resp_i.r
 TreeUpdate [SetDefaultTree]
 WaveRestoreCursors {{Cursor 1} {70 ns} 0}
diff --git a/test/tb_axi_serializer.wave.do b/test/tb_axi_serializer.wave.do
index 4658a5ed5..37f98322f 100644
--- a/test/tb_axi_serializer.wave.do
+++ b/test/tb_axi_serializer.wave.do
@@ -2,9 +2,9 @@ onerror {resume}
 quietly WaveActivateNextPane {} 0
 add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/clk_i
 add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/rst_ni
-add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/sbr_req_i
+add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/sbr_port_req_i
 add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/sbr_resp_o
-add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/mgr_req_o
+add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/mgr_port_req_o
 add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/mgr_resp_i
 add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/rd_fifo_full
 add wave -noupdate /tb_axi_serializer/i_dut/i_axi_serializer/rd_fifo_empty
diff --git a/test/tb_axi_subordinate_compare.sv b/test/tb_axi_subordinate_compare.sv
index 46a20baaf..af6b64db1 100644
--- a/test/tb_axi_subordinate_compare.sv
+++ b/test/tb_axi_subordinate_compare.sv
@@ -138,10 +138,10 @@ module tb_axi_subordinate_compare #(
   ) i_axi_multicut (
     .clk_i     ( clk           ),
     .rst_ni    ( rst_n         ),
-    .sbr_req_i ( axi_req_b_out ),
-    .sbr_rsp_o ( axi_rsp_b_out ),
-    .mgr_req_o ( axi_req_b_dly ),
-    .mgr_rsp_i ( axi_rsp_b_dly )
+    .sbr_port_req_i ( axi_req_b_out ),
+    .sbr_port_rsp_o ( axi_rsp_b_out ),
+    .mgr_port_req_o ( axi_req_b_dly ),
+    .mgr_port_rsp_i ( axi_rsp_b_dly )
   );
 
   axi_sim_mem #(