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Complete formal proofs for LSU, Dcache and CPU modules #151

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stffrdhrn opened this issue May 13, 2022 · 0 comments
Open

Complete formal proofs for LSU, Dcache and CPU modules #151

stffrdhrn opened this issue May 13, 2022 · 0 comments

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@stffrdhrn
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When fixing #146 I rewrote formal properties to do a better job of simulating real Load/Store and Dcache transactions.

I was able to track down the bug and fix it. However, the formal verification for LSU, Dcache and CPU now has a few limitations.

  • The mor1k_lsu_cappuccino, mor1k_cappuccino and mor1k formal no longer passes induction, only bmc is enabled
  • The LSU validation runs with dmmu off, this was done to simplify scope and focus on the d-cache bug
  • The D-Cache and/or DMMU validation runs with only a single way, this was done for simplification, but we should test multiple way
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