Error 7 thrown on deployment when using UDVs larger than 32-bits on EtherCAT slave

[jtcalvert]

Describe the bug
If you configure a custom bitfile with UDVs larger than 32 bits for an NI EtherCAT slave (NI-914x), upon deployment VeriStand will throw error 7: File not found.

Using UDVs 32-bits or smaller does not throw any error.

Full error text:

Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> Project Window.lvlib:Connect to System.vi
=========================
NI VeriStand: NI VeriStand Engine.lvlib:VeriStand Engine Wrapper (RT).vi >> NI VeriStand Engine.lvlib:VeriStand Engine.vi >> NI VeriStand Engine.lvlib:VeriStand Engine State Machine.vi >> NI VeriStand Engine.lvlib:Initialize Inline Custom Devices.vi >> Custom Devices Storage.lvlib:Initialize Device (HW Interface).vi
=========================
NI VeriStand: Error occurred at the following location:

"Targets/Controller/Custom Devices/Scan Engine and EtherCAT"
Error 7 occurred at Project Window.lvlib:Project Window.vi >> Project Window.lvlib:Command Loop.vi >> Project Window.lvlib:Connect to System.vi

Possible reason(s):

LabVIEW: (Hex 0x7) File not found. The file might be in a different location or deleted. Use the command prompt or the file explorer to verify that the path is correct.

Nonexistent GPIB interface.

NI VeriStand: NI VeriStand Engine.lvlib:VeriStand Engine Wrapper (RT).vi >> NI VeriStand Engine.lvlib:VeriStand Engine.vi >> NI VeriStand Engine.lvlib:VeriStand Engine State Machine.vi >> NI VeriStand Engine.lvlib:Initialize Inline Custom Devices.vi >> Custom Devices Storage.lvlib:Initialize Device (HW Interface).vi
=========================
NI VeriStand: Error occurred at the following location:

"Targets/Controller/Custom Devices/Scan Engine and EtherCAT"

To Reproduce
Steps to reproduce the behavior:

1. Create LabVIEW project with an RT controller, EtherCAT master, and 914x EtherCAT chassis.
2. Create a fixed-point UDV with more than 32 bits.
3. Create FPGA VI and compile bitfile.
4. In VeriStand SDF, add the Scan Engine custom device.
5. Add EtherCAT master, NI 914x slave chassis.
6. Select the bitfile to add the UDVs to the chassis in the SDF and download the bitfile to the chassis.
7. Save and deploy the project. Error 7 is thrown with no indication that the issue is related to UDV datatype.
8. If you configure the UDVs to be 32-bits or smaller, the custom bitfile will deploy successfully.

Expected behavior
You should be able to configure UDVs to be whatever datatype you want, since these chassis allow for 512 bytes worth of UDV data.

Desktop (please complete the following information):

• OS: Linux RT
• VeriStand 2020 R5

Additional context
This issue was on the known issues list on the old VeriStand Add-ons community page