From 70e7720d3b9db04b0f88689540ac4a872b866625 Mon Sep 17 00:00:00 2001 From: Lucas Klemmer Date: Thu, 25 Apr 2024 16:21:00 +0200 Subject: [PATCH] update SV array support --- pylintrc | 2 -- tests/test_trace_reader.py | 15 +++++++++++++++ tests/traces/array.fst | Bin 0 -> 564 bytes tests/traces/array.vcd | 33 +++++++++++++++++++++++++++++++++ wal/trace/fst.py | 7 +++++-- wal/trace/vcd.py | 9 ++++++--- 6 files changed, 59 insertions(+), 7 deletions(-) delete mode 100644 pylintrc create mode 100644 tests/test_trace_reader.py create mode 100644 tests/traces/array.fst create mode 100644 tests/traces/array.vcd diff --git a/pylintrc b/pylintrc deleted file mode 100644 index d74e9b7..0000000 --- a/pylintrc +++ /dev/null @@ -1,2 +0,0 @@ -[MESSAGES CONTROL] -disable=wildcard-import,unused-wildcard-import,unnecessary-lambda-assignment, too-many-instance-attributes, C0301, C3001 \ No newline at end of file diff --git a/tests/test_trace_reader.py b/tests/test_trace_reader.py new file mode 100644 index 0000000..e09a5f3 --- /dev/null +++ b/tests/test_trace_reader.py @@ -0,0 +1,15 @@ +'''Test wal trace readers''' +import unittest + +from wal.core import Wal + +class BasicParserTest(unittest.TestCase): + '''Test trace readers''' + + def test_sv_arrays(self): + '''Test SystemVerilog arrays''' + for trace_format in ['vcd', 'fst']: + wal = Wal() + wal.load(f'tests/traces/array.{trace_format}') + self.assertEqual(wal.eval_str('TOP.tb.data<0>'), 2) + self.assertEqual(wal.eval_str('TOP.tb.data<1>'), 0) diff --git a/tests/traces/array.fst b/tests/traces/array.fst new file mode 100644 index 0000000000000000000000000000000000000000..d6b3325d9e32d364209adbf849c967779a76f450 GIT binary patch literal 564 zcmZQz00Tx(2n{E>GQ&l>x%RU-!Lgu7!N^p>(98;mObiu_42(=*E~TmEK*M2yl!|5%%zm)|9d~R1c*(6*bIox Qf!IQb;esVxF~k4=0M~&mTmS$7 literal 0 HcmV?d00001 diff --git a/tests/traces/array.vcd b/tests/traces/array.vcd new file mode 100644 index 0000000..c55f8cf --- /dev/null +++ b/tests/traces/array.vcd @@ -0,0 +1,33 @@ +$version Generated by VerilatedVcd $end +$timescale 1ps $end + + $scope module TOP $end + $scope module tb $end + $var wire 8 # data[0] [7:0] $end + $var wire 8 $ data[1] [7:0] $end + $var wire 8 % data[2] [7:0] $end + $var wire 8 & data[3] [7:0] $end + $var wire 8 ' data[4] [7:0] $end + $var wire 8 ( data[5] [7:0] $end + $var wire 8 ) data[6] [7:0] $end + $var wire 8 * data[7] [7:0] $end + $var wire 8 + data[8] [7:0] $end + $var wire 8 , data[9] [7:0] $end + $upscope $end + $upscope $end +$enddefinitions $end + + +#0 +b00000010 # +b00000000 $ +b00000000 % +b00000000 & +b00000000 ' +b00000000 ( +b00000000 ) +b00000000 * +b00000000 + +b00000000 , +#10 +b00000100 # diff --git a/wal/trace/fst.py b/wal/trace/fst.py index 2cbc0f9..d7403c3 100644 --- a/wal/trace/fst.py +++ b/wal/trace/fst.py @@ -25,9 +25,12 @@ def __init__(self, file, tid, container, from_string=False, keep_signals=None): # get mapping from name to tid and remove trailing signal width, ' [31:0]' etc. self.references_to_ids = {re.sub(r' *\[\d+:\d+\]', '', k): v for k, v in self.references_to_ids.items()} - # rename grouped signals like reg(0), reg(1) to reg_0, reg_1 + # rename grouped signals like reg(0), reg(1) to reg<0>, reg<1> self.references_to_ids = { - re.sub(r'\(([0-9]+)\)', r'_\1', k): v for k, v in self.references_to_ids.items()} + re.sub(r'\(([0-9]+)\)', r'<\1>', k): v for k, v in self.references_to_ids.items()} + # rename grouped signals like reg[0], reg[1] to reg<0>, reg<1> + self.references_to_ids = { + re.sub(r'\[([0-9]+)\]', r'<\1>', k): v for k, v in self.references_to_ids.items()} self.rawsignals = list(self.references_to_ids.keys()) self.signals = set(self.rawsignals) diff --git a/wal/trace/vcd.py b/wal/trace/vcd.py index 192e870..7533de9 100644 --- a/wal/trace/vcd.py +++ b/wal/trace/vcd.py @@ -49,9 +49,12 @@ def parse(self, vcddata): id = tokens[i + 3] name = tokens[i + 4] - # Remove bit width annotations from the name - if name.endswith(']'): - name= name.split('[')[0] + # Remove array indices width annotations from name([..]) + for delim in [('[', ']'), ('(', ')')]: + if name.endswith(delim[1]): + split = name.split(delim[0]) + addr = split[-1].replace(delim[1], '>') + name = ''.join(split[:-1]) + '<' + addr # only append scope. if not in root scope if scope: