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riscv.cxx
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riscv.cxx
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/*
This is a simplistic 64-bit RISC-V emulator.
Only physical memory is supported.
The core set of instructions "rv64imadfc" are implemented: integer, multiply/divide, atomic, double, float, compressed
I tested with a variety of C and C++ apps compiled with four different versions of g++ (each exposed different bugs)
I also tested with the BASIC test suite for my compiler BA, which targets risc-v.
It's slightly faster than the 400Mhz K210 processor on my AMD 5950x machine.
Written by David Lee in February 2023
Useful: https://luplab.gitlab.io/rvcodecjs/#q=c00029f3&abi=false&isa=AUTO
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc#abi-lp64d
https://en.wikipedia.org/wiki/Executable_and_Linkable_Format#:~:text=In%20computing%2C%20the%20Executable%20and,shared%20libraries%2C%20and%20core%20dumps.
https://jemu.oscc.cc/AUIPC
https://inst.eecs.berkeley.edu/~cs61c/resources/su18_lec/Lecture7.pdf
https://riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf
*/
#include <stdint.h>
#include <memory.h>
#include <stdio.h>
#include <stdlib.h>
#include <assert.h>
#include <math.h>
#include <chrono>
#include <djl_128.hxx>
#include <djltrace.hxx>
#include "riscv.hxx"
using namespace std;
using namespace std::chrono;
// conditional move and conditional return instruction extensions
#define USE_DJL_RISCV_EXTENSIONS 0
// set to 1 to use the instruction decompression lookup table
// set to 0 to use the C code or to generate the table
#define USE_RVCTABLE 1
// these instruction types are mostly just useful for debugging
const uint8_t IllType = 0;
const uint8_t UType = 1;
const uint8_t JType = 2;
const uint8_t IType = 3;
const uint8_t BType = 4;
const uint8_t SType = 5;
const uint8_t RType = 6;
const uint8_t CsrType = 7;
const uint8_t R4Type = 8;
const uint8_t ShiftType = 9;
const uint8_t CType = 10; // risc-v extension for cmvxx instructions
static const char instruction_types[] =
{
'!', 'U', 'J', 'I', 'B', 'S', 'R', 'C', 'r', 's', 'c',
};
static uint32_t g_State = 0;
const uint32_t stateTraceInstructions = 1;
const uint32_t stateEndEmulation = 2;
bool RiscV::trace_instructions( bool t )
{
bool prev = ( 0 != ( g_State & stateTraceInstructions ) );
if ( t )
g_State |= stateTraceInstructions;
else
g_State &= ~stateTraceInstructions;
return prev;
} //trace_instructions
void RiscV::end_emulation() { g_State |= stateEndEmulation; }
// for the 32 opcode_types ( ( opcode >> 2 ) & 0x1f )
static const uint8_t riscv_types[ 32 ] =
{
IType, // 0
IType, // 1
CType, // 2 // risc-v extension for cmvxx instructions
IType, // 3
IType, // 4
UType, // 5
IType, // 6
IllType, // 7
SType, // 8
SType, // 9
RType, // a // risc-v extension for jrxx instructions
RType, // b
RType, // c
UType, // d
RType, // e
IllType, // f
RType, // 10
RType, // 11
RType, // 12
IllType, // 13
RType, // 14
IllType, // 15
IllType, // 16
IllType, // 17
BType, // 18
IType, // 19
IllType, // 1a
JType, // 1b
IType, // 1c
IllType, // 1d
IllType, // 1e
IllType, // 1f
};
#pragma warning(disable: 4100)
void RiscV::assert_type( uint8_t t ) { assert( t == riscv_types[ opcode_type ] ); }
static const char * register_names[ 32 ] =
{
"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
"s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
"a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
"s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
};
static const char * fregister_names[ 32 ] =
{
"ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
"fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
"fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
"fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11",
};
const char * RiscV::reg_name( uint64_t reg )
{
if ( reg >= 32 )
return "invalid register";
return register_names[ reg ];
} //reg_name
const char * RiscV::freg_name( uint64_t reg )
{
if ( reg >= 32 )
return "invalid f register";
return fregister_names[ reg ];
} //freg_name
static void unhandled_op16( uint16_t x )
{
printf( "compressed opcode not handled: %04x\n", x );
tracer.Trace( "compressed opcode not handled: %04x\n", x );
exit( 1 );
} //unhandled_op16
static bool g_failOnUncompressError = true;
#if USE_RVCTABLE
#include "rvctable.txt"
uint32_t RiscV::uncompress_rvc( uint16_t x )
{
uint32_t op32 = rvc_lookup[ x ];
if ( 0 == op32 )
unhandled_op16( x );
return op32;
} //uncompress_rvc
#else // code, not a table
static uint32_t compose_I( uint32_t funct3, uint32_t rd, uint32_t rs1, uint32_t imm, uint32_t opcode_type )
{
//if ( g_State & stateTraceInstructions )
// tracer.Trace( " composing I funct3 %02x, rd %x, rs1 %x, imm %d, opcode_type %x\n", funct3, rd, rs1, imm, opcode_type );
return ( funct3 << 12 ) | ( rd << 7 ) | ( rs1 << 15 ) | ( imm << 20 ) | ( opcode_type << 2 ) | 0x3;
} //compose_I
static uint32_t compose_R( uint32_t funct3, uint32_t funct7, uint32_t rd, uint32_t rs1, uint32_t rs2, uint32_t opcode_type )
{
//if ( g_State & stateTraceInstructions )
// tracer.Trace( " composing R funct3 %02x, funct7 %02x, rd %x, rs1 %x, rs2 %x, opcode_type %x\n", funct3, funct7, rd, rs1, rs2, opcode_type );
return ( funct3 << 12 ) | ( funct7 << 25 ) | ( rd << 7 ) | ( rs1 << 15 ) | ( rs2 << 20 ) | ( opcode_type << 2 ) | 0x3;
} //compose_R
static uint32_t compose_S( uint32_t funct3, uint32_t rs1, uint32_t rs2, uint32_t imm, uint32_t opcode_type )
{
//if ( g_State & stateTraceInstructions )
// tracer.Trace( " composing S funct3 %02x, rs1 %x, rs2 %x, imm %d, opcode_type %x\n", funct3, rs1, rs2, imm, opcode_type );
uint32_t i = ( ( imm << 7 ) & 0xf80 ) | ( ( imm << 20 ) & 0xfe000000 );
return ( funct3 << 12 ) | ( rs1 << 15 ) | ( rs2 << 20 ) | i | ( opcode_type << 2 ) | 0x3;
} //compose_S
static uint32_t compose_U( uint32_t rd, uint32_t imm, uint32_t opcode_type )
{
return ( rd << 7 ) | ( imm << 12 ) | ( opcode_type << 2 ) | 0x3;
} //compose_U
static uint32_t compose_J( uint32_t offset, uint32_t opcode_type )
{
// 31 30 20 19
// j itself decodes from upper 20 bits as imm[20|10:1|11|19:12]
offset = ( ( offset << 11 ) & 0x80000000 ) |
( ( offset << 20 ) & 0x7fe00000 ) |
( ( offset << 9 ) & 0x00100000 ) |
( offset & 0x000ff000 );
//tracer.Trace( "j offset re-encoded as %x = %d\n", offset, offset );
return offset | ( opcode_type << 2 ) | 0x3;
} //compose_J
static uint32_t compose_B( uint32_t funct3, uint32_t rs1, uint32_t rs2, uint32_t imm, uint32_t opcode_type )
{
// offset 12..1
uint32_t offset = ( ( imm << 19 ) & 0x80000000 ) | ( ( imm << 20 ) & 0x7e000000 ) |
( ( imm << 7 ) & 0xf00 ) | ( ( imm >> 4 ) & 0x80 );
//tracer.Trace( "offset before %x and after composing: %x\n", imm, offset );
return ( funct3 << 12 ) | ( rs1 << 15 ) | ( rs2 << 20 ) | offset | ( opcode_type << 2 ) | 0x3;
} //compose_B
uint32_t RiscV::uncompress_rvc( uint16_t x )
{
uint32_t op32 = 0;
uint16_t op2 = x & 0x3;
const uint32_t rprime_offset = 8; // add this to r' to get a final r
uint16_t p_funct3 = ( x >> 13 ) & 0x7; // p_ for prime -- the compressed version
uint16_t bit12 = ( x >> 12 ) & 1;
if ( g_State & stateTraceInstructions )
tracer.Trace( "rvc op %04x op2 %d funct3 %d bit12 %d\n", x, op2, p_funct3, bit12 );
/*
From https://riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf
There are many exceptions to these rules.
Format Meaning 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR Register funct3 rd/rs1 rs2 op
CI Immediate funct3 imm rd/rs1 imm op
CSS Stack-relative Store funct3 imm rs2 op
CIW Wide Immediate funct3 imm rd op
CL Load funct3 imm rs1 x imm rd op
CS Store funct3 imm rs1 x imm rs2 op
CB Branch funct3 offset rs1 offset op
CJ Jump funct3 jump-target op
*/
switch ( op2 )
{
case 0:
{
uint32_t p_imm = ( ( x >> 7 ) & 0x38 ) | ( ( x << 1 ) & 0xc0 );
uint32_t p_rs1 = ( ( x >> 7 ) & 0x7 ) + rprime_offset;
uint32_t p_rdrs2 = ( ( x >> 2 ) & 0x7 ) + rprime_offset;
switch( p_funct3 )
{
case 0: // c.addi4spn
{
uint32_t amount = ( ( x >> 7 ) & 0x30 ) | ( ( x >> 1 ) & 0x3c0 ) | ( ( x >> 4 ) & 0x4 ) | ( ( x >> 2 ) & 0x8 );
//tracer.Trace( "adjusting pointer to sp-offset using addi, amount %d\n", amount );
// addi funct3 = 0, rd = p_rdrs2, rs1 = sp, i_imm = amount
op32 = compose_I( 0, p_rdrs2, sp, amount, 0x4 );
break;
}
case 1: // c.fld
{
op32 = compose_I( 3, p_rdrs2, p_rs1, p_imm, 1 );
break;
}
case 2: // c.lw
{
p_imm = ( ( x >> 7 ) & 0x38 ) | ( ( x >> 4 ) & 0x4 ) | ( ( x << 1 ) & 0x40 );
op32 = compose_I( 2, p_rdrs2, p_rs1, p_imm, 0 );
break;
}
case 3: // c.ld
{
op32 = compose_I( 3, p_rdrs2, p_rs1, p_imm, 0 );
break;
}
case 4: // reserved
{
break;
}
case 5: // c.fsd
{
op32 = compose_S( 3, p_rs1, p_rdrs2, p_imm, 9 );
break;
}
case 6: // c.sw
{
p_imm = ( ( x >> 7 ) & 0x38 ) | ( ( x >> 4 ) & 0x4 ) | ( ( x << 1 ) & 0x40 );
op32 = compose_S( 2, p_rs1, p_rdrs2, p_imm, 8 );
break;
}
case 7: // c.sd
{
op32 = compose_S( 3, p_rs1, p_rdrs2, p_imm, 8 );
break;
}
}
break;
}
case 1:
{
uint32_t p_imm = (uint32_t) sign_extend( ( ( x >> 7 ) & 0x20 ) | ( ( x >> 2 ) & 0x1f ), 5 );
uint32_t p_rs1rd = ( ( x >> 7 ) & 0x1f );
switch( p_funct3 )
{
case 0: // c.addi
{
op32 = compose_I( 0, p_rs1rd, p_rs1rd, p_imm, 4 );
break;
}
case 1: // c.addiw
{
op32 = compose_I( 0, p_rs1rd, p_rs1rd, p_imm, 6);
break;
}
case 2: // c.li
{
op32 = compose_I( 0, p_rs1rd, zero, p_imm, 4 ); // addi rd, zero, imm
break;
}
case 3:
{
if ( 2 == p_rs1rd ) // c.addi16sp
{
uint32_t amount = ( ( x >> 3 ) & 0x200 ) | ( ( x >> 2 ) & 0x10 ) | ( ( x << 1 ) & 0x40 ) |
( ( x << 4 ) & 0x180 ) | ( ( x << 3 ) & 0x20 );
amount = (uint32_t) sign_extend( amount, 9 );
op32 = compose_I( 0, sp, sp, amount, 0x4 );
}
else // c.lui
{
uint32_t amount = ( ( x << 5 ) & 0x20000 ) | ( ( x << 10 ) & 0x1f000 );
amount = (uint32_t) sign_extend( amount, 17 );
amount >>= 12;
op32 = compose_U( p_rs1rd, amount, 0xd );
}
break;
}
case 4: // many
{
uint16_t funct11_10 = ( x >> 10 ) & 0x3;
p_rs1rd = ( ( x >> 7 ) & 0x7 ) + rprime_offset;
uint32_t p_rs2 = ( ( x >> 2 ) & 0x7 ) + rprime_offset;
switch ( funct11_10 )
{
case 0: // c.srli + c.srli64
{
uint32_t amount = ( ( x >> 7 ) & 0x20 ) | ( ( x >> 2 ) & 0x1f );
op32 = compose_I( 5, p_rs1rd, p_rs1rd, amount, 4 );
break;
}
case 1: // c.srai + c.srai64
{
uint32_t amount = ( ( x >> 7 ) & 0x20 ) | ( ( x >> 2 ) & 0x1f );
amount |= 0x400; // set this bit so it's srai, not srli
op32 = compose_I( 5, p_rs1rd, p_rs1rd, amount, 4 );
break;
}
case 2: // c.andi
{
op32 = compose_I( 7, p_rs1rd, p_rs1rd, p_imm, 4 );
break;
}
case 3:
{
uint16_t funct6_5 = ( x >> 5 ) & 0x3;
if ( 0 == bit12 )
{
if ( 0 == funct6_5 ) // c.sub
op32 = compose_R( 0, 0x20, p_rs1rd, p_rs1rd, p_rs2, 0xc );
else if ( 1 == funct6_5 ) // c.xor
op32 = compose_R( 4, 0, p_rs1rd, p_rs1rd, p_rs2, 0xc );
else if ( 2 == funct6_5 ) // c.or
op32 = compose_R( 6, 0, p_rs1rd, p_rs1rd, p_rs2, 0xc );
else if ( 3 == funct6_5 ) // c.and
op32 = compose_R( 7, 0, p_rs1rd, p_rs1rd, p_rs2, 0xc );
}
else
{
if ( 0 == funct6_5 ) // c.subw
op32 = compose_R( 0, 0x20, p_rs1rd, p_rs1rd, p_rs2, 0xe );
else if ( 1 == funct6_5 ) // c.addw
op32 = compose_R( 0, 0, p_rs1rd, p_rs1rd, p_rs2, 0xe );
}
}
}
break;
}
case 5: // c.j
{
// j offset. J type. opcode_type 0x1b
// 12 11 10 8 7 6 5 2
// bits 12:2 should be decoded as 12 bits: imm[11|4|9:8|10|6|7|3:1|5]
uint32_t offset = ( ( x >> 1 ) & 0x800 ) | ( ( x >> 7 ) & 0x10 ) | ( ( x >> 1 ) & 0x300 ) | ( ( x << 2 ) & 0x400 ) |
( ( x >> 1 ) & 0x40 ) | ( ( x << 1 ) & 0x80 ) | ( ( x >> 2 ) & 0xe ) | ( ( x << 3 ) & 0x20 );
offset = (uint32_t) sign_extend( offset, 11 );
op32 = compose_J( offset, 0x1b );
break;
}
case 6: // c.beqz
{
uint32_t p_rs1 = ( ( x >> 7 ) & 0x7 ) + rprime_offset;
uint32_t offset = ( ( x >> 4 ) & 0x100 ) | ( ( x >> 7 ) & 0x18 ) | ( ( x << 1 ) & 0xc0 ) |
( ( x >> 2 ) & 0x6 ) | ( ( x << 3 ) & 0x20 );
offset = (uint32_t) sign_extend( offset, 8 );
op32 = compose_B( 0, p_rs1, zero, offset, 0x18 );
break;
}
case 7: // c.bnez
{
uint32_t p_rs1 = ( ( x >> 7 ) & 0x7 ) + rprime_offset;
uint32_t offset = ( ( x >> 4 ) & 0x100 ) | ( ( x >> 7 ) & 0x18 ) | ( ( x << 1 ) & 0xc0 ) |
( ( x >> 2 ) & 0x6 ) | ( ( x << 3 ) & 0x20 );
offset = (uint32_t) sign_extend( offset, 8 );
op32 = compose_B( 1, p_rs1, zero, offset, 0x18 );
break;
}
}
break;
}
case 2:
{
uint32_t p_rs1rd = ( ( x >> 7 ) & 0x1f );
uint32_t p_rs2 = ( ( x >> 2 ) & 0x1f );
switch( p_funct3 )
{
case 0: // c.cslli
{
if ( 0 == bit12 && 0 == p_rs2 ) // slli64
{
tracer.Trace( "warning: ignoring slli64\n" );
}
else // slli
{
uint32_t amount = ( ( x >> 7 ) & 0x20 ) | p_rs2;
op32 = compose_I( 1, p_rs1rd, p_rs1rd, amount, 4 );
}
break;
}
case 1: // c.fldsp
{
uint32_t i = ( ( x >> 7 ) & 0x20 ) | ( ( x >> 2 ) & 0x18 ) | ( ( x << 4 ) & 0x1c0 );
op32 = compose_I( 3, p_rs1rd, sp, i, 1 );
break;
}
case 2: // c.lwsp
{
uint32_t i = ( ( x >> 7 ) & 0x20 ) | ( ( x >> 2 ) & 0x1c ) | ( ( x << 4 ) & 0x0c0 );
op32 = compose_I( 2, p_rs1rd, sp, i, 0 );
break;
}
case 3: // c.ldsp
{
uint32_t i = ( ( x >> 7 ) & 0x20 ) | ( ( x >> 2 ) & 0x18 ) | ( ( x << 4 ) & 0x1c0 );
op32 = compose_I( 3, p_rs1rd, sp, i, 0 );
break;
}
case 4: // several
{
if ( 0 == bit12 )
{
if ( 0 == p_rs2 ) // c.jr
op32 = compose_I( 0, 0, p_rs1rd, 0, 0x19 ); // I type jalr (p_rs1rd) + 0
else // c.mv
op32 = compose_I( 0, p_rs1rd, p_rs2, 0, 4 ); // add rd, rs, zero
}
else
{
if ( 0 == p_rs1rd ) // c.ebreak;
op32 = 0x00100073;
else
{
if ( 0 == p_rs2 ) // c.jalr
op32 = compose_I( 0, 1, p_rs1rd, 0, 0x19 ); // always store ra in ra/x1
else // c.add
op32 = compose_R( 0, 0, p_rs1rd, p_rs1rd, p_rs2, 0xc );
}
}
break;
}
case 5: // c.fsdsp
{
uint32_t p_imm = ( ( x >> 7 ) & 0x38 ) | ( ( x >> 1 ) & 0x1c0 );
op32 = compose_S( 3, sp, p_rs2, p_imm, 9 );
break;
}
case 6: // c.swsp
{
uint32_t p_imm = ( ( x >> 7 ) & 0x3c ) | ( ( x >> 1 ) & 0xc0 );
op32 = compose_S( 2, sp, p_rs2, p_imm, 8 );
break;
}
case 7: // c.sdsp
{
uint32_t p_imm = ( ( x >> 7 ) & 0x38 ) | ( ( x >> 1 ) & 0x1c0 );
op32 = compose_S( 3, sp, p_rs2, p_imm, 8 );
break;
}
}
break;
}
default:
{
assert( !"opcode does not appear to be compressed\n" );
break;
}
}
if ( 0 == op32 && g_failOnUncompressError )
unhandled_op16( x );
return op32;
} //uncompress_rvc
#endif // use code for rvc decompression, not a table
bool RiscV::generate_rvc_table( const char * path )
{
g_failOnUncompressError = false;
FILE * fp = fopen( path, "w" );
if ( fp )
{
fprintf( fp, "static const uint32_t rvc_lookup[65536] = \n{" );
for ( uint32_t i = 0; i <= 0xffff; i++ )
{
if ( 0 == ( i % 16 ) )
fprintf( fp, "\n " );
uint32_t op32 = 0;
if ( 0x3 != ( i & 0x3 ) )
op32 = uncompress_rvc( (uint16_t) i );
fprintf( fp, ( 0 == op32 ) ? "%x, " : "0x%x, ", op32 );
}
fprintf( fp, "\n};" );
fclose( fp );
}
else
return false;
return true;
} //generate_rvc_table
static const char * comparison_types[] =
{
"eq", "ne", "error-le?", "error-gt?", "lt", "ge", "ltu", "geu",
};
static const char * cmp_type( uint64_t t )
{
assert( t < _countof( comparison_types ) );
return comparison_types[ t ];
} //cmp_type
#if defined( __GNUC__ ) && !defined( __APPLE__ ) // bogus warning in g++ (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0
#pragma GCC diagnostic ignored "-Wformat="
#endif
void RiscV::trace_state()
{
uint8_t optype = riscv_types[ opcode_type ];
//tracer.TraceBinaryData( getmem( 0x7e8d0 ), 16, 2 );
static char acExtra[ 1024 ];
acExtra[ 0 ] = 0;
snprintf( acExtra, _countof( acExtra ), "t0 %llx t1 %llx s0 %llx s1 %llx, s7 %llx", regs[ t0 ], regs[ t1 ], regs[ s0 ], regs[ s1 ], regs[ s7 ] );
static const char * previous_symbol = 0;
uint64_t offset;
const char * symbol_name = riscv_symbol_lookup( pc, offset );
if ( symbol_name == previous_symbol )
symbol_name = "";
else
previous_symbol = symbol_name;
char symbol_offset[40];
symbol_offset[ 0 ] = 0;
if ( 0 != symbol_name[ 0 ] )
{
if ( 0 != offset )
snprintf( symbol_offset, _countof( symbol_offset ), " + %llx", offset );
strcat( symbol_offset, "\n " );
}
tracer.Trace( "pc %8llx %s%s op %8llx a0 %llx a1 %llx a2 %llx a3 %llx a4 %llx a5 %llx gp %llx %s ra %llx sp %llx t %2llx %c => ",
pc, symbol_name, symbol_offset,
op, regs[ a0 ], regs[ a1 ], regs[ a2 ], regs[ a3 ], regs[ a4 ], regs[ a5 ], regs[ gp ], acExtra,
regs[ ra ], regs[ sp ], opcode_type, instruction_types[ optype ] );
switch ( optype )
{
case IllType:
{
tracer.Trace( "illegal optype!\n" );
break;
}
case UType:
{
decode_U();
if ( 0x5 == opcode_type )
tracer.Trace( "auipc %s, %lld # %llx\n", reg_name( rd ), (u_imm << 12 ), pc + ( u_imm << 12 ) );
else if ( 0xd == opcode_type )
tracer.Trace( "lui %s, %lld # %llx\n", reg_name( rd ), u_imm << 12, u_imm << 12 );
break;
}
case JType:
{
decode_J();
if ( 0x1b == opcode_type )
tracer.Trace( "jal %lld # %8llx\n", j_imm_u, pc + j_imm_u );
break;
}
case IType:
{
decode_I();
//tracer.Trace( "\ni_imm %llx, i_imm_u %llx, rs1 %s, funct3 %llx, rd %s\n", i_imm, i_imm_u, reg_name( rs1 ), funct3, reg_name( rd ) );
if ( 0x0 == opcode_type )
{
switch( funct3 )
{
case 0: tracer.Trace( "lb %s, %lld(%s)\n", reg_name( rd ), i_imm, reg_name( rs1 ) ); break;
case 1: tracer.Trace( "lh %s, %lld(%s)\n", reg_name( rd ), i_imm, reg_name( rs1 ) ); break;
case 2: tracer.Trace( "lw %s, %lld(%s)\n", reg_name( rd ), i_imm, reg_name( rs1 ) ); break;
case 3: tracer.Trace( "ld %s, %lld(%s) # %lld(%llx)\n", reg_name( rd ), i_imm, reg_name( rs1 ), i_imm, regs[ rs1 ] ); break;
case 4: tracer.Trace( "lbu %s, %lld(%s)\n", reg_name( rd ), i_imm, reg_name( rs1 ) ); break;
case 5: tracer.Trace( "lhu %s, %lld(%s)\n", reg_name( rd ), i_imm, reg_name( rs1 ) ); break;
case 6: tracer.Trace( "lwu %s, %lld(%s)\n", reg_name( rd ), i_imm, reg_name( rs1 ) ); break;
}
}
else if ( 1 == opcode_type )
{
if ( 2 == funct3 )
tracer.Trace( "flw %s, %d(%s) # %.2f\n", freg_name( rd ), i_imm, reg_name( rs1 ), getfloat( i_imm + regs[ rs1 ] ) );
else if ( 3 == funct3 )
tracer.Trace( "fld %s, %d(%s) # %.2f\n", freg_name( rd ), i_imm, reg_name( rs1 ), getdouble( i_imm + regs[ rs1 ] ) );
}
else if ( 3 == opcode_type )
{
if ( 0 == funct3 || 1 == funct3 )
tracer.Trace( "fence\n" );
}
else if ( 4 == opcode_type )
{
decode_I_shift();
switch( funct3 )
{
case 0: tracer.Trace( "addi %s, %s, %lld\n", reg_name( rd ), reg_name( rs1 ), i_imm ); break;
case 1: tracer.Trace( "slli %s, %s, %lld\n", reg_name( rd ), reg_name( rs1 ), i_shamt6 ); break;
case 2: tracer.Trace( "slti %s, %s, %lld\n", reg_name( rd ), reg_name( rs1 ), i_imm ); break;
case 3: tracer.Trace( "sltiu %s, %s, %llu\n", reg_name( rd ), reg_name( rs1 ), i_imm ); break;
case 4: tracer.Trace( "xori %s, %s, %lld\n", reg_name( rd ), reg_name( rs1 ), i_imm ); break;
case 5:
{
if ( 0 == i_top2 )
tracer.Trace( "srli %s, %s, %lld\n", reg_name( rd ), reg_name( rs1 ), i_shamt6 );
else if ( 1 == i_top2 )
tracer.Trace( "srai %s, %s, %lld\n", reg_name( rd ), reg_name( rs1 ), i_shamt5 );
break;
}
case 6: tracer.Trace( "ori %s, %s, %lld\n", reg_name( rd ), reg_name( rs1 ), i_imm ); break;
case 7: tracer.Trace( "andi %s, %s, %lld\n", reg_name( rd ), reg_name( rs1 ), i_imm ); break;
}
}
else if ( 6 == opcode_type )
{
decode_I_shift();
if ( 0 == funct3 )
{
uint32_t x = (uint32_t) ( ( 0xffffffff & regs[ rs1 ] ) + i_imm );
uint64_t ext = sign_extend( x, 31 );
tracer.Trace( "addiw %s, %s, %lld # %d + %d = %lld\n", reg_name( rd ), reg_name( rs1 ), i_imm, regs[ rs1 ], i_imm, ext );
}
else if ( 1 == funct3 )
{
if ( 0 == i_top2 )
{
uint32_t val = (uint32_t) regs[ rs1 ];
//uint32_t result = val << i_shamt5;
//uint64_t result64 = sign_extend( result, 31 );
tracer.Trace( "slliw %s, %s, %lld # %x << %d\n", reg_name( rd ), reg_name( rs1 ), i_shamt5, val, i_shamt5 );
}
}
else if ( 5 == funct3 )
{
if ( 0 == i_top2 )
tracer.Trace( "srliw %s, %s, %lld # %x >> %d = %x\n", reg_name( rd ), reg_name( rs1 ), i_shamt5, regs[ rs1 ], i_shamt5,
( ( 0xffffffff & regs[ rs1 ] ) >> i_shamt5 ) );
else if ( 1 == i_top2 )
tracer.Trace( "sraiw %s, %s, %lld\n", reg_name( rd ), reg_name( rs1 ), i_shamt5 );
}
}
else if ( 0x19 == opcode_type )
{
if ( 0 == funct3 )
tracer.Trace( "jalr %s, %s, %lld\n", reg_name( rd ), reg_name( rs1 ), i_imm );
}
else if ( 0x1c == opcode_type )
{
uint64_t csr = i_imm_u;
// funct3
// 000 system (ecall / ebreak / sfence / hfence)
// 001 csrrw write csr
// 010 csrrs read csr
// 011 csrrc clear bits in csr
// 101 csrrwi write csr immediate
// 110 csrrsi set bits in csr immediate
// 111 csrrci clear bits in csr immediate
if ( 0 == funct3 ) // system
{
if ( 0x73 == op )
tracer.Trace( "ecall\n" );
else if ( 0x100073 == op )
tracer.Trace( "ebreak\n" );
else
tracer.Trace( "unknown system e instruction\n" );
}
else if ( 1 == funct3 ) // write csr
{
if ( 1 == csr )
tracer.Trace( "csrrw %s, fflags, %s # read fp exception flags\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 2 == csr )
tracer.Trace( "csrrw %s, frm, %s # read fp rounding mode\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0xc00 == csr )
tracer.Trace( "csrrw %s, cycle, %s\n", reg_name( rd ), reg_name( rs1 ) );
else
tracer.Trace( "csrrw unknown\n" );
}
else if ( 2 == funct3 ) // read csr
{
if ( 1 == csr )
tracer.Trace( "csrrs %s, fflags, %s # read fp exception flags\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 2 == csr )
tracer.Trace( "csrrs %s, frm, %s # read fp rounding mode\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x100 == csr )
tracer.Trace( "csrrs %s, sstatus, %s # supervisor status\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x104 == csr )
tracer.Trace( "csrrs %s, sie, %s # supervisor interrupt-enable\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x105 == csr )
tracer.Trace( "csrrs %s, stvec, %s # supervisor trap handler base address\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x140 == csr )
tracer.Trace( "csrrs %s, sscratch, %s # supervisor scratch register for trap handlers\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x141 == csr )
tracer.Trace( "csrrs %s, sepc, %s # supervisor exception program counter\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x142 == csr )
tracer.Trace( "csrrs %s, scause, %s # supervisor trap cause\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x143 == csr )
tracer.Trace( "csrrs %s, stval, %s # supervisor bad address or instruction\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x180 == csr )
tracer.Trace( "csrrs %s, satp, %s # supervisor adress translation and protection\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x302 == csr )
tracer.Trace( "csrrs %s, medeleg, %s # machine exception delegation\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x303 == csr )
tracer.Trace( "csrrs %s, mideleg, %s # machine interrupt delegation\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x304 == csr )
tracer.Trace( "csrrs %s, mie, %s # machine interrupt-enable\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x305 == csr )
tracer.Trace( "csrrs %s, mtvec, %s # machine trap-handler base addess\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x306 == csr )
tracer.Trace( "csrrs %s, mcounteren, %s # machine counter enable\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x340 == csr )
tracer.Trace( "csrrs %s, mscratch, %s # machine scratch for trap handlers\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0x341 == csr )
tracer.Trace( "csrrs %s, mepc, %s # machine exception program counter\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0xb00 == csr )
tracer.Trace( "csrrs %s, mcycle, %s # rdmcycle read machine cycle counter\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0xb02 == csr )
tracer.Trace( "csrrs %s, minstret, %s # rdminstret read machine instrutions retired\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0xc00 == csr )
tracer.Trace( "csrrs %s, cycle, %s # rdcycle read cycle counter\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0xc01 == csr )
tracer.Trace( "csrrs %s, time, %s # rdtime read time\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0xc02 == csr )
tracer.Trace( "csrrs %s, instret, %s # rdinstret read instrutions retired\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0xf11 == csr ) // mvendorid vendor
tracer.Trace( "csrrs %s, mvendorid, %s # vendor id\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0xf12 == csr ) // marchid architecture
tracer.Trace( "csrrs %s, marchid, %s # architecture id\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 0xf13 == csr ) // mimpid implementation
tracer.Trace( "csrrs %s, mimpid, %s # implementation id\n", reg_name( rd ), reg_name( rs1 ) );
else
tracer.Trace( "csrrs unknown\n" );
}
else if ( 6 == funct3 ) // set bits in csr immediate
{
if ( 1 == csr )
tracer.Trace( "csrrsi %s, fflags, %d # set fp crs flags\n", reg_name( rd ), rs1 );
else
tracer.Trace( "unknown csr set bit instruction\n" );
}
}
break;
}
case BType:
{
decode_B();
if ( 0x18 == opcode_type )
tracer.Trace( "b%s %s, %s, %lld # %8llx\n", cmp_type( funct3 ), reg_name( rs1 ), reg_name( rs2 ), b_imm, pc + b_imm );
break;
}
case SType:
{
decode_S();
//tracer.Trace( "s_imm %llx, rs2 %s, rs1 %s, funct3 %llx\n", s_imm, reg_name( rs2 ), reg_name( rs1 ), funct3 );
if ( 8 == opcode_type )
{
if ( 0 == funct3 )
tracer.Trace( "sb %s, %lld(%s) # %2x, %lld(%llx)\n", reg_name( rs2 ), s_imm, reg_name( rs1 ), (uint8_t) regs[ rs2 ], s_imm, regs[ rs1 ] );
else if ( 1 == funct3 )
tracer.Trace( "sh %s, %lld(%s) # %4x, %lld(%llx)\n", reg_name( rs2 ), s_imm, reg_name( rs1 ), (uint16_t) regs[ rs2 ], s_imm, regs[ rs1 ] );
else if ( 2 == funct3 )
tracer.Trace( "sw %s, %lld(%s)\n", reg_name( rs2 ), s_imm, reg_name( rs1 ) );
else if ( 3 == funct3 )
tracer.Trace( "sd %s, %lld(%s) # %lld(%llx)\n", reg_name( rs2 ), s_imm, reg_name( rs1 ), s_imm, regs[ rs1 ] );
}
else if ( 9 == opcode_type )
{
if ( 2 == funct3 )
tracer.Trace( "fsw %s, %lld(%s) # %.2f\n", freg_name( rs2 ), s_imm, reg_name( rs1 ), fregs[ rs2 ].f );
else if ( 3 == funct3 )
tracer.Trace( "fsd %s, %lld(%s), # %.2f\n", freg_name( rs2 ), s_imm, reg_name( rs1 ), fregs[ rs2 ].d );
}
break;
}
case ShiftType:
{
break;
}
case RType:
{
decode_R();
//tracer.Trace( "\nfunct7 %llx, rs2 %llx, rs1 %llx, funct3 %llx, rd %llx\n", funct7, rs2, rs1, funct3, rd );
if ( 0xa == opcode_type )
{
if ( 0 == funct7 )
tracer.Trace( "jr%s %s, %s, %s\n", cmp_type( funct3 ), reg_name( rs1 ), reg_name( rs2 ), reg_name( rd ) );
}
else if ( 0xb == opcode_type )
{
uint32_t top5 = (uint32_t) ( funct7 >> 2 );
if ( 0 == top5 )
{
if ( 2 == funct3 )
tracer.Trace( "amoadd.w %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
else if ( 3 == funct3 )
tracer.Trace( "amoadd.d %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
}
else if ( 1 == top5 )
{
if ( 2 == funct3 )
tracer.Trace( "amoswap.w %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
else if ( 3 == funct3 )
tracer.Trace( "amoswap.d %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
}
else if ( 2 == top5 )
{
if ( 2 == funct3 )
tracer.Trace( "lr.w %s, (%s)\n", reg_name( rd ), reg_name( rs1 ) );
else if ( 3 == funct3 )
tracer.Trace( "lr.d %s, (%s)\n", reg_name( rd ), reg_name( rs1 ) );
}
else if ( 3 == top5 )
{
if ( 2 == funct3 )
tracer.Trace( "sc.w %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
else if ( 3 == funct3 )
tracer.Trace( "sc.d %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
}
else if ( 4 == top5 )
{
if ( 2 == funct3 )
tracer.Trace( "amoxor.w %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
else if ( 3 == funct3 )
tracer.Trace( "amoxor.d %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
}
else if ( 8 == top5 )
{
if ( 2 == funct3 )
tracer.Trace( "amoor.w %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
else if ( 3 == funct3 )
tracer.Trace( "amoor.d %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
}
else if ( 0xc == top5 )
{
if ( 2 == funct3 )
tracer.Trace( "amoand.w %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
else if ( 3 == funct3 )
tracer.Trace( "amoand.d %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
}
else if ( 0x10 == top5 )
{
if ( 2 == funct3 )
tracer.Trace( "amomin.w %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
else if ( 3 == funct3 )
tracer.Trace( "amomin.d %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
}
else if ( 0x14 == top5 )
{
if ( 2 == funct3 )
tracer.Trace( "amomax.w %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
else if ( 3 == funct3 )
tracer.Trace( "amomax.d %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
}
else if ( 0x18 == top5 )
{
if ( 2 == funct3 )
tracer.Trace( "amominu.w %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
else if ( 3 == funct3 )
tracer.Trace( "amominu.d %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
}
else if ( 0x1c == top5 )
{
if ( 2 == funct3 )
tracer.Trace( "amomaxu.w %s, %s, (%s) # max( %u, %u )\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ),
(uint32_t) regs[ rs2 ], getui32( regs[ rs1 ] ) );
else if ( 3 == funct3 )
tracer.Trace( "amomaxu.d %s, %s, (%s)\n", reg_name( rd ), reg_name( rs2 ), reg_name( rs1 ) );
}
}
else if ( 0xc == opcode_type )
{
if ( 0 == funct7 )
{
if ( 0 == funct3 )
tracer.Trace( "add %s, %s, %s # %llx + %llx\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ), regs[ rs1 ], regs[ rs2 ] );
else if ( 1 == funct3 )
tracer.Trace( "sll %s, %s, %s\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ) );
else if ( 2 == funct3 )
tracer.Trace( "slt %s, %s, %s # %d == %lld < %lld\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ),
(int64_t) regs[rs1] < (int64_t) regs[rs2], regs[rs1], regs[rs2] );
else if ( 3 == funct3 )
tracer.Trace( "sltu %s, %s, %s # %d == %llu < %llu\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ),
regs[rs1] < regs[rs2], regs[rs1], regs[rs2] );
else if ( 4 == funct3 )
tracer.Trace( "xor %s, %s, %s # %d == %llx\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ), regs[rs1] ^ regs[rs2] );
else if ( 5 == funct3 )
tracer.Trace( "srl %s, %s, %s\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ) );
else if ( 6 == funct3 )
tracer.Trace( "or %s, %s, %s\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ) );
else if ( 7 == funct3 )
tracer.Trace( "and %s, %s, %s\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ) );
}
else if ( 1 == funct7 )
{
if ( 0 == funct3 )
tracer.Trace( "mul %s, %s, %s # %llx * %llx\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ), regs[ rs1 ], regs[ rs2 ] );
else if ( 1 == funct3 )
tracer.Trace( "mulh %s, %s, %s # %lld * %lld\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ), regs[ rs1 ], regs[ rs2 ] );
else if ( 2 == funct3 )
tracer.Trace( "mulhsu %s, %s, %s # %lld * %llu\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ), regs[ rs1 ], regs[ rs2 ] );
else if ( 3 == funct3 )
tracer.Trace( "mulhu %s, %s, %s # %llu * %llu\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ), regs[ rs1 ], regs[ rs2 ] );
else if ( 4 == funct3 )
tracer.Trace( "div %s, %s, %s # %lld / %lld\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ), regs[ rs1 ], regs[ rs2 ] );
else if ( 5 == funct3 )
tracer.Trace( "udiv %s, %s, %s # %llu / %llu\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ), regs[ rs1 ], regs[ rs2 ] );
else if ( 6 == funct3 )
tracer.Trace( "rem %s, %s, %s\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ) );
else if ( 7 == funct3 )
tracer.Trace( "remu %s, %s, %s\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ) );
}
else if ( 0x20 == funct7 )
{
if ( 0 == funct3 )
tracer.Trace( "sub %s, %s, %s\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ) );
else if ( 5== funct3 )
tracer.Trace( "sra %s, %s, %s\n", reg_name( rd ), reg_name( rs1 ), reg_name( rs2 ) );
}
}