diff --git a/config/boards/inovato-quadra.csc b/config/boards/inovato-quadra.conf similarity index 93% rename from config/boards/inovato-quadra.csc rename to config/boards/inovato-quadra.conf index abb5eb2afb90..b4a2be00f763 100644 --- a/config/boards/inovato-quadra.csc +++ b/config/boards/inovato-quadra.conf @@ -1,7 +1,7 @@ # Allwinner H6 quad core 2GB SoC WiFi eMMC BOARD_NAME="Inovato Quadra" BOARDFAMILY="sun50iw6" -BOARD_MAINTAINER="" +BOARD_MAINTAINER="NicoD-SBC" BOOTCONFIG="tanix_tx6_defconfig" CRUSTCONFIG="tanix_tx6_defconfig" BOOT_FDT_FILE="allwinner/sun50i-h6-inovato-quadra.dtb" diff --git a/config/bootscripts/boot-odroid-xu4.ini b/config/bootscripts/boot-odroid-xu4.ini index 41382e66ebda..42a95c35d8d3 100644 --- a/config/bootscripts/boot-odroid-xu4.ini +++ b/config/bootscripts/boot-odroid-xu4.ini @@ -281,7 +281,7 @@ if test "${cs2enable}" = "true"; then setenv overlays "i2c0 i2c1 hktft-cs-ogst" for overlay in ${overlays}; do - ext4load mmc 0:1 0x60000000 /boot/dtb/overlays/${overlay}.dtbo + ext4load mmc 0:1 0x60000000 /boot/dtb/${overlay}.dtbo fdt apply 0x60000000 done fi diff --git a/config/kernel/linux-meson-edge.config b/config/kernel/linux-meson-edge.config index 4b844120a9ff..91933cad6463 100644 --- a/config/kernel/linux-meson-edge.config +++ b/config/kernel/linux-meson-edge.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 6.8.9 Kernel Configuration +# Linux/arm 6.9.2 Kernel Configuration # CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0" CONFIG_CC_IS_GCC=y @@ -184,6 +184,7 @@ CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y CONFIG_CGROUP_MISC=y +# CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y @@ -211,9 +212,10 @@ CONFIG_LD_ORPHAN_WARN=y CONFIG_LD_ORPHAN_WARN_LEVEL="warn" CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y -# CONFIG_EXPERT is not set +CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y @@ -234,9 +236,12 @@ CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KCMP=y CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set CONFIG_CACHESTAT_SYSCALL=y +# CONFIG_PC104 is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_SELFTEST is not set +# CONFIG_KALLSYMS_ALL is not set CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_HAVE_PERF_EVENTS=y @@ -246,6 +251,7 @@ CONFIG_PERF_USE_VMALLOC=y # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set # end of Kernel Performance Events And Counters CONFIG_SYSTEM_DATA_VERIFICATION=y @@ -255,7 +261,6 @@ CONFIG_TRACEPOINTS=y # # Kexec and crash features # -CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_KEXEC=y # CONFIG_CRASH_DUMP is not set @@ -574,6 +579,7 @@ CONFIG_KERNEL_MODE_NEON=y # CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set # CONFIG_HIBERNATION is not set CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y @@ -657,8 +663,11 @@ CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_4KB=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SHIFT=12 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -704,6 +713,7 @@ CONFIG_MODULE_COMPRESS_NONE=y # CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" +# CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLOCK_LEGACY_AUTOLOAD=y @@ -808,6 +818,7 @@ CONFIG_ZSMALLOC_CHAIN_SIZE=8 # Slab allocator options # CONFIG_SLUB=y +# CONFIG_SLUB_TINY is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set @@ -841,6 +852,7 @@ CONFIG_CMA=y CONFIG_CMA_AREAS=7 CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CPU_CACHE_ALIASING=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y CONFIG_VM_EVENT_COUNTERS=y # CONFIG_PERCPU_STATS is not set @@ -876,7 +888,6 @@ CONFIG_SKB_EXTENSIONS=y CONFIG_PACKET=y CONFIG_PACKET_DIAG=m CONFIG_UNIX=y -CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y CONFIG_UNIX_DIAG=m CONFIG_TLS=m @@ -1253,6 +1264,7 @@ CONFIG_IP_VS_PE_SIP=m # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m +CONFIG_IP_NF_IPTABLES_LEGACY=m CONFIG_NF_SOCKET_IPV4=m CONFIG_NF_TPROXY_IPV4=m CONFIG_NF_TABLES_IPV4=y @@ -1284,6 +1296,7 @@ CONFIG_IP_NF_TARGET_ECN=m CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_ARPTABLES=m +CONFIG_NFT_COMPAT_ARP=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # end of IP: Netfilter Configuration @@ -1291,6 +1304,7 @@ CONFIG_IP_NF_ARP_MANGLE=m # # IPv6: Netfilter Configuration # +CONFIG_IP6_NF_IPTABLES_LEGACY=m CONFIG_NF_SOCKET_IPV6=m CONFIG_NF_TPROXY_IPV6=m CONFIG_NF_TABLES_IPV6=y @@ -1327,6 +1341,7 @@ CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES_LEGACY=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -1360,6 +1375,12 @@ CONFIG_IP_DCCP_CCID3=y CONFIG_IP_DCCP_TFRC_LIB=y # end of DCCP CCIDs Configuration +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +# end of DCCP Kernel Hacking + CONFIG_IP_SCTP=y # CONFIG_SCTP_DBG_OBJCNT is not set CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y @@ -1500,7 +1521,6 @@ CONFIG_NET_ACT_GACT=m CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=m CONFIG_NET_ACT_SAMPLE=m -CONFIG_NET_ACT_IPT=m CONFIG_NET_ACT_NAT=m CONFIG_NET_ACT_PEDIT=m CONFIG_NET_ACT_SIMP=m @@ -1593,6 +1613,7 @@ CONFIG_BT_LEDS=y CONFIG_BT_MSFTEXT=y CONFIG_BT_AOSPEXT=y CONFIG_BT_DEBUGFS=y +# CONFIG_BT_SELFTEST is not set CONFIG_BT_FEATURE_DEBUG=y # @@ -1656,6 +1677,7 @@ CONFIG_WEXT_PROC=y CONFIG_CFG80211=m # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y CONFIG_CFG80211_DEFAULT_PS=y @@ -1704,6 +1726,7 @@ CONFIG_ETHTOOL_NETLINK=y # Device Drivers # CONFIG_HAVE_PCI=y +CONFIG_GENERIC_PCI_IOMAP=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y @@ -1717,6 +1740,7 @@ CONFIG_PCIEASPM_DEFAULT=y # CONFIG_PCIE_PTM is not set CONFIG_PCI_MSI=y CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set CONFIG_PCI_ECAM=y # CONFIG_PCI_IOV is not set @@ -1724,6 +1748,11 @@ CONFIG_PCI_ECAM=y # CONFIG_PCI_PASID is not set CONFIG_PCI_LABEL=y # CONFIG_PCI_DYNAMIC_OF_NODES is not set +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 # CONFIG_HOTPLUG_PCI is not set @@ -1805,6 +1834,9 @@ CONFIG_FW_CACHE=y CONFIG_WANT_DEV_COREDUMP=y CONFIG_ALLOW_DEV_COREDUMP=y CONFIG_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y @@ -1854,6 +1886,7 @@ CONFIG_ARM_SCMI_POWER_CONTROL=m # end of ARM System Control and Management Interface Protocol # CONFIG_ARM_SCPI_PROTOCOL is not set +# CONFIG_FIRMWARE_MEMMAP is not set CONFIG_DMIID=y # CONFIG_DMI_SYSFS is not set # CONFIG_FW_CFG_SYSFS is not set @@ -2490,6 +2523,9 @@ CONFIG_MICROCHIP_PHY=m # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_NCN26000_PHY is not set # CONFIG_AT803X_PHY is not set +# CONFIG_QCA83XX_PHY is not set +# CONFIG_QCA808X_PHY is not set +# CONFIG_QCA807X_PHY is not set # CONFIG_QSEMI_PHY is not set CONFIG_REALTEK_PHY=y # CONFIG_RENESAS_PHY is not set @@ -2965,7 +3001,6 @@ CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y @@ -3015,6 +3050,7 @@ CONFIG_HVC_DRIVER=y # CONFIG_RPMSG_TTY is not set CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_TTY_PRINTK is not set CONFIG_VIRTIO_CONSOLE=y # CONFIG_IPMI_HANDLER is not set # CONFIG_SSIF_IPMI_BMC is not set @@ -3128,6 +3164,7 @@ CONFIG_I2C_SLAVE_EEPROM=y # CONFIG_I3C is not set CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y @@ -3206,6 +3243,8 @@ CONFIG_PINMUX=y CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AW9523 is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set @@ -3226,6 +3265,8 @@ CONFIG_PINCTRL_MESON8_PMX=y CONFIG_GPIOLIB=y CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y @@ -3394,9 +3435,11 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set CONFIG_SENSORS_ARM_SCMI=m # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CHIPCAP2 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set # CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DRIVETEMP is not set @@ -3433,6 +3476,7 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LTC4282 is not set # CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set @@ -3481,10 +3525,12 @@ CONFIG_SENSORS_IIO_HWMON=y # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set # CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set +# CONFIG_SENSORS_PT5161L is not set CONFIG_SENSORS_PWM_FAN=m # CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SBRMI is not set @@ -3543,7 +3589,6 @@ CONFIG_THERMAL=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -# CONFIG_THERMAL_WRITABLE_TRIPS is not set CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set @@ -4261,8 +4306,6 @@ CONFIG_VIDEOBUF2_VMALLOC=m CONFIG_VIDEOBUF2_DMA_SG=m # end of Media drivers -CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y - # # Media ancillary drivers # @@ -4370,23 +4413,109 @@ CONFIG_VIDEO_OV7640=m # end of Flash devices # -# audio, video and radio I2C drivers auto-selected by 'Autoselect ancillary drivers' +# Audio decoders, processors and mixers # +# CONFIG_VIDEO_CS3308 is not set +# CONFIG_VIDEO_CS5345 is not set CONFIG_VIDEO_CS53L32A=m CONFIG_VIDEO_MSP3400=m CONFIG_VIDEO_SONY_BTF_MPX=m +# CONFIG_VIDEO_TDA1997X is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_TVAUDIO is not set CONFIG_VIDEO_UDA1342=m +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_WM8739 is not set CONFIG_VIDEO_WM8775=m +# end of Audio decoders, processors and mixers + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set +# end of RDS decoders + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV748X is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_ISL7998X is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_SAA7110 is not set CONFIG_VIDEO_SAA711X=m +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TC358746 is not set +# CONFIG_VIDEO_TVP514X is not set CONFIG_VIDEO_TVP5150=m +# CONFIG_VIDEO_TVP7002 is not set CONFIG_VIDEO_TW2804=m +# CONFIG_VIDEO_TW9900 is not set CONFIG_VIDEO_TW9903=m CONFIG_VIDEO_TW9906=m +# CONFIG_VIDEO_TW9910 is not set +# CONFIG_VIDEO_VPX3220 is not set # # Video and audio decoders # +# CONFIG_VIDEO_SAA717X is not set CONFIG_VIDEO_CX25840=m +# end of Video decoders + +# +# Video encoders +# +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV7511 is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_THS8200 is not set +# end of Video encoders + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# end of Video improvement chips + +# +# Audio/Video compression chips +# +# CONFIG_VIDEO_SAA6752HS is not set +# end of Audio/Video compression chips + +# +# SDR tuner chips +# +# CONFIG_SDR_MAX2175 is not set +# end of SDR tuner chips + +# +# Miscellaneous helper chips +# +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# CONFIG_VIDEO_THS7303 is not set +# end of Miscellaneous helper chips # # Video serializers and deserializers @@ -4396,10 +4525,6 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_DS90UB960 is not set # end of Video serializers and deserializers -# -# SPI I2C drivers auto-selected by 'Autoselect ancillary drivers' -# - # # Media SPI Adapters # @@ -4410,7 +4535,7 @@ CONFIG_VIDEO_CX25840=m CONFIG_MEDIA_TUNER=m # -# Tuner drivers auto-selected by 'Autoselect ancillary drivers' +# Customize TV tuners # CONFIG_MEDIA_TUNER_E4000=m CONFIG_MEDIA_TUNER_FC0011=m @@ -4418,15 +4543,19 @@ CONFIG_MEDIA_TUNER_FC0012=m CONFIG_MEDIA_TUNER_FC0013=m CONFIG_MEDIA_TUNER_FC2580=m CONFIG_MEDIA_TUNER_IT913X=m +# CONFIG_MEDIA_TUNER_M88RS6000T is not set CONFIG_MEDIA_TUNER_MAX2165=m CONFIG_MEDIA_TUNER_MC44S803=m CONFIG_MEDIA_TUNER_MSI001=m CONFIG_MEDIA_TUNER_MT2060=m CONFIG_MEDIA_TUNER_MT2063=m CONFIG_MEDIA_TUNER_MT20XX=m +# CONFIG_MEDIA_TUNER_MT2131 is not set CONFIG_MEDIA_TUNER_MT2266=m +# CONFIG_MEDIA_TUNER_MXL301RF is not set CONFIG_MEDIA_TUNER_MXL5005S=m CONFIG_MEDIA_TUNER_MXL5007T=m +# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set CONFIG_MEDIA_TUNER_QM1D1C0042=m CONFIG_MEDIA_TUNER_QT1010=m CONFIG_MEDIA_TUNER_R820T=m @@ -4445,19 +4574,23 @@ CONFIG_MEDIA_TUNER_TUA9001=m CONFIG_MEDIA_TUNER_XC2028=m CONFIG_MEDIA_TUNER_XC4000=m CONFIG_MEDIA_TUNER_XC5000=m +# end of Customize TV tuners # -# DVB Frontend drivers auto-selected by 'Autoselect ancillary drivers' +# Customise DVB Frontends # # # Multistandard (satellite) frontends # CONFIG_DVB_M88DS3103=m +# CONFIG_DVB_MXL5XX is not set CONFIG_DVB_STB0899=m CONFIG_DVB_STB6100=m CONFIG_DVB_STV090x=m +# CONFIG_DVB_STV0910 is not set CONFIG_DVB_STV6110x=m +# CONFIG_DVB_STV6111 is not set # # Multistandard (cable + terrestrial) frontends @@ -4471,10 +4604,13 @@ CONFIG_DVB_TDA18271C2DD=m # # DVB-S (satellite) frontends # +# CONFIG_DVB_CX24110 is not set CONFIG_DVB_CX24116=m +# CONFIG_DVB_CX24117 is not set CONFIG_DVB_CX24120=m CONFIG_DVB_CX24123=m CONFIG_DVB_DS3000=m +# CONFIG_DVB_MB86A16 is not set CONFIG_DVB_MT312=m CONFIG_DVB_S5H1420=m CONFIG_DVB_SI21XX=m @@ -4486,10 +4622,14 @@ CONFIG_DVB_STV6110=m CONFIG_DVB_TDA10071=m CONFIG_DVB_TDA10086=m CONFIG_DVB_TDA8083=m +# CONFIG_DVB_TDA8261 is not set CONFIG_DVB_TDA826X=m CONFIG_DVB_TS2020=m +# CONFIG_DVB_TUA6100 is not set CONFIG_DVB_TUNER_CX24113=m CONFIG_DVB_TUNER_ITD1000=m +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_ZL10036 is not set CONFIG_DVB_ZL10039=m # @@ -4505,24 +4645,31 @@ CONFIG_DVB_DIB3000MB=m CONFIG_DVB_DIB3000MC=m CONFIG_DVB_DIB7000M=m CONFIG_DVB_DIB7000P=m +# CONFIG_DVB_DIB9000 is not set CONFIG_DVB_DRXD=m CONFIG_DVB_EC100=m CONFIG_DVB_GP8PSK_FE=m +# CONFIG_DVB_L64781 is not set CONFIG_DVB_MT352=m CONFIG_DVB_NXT6000=m CONFIG_DVB_RTL2830=m CONFIG_DVB_RTL2832=m CONFIG_DVB_RTL2832_SDR=m +# CONFIG_DVB_S5H1432 is not set CONFIG_DVB_SI2168=m +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_STV0367 is not set CONFIG_DVB_TDA10048=m CONFIG_DVB_TDA1004X=m CONFIG_DVB_ZD1301_DEMOD=m CONFIG_DVB_ZL10353=m +# CONFIG_DVB_CXD2880 is not set # # DVB-C (cable) frontends # CONFIG_DVB_STV0297=m +# CONFIG_DVB_TDA10021 is not set CONFIG_DVB_TDA10023=m CONFIG_DVB_VES1820=m @@ -4539,6 +4686,8 @@ CONFIG_DVB_LGDT3306A=m CONFIG_DVB_LGDT330X=m CONFIG_DVB_MXL692=m CONFIG_DVB_NXT200X=m +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_OR51211 is not set CONFIG_DVB_S5H1409=m CONFIG_DVB_S5H1411=m @@ -4552,6 +4701,7 @@ CONFIG_DVB_S921=m # # ISDB-S (satellite) & ISDB-T (terrestrial) frontends # +# CONFIG_DVB_MN88443X is not set CONFIG_DVB_TC90522=m # @@ -4566,20 +4716,30 @@ CONFIG_DVB_TUNER_DIB0090=m # CONFIG_DVB_A8293=m CONFIG_DVB_AF9033=m +# CONFIG_DVB_ASCOT2E is not set CONFIG_DVB_ATBM8830=m +# CONFIG_DVB_HELENE is not set +# CONFIG_DVB_HORUS3A is not set +# CONFIG_DVB_ISL6405 is not set CONFIG_DVB_ISL6421=m CONFIG_DVB_ISL6423=m CONFIG_DVB_IX2505V=m +# CONFIG_DVB_LGS8GL5 is not set CONFIG_DVB_LGS8GXX=m +# CONFIG_DVB_LNBH25 is not set +# CONFIG_DVB_LNBH29 is not set CONFIG_DVB_LNBP21=m CONFIG_DVB_LNBP22=m CONFIG_DVB_M88RS2000=m +# CONFIG_DVB_TDA665x is not set CONFIG_DVB_DRX39XYJ=m # # Common Interface (EN50221) controller drivers # +# CONFIG_DVB_CXD2099 is not set CONFIG_DVB_SP2=m +# end of Customise DVB Frontends # # Tools to develop new frontends @@ -4591,14 +4751,16 @@ CONFIG_DVB_SP2=m # Graphics support # CONFIG_APERTURE_HELPERS=y -CONFIG_VIDEO_CMDLINE=y -CONFIG_VIDEO_NOMODESET=y +CONFIG_VIDEO=y # CONFIG_AUXDISPLAY is not set CONFIG_DRM=y # CONFIG_DRM_DEBUG_MM is not set CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set CONFIG_DRM_DISPLAY_HELPER=y CONFIG_DRM_DISPLAY_HDMI_HELPER=y @@ -4628,6 +4790,7 @@ CONFIG_DRM_MALI_DISPLAY=y # CONFIG_DRM_RADEON is not set # CONFIG_DRM_AMDGPU is not set # CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_XE is not set # CONFIG_DRM_VGEM is not set # CONFIG_DRM_VKMS is not set # CONFIG_DRM_UDL is not set @@ -4646,12 +4809,9 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_AUO_A030JTN01 is not set # CONFIG_DRM_PANEL_LVDS is not set -# CONFIG_DRM_PANEL_SIMPLE is not set -# CONFIG_DRM_PANEL_EDP is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set @@ -4659,17 +4819,20 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set # CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set # CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_EDP is not set +# CONFIG_DRM_PANEL_SIMPLE is not set # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set @@ -4730,8 +4893,8 @@ CONFIG_DRM_DW_HDMI=y # CONFIG_DRM_LOGICVC is not set CONFIG_DRM_MESON=y CONFIG_DRM_MESON_DW_HDMI=y -# CONFIG_DRM_MESON_DW_MIPI_DSI is not set CONFIG_DRM_MESON_TRANSWITCH_HDMI=y +# CONFIG_DRM_MESON_DW_MIPI_DSI is not set # CONFIG_DRM_ARCPGU is not set # CONFIG_DRM_BOCHS is not set # CONFIG_DRM_CIRRUS_QEMU is not set @@ -4826,6 +4989,7 @@ CONFIG_FB_MODE_HELPERS=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=m # CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set # CONFIG_BACKLIGHT_PWM is not set # CONFIG_BACKLIGHT_QCOM_WLED is not set @@ -5335,6 +5499,7 @@ CONFIG_USB_OTG=y # CONFIG_USB_OTG_FSM is not set CONFIG_USB_LEDS_TRIGGER_USBPORT=y CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 # CONFIG_USB_MON is not set # @@ -5523,6 +5688,7 @@ CONFIG_USB_ULPI_VIEWPORT=y # end of USB Physical Layer drivers CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set # CONFIG_USB_GADGET_DEBUG_FILES is not set # CONFIG_USB_GADGET_DEBUG_FS is not set CONFIG_USB_GADGET_VBUS_DRAW=2 @@ -5682,8 +5848,6 @@ CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_LP3952 is not set -# CONFIG_LEDS_LP50XX is not set -# CONFIG_LEDS_LP55XX_COMMON is not set # CONFIG_LEDS_LP8860 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -6240,6 +6404,7 @@ CONFIG_IIO_TRIGGERED_EVENT=m # CONFIG_AD7923 is not set # CONFIG_AD7949 is not set # CONFIG_AD799X is not set +# CONFIG_AD9467 is not set # CONFIG_ADI_AXI_ADC is not set # CONFIG_CC10001_ADC is not set # CONFIG_ENVELOPE_DETECTOR is not set @@ -6266,6 +6431,7 @@ CONFIG_IIO_TRIGGERED_EVENT=m # CONFIG_MCP3911 is not set CONFIG_MESON_SARADC=m # CONFIG_NAU7802 is not set +# CONFIG_PAC1934 is not set # CONFIG_RICHTEK_RTQ6056 is not set # CONFIG_SD_ADC_MODULATOR is not set # CONFIG_TI_ADC081C is not set @@ -6278,6 +6444,7 @@ CONFIG_MESON_SARADC=m # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS7924 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS7950 is not set # CONFIG_TI_ADS8344 is not set # CONFIG_TI_ADS8688 is not set @@ -6427,6 +6594,7 @@ CONFIG_MESON_SARADC=m # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set # CONFIG_ADF4377 is not set +# CONFIG_ADMFM2000 is not set # CONFIG_ADMV1013 is not set # CONFIG_ADMV4420 is not set # CONFIG_ADRF6780 is not set @@ -6563,6 +6731,7 @@ CONFIG_MPU3050_I2C=y # # Magnetometer sensors # +# CONFIG_AF8133J is not set # CONFIG_AK8974 is not set # CONFIG_AK8975 is not set # CONFIG_AK09911 is not set @@ -6705,6 +6874,7 @@ CONFIG_IIO_HRTIMER_TRIGGER=y # CONFIG_NTB is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set # CONFIG_PWM_ATMEL_TCB is not set # CONFIG_PWM_CLK is not set # CONFIG_PWM_DWC is not set @@ -6726,9 +6896,11 @@ CONFIG_MESON_IRQ_GPIO=y # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_GPIO is not set CONFIG_RESET_MESON=y CONFIG_RESET_MESON_AUDIO_ARB=m CONFIG_RESET_SCMI=m +# CONFIG_RESET_SIMPLE is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RESET_TI_TPS380X is not set @@ -6885,6 +7057,9 @@ CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y CONFIG_XFS_DRAIN_INTENTS=y +CONFIG_XFS_LIVE_HOOKS=y +CONFIG_XFS_MEMORY_BUFS=y +CONFIG_XFS_BTREE_IN_MEM=y CONFIG_XFS_ONLINE_SCRUB=y CONFIG_XFS_ONLINE_SCRUB_STATS=y CONFIG_XFS_ONLINE_REPAIR=y @@ -6944,6 +7119,7 @@ CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=y CONFIG_CUSE=y CONFIG_VIRTIO_FS=y +CONFIG_FUSE_PASSTHROUGH=y CONFIG_OVERLAY_FS=y # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -6985,12 +7161,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_FAT_DEFAULT_UTF8=y CONFIG_EXFAT_FS=y CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" -CONFIG_NTFS_FS=y -# CONFIG_NTFS_DEBUG is not set -CONFIG_NTFS_RW=y CONFIG_NTFS3_FS=y CONFIG_NTFS3_LZX_XPRESS=y CONFIG_NTFS3_FS_POSIX_ACL=y +CONFIG_NTFS_FS=y # end of DOS/FAT/EXFAT/NT Filesystems # @@ -7507,7 +7681,6 @@ CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=m CONFIG_PRIME_NUMBERS=m CONFIG_RATIONAL=y -CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # @@ -7619,6 +7792,7 @@ CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set # CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y +# CONFIG_FORCE_NR_CPUS is not set CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_GLOB=y @@ -7662,23 +7836,32 @@ CONFIG_PRINTK_TIME=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_DYNAMIC_DEBUG_CORE is not set CONFIG_SYMBOLIC_ERRNAME=y CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options -# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y # # Compile-time checks and compiler options # CONFIG_AS_HAS_NON_CONST_ULEB128=y +CONFIG_DEBUG_INFO_NONE=y +# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set # CONFIG_HEADERS_INSTALL is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_VMLINUX_MAP is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options # @@ -7693,7 +7876,8 @@ CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN=y # CONFIG_UBSAN is not set CONFIG_HAVE_KCSAN_COMPILER=y # end of Generic Kernel Debugging Instruments @@ -7701,22 +7885,36 @@ CONFIG_HAVE_KCSAN_COMPILER=y # # Networking Debugging # +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# CONFIG_DEBUG_NET is not set # end of Networking Debugging # # Memory Debugging # # CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set CONFIG_SLUB_DEBUG=y # CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_PAGE_REF is not set # CONFIG_DEBUG_RODATA_TEST is not set -# CONFIG_DEBUG_WX is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_PER_VMA_LOCK_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set # CONFIG_SHRINKER_DEBUG is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_SCHED_STACK_END_CHECK is not set +# CONFIG_DEBUG_VM is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_KMAP_LOCAL is not set +# CONFIG_DEBUG_HIGHMEM is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y @@ -7726,20 +7924,29 @@ CONFIG_HAVE_ARCH_KFENCE=y # CONFIG_KFENCE is not set # end of Memory Debugging +# CONFIG_DEBUG_SHIRQ is not set + # # Debug Oops, Lockups and Hangs # # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SOFTLOCKUP_DETECTOR is not set CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set # CONFIG_TEST_LOCKUP is not set # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # +CONFIG_SCHED_DEBUG=y CONFIG_SCHED_INFO=y +# CONFIG_SCHEDSTATS is not set # end of Scheduler Debugging # CONFIG_DEBUG_TIMEKEEPING is not set @@ -7748,27 +7955,54 @@ CONFIG_SCHED_INFO=y # Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set # CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set # end of Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set # # Debug kernel data structures # +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_DEBUG_CLOSURES is not set +# CONFIG_DEBUG_MAPLE_TREE is not set # end of Debug kernel data structures # # RCU Debugging # +# CONFIG_RCU_SCALE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=21 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 # CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_RCU_TRACE=y +# CONFIG_RCU_EQS_DEBUG is not set # end of RCU Debugging +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_DEBUG_CGROUP_REF is not set CONFIG_NOP_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y @@ -7823,10 +8057,14 @@ CONFIG_PROBE_EVENTS=y # # arm Debugging # +# CONFIG_ARM_PTDUMP_DEBUGFS is not set +# CONFIG_ARM_DEBUG_WX is not set # CONFIG_UNWINDER_FRAME_POINTER is not set CONFIG_UNWINDER_ARM=y CONFIG_ARM_UNWIND=y +# CONFIG_BACKTRACE_VERBOSE is not set # CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_LL is not set CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" # CONFIG_ARM_KPROBES_TEST is not set @@ -7838,7 +8076,9 @@ CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" # Kernel Testing and Coverage # # CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set # CONFIG_FUNCTION_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set @@ -7847,12 +8087,15 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_LKDTM is not set # CONFIG_TEST_MIN_HEAP is not set # CONFIG_TEST_DIV64 is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set +# CONFIG_RBTREE_TEST is not set # CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set # CONFIG_ASYNC_RAID6_TEST is not set # CONFIG_TEST_HEXDUMP is not set -# CONFIG_STRING_SELFTEST is not set -# CONFIG_TEST_STRING_HELPERS is not set # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set # CONFIG_TEST_SCANF is not set @@ -7877,6 +8120,7 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_MEMCAT_P is not set # CONFIG_TEST_MEMINIT is not set # CONFIG_TEST_FREE_PAGES is not set +# CONFIG_TEST_OBJPOOL is not set CONFIG_ARCH_USE_MEMTEST=y # CONFIG_MEMTEST is not set # end of Kernel Testing and Coverage diff --git a/config/kernel/linux-meson64-edge.config b/config/kernel/linux-meson64-edge.config index ee68501d48b4..9a0ab52bc789 100644 --- a/config/kernel/linux-meson64-edge.config +++ b/config/kernel/linux-meson64-edge.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.8.9 Kernel Configuration +# Linux/arm64 6.9.2 Kernel Configuration # CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0" CONFIG_CC_IS_GCC=y @@ -11,8 +11,6 @@ CONFIG_AS_VERSION=23800 CONFIG_LD_IS_BFD=y CONFIG_LD_VERSION=23800 CONFIG_LLD_VERSION=0 -CONFIG_CC_CAN_LINK=y -CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y @@ -193,6 +191,7 @@ CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y # CONFIG_CGROUP_MISC is not set +# CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y @@ -222,9 +221,10 @@ CONFIG_LD_ORPHAN_WARN_LEVEL="warn" CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y -# CONFIG_EXPERT is not set +CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y @@ -245,9 +245,12 @@ CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KCMP=y CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set CONFIG_CACHESTAT_SYSCALL=y +# CONFIG_PC104 is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_SELFTEST is not set +# CONFIG_KALLSYMS_ALL is not set CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_HAVE_PERF_EVENTS=y @@ -257,6 +260,7 @@ CONFIG_GUEST_PERF_EVENTS=y # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set # end of Kernel Performance Events And Counters CONFIG_SYSTEM_DATA_VERIFICATION=y @@ -265,7 +269,8 @@ CONFIG_PROFILING=y # # Kexec and crash features # -CONFIG_CRASH_CORE=y +CONFIG_CRASH_RESERVE=y +CONFIG_VMCORE_INFO=y CONFIG_KEXEC_CORE=y CONFIG_KEXEC=y # CONFIG_KEXEC_FILE is not set @@ -277,7 +282,6 @@ CONFIG_ARM64=y CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_64BIT=y CONFIG_MMU=y -CONFIG_ARM64_PAGE_SHIFT=12 CONFIG_ARM64_CONT_PTE_SHIFT=4 CONFIG_ARM64_CONT_PMD_SHIFT=4 CONFIG_ARCH_MMAP_RND_BITS_MIN=18 @@ -407,6 +411,7 @@ CONFIG_ARM64_4K_PAGES=y # CONFIG_ARM64_64K_PAGES is not set # CONFIG_ARM64_VA_BITS_39 is not set CONFIG_ARM64_VA_BITS_48=y +# CONFIG_ARM64_VA_BITS_52 is not set CONFIG_ARM64_VA_BITS=48 CONFIG_ARM64_PA_BITS_48=y CONFIG_ARM64_PA_BITS=48 @@ -517,6 +522,7 @@ CONFIG_RELOCATABLE=y # CONFIG_RANDOMIZE_BASE is not set CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y CONFIG_STACKPROTECTOR_PER_TASK=y +CONFIG_ARM64_CONTPTE=y # end of Kernel Features # @@ -534,9 +540,13 @@ CONFIG_DMI=y # CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set CONFIG_HIBERNATE_CALLBACKS=y CONFIG_HIBERNATION=y CONFIG_HIBERNATION_SNAPSHOT_DEV=y +CONFIG_HIBERNATION_COMP_LZO=y +# CONFIG_HIBERNATION_COMP_LZ4 is not set +CONFIG_HIBERNATION_DEF_COMP="lzo" CONFIG_PM_STD_PARTITION="" CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y @@ -605,10 +615,10 @@ CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # CONFIG_CPUFREQ_DT=y CONFIG_CPUFREQ_DT_PLATDEV=y -CONFIG_ACPI_CPPC_CPUFREQ=m -CONFIG_ACPI_CPPC_CPUFREQ_FIE=y CONFIG_ARM_SCPI_CPUFREQ=y CONFIG_ARM_SCMI_CPUFREQ=m +CONFIG_ACPI_CPPC_CPUFREQ=m +CONFIG_ACPI_CPPC_CPUFREQ_FIE=y # end of CPU Frequency scaling # end of CPU Power Management @@ -641,7 +651,6 @@ CONFIG_ACPI_TABLE_UPGRADE=y # CONFIG_ACPI_PCI_SLOT is not set CONFIG_ACPI_CONTAINER=y CONFIG_ACPI_HED=y -# CONFIG_ACPI_CUSTOM_METHOD is not set # CONFIG_ACPI_BGRT is not set CONFIG_ACPI_REDUCED_HARDWARE_ONLY=y CONFIG_ACPI_NUMA=y @@ -652,6 +661,7 @@ CONFIG_ACPI_APEI_GHES=y CONFIG_ACPI_APEI_SEA=y CONFIG_ACPI_APEI_MEMORY_FAILURE=y CONFIG_ACPI_APEI_EINJ=y +CONFIG_ACPI_APEI_EINJ_CXL=y # CONFIG_ACPI_APEI_ERST_DEBUG is not set CONFIG_ACPI_WATCHDOG=y # CONFIG_ACPI_CONFIGFS is not set @@ -664,7 +674,6 @@ CONFIG_ACPI_PCC=y # CONFIG_ACPI_FFH is not set # CONFIG_PMIC_OPREGION is not set CONFIG_ACPI_PRMT=y -CONFIG_HAVE_KVM=y CONFIG_KVM_COMMON=y CONFIG_HAVE_KVM_IRQCHIP=y CONFIG_HAVE_KVM_IRQ_ROUTING=y @@ -673,6 +682,7 @@ CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP=y CONFIG_KVM_MMIO=y CONFIG_HAVE_KVM_MSI=y +CONFIG_HAVE_KVM_READONLY_MEM=y CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y CONFIG_KVM_VFIO=y CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y @@ -718,6 +728,7 @@ CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_RUST=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y @@ -765,8 +776,11 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_4KB=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SHIFT=12 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -823,6 +837,7 @@ CONFIG_MODULE_COMPRESS_NONE=y # CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" +# CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLOCK_LEGACY_AUTOLOAD=y @@ -909,7 +924,6 @@ CONFIG_ZPOOL=y CONFIG_SWAP=y CONFIG_ZSWAP=y CONFIG_ZSWAP_DEFAULT_ON=y -# CONFIG_ZSWAP_EXCLUSIVE_LOADS_DEFAULT_ON is not set # CONFIG_ZSWAP_SHRINKER_DEFAULT_ON is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set @@ -932,6 +946,7 @@ CONFIG_ZSMALLOC_CHAIN_SIZE=8 # Slab allocator options # CONFIG_SLUB=y +# CONFIG_SLUB_TINY is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set @@ -972,6 +987,7 @@ CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_MEMORY_FAILURE=y +# CONFIG_HWPOISON_INJECT is not set CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y @@ -993,6 +1009,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_ARCH_HAS_ZONE_DMA_SET=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y CONFIG_GET_FREE_REGION=y @@ -1037,7 +1054,6 @@ CONFIG_SKB_EXTENSIONS=y CONFIG_PACKET=y CONFIG_PACKET_DIAG=m CONFIG_UNIX=y -CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y CONFIG_UNIX_DIAG=m CONFIG_TLS=m @@ -1419,6 +1435,7 @@ CONFIG_IP_VS_PE_SIP=m # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m +CONFIG_IP_NF_IPTABLES_LEGACY=m CONFIG_NF_SOCKET_IPV4=m CONFIG_NF_TPROXY_IPV4=m CONFIG_NF_TABLES_IPV4=y @@ -1451,6 +1468,7 @@ CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_SECURITY=m CONFIG_IP_NF_ARPTABLES=m +CONFIG_NFT_COMPAT_ARP=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # end of IP: Netfilter Configuration @@ -1458,6 +1476,7 @@ CONFIG_IP_NF_ARP_MANGLE=m # # IPv6: Netfilter Configuration # +CONFIG_IP6_NF_IPTABLES_LEGACY=m CONFIG_NF_SOCKET_IPV6=m CONFIG_NF_TPROXY_IPV6=m CONFIG_NF_TABLES_IPV6=y @@ -1495,6 +1514,7 @@ CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES_LEGACY=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -1528,6 +1548,12 @@ CONFIG_IP_DCCP_CCID3=y CONFIG_IP_DCCP_TFRC_LIB=y # end of DCCP CCIDs Configuration +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +# end of DCCP Kernel Hacking + CONFIG_IP_SCTP=m CONFIG_SCTP_DBG_OBJCNT=y CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y @@ -1692,7 +1718,6 @@ CONFIG_NET_ACT_GACT=m CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=m CONFIG_NET_ACT_SAMPLE=m -CONFIG_NET_ACT_IPT=m CONFIG_NET_ACT_NAT=m CONFIG_NET_ACT_PEDIT=m CONFIG_NET_ACT_SIMP=m @@ -1809,6 +1834,7 @@ CONFIG_BT_LEDS=y # CONFIG_BT_MSFTEXT is not set # CONFIG_BT_AOSPEXT is not set # CONFIG_BT_DEBUGFS is not set +# CONFIG_BT_SELFTEST is not set # # Bluetooth device drivers @@ -1875,6 +1901,7 @@ CONFIG_WEXT_PRIV=y CONFIG_CFG80211=m # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y # CONFIG_CFG80211_DEFAULT_PS is not set @@ -1976,6 +2003,7 @@ CONFIG_NET_TEST=m # CONFIG_ARM_AMBA=y CONFIG_HAVE_PCI=y +CONFIG_GENERIC_PCI_IOMAP=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y @@ -1989,6 +2017,7 @@ CONFIG_PCIEASPM_DEFAULT=y # CONFIG_PCIE_PTM is not set CONFIG_PCI_MSI=y CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set # CONFIG_PCI_STUB is not set # CONFIG_PCI_PF_STUB is not set @@ -2001,6 +2030,11 @@ CONFIG_PCI_IOV=y CONFIG_PCI_LABEL=y # CONFIG_PCI_HYPERV is not set # CONFIG_PCI_DYNAMIC_OF_NODES is not set +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 CONFIG_HOTPLUG_PCI=y @@ -2071,7 +2105,6 @@ CONFIG_CXL_PORT=m CONFIG_CXL_SUSPEND=y CONFIG_CXL_REGION=y # CONFIG_CXL_REGION_INVALIDATION_TEST is not set -CONFIG_CXL_PMU=m # CONFIG_PCCARD is not set # CONFIG_RAPIDIO is not set @@ -2105,6 +2138,9 @@ CONFIG_FW_UPLOAD=y CONFIG_WANT_DEV_COREDUMP=y CONFIG_ALLOW_DEV_COREDUMP=y CONFIG_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set CONFIG_HMEM_REPORTING=y # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set # CONFIG_DM_KUNIT_TEST is not set @@ -2172,6 +2208,7 @@ CONFIG_ARM_SCMI_POWER_CONTROL=m CONFIG_ARM_SCPI_PROTOCOL=y # CONFIG_ARM_SDE_INTERFACE is not set +# CONFIG_FIRMWARE_MEMMAP is not set CONFIG_DMIID=y # CONFIG_DMI_SYSFS is not set # CONFIG_ISCSI_IBFT is not set @@ -2209,7 +2246,6 @@ CONFIG_UEFI_CPER=y CONFIG_UEFI_CPER_ARM=y # CONFIG_TEE_STMM_EFI is not set CONFIG_MESON_SM=y -CONFIG_MESON_GX_PM=y CONFIG_ARM_PSCI_FW=y # CONFIG_ARM_PSCI_CHECKER is not set @@ -2296,7 +2332,6 @@ CONFIG_MTD_PHYSMAP=m # CONFIG_MTD_PHYSMAP_OF is not set # CONFIG_MTD_PHYSMAP_GPIO_ADDR is not set CONFIG_MTD_PCI=m -# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # end of Mapping drivers for chip access @@ -2385,6 +2420,7 @@ CONFIG_MTD_HYPERBUS=m CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set +CONFIG_OF_KUNIT_TEST=m CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_KOBJ=y @@ -2531,6 +2567,7 @@ CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_PROC_FS is not set +CONFIG_SCSI_LIB_KUNIT_TEST=m # # SCSI support type (disk, tape, CD-ROM) @@ -2544,6 +2581,7 @@ CONFIG_BLK_DEV_BSG=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_PROTO_TEST=m # # SCSI Transports @@ -2765,6 +2803,7 @@ CONFIG_DM_LOG_WRITES=m CONFIG_DM_INTEGRITY=m CONFIG_DM_ZONED=m CONFIG_DM_AUDIT=y +# CONFIG_DM_VDO is not set CONFIG_TARGET_CORE=m CONFIG_TCM_IBLOCK=m CONFIG_TCM_FILEIO=m @@ -2884,10 +2923,8 @@ CONFIG_NET_DSA_XRS700X=m CONFIG_NET_DSA_XRS700X_I2C=m CONFIG_NET_DSA_XRS700X_MDIO=m CONFIG_NET_DSA_REALTEK=m -CONFIG_NET_DSA_REALTEK_MDIO=m -CONFIG_NET_DSA_REALTEK_SMI=m -CONFIG_NET_DSA_REALTEK_RTL8365MB=m -CONFIG_NET_DSA_REALTEK_RTL8366RB=m +# CONFIG_NET_DSA_REALTEK_MDIO is not set +# CONFIG_NET_DSA_REALTEK_SMI is not set CONFIG_NET_DSA_SMSC_LAN9303=m CONFIG_NET_DSA_SMSC_LAN9303_I2C=m CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m @@ -3030,6 +3067,7 @@ CONFIG_OCTEONTX2_MBOX=m CONFIG_OCTEONTX2_PF=m CONFIG_OCTEONTX2_VF=m CONFIG_OCTEON_EP=m +# CONFIG_OCTEON_EP_VF is not set CONFIG_PRESTERA=m CONFIG_PRESTERA_PCI=m CONFIG_NET_VENDOR_MELLANOX=y @@ -3209,7 +3247,11 @@ CONFIG_MOTORCOMM_PHY=m CONFIG_NXP_C45_TJA11XX_PHY=m CONFIG_NXP_TJA11XX_PHY=m # CONFIG_NCN26000_PHY is not set +CONFIG_QCOM_NET_PHYLIB=m CONFIG_AT803X_PHY=m +# CONFIG_QCA83XX_PHY is not set +# CONFIG_QCA808X_PHY is not set +# CONFIG_QCA807X_PHY is not set # CONFIG_QSEMI_PHY is not set CONFIG_REALTEK_PHY=m # CONFIG_RENESAS_PHY is not set @@ -3250,6 +3292,7 @@ CONFIG_CAN_CC770_PLATFORM=m CONFIG_CAN_CTUCANFD=m CONFIG_CAN_CTUCANFD_PCI=m CONFIG_CAN_CTUCANFD_PLATFORM=m +# CONFIG_CAN_ESD_402_PCI is not set # CONFIG_CAN_IFI_CANFD is not set CONFIG_CAN_M_CAN=m CONFIG_CAN_M_CAN_PCI=m @@ -3849,6 +3892,8 @@ CONFIG_TOUCHSCREEN_DA9052=m CONFIG_TOUCHSCREEN_EXC3000=m # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set # CONFIG_TOUCHSCREEN_HIDEEP is not set CONFIG_TOUCHSCREEN_HYCON_HY46XX=m # CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set @@ -3925,7 +3970,6 @@ CONFIG_TOUCHSCREEN_IQS5XX=m # CONFIG_TOUCHSCREEN_IQS7211 is not set CONFIG_TOUCHSCREEN_ZINITIX=m # CONFIG_TOUCHSCREEN_HIMAX_HX83112B is not set -CONFIG_TOUCHSCREEN_DWAV_USB_MT=m CONFIG_INPUT_MISC=y CONFIG_INPUT_88PM860X_ONKEY=m CONFIG_INPUT_88PM80X_ONKEY=m @@ -4028,7 +4072,6 @@ CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y @@ -4118,6 +4161,7 @@ CONFIG_HVC_XEN_FRONTEND=y # CONFIG_RPMSG_TTY is not set CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_TTY_PRINTK is not set CONFIG_VIRTIO_CONSOLE=y CONFIG_IPMI_HANDLER=m CONFIG_IPMI_DMI_DECODE=y @@ -4289,6 +4333,7 @@ CONFIG_DW_I3C_MASTER=m CONFIG_SVC_I3C_MASTER=m CONFIG_MIPI_I3C_HCI=m CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y @@ -4383,6 +4428,7 @@ CONFIG_PTP_1588_CLOCK_INES=m CONFIG_PTP_1588_CLOCK_KVM=m CONFIG_PTP_1588_CLOCK_IDT82P33=m CONFIG_PTP_1588_CLOCK_IDTCM=m +# CONFIG_PTP_1588_CLOCK_FC3W is not set # CONFIG_PTP_1588_CLOCK_MOCK is not set CONFIG_PTP_1588_CLOCK_OCP=m # end of PTP clock support @@ -4393,9 +4439,11 @@ CONFIG_PINMUX=y CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set CONFIG_PINCTRL_AMD=y CONFIG_PINCTRL_AS3722=m CONFIG_PINCTRL_AXP209=m +# CONFIG_PINCTRL_AW9523 is not set CONFIG_PINCTRL_CY8C95X0=m CONFIG_PINCTRL_DA9062=m CONFIG_PINCTRL_MAX77620=y @@ -4436,6 +4484,8 @@ CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIO_ACPI=y CONFIG_GPIOLIB_IRQCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y @@ -4491,6 +4541,7 @@ CONFIG_GPIO_ARIZONA=m CONFIG_GPIO_BD71815=m CONFIG_GPIO_BD71828=m CONFIG_GPIO_BD9571MWV=m +# CONFIG_GPIO_CROS_EC is not set CONFIG_GPIO_DA9052=m CONFIG_GPIO_DA9055=m CONFIG_GPIO_DLN2=m @@ -4564,6 +4615,7 @@ CONFIG_W1_MASTER_DS2490=m CONFIG_W1_MASTER_DS2482=m CONFIG_W1_MASTER_GPIO=m CONFIG_W1_MASTER_SGI=m +# CONFIG_W1_MASTER_UART is not set # end of 1-wire Bus Masters # @@ -4596,7 +4648,6 @@ CONFIG_POWER_RESET_ATC260X=m # CONFIG_POWER_RESET_GPIO is not set # CONFIG_POWER_RESET_GPIO_RESTART is not set # CONFIG_POWER_RESET_ODROID_GO_ULTRA_POWEROFF is not set -CONFIG_POWER_RESET_MESON64=y # CONFIG_POWER_RESET_LTC2952 is not set # CONFIG_POWER_RESET_MT6323 is not set # CONFIG_POWER_RESET_REGULATOR is not set @@ -4718,10 +4769,12 @@ CONFIG_SENSORS_AHT10=m CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m CONFIG_SENSORS_AS370=m CONFIG_SENSORS_ASC7621=m +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set CONFIG_SENSORS_AXI_FAN_CONTROL=m CONFIG_SENSORS_ARM_SCMI=m CONFIG_SENSORS_ARM_SCPI=m CONFIG_SENSORS_ATXP1=m +# CONFIG_SENSORS_CHIPCAP2 is not set CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_CORSAIR_PSU=m CONFIG_SENSORS_DRIVETEMP=m @@ -4765,6 +4818,7 @@ CONFIG_SENSORS_LTC4222=m CONFIG_SENSORS_LTC4245=m CONFIG_SENSORS_LTC4260=m CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_LTC4282 is not set CONFIG_SENSORS_MAX1111=m CONFIG_SENSORS_MAX127=m CONFIG_SENSORS_MAX16065=m @@ -4815,6 +4869,7 @@ CONFIG_SENSORS_NCT7802=m CONFIG_SENSORS_NCT7904=m CONFIG_SENSORS_NPCM7XX=m CONFIG_SENSORS_NZXT_KRAKEN2=m +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set CONFIG_SENSORS_NZXT_SMART2=m CONFIG_SENSORS_OCC_P8_I2C=m CONFIG_SENSORS_OCC=m @@ -4862,6 +4917,7 @@ CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP5023=m # CONFIG_SENSORS_MP5990 is not set # CONFIG_SENSORS_MPQ7932 is not set +# CONFIG_SENSORS_MPQ8785 is not set CONFIG_SENSORS_PIM4328=m CONFIG_SENSORS_PLI1209BC=m # CONFIG_SENSORS_PLI1209BC_REGULATOR is not set @@ -4879,6 +4935,7 @@ CONFIG_SENSORS_XDPE152=m CONFIG_SENSORS_XDPE122=m # CONFIG_SENSORS_XDPE122_REGULATOR is not set CONFIG_SENSORS_ZL6100=m +# CONFIG_SENSORS_PT5161L is not set CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_SBTSI=m CONFIG_SENSORS_SBRMI=m @@ -4948,7 +5005,6 @@ CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set @@ -4991,6 +5047,7 @@ CONFIG_WATCHDOG_PRETIMEOUT_DEFAULT_GOV_NOOP=y CONFIG_SOFT_WATCHDOG=m CONFIG_SOFT_WATCHDOG_PRETIMEOUT=y CONFIG_BD957XMUF_WATCHDOG=m +# CONFIG_CROS_EC_WATCHDOG is not set CONFIG_DA9052_WATCHDOG=m CONFIG_DA9055_WATCHDOG=m CONFIG_DA9063_WATCHDOG=m @@ -5891,8 +5948,6 @@ CONFIG_VIDEOBUF2_DMA_SG=m CONFIG_VIDEOBUF2_DVB=m # end of Media drivers -CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y - # # Media ancillary drivers # @@ -6005,30 +6060,59 @@ CONFIG_VIDEO_LM3646=m # end of Flash devices # -# audio, video and radio I2C drivers auto-selected by 'Autoselect ancillary drivers' +# Audio decoders, processors and mixers # CONFIG_VIDEO_CS3308=m CONFIG_VIDEO_CS5345=m CONFIG_VIDEO_CS53L32A=m CONFIG_VIDEO_MSP3400=m CONFIG_VIDEO_SONY_BTF_MPX=m +# CONFIG_VIDEO_TDA1997X is not set CONFIG_VIDEO_TDA7432=m +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set CONFIG_VIDEO_TVAUDIO=m CONFIG_VIDEO_UDA1342=m CONFIG_VIDEO_VP27SMPX=m CONFIG_VIDEO_WM8739=m CONFIG_VIDEO_WM8775=m +# end of Audio decoders, processors and mixers + +# +# RDS decoders +# CONFIG_VIDEO_SAA6588=m +# end of RDS decoders + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV748X is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842 is not set CONFIG_VIDEO_BT819=m CONFIG_VIDEO_BT856=m CONFIG_VIDEO_BT866=m +# CONFIG_VIDEO_ISL7998X is not set CONFIG_VIDEO_KS0127=m +# CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_ML86V7667 is not set CONFIG_VIDEO_SAA7110=m CONFIG_VIDEO_SAA711X=m +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TC358746 is not set +# CONFIG_VIDEO_TVP514X is not set CONFIG_VIDEO_TVP5150=m +# CONFIG_VIDEO_TVP7002 is not set CONFIG_VIDEO_TW2804=m +# CONFIG_VIDEO_TW9900 is not set CONFIG_VIDEO_TW9903=m CONFIG_VIDEO_TW9906=m +# CONFIG_VIDEO_TW9910 is not set CONFIG_VIDEO_VPX3220=m # @@ -6036,14 +6120,49 @@ CONFIG_VIDEO_VPX3220=m # CONFIG_VIDEO_SAA717X=m CONFIG_VIDEO_CX25840=m +# end of Video decoders + +# +# Video encoders +# CONFIG_VIDEO_ADV7170=m CONFIG_VIDEO_ADV7175=m +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV7511 is not set +# CONFIG_VIDEO_AK881X is not set CONFIG_VIDEO_SAA7127=m CONFIG_VIDEO_SAA7185=m +# CONFIG_VIDEO_THS8200 is not set +# end of Video encoders + +# +# Video improvement chips +# CONFIG_VIDEO_UPD64031A=m CONFIG_VIDEO_UPD64083=m +# end of Video improvement chips + +# +# Audio/Video compression chips +# CONFIG_VIDEO_SAA6752HS=m +# end of Audio/Video compression chips + +# +# SDR tuner chips +# +# CONFIG_SDR_MAX2175 is not set +# end of SDR tuner chips + +# +# Miscellaneous helper chips +# +# CONFIG_VIDEO_I2C is not set CONFIG_VIDEO_M52790=m +# CONFIG_VIDEO_ST_MIPID02 is not set +# CONFIG_VIDEO_THS7303 is not set +# end of Miscellaneous helper chips # # Video serializers and deserializers @@ -6053,10 +6172,6 @@ CONFIG_VIDEO_M52790=m # CONFIG_VIDEO_DS90UB960 is not set # end of Video serializers and deserializers -# -# SPI I2C drivers auto-selected by 'Autoselect ancillary drivers' -# - # # Media SPI Adapters # @@ -6067,7 +6182,7 @@ CONFIG_VIDEO_GS1662=m CONFIG_MEDIA_TUNER=m # -# Tuner drivers auto-selected by 'Autoselect ancillary drivers' +# Customize TV tuners # CONFIG_MEDIA_TUNER_E4000=m CONFIG_MEDIA_TUNER_FC0011=m @@ -6106,9 +6221,10 @@ CONFIG_MEDIA_TUNER_TUA9001=m CONFIG_MEDIA_TUNER_XC2028=m CONFIG_MEDIA_TUNER_XC4000=m CONFIG_MEDIA_TUNER_XC5000=m +# end of Customize TV tuners # -# DVB Frontend drivers auto-selected by 'Autoselect ancillary drivers' +# Customise DVB Frontends # # @@ -6153,10 +6269,13 @@ CONFIG_DVB_STV6110=m CONFIG_DVB_TDA10071=m CONFIG_DVB_TDA10086=m CONFIG_DVB_TDA8083=m +# CONFIG_DVB_TDA8261 is not set CONFIG_DVB_TDA826X=m CONFIG_DVB_TS2020=m +# CONFIG_DVB_TUA6100 is not set CONFIG_DVB_TUNER_CX24113=m CONFIG_DVB_TUNER_ITD1000=m +# CONFIG_DVB_VES1X93 is not set CONFIG_DVB_ZL10036=m CONFIG_DVB_ZL10039=m @@ -6173,14 +6292,17 @@ CONFIG_DVB_DIB3000MB=m CONFIG_DVB_DIB3000MC=m CONFIG_DVB_DIB7000M=m CONFIG_DVB_DIB7000P=m +# CONFIG_DVB_DIB9000 is not set CONFIG_DVB_DRXD=m CONFIG_DVB_EC100=m CONFIG_DVB_GP8PSK_FE=m +# CONFIG_DVB_L64781 is not set CONFIG_DVB_MT352=m CONFIG_DVB_NXT6000=m CONFIG_DVB_RTL2830=m CONFIG_DVB_RTL2832=m CONFIG_DVB_RTL2832_SDR=m +# CONFIG_DVB_S5H1432 is not set CONFIG_DVB_SI2168=m CONFIG_DVB_SP887X=m CONFIG_DVB_STV0367=m @@ -6188,6 +6310,7 @@ CONFIG_DVB_TDA10048=m CONFIG_DVB_TDA1004X=m CONFIG_DVB_ZD1301_DEMOD=m CONFIG_DVB_ZL10353=m +# CONFIG_DVB_CXD2880 is not set # # DVB-C (cable) frontends @@ -6225,6 +6348,7 @@ CONFIG_DVB_S921=m # # ISDB-S (satellite) & ISDB-T (terrestrial) frontends # +# CONFIG_DVB_MN88443X is not set CONFIG_DVB_TC90522=m # @@ -6239,13 +6363,18 @@ CONFIG_DVB_TUNER_DIB0090=m # CONFIG_DVB_A8293=m CONFIG_DVB_AF9033=m +# CONFIG_DVB_ASCOT2E is not set CONFIG_DVB_ATBM8830=m +# CONFIG_DVB_HELENE is not set +# CONFIG_DVB_HORUS3A is not set CONFIG_DVB_ISL6405=m CONFIG_DVB_ISL6421=m CONFIG_DVB_ISL6423=m CONFIG_DVB_IX2505V=m +# CONFIG_DVB_LGS8GL5 is not set CONFIG_DVB_LGS8GXX=m CONFIG_DVB_LNBH25=m +# CONFIG_DVB_LNBH29 is not set CONFIG_DVB_LNBP21=m CONFIG_DVB_LNBP22=m CONFIG_DVB_M88RS2000=m @@ -6257,6 +6386,7 @@ CONFIG_DVB_DRX39XYJ=m # CONFIG_DVB_CXD2099=m CONFIG_DVB_SP2=m +# end of Customise DVB Frontends # # Tools to develop new frontends @@ -6268,17 +6398,17 @@ CONFIG_DVB_DUMMY_FE=m # Graphics support # CONFIG_APERTURE_HELPERS=y -CONFIG_VIDEO_CMDLINE=y -CONFIG_VIDEO_NOMODESET=y +CONFIG_VIDEO=y CONFIG_AUXDISPLAY=y # CONFIG_HD44780 is not set -# CONFIG_IMG_ASCII_LCD is not set -# CONFIG_HT16K33 is not set # CONFIG_LCD2S is not set -CONFIG_TM1628=m # CONFIG_CHARLCD_BL_OFF is not set # CONFIG_CHARLCD_BL_ON is not set CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_IMG_ASCII_LCD is not set +# CONFIG_HT16K33 is not set +# CONFIG_MAX6959 is not set +# CONFIG_SEG_LED_GPIO is not set CONFIG_DRM=y CONFIG_DRM_MIPI_DBI=m CONFIG_DRM_MIPI_DSI=y @@ -6286,8 +6416,11 @@ CONFIG_DRM_MIPI_DSI=y CONFIG_DRM_KUNIT_TEST_HELPERS=m CONFIG_DRM_KUNIT_TEST=m CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set CONFIG_DRM_DP_AUX_BUS=m CONFIG_DRM_DISPLAY_HELPER=y @@ -6347,15 +6480,15 @@ CONFIG_DRM_PANEL_ARM_VERSATILE=m # CONFIG_DRM_PANEL_AUO_A030JTN01 is not set # CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0 is not set CONFIG_DRM_PANEL_BOE_HIMAX8279D=m +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m -CONFIG_DRM_PANEL_DSI_CM=m -CONFIG_DRM_PANEL_LVDS=m -CONFIG_DRM_PANEL_SIMPLE=m -CONFIG_DRM_PANEL_EDP=m CONFIG_DRM_PANEL_EBBG_FT8719=m CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_DSI_CM=m +CONFIG_DRM_PANEL_LVDS=m +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set CONFIG_DRM_PANEL_ILITEK_IL9322=m CONFIG_DRM_PANEL_ILITEK_ILI9341=m @@ -6365,17 +6498,17 @@ CONFIG_DRM_PANEL_ILITEK_ILI9881C=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m # CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set -CONFIG_DRM_PANEL_JDI_LT070ME05000=m # CONFIG_DRM_PANEL_JDI_LPM102A188A is not set +CONFIG_DRM_PANEL_JDI_LT070ME05000=m # CONFIG_DRM_PANEL_JDI_R63452 is not set CONFIG_DRM_PANEL_KHADAS_TS050=m CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set CONFIG_DRM_PANEL_LG_LB035Q02=m # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m CONFIG_DRM_PANEL_NEC_NL8048HL11=m # CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set CONFIG_DRM_PANEL_NEWVISION_NV3052C=m @@ -6384,8 +6517,8 @@ CONFIG_DRM_PANEL_NOVATEK_NT35560=m # CONFIG_DRM_PANEL_NOVATEK_NT35950 is not set # CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set CONFIG_DRM_PANEL_NOVATEK_NT36672A=m +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set CONFIG_DRM_PANEL_NOVATEK_NT39016=m -CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m # CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m @@ -6396,15 +6529,16 @@ CONFIG_DRM_PANEL_RAYDIUM_RM67191=m CONFIG_DRM_PANEL_RAYDIUM_RM68200=m # CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set CONFIG_DRM_PANEL_RONBO_RB070D30=m +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m CONFIG_DRM_PANEL_SAMSUNG_DB7430=m +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m # CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set -CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m CONFIG_DRM_PANEL_SEIKO_43WVF1G=m @@ -6415,19 +6549,21 @@ CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m CONFIG_DRM_PANEL_SITRONIX_ST7701=m CONFIG_DRM_PANEL_SITRONIX_ST7703=m # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set -# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set CONFIG_DRM_PANEL_SONY_ACX565AKM=m # CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set # CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521 is not set # CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set +CONFIG_DRM_PANEL_EDP=m +CONFIG_DRM_PANEL_SIMPLE=m +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set CONFIG_DRM_PANEL_TDO_TL070WSH30=m CONFIG_DRM_PANEL_TPO_TD028TTEC1=m CONFIG_DRM_PANEL_TPO_TD043MTEA1=m CONFIG_DRM_PANEL_TPO_TPG110=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set # CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set -# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m CONFIG_DRM_PANEL_XINPENG_XPP055C272=m # end of Display Panels @@ -6611,6 +6747,7 @@ CONFIG_LCD_CLASS_DEVICE=m CONFIG_LCD_OTM3225A=m CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_KTD253=m +# CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LM3533=m CONFIG_BACKLIGHT_PWM=m @@ -6674,6 +6811,7 @@ CONFIG_SND_DMAENGINE_PCM=m CONFIG_SND_HWDEP=m CONFIG_SND_SEQ_DEVICE=m CONFIG_SND_RAWMIDI=m +CONFIG_SND_CORE_TEST=m CONFIG_SND_COMPRESS_OFFLOAD=m CONFIG_SND_JACK=y CONFIG_SND_JACK_INPUT_DEV=y @@ -6795,6 +6933,7 @@ CONFIG_SND_HDA_CIRRUS_SCODEC=m CONFIG_SND_HDA_CIRRUS_SCODEC_KUNIT_TEST=m CONFIG_SND_HDA_SCODEC_CS35L41=m CONFIG_SND_HDA_CS_DSP_CONTROLS=m +CONFIG_SND_HDA_SCODEC_COMPONENT=m CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m # CONFIG_SND_HDA_SCODEC_CS35L56_I2C is not set @@ -6953,6 +7092,8 @@ CONFIG_SND_SOC_BT_SCO=m # CONFIG_SND_SOC_CHV3_CODEC is not set CONFIG_SND_SOC_CPCAP=m # CONFIG_SND_SOC_CROS_EC_CODEC is not set +CONFIG_SND_SOC_CS_AMP_LIB=m +CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CS35L32=m CONFIG_SND_SOC_CS35L33=m CONFIG_SND_SOC_CS35L34=m @@ -7341,6 +7482,7 @@ CONFIG_USB_OTG=y CONFIG_USB_OTG_FSM=m CONFIG_USB_LEDS_TRIGGER_USBPORT=y CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 CONFIG_USB_MON=m # @@ -7592,6 +7734,7 @@ CONFIG_USB_ULPI_VIEWPORT=y # end of USB Physical Layer drivers CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set # CONFIG_USB_GADGET_DEBUG_FILES is not set # CONFIG_USB_GADGET_DEBUG_FS is not set CONFIG_USB_GADGET_VBUS_DRAW=2 @@ -7725,6 +7868,7 @@ CONFIG_TYPEC_WUSB3801=m CONFIG_TYPEC_MUX_FSA4480=m # CONFIG_TYPEC_MUX_GPIO_SBU is not set CONFIG_TYPEC_MUX_PI3USB30532=m +# CONFIG_TYPEC_MUX_IT5205 is not set # CONFIG_TYPEC_MUX_NB7VPQ904M is not set # CONFIG_TYPEC_MUX_PTN36502 is not set # CONFIG_TYPEC_MUX_WCD939X_USBSS is not set @@ -7776,6 +7920,7 @@ CONFIG_MMC_DW_PLTFM=y # CONFIG_MMC_DW_BLUEFIELD is not set CONFIG_MMC_DW_EXYNOS=y CONFIG_MMC_DW_HI3798CV200=y +# CONFIG_MMC_DW_HI3798MV200 is not set CONFIG_MMC_DW_K3=y # CONFIG_MMC_DW_PCI is not set # CONFIG_MMC_VUB300 is not set @@ -7878,6 +8023,7 @@ CONFIG_LEDS_TPS6105X=m # # CONFIG_LEDS_GROUP_MULTICOLOR is not set # CONFIG_LEDS_KTD202X is not set +# CONFIG_LEDS_NCP5623 is not set CONFIG_LEDS_PWM_MULTICOLOR=m CONFIG_LEDS_QCOM_LPG=m # CONFIG_LEDS_MT6370_RGB is not set @@ -8150,6 +8296,7 @@ CONFIG_VFIO_PCI_CORE=y CONFIG_VFIO_PCI_MMAP=y CONFIG_VFIO_PCI_INTX=y CONFIG_VFIO_PCI=y +# CONFIG_NVGRACE_GPU_VFIO_PCI is not set # end of VFIO support for PCI devices # @@ -8293,7 +8440,6 @@ CONFIG_VIDEO_MESON_VDEC=m # StarFive media platform drivers # # CONFIG_STAGING_MEDIA_DEPRECATED is not set -# CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set CONFIG_FB_TFT=m CONFIG_FB_TFT_AGM1264K_FL=m @@ -8521,7 +8667,6 @@ CONFIG_RPMSG_QCOM_GLINK_RPM=y CONFIG_MESON_CANVAS=y CONFIG_MESON_CLK_MEASURE=y CONFIG_MESON_GX_SOCINFO=y -CONFIG_MESON_GX_SOCINFO_SM=y # end of Amlogic SoC drivers # @@ -8561,6 +8706,7 @@ CONFIG_LITEX_SOC_CONTROLLER=m # # CONFIG_QCOM_PMIC_GLINK is not set CONFIG_QCOM_QMI_HELPERS=m +# CONFIG_QCOM_PBS is not set # end of Qualcomm SoC drivers CONFIG_SOC_TI=y @@ -8649,11 +8795,13 @@ CONFIG_IIO_BUFFER_HW_CONSUMER=m CONFIG_IIO_KFIFO_BUF=y CONFIG_IIO_TRIGGERED_BUFFER=y CONFIG_IIO_CONFIGFS=m +CONFIG_IIO_GTS_HELPER=m CONFIG_IIO_TRIGGER=y CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 CONFIG_IIO_SW_DEVICE=m CONFIG_IIO_SW_TRIGGER=m CONFIG_IIO_TRIGGERED_EVENT=m +CONFIG_IIO_BACKEND=m # # Accelerometers @@ -8684,6 +8832,7 @@ CONFIG_BMC150_ACCEL=m CONFIG_BMC150_ACCEL_I2C=m CONFIG_BMC150_ACCEL_SPI=m CONFIG_BMI088_ACCEL=m +CONFIG_BMI088_ACCEL_I2C=m CONFIG_BMI088_ACCEL_SPI=m CONFIG_DA280=m CONFIG_DA311=m @@ -8785,6 +8934,7 @@ CONFIG_MEDIATEK_MT6360_ADC=m CONFIG_MESON_SARADC=m CONFIG_MP2629_ADC=m # CONFIG_NAU7802 is not set +# CONFIG_PAC1934 is not set CONFIG_PALMAS_GPADC=m CONFIG_QCOM_VADC_COMMON=m # CONFIG_QCOM_SPMI_IADC is not set @@ -8803,6 +8953,7 @@ CONFIG_TI_ADC161S626=m CONFIG_TI_ADS1015=m # CONFIG_TI_ADS7924 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1298 is not set CONFIG_TI_ADS7950=m CONFIG_TI_ADS8344=m CONFIG_TI_ADS8688=m @@ -8976,6 +9127,7 @@ CONFIG_ADMV8818=m # CONFIG_ADF4350 is not set CONFIG_ADF4371=m # CONFIG_ADF4377 is not set +# CONFIG_ADMFM2000 is not set CONFIG_ADMV1013=m CONFIG_ADMV1014=m CONFIG_ADMV4420=m @@ -9138,6 +9290,7 @@ CONFIG_ZOPT2201=m # # Magnetometer sensors # +# CONFIG_AF8133J is not set CONFIG_AK8974=m CONFIG_AK8975=m CONFIG_AK09911=m @@ -9173,6 +9326,7 @@ CONFIG_HID_SENSOR_INCLINOMETER_3D=m CONFIG_HID_SENSOR_DEVICE_ROTATION=m # end of Inclinometer sensors +CONFIG_IIO_GTS_KUNIT_TEST=m CONFIG_IIO_FORMAT_KUNIT_TEST=m # @@ -9299,6 +9453,7 @@ CONFIG_MAX31865=m # CONFIG_NTB is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set CONFIG_PWM_ATMEL_TCB=m CONFIG_PWM_CLK=m # CONFIG_PWM_CROS_EC is not set @@ -9333,9 +9488,11 @@ CONFIG_MESON_IRQ_GPIO=y # CONFIG_IPACK_BUS is not set CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_GPIO is not set CONFIG_RESET_MESON=y CONFIG_RESET_MESON_AUDIO_ARB=m CONFIG_RESET_SCMI=y +# CONFIG_RESET_SIMPLE is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RESET_TI_TPS380X is not set @@ -9400,6 +9557,7 @@ CONFIG_HNS3_PMU=m # CONFIG_DWC_PCIE_PMU is not set # CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set CONFIG_MESON_DDR_PMU=m +CONFIG_CXL_PMU=m # end of Performance monitor support CONFIG_RAS=y @@ -9581,6 +9739,7 @@ CONFIG_AUTOFS_FS=m CONFIG_FUSE_FS=y CONFIG_CUSE=m CONFIG_VIRTIO_FS=m +CONFIG_FUSE_PASSTHROUGH=y CONFIG_OVERLAY_FS=y # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -9624,11 +9783,11 @@ CONFIG_FAT_DEFAULT_UTF8=y CONFIG_FAT_KUNIT_TEST=m CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" -# CONFIG_NTFS_FS is not set CONFIG_NTFS3_FS=m # CONFIG_NTFS3_64BIT_CLUSTER is not set CONFIG_NTFS3_LZX_XPRESS=y CONFIG_NTFS3_FS_POSIX_ACL=y +# CONFIG_NTFS_FS is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -10210,6 +10369,7 @@ CONFIG_CRYPTO_DEV_QAT_4XXX=m CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m CONFIG_CRYPTO_DEV_QAT_C62XVF=m +# CONFIG_CRYPTO_DEV_QAT_ERROR_INJECTION is not set # CONFIG_CRYPTO_DEV_CAVIUM_ZIP is not set CONFIG_CRYPTO_DEV_VIRTIO=m CONFIG_CRYPTO_DEV_SAFEXCEL=m @@ -10263,7 +10423,6 @@ CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=m CONFIG_PRIME_NUMBERS=m CONFIG_RATIONAL=y -CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y @@ -10392,6 +10551,7 @@ CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set # CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y +# CONFIG_FORCE_NR_CPUS is not set CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_GLOB=y @@ -10453,25 +10613,35 @@ CONFIG_PRINTK_TIME=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set CONFIG_DYNAMIC_DEBUG=y CONFIG_DYNAMIC_DEBUG_CORE=y CONFIG_SYMBOLIC_ERRNAME=y CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options -# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y # # Compile-time checks and compiler options # CONFIG_AS_HAS_NON_CONST_ULEB128=y +CONFIG_DEBUG_INFO_NONE=y +# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_FRAME_WARN=1024 # CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set # CONFIG_HEADERS_INSTALL is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set CONFIG_ARCH_WANT_FRAME_POINTERS=y CONFIG_FRAME_POINTER=y +# CONFIG_VMLINUX_MAP is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options # @@ -10486,35 +10656,51 @@ CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN=y # CONFIG_UBSAN is not set +CONFIG_HAVE_ARCH_KCSAN=y CONFIG_HAVE_KCSAN_COMPILER=y +# CONFIG_KCSAN is not set # end of Generic Kernel Debugging Instruments # # Networking Debugging # +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# CONFIG_DEBUG_NET is not set # end of Networking Debugging # # Memory Debugging # # CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set CONFIG_SLUB_DEBUG=y # CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_TABLE_CHECK is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_RODATA_TEST is not set CONFIG_ARCH_HAS_DEBUG_WX=y # CONFIG_DEBUG_WX is not set CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_PER_VMA_LOCK_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set # CONFIG_SHRINKER_DEBUG is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_SCHED_STACK_END_CHECK is not set CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_VM_PGTABLE is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y @@ -10527,49 +10713,87 @@ CONFIG_HAVE_ARCH_KFENCE=y # CONFIG_KFENCE is not set # end of Memory Debugging +# CONFIG_DEBUG_SHIRQ is not set + # # Debug Oops, Lockups and Hangs # # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SOFTLOCKUP_DETECTOR is not set CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set CONFIG_TEST_LOCKUP=m # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # +CONFIG_SCHED_DEBUG=y CONFIG_SCHED_INFO=y +# CONFIG_SCHEDSTATS is not set # end of Scheduler Debugging # CONFIG_DEBUG_TIMEKEEPING is not set +# CONFIG_DEBUG_PREEMPT is not set # # Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set # CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set # end of Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set # # Debug kernel data structures # +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_DEBUG_CLOSURES is not set +# CONFIG_DEBUG_MAPLE_TREE is not set # end of Debug kernel data structures # # RCU Debugging # +# CONFIG_RCU_SCALE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=60 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 # CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_RCU_TRACE=y +# CONFIG_RCU_EQS_DEBUG is not set # end of RCU Debugging +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_DEBUG_CGROUP_REF is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y @@ -10578,6 +10802,7 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACE_CLOCK=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_SAMPLES is not set @@ -10603,7 +10828,9 @@ CONFIG_KUNIT_TEST=m CONFIG_KUNIT_EXAMPLE_TEST=m CONFIG_KUNIT_ALL_TESTS=m CONFIG_KUNIT_DEFAULT_ENABLED=y +# CONFIG_NOTIFIER_ERROR_INJECTION is not set CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y CONFIG_RUNTIME_TESTING_MENU=y @@ -10615,12 +10842,18 @@ CONFIG_TEST_MIN_HEAP=m # CONFIG_TEST_SORT is not set CONFIG_TEST_DIV64=m CONFIG_TEST_IOV_ITER=m +CONFIG_KPROBES_SANITY_TEST=m +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set +# CONFIG_RBTREE_TEST is not set CONFIG_REED_SOLOMON_TEST=m +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set CONFIG_ASYNC_RAID6_TEST=m # CONFIG_TEST_HEXDUMP is not set -# CONFIG_STRING_SELFTEST is not set -# CONFIG_TEST_STRING_HELPERS is not set +CONFIG_STRING_KUNIT_TEST=m +CONFIG_STRING_HELPERS_KUNIT_TEST=m # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set CONFIG_TEST_SCANF=m @@ -10652,7 +10885,6 @@ CONFIG_BITS_TEST=m CONFIG_SLUB_KUNIT_TEST=m CONFIG_RATIONAL_KUNIT_TEST=m CONFIG_MEMCPY_KUNIT_TEST=m -CONFIG_MEMCPY_SLOW_KUNIT_TEST=y CONFIG_IS_SIGNED_TYPE_KUNIT_TEST=m CONFIG_OVERFLOW_KUNIT_TEST=m CONFIG_STACKINIT_KUNIT_TEST=m @@ -10667,6 +10899,7 @@ CONFIG_TEST_DYNAMIC_DEBUG=m CONFIG_TEST_MEMCAT_P=m # CONFIG_TEST_MEMINIT is not set CONFIG_TEST_FREE_PAGES=m +# CONFIG_TEST_OBJPOOL is not set CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y # CONFIG_HYPERV_TESTING is not set diff --git a/config/kernel/linux-rockchip-edge.config b/config/kernel/linux-rockchip-edge.config index 77f049103fbc..1f88632006c2 100644 --- a/config/kernel/linux-rockchip-edge.config +++ b/config/kernel/linux-rockchip-edge.config @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm 6.8.1 Kernel Configuration +# Linux/arm 6.9.1 Kernel Configuration # CONFIG_CC_VERSION_TEXT="arm-linux-gnueabihf-gcc (Ubuntu 11.3.0-1ubuntu1~22.04) 11.3.0" CONFIG_CC_IS_GCC=y @@ -260,7 +260,6 @@ CONFIG_PROFILING=y # Kexec and crash features # # CONFIG_KEXEC is not set -# CONFIG_CRASH_DUMP is not set # end of Kexec and crash features # end of General setup @@ -595,6 +594,7 @@ CONFIG_ARCH_HIBERNATION_POSSIBLE=y # end of Power management options CONFIG_AS_VFP_VMRS_FPINST=y +CONFIG_CPU_MITIGATIONS=y # # General architecture-dependent options @@ -655,8 +655,11 @@ CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y CONFIG_ARCH_MMAP_RND_BITS=8 +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_4KB=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SHIFT=12 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -802,7 +805,6 @@ CONFIG_ZPOOL=y CONFIG_SWAP=y CONFIG_ZSWAP=y CONFIG_ZSWAP_DEFAULT_ON=y -# CONFIG_ZSWAP_EXCLUSIVE_LOADS_DEFAULT_ON is not set CONFIG_ZSWAP_SHRINKER_DEFAULT_ON=y # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set @@ -855,13 +857,13 @@ CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_CMA=y -# CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set CONFIG_CMA_SYSFS=y CONFIG_CMA_AREAS=7 CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_PAGE_IDLE_FLAG=y CONFIG_IDLE_PAGE_TRACKING=y +CONFIG_ARCH_HAS_CPU_CACHE_ALIASING=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y CONFIG_VM_EVENT_COUNTERS=y # CONFIG_PERCPU_STATS is not set @@ -899,7 +901,6 @@ CONFIG_SKB_EXTENSIONS=y CONFIG_PACKET=y CONFIG_PACKET_DIAG=m CONFIG_UNIX=y -CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y CONFIG_UNIX_DIAG=m CONFIG_TLS=m @@ -1275,6 +1276,7 @@ CONFIG_IP_VS_PE_SIP=m # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m +CONFIG_IP_NF_IPTABLES_LEGACY=m CONFIG_NF_SOCKET_IPV4=m CONFIG_NF_TPROXY_IPV4=m CONFIG_NF_TABLES_IPV4=y @@ -1307,6 +1309,7 @@ CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_SECURITY=m CONFIG_IP_NF_ARPTABLES=m +CONFIG_NFT_COMPAT_ARP=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # end of IP: Netfilter Configuration @@ -1314,6 +1317,7 @@ CONFIG_IP_NF_ARP_MANGLE=m # # IPv6: Netfilter Configuration # +CONFIG_IP6_NF_IPTABLES_LEGACY=m CONFIG_NF_SOCKET_IPV6=m CONFIG_NF_TPROXY_IPV6=m CONFIG_NF_TABLES_IPV6=y @@ -1351,6 +1355,7 @@ CONFIG_NF_TABLES_BRIDGE=m # CONFIG_NFT_BRIDGE_META is not set CONFIG_NFT_BRIDGE_REJECT=m # CONFIG_NF_CONNTRACK_BRIDGE is not set +CONFIG_BRIDGE_NF_EBTABLES_LEGACY=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -1548,7 +1553,6 @@ CONFIG_NET_ACT_GACT=m CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=m CONFIG_NET_ACT_SAMPLE=m -CONFIG_NET_ACT_IPT=m CONFIG_NET_ACT_NAT=m CONFIG_NET_ACT_PEDIT=m CONFIG_NET_ACT_SIMP=m @@ -1626,7 +1630,6 @@ CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y # CONFIG_BT_BNEP is not set CONFIG_BT_HIDP=y -CONFIG_BT_HS=y CONFIG_BT_LE=y CONFIG_BT_LE_L2CAP_ECRED=y CONFIG_BT_6LOWPAN=m @@ -1739,6 +1742,7 @@ CONFIG_ETHTOOL_NETLINK=y # CONFIG_ARM_AMBA=y CONFIG_HAVE_PCI=y +CONFIG_GENERIC_PCI_IOMAP=y # CONFIG_PCI is not set # CONFIG_PCCARD is not set @@ -2242,6 +2246,9 @@ CONFIG_MICROCHIP_T1_PHY=m # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_NCN26000_PHY is not set # CONFIG_AT803X_PHY is not set +# CONFIG_QCA83XX_PHY is not set +# CONFIG_QCA808X_PHY is not set +# CONFIG_QCA807X_PHY is not set # CONFIG_QSEMI_PHY is not set CONFIG_REALTEK_PHY=m # CONFIG_RENESAS_PHY is not set @@ -2557,6 +2564,7 @@ CONFIG_WLAN_VENDOR_TI=y # CONFIG_WL12XX is not set # CONFIG_WL18XX is not set # CONFIG_WLCORE is not set +CONFIG_RTL8723DS=m # CONFIG_RTL8822BU is not set # CONFIG_RTL8821CU is not set # CONFIG_88XXAU is not set @@ -2715,6 +2723,8 @@ CONFIG_TOUCHSCREEN_BU21029=m # CONFIG_TOUCHSCREEN_EXC3000 is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set # CONFIG_TOUCHSCREEN_HIDEEP is not set # CONFIG_TOUCHSCREEN_HYCON_HY46XX is not set # CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set @@ -2861,7 +2871,6 @@ CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set @@ -3093,6 +3102,7 @@ CONFIG_DP83640_PHY=m CONFIG_PTP_1588_CLOCK_KVM=y # CONFIG_PTP_1588_CLOCK_IDT82P33 is not set # CONFIG_PTP_1588_CLOCK_IDTCM is not set +# CONFIG_PTP_1588_CLOCK_FC3W is not set # CONFIG_PTP_1588_CLOCK_MOCK is not set # end of PTP clock support @@ -3101,6 +3111,7 @@ CONFIG_PINMUX=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y # CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AW9523 is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_MCP23S08 is not set # CONFIG_PINCTRL_MICROCHIP_SGPIO is not set @@ -3212,6 +3223,7 @@ CONFIG_W1_CON=y # CONFIG_W1_MASTER_DS2482 is not set CONFIG_W1_MASTER_GPIO=m CONFIG_W1_MASTER_SGI=m +# CONFIG_W1_MASTER_UART is not set # end of 1-wire Bus Masters # @@ -3327,9 +3339,11 @@ CONFIG_HWMON=y # CONFIG_SENSORS_AQUACOMPUTER_D5NEXT is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_ARM_SCMI is not set # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CHIPCAP2 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set # CONFIG_SENSORS_CORSAIR_PSU is not set # CONFIG_SENSORS_DS620 is not set @@ -3364,6 +3378,7 @@ CONFIG_SENSORS_GPIO_FAN=y # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LTC4282 is not set # CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set @@ -3412,10 +3427,12 @@ CONFIG_SENSORS_GPIO_FAN=y # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_NZXT_KRAKEN2 is not set +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set # CONFIG_SENSORS_NZXT_SMART2 is not set # CONFIG_SENSORS_OCC_P8_I2C is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set +# CONFIG_SENSORS_PT5161L is not set CONFIG_SENSORS_PWM_FAN=y # CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SBRMI is not set @@ -3470,7 +3487,6 @@ CONFIG_THERMAL=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -# CONFIG_THERMAL_WRITABLE_TRIPS is not set CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set @@ -4573,8 +4589,7 @@ CONFIG_DVB_AF9033=m # Graphics support # CONFIG_APERTURE_HELPERS=y -CONFIG_VIDEO_CMDLINE=y -CONFIG_VIDEO_NOMODESET=y +CONFIG_VIDEO=y # CONFIG_AUXDISPLAY is not set CONFIG_DRM=y # CONFIG_DRM_DEBUG_MM is not set @@ -4636,12 +4651,9 @@ CONFIG_DRM_PANEL=y # CONFIG_DRM_PANEL_ARM_VERSATILE is not set # CONFIG_DRM_PANEL_AUO_A030JTN01 is not set # CONFIG_DRM_PANEL_LVDS is not set -CONFIG_DRM_PANEL_SIMPLE=m -# CONFIG_DRM_PANEL_EDP is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set @@ -4649,17 +4661,20 @@ CONFIG_DRM_PANEL_SIMPLE=m # CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set # CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set # CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20 is not set # CONFIG_DRM_PANEL_SAMSUNG_DB7430 is not set +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set # CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set # CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set # CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_EDP is not set +CONFIG_DRM_PANEL_SIMPLE=m # CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set # CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set # CONFIG_DRM_PANEL_TPO_TPG110 is not set @@ -4779,6 +4794,7 @@ CONFIG_FB_MODE_HELPERS=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_PWM=y # CONFIG_BACKLIGHT_QCOM_WLED is not set @@ -5318,6 +5334,7 @@ CONFIG_USB_OTG=y # CONFIG_USB_OTG_FSM is not set CONFIG_USB_LEDS_TRIGGER_USBPORT=y CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 CONFIG_USB_MON=y # @@ -5635,6 +5652,7 @@ CONFIG_MMC_DW_PLTFM=y CONFIG_MMC_DW_BLUEFIELD=m # CONFIG_MMC_DW_EXYNOS is not set # CONFIG_MMC_DW_HI3798CV200 is not set +# CONFIG_MMC_DW_HI3798MV200 is not set # CONFIG_MMC_DW_K3 is not set CONFIG_MMC_DW_ROCKCHIP=y # CONFIG_MMC_VUB300 is not set @@ -5672,8 +5690,6 @@ CONFIG_LEDS_LM3532=m CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_LP3952 is not set -# CONFIG_LEDS_LP50XX is not set -# CONFIG_LEDS_LP55XX_COMMON is not set # CONFIG_LEDS_LP8860 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -5982,7 +5998,6 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m # StarFive media platform drivers # # CONFIG_STAGING_MEDIA_DEPRECATED is not set -# CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set CONFIG_FB_TFT=m CONFIG_FB_TFT_AGM1264K_FL=m @@ -6335,6 +6350,7 @@ CONFIG_AD7768_1=m # CONFIG_AD7923 is not set # CONFIG_AD7949 is not set # CONFIG_AD799X is not set +# CONFIG_AD9467 is not set # CONFIG_ADI_AXI_ADC is not set # CONFIG_CC10001_ADC is not set # CONFIG_CPCAP_ADC is not set @@ -6361,6 +6377,7 @@ CONFIG_AD7768_1=m # CONFIG_MCP3564 is not set # CONFIG_MCP3911 is not set # CONFIG_NAU7802 is not set +# CONFIG_PAC1934 is not set CONFIG_ROCKCHIP_SARADC=y # CONFIG_RICHTEK_RTQ6056 is not set # CONFIG_SD_ADC_MODULATOR is not set @@ -6374,6 +6391,7 @@ CONFIG_ROCKCHIP_SARADC=y # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS7924 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS7950 is not set CONFIG_TI_ADS8344=m # CONFIG_TI_ADS8688 is not set @@ -6528,6 +6546,7 @@ CONFIG_TI_DAC7612=m # CONFIG_ADF4350 is not set # CONFIG_ADF4371 is not set # CONFIG_ADF4377 is not set +# CONFIG_ADMFM2000 is not set # CONFIG_ADMV1013 is not set # CONFIG_ADMV4420 is not set # CONFIG_ADRF6780 is not set @@ -6672,6 +6691,7 @@ CONFIG_TSL2772=m # # Magnetometer sensors # +# CONFIG_AF8133J is not set # CONFIG_AK8974 is not set # CONFIG_AK8975 is not set # CONFIG_AK09911 is not set @@ -6839,6 +6859,7 @@ CONFIG_MADERA_IRQ=m # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_GPIO=y CONFIG_RESET_SCMI=m CONFIG_RESET_SIMPLE=y # CONFIG_RESET_TI_SYSCON is not set @@ -6877,6 +6898,7 @@ CONFIG_PHY_ROCKCHIP_INNO_USB2=y # CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY is not set # CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY is not set # CONFIG_PHY_ROCKCHIP_PCIE is not set +# CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX is not set # CONFIG_PHY_ROCKCHIP_SNPS_PCIE3 is not set # CONFIG_PHY_ROCKCHIP_TYPEC is not set CONFIG_PHY_ROCKCHIP_USB=y @@ -6996,6 +7018,8 @@ CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y CONFIG_XFS_DRAIN_INTENTS=y +CONFIG_XFS_LIVE_HOOKS=y +CONFIG_XFS_MEMORY_BUFS=y CONFIG_XFS_ONLINE_SCRUB=y CONFIG_XFS_ONLINE_SCRUB_STATS=y # CONFIG_XFS_ONLINE_REPAIR is not set @@ -7056,6 +7080,7 @@ CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m CONFIG_CUSE=m CONFIG_VIRTIO_FS=m +CONFIG_FUSE_PASSTHROUGH=y CONFIG_OVERLAY_FS=m # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -7097,12 +7122,10 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" -CONFIG_NTFS_FS=m -# CONFIG_NTFS_DEBUG is not set -CONFIG_NTFS_RW=y CONFIG_NTFS3_FS=m CONFIG_NTFS3_LZX_XPRESS=y CONFIG_NTFS3_FS_POSIX_ACL=y +CONFIG_NTFS_FS=m # end of DOS/FAT/EXFAT/NT Filesystems # @@ -7621,7 +7644,6 @@ CONFIG_GENERIC_NET_UTILS=y # CONFIG_CORDIC is not set # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y -CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y # @@ -7820,7 +7842,7 @@ CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +CONFIG_ARCH_HAS_UBSAN=y # CONFIG_UBSAN is not set CONFIG_HAVE_KCSAN_COMPILER=y # end of Generic Kernel Debugging Instruments @@ -7842,7 +7864,6 @@ CONFIG_PAGE_EXTENSION=y # CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_RODATA_TEST is not set -# CONFIG_DEBUG_WX is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y # CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_PER_VMA_LOCK_STATS is not set @@ -7965,6 +7986,7 @@ CONFIG_STRICT_DEVMEM=y # arm Debugging # # CONFIG_ARM_PTDUMP_DEBUGFS is not set +# CONFIG_ARM_DEBUG_WX is not set CONFIG_UNWINDER_FRAME_POINTER=y # CONFIG_UNWINDER_ARM is not set # CONFIG_BACKTRACE_VERBOSE is not set diff --git a/config/kernel/linux-rockchip64-edge.config b/config/kernel/linux-rockchip64-edge.config index 9a423f070874..9583a87f678c 100644 --- a/config/kernel/linux-rockchip64-edge.config +++ b/config/kernel/linux-rockchip64-edge.config @@ -1,23 +1,24 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 6.8.6 Kernel Configuration +# Linux/arm64 6.9.3 Kernel Configuration # -CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0" +CONFIG_CC_VERSION_TEXT="aarch64-linux-gnu-gcc (Ubuntu 11.4.0-1ubuntu1~22.04) 11.4.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=120200 +CONFIG_GCC_VERSION=110400 CONFIG_CLANG_VERSION=0 CONFIG_AS_IS_GNU=y -CONFIG_AS_VERSION=24000 +CONFIG_AS_VERSION=23800 CONFIG_LD_IS_BFD=y -CONFIG_LD_VERSION=24000 +CONFIG_LD_VERSION=23800 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO_OUTPUT=y CONFIG_CC_HAS_ASM_GOTO_TIED_OUTPUT=y CONFIG_GCC_ASM_GOTO_OUTPUT_WORKAROUND=y CONFIG_CC_HAS_ASM_INLINE=y CONFIG_CC_HAS_NO_PROFILE_FN_ATTR=y -CONFIG_PAHOLE_VERSION=124 +CONFIG_PAHOLE_VERSION=125 CONFIG_IRQ_WORK=y CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y @@ -193,6 +194,7 @@ CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y # CONFIG_CGROUP_MISC is not set +# CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y @@ -224,9 +226,10 @@ CONFIG_LD_ORPHAN_WARN_LEVEL="warn" CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y -# CONFIG_EXPERT is not set +CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y +# CONFIG_SGETMASK_SYSCALL is not set CONFIG_SYSFS_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y @@ -247,9 +250,12 @@ CONFIG_ADVISE_SYSCALLS=y CONFIG_MEMBARRIER=y CONFIG_KCMP=y CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set CONFIG_CACHESTAT_SYSCALL=y +# CONFIG_PC104 is not set CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_SELFTEST is not set +# CONFIG_KALLSYMS_ALL is not set CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_HAVE_PERF_EVENTS=y @@ -259,6 +265,7 @@ CONFIG_GUEST_PERF_EVENTS=y # Kernel Performance Events And Counters # CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set # end of Kernel Performance Events And Counters CONFIG_SYSTEM_DATA_VERIFICATION=y @@ -268,7 +275,8 @@ CONFIG_TRACEPOINTS=y # # Kexec and crash features # -CONFIG_CRASH_CORE=y +CONFIG_CRASH_RESERVE=y +CONFIG_VMCORE_INFO=y CONFIG_KEXEC_CORE=y CONFIG_KEXEC=y # CONFIG_KEXEC_FILE is not set @@ -280,7 +288,6 @@ CONFIG_ARM64=y CONFIG_GCC_SUPPORTS_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_64BIT=y CONFIG_MMU=y -CONFIG_ARM64_PAGE_SHIFT=12 CONFIG_ARM64_CONT_PTE_SHIFT=4 CONFIG_ARM64_CONT_PMD_SHIFT=4 CONFIG_ARCH_MMAP_RND_BITS_MIN=18 @@ -410,6 +417,7 @@ CONFIG_ARM64_4K_PAGES=y # CONFIG_ARM64_64K_PAGES is not set # CONFIG_ARM64_VA_BITS_39 is not set CONFIG_ARM64_VA_BITS_48=y +# CONFIG_ARM64_VA_BITS_52 is not set CONFIG_ARM64_VA_BITS=48 CONFIG_ARM64_PA_BITS_48=y CONFIG_ARM64_PA_BITS=48 @@ -430,7 +438,6 @@ CONFIG_HZ=250 CONFIG_SCHED_HRTICK=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_HW_PERF_EVENTS=y -CONFIG_CC_HAVE_SHADOW_CALL_STACK=y CONFIG_PARAVIRT=y # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set CONFIG_ARCH_SUPPORTS_KEXEC=y @@ -521,6 +528,7 @@ CONFIG_RELOCATABLE=y # CONFIG_RANDOMIZE_BASE is not set CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y CONFIG_STACKPROTECTOR_PER_TASK=y +CONFIG_ARM64_CONTPTE=y # end of Kernel Features # @@ -537,9 +545,13 @@ CONFIG_DMI=y # CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set CONFIG_HIBERNATE_CALLBACKS=y CONFIG_HIBERNATION=y CONFIG_HIBERNATION_SNAPSHOT_DEV=y +CONFIG_HIBERNATION_COMP_LZO=y +# CONFIG_HIBERNATION_COMP_LZ4 is not set +CONFIG_HIBERNATION_DEF_COMP="lzo" CONFIG_PM_STD_PARTITION="" CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y @@ -615,7 +627,6 @@ CONFIG_ARM_SCPI_CPUFREQ=y CONFIG_ARCH_SUPPORTS_ACPI=y # CONFIG_ACPI is not set -CONFIG_HAVE_KVM=y CONFIG_KVM_COMMON=y CONFIG_HAVE_KVM_IRQCHIP=y CONFIG_HAVE_KVM_IRQ_ROUTING=y @@ -624,6 +635,7 @@ CONFIG_HAVE_KVM_DIRTY_RING_ACQ_REL=y CONFIG_NEED_KVM_DIRTY_RING_WITH_BITMAP=y CONFIG_KVM_MMIO=y CONFIG_HAVE_KVM_MSI=y +CONFIG_HAVE_KVM_READONLY_MEM=y CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT=y CONFIG_KVM_VFIO=y CONFIG_KVM_GENERIC_DIRTYLOG_READ_PROTECT=y @@ -635,6 +647,7 @@ CONFIG_KVM_GENERIC_MMU_NOTIFIER=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=y # CONFIG_NVHE_EL2_DEBUG is not set +CONFIG_CPU_MITIGATIONS=y # # General architecture-dependent options @@ -669,6 +682,7 @@ CONFIG_ARCH_WANTS_NO_INSTR=y CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_RUST=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_PERF_REGS=y @@ -693,8 +707,6 @@ CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y -CONFIG_ARCH_SUPPORTS_SHADOW_CALL_STACK=y -# CONFIG_SHADOW_CALL_STACK is not set CONFIG_ARCH_SUPPORTS_LTO_CLANG=y CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y CONFIG_LTO_NONE=y @@ -718,8 +730,11 @@ CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_ARCH_MMAP_RND_BITS=18 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=11 +CONFIG_HAVE_PAGE_SIZE_4KB=y +CONFIG_PAGE_SIZE_4KB=y CONFIG_PAGE_SIZE_LESS_THAN_64KB=y CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SHIFT=12 CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT=y CONFIG_CLONE_BACKWARDS=y CONFIG_OLD_SIGSUSPEND3=y @@ -776,6 +791,7 @@ CONFIG_MODULE_COMPRESS_NONE=y # CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set CONFIG_MODPROBE_PATH="/sbin/modprobe" +# CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLOCK_LEGACY_AUTOLOAD=y @@ -864,7 +880,6 @@ CONFIG_ZPOOL=y CONFIG_SWAP=y CONFIG_ZSWAP=y CONFIG_ZSWAP_DEFAULT_ON=y -# CONFIG_ZSWAP_EXCLUSIVE_LOADS_DEFAULT_ON is not set # CONFIG_ZSWAP_SHRINKER_DEFAULT_ON is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set # CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO is not set @@ -887,6 +902,7 @@ CONFIG_ZSMALLOC_CHAIN_SIZE=8 # Slab allocator options # CONFIG_SLUB=y +# CONFIG_SLUB_TINY is not set CONFIG_SLAB_MERGE_DEFAULT=y # CONFIG_SLAB_FREELIST_RANDOM is not set # CONFIG_SLAB_FREELIST_HARDENED is not set @@ -948,6 +964,7 @@ CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_CURRENT_STACK_POINTER=y CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_ARCH_HAS_ZONE_DMA_SET=y CONFIG_ZONE_DMA=y CONFIG_ZONE_DMA32=y CONFIG_GET_FREE_REGION=y @@ -992,7 +1009,6 @@ CONFIG_SKB_EXTENSIONS=y CONFIG_PACKET=y CONFIG_PACKET_DIAG=m CONFIG_UNIX=y -CONFIG_UNIX_SCM=y CONFIG_AF_UNIX_OOB=y CONFIG_UNIX_DIAG=m CONFIG_TLS=m @@ -1372,6 +1388,7 @@ CONFIG_IP_VS_PE_SIP=m # IP: Netfilter Configuration # CONFIG_NF_DEFRAG_IPV4=m +CONFIG_IP_NF_IPTABLES_LEGACY=m CONFIG_NF_SOCKET_IPV4=m CONFIG_NF_TPROXY_IPV4=m CONFIG_NF_TABLES_IPV4=y @@ -1404,6 +1421,7 @@ CONFIG_IP_NF_TARGET_TTL=m CONFIG_IP_NF_RAW=m CONFIG_IP_NF_SECURITY=m CONFIG_IP_NF_ARPTABLES=m +CONFIG_NFT_COMPAT_ARP=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m # end of IP: Netfilter Configuration @@ -1411,6 +1429,7 @@ CONFIG_IP_NF_ARP_MANGLE=m # # IPv6: Netfilter Configuration # +CONFIG_IP6_NF_IPTABLES_LEGACY=m CONFIG_NF_SOCKET_IPV6=m CONFIG_NF_TPROXY_IPV6=m CONFIG_NF_TABLES_IPV6=y @@ -1448,6 +1467,7 @@ CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m CONFIG_NFT_BRIDGE_REJECT=m CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_BRIDGE_NF_EBTABLES_LEGACY=m CONFIG_BRIDGE_NF_EBTABLES=m CONFIG_BRIDGE_EBT_BROUTE=m CONFIG_BRIDGE_EBT_T_FILTER=m @@ -1634,7 +1654,6 @@ CONFIG_NET_ACT_GACT=m CONFIG_GACT_PROB=y CONFIG_NET_ACT_MIRRED=m CONFIG_NET_ACT_SAMPLE=m -CONFIG_NET_ACT_IPT=m CONFIG_NET_ACT_NAT=m CONFIG_NET_ACT_PEDIT=m CONFIG_NET_ACT_SIMP=m @@ -1751,6 +1770,7 @@ CONFIG_BT_LEDS=y # CONFIG_BT_MSFTEXT is not set # CONFIG_BT_AOSPEXT is not set # CONFIG_BT_DEBUGFS is not set +# CONFIG_BT_SELFTEST is not set # # Bluetooth device drivers @@ -1816,6 +1836,7 @@ CONFIG_WEXT_PRIV=y CONFIG_CFG80211=m # CONFIG_NL80211_TESTMODE is not set # CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set CONFIG_CFG80211_REQUIRE_SIGNED_REGDB=y CONFIG_CFG80211_USE_KERNEL_REGDB_KEYS=y # CONFIG_CFG80211_DEFAULT_PS is not set @@ -1917,6 +1938,7 @@ CONFIG_NETDEV_ADDR_LIST_TEST=m # CONFIG_ARM_AMBA=y CONFIG_HAVE_PCI=y +CONFIG_GENERIC_PCI_IOMAP=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_PCI_DOMAINS_GENERIC=y @@ -1936,6 +1958,7 @@ CONFIG_PCIE_PME=y # CONFIG_PCIE_PTM is not set CONFIG_PCI_MSI=y CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set # CONFIG_PCI_STUB is not set # CONFIG_PCI_PF_STUB is not set @@ -1946,6 +1969,11 @@ CONFIG_PCI_IOV=y # CONFIG_PCI_PASID is not set CONFIG_PCI_LABEL=y # CONFIG_PCI_DYNAMIC_OF_NODES is not set +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 CONFIG_HOTPLUG_PCI=y @@ -2015,7 +2043,6 @@ CONFIG_CXL_BUS=m CONFIG_CXL_PORT=m CONFIG_CXL_REGION=y # CONFIG_CXL_REGION_INVALIDATION_TEST is not set -# CONFIG_CXL_PMU is not set # CONFIG_PCCARD is not set # CONFIG_RAPIDIO is not set @@ -2048,6 +2075,9 @@ CONFIG_FW_UPLOAD=y CONFIG_WANT_DEV_COREDUMP=y CONFIG_ALLOW_DEV_COREDUMP=y CONFIG_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set # CONFIG_DM_KUNIT_TEST is not set # CONFIG_DRIVER_PE_KUNIT_TEST is not set @@ -2111,6 +2141,7 @@ CONFIG_ARM_SCMI_TRANSPORT_SMC=y # end of ARM System Control and Management Interface Protocol CONFIG_ARM_SCPI_PROTOCOL=y +# CONFIG_FIRMWARE_MEMMAP is not set CONFIG_DMIID=y # CONFIG_DMI_SYSFS is not set # CONFIG_FW_CFG_SYSFS is not set @@ -2224,7 +2255,6 @@ CONFIG_MTD_CFI_UTIL=m CONFIG_MTD_COMPLEX_MAPPINGS=y # CONFIG_MTD_PHYSMAP is not set # CONFIG_MTD_PCI is not set -# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # end of Mapping drivers for chip access @@ -2279,6 +2309,7 @@ CONFIG_MTD_HYPERBUS=m CONFIG_DTC=y CONFIG_OF=y # CONFIG_OF_UNITTEST is not set +# CONFIG_OF_KUNIT_TEST is not set CONFIG_OF_FLATTREE=y CONFIG_OF_EARLY_FLATTREE=y CONFIG_OF_KOBJ=y @@ -2428,6 +2459,7 @@ CONFIG_SCSI_COMMON=y CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_PROC_FS is not set +# CONFIG_SCSI_LIB_KUNIT_TEST is not set # # SCSI support type (disk, tape, CD-ROM) @@ -2441,6 +2473,7 @@ CONFIG_BLK_DEV_BSG=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set +# CONFIG_SCSI_PROTO_TEST is not set # # SCSI Transports @@ -2658,6 +2691,7 @@ CONFIG_DM_LOG_WRITES=m CONFIG_DM_INTEGRITY=m CONFIG_DM_ZONED=m CONFIG_DM_AUDIT=y +# CONFIG_DM_VDO is not set CONFIG_TARGET_CORE=m CONFIG_TCM_IBLOCK=m CONFIG_TCM_FILEIO=m @@ -2776,8 +2810,8 @@ CONFIG_NET_DSA_XRS700X=m CONFIG_NET_DSA_XRS700X_I2C=m CONFIG_NET_DSA_XRS700X_MDIO=m CONFIG_NET_DSA_REALTEK=m -# CONFIG_NET_DSA_REALTEK_RTL8365MB is not set -# CONFIG_NET_DSA_REALTEK_RTL8366RB is not set +# CONFIG_NET_DSA_REALTEK_MDIO is not set +# CONFIG_NET_DSA_REALTEK_SMI is not set CONFIG_NET_DSA_SMSC_LAN9303=m CONFIG_NET_DSA_SMSC_LAN9303_I2C=m CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m @@ -2924,6 +2958,7 @@ CONFIG_OCTEONTX2_MBOX=m CONFIG_OCTEONTX2_PF=m CONFIG_OCTEONTX2_VF=m CONFIG_OCTEON_EP=m +# CONFIG_OCTEON_EP_VF is not set # CONFIG_PRESTERA is not set CONFIG_NET_VENDOR_MELLANOX=y # CONFIG_MLX4_EN is not set @@ -3100,7 +3135,11 @@ CONFIG_NATIONAL_PHY=m CONFIG_NXP_C45_TJA11XX_PHY=m # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_NCN26000_PHY is not set +CONFIG_QCOM_NET_PHYLIB=m CONFIG_AT803X_PHY=m +# CONFIG_QCA83XX_PHY is not set +# CONFIG_QCA808X_PHY is not set +# CONFIG_QCA807X_PHY is not set CONFIG_QSEMI_PHY=m CONFIG_REALTEK_PHY=m # CONFIG_RENESAS_PHY is not set @@ -3140,6 +3179,7 @@ CONFIG_CAN_CC770_PLATFORM=m CONFIG_CAN_CTUCANFD=m CONFIG_CAN_CTUCANFD_PCI=m CONFIG_CAN_CTUCANFD_PLATFORM=m +# CONFIG_CAN_ESD_402_PCI is not set # CONFIG_CAN_IFI_CANFD is not set CONFIG_CAN_M_CAN=m CONFIG_CAN_M_CAN_PCI=m @@ -3545,7 +3585,6 @@ CONFIG_RTL8723DS=m # CONFIG_RTL8821CU is not set # CONFIG_88XXAU is not set CONFIG_RTL8192EU=m -CONFIG_RTL8189FS=m CONFIG_RTL8189ES=m CONFIG_WLAN_VENDOR_ZYDAS=y CONFIG_ZD1211RW=m @@ -3753,6 +3792,8 @@ CONFIG_TOUCHSCREEN_EGALAX_SERIAL=m CONFIG_TOUCHSCREEN_EXC3000=m CONFIG_TOUCHSCREEN_FUJITSU=m CONFIG_TOUCHSCREEN_GOODIX=m +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set CONFIG_TOUCHSCREEN_HIDEEP=m CONFIG_TOUCHSCREEN_HYCON_HY46XX=m # CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX is not set @@ -3907,7 +3948,6 @@ CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y @@ -3993,6 +4033,7 @@ CONFIG_HVC_XEN_FRONTEND=y # CONFIG_HVC_DCC is not set CONFIG_SERIAL_DEV_BUS=y CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_TTY_PRINTK is not set CONFIG_VIRTIO_CONSOLE=y # CONFIG_IPMI_HANDLER is not set # CONFIG_SSIF_IPMI_BMC is not set @@ -4119,6 +4160,7 @@ CONFIG_DW_I3C_MASTER=m CONFIG_SVC_I3C_MASTER=m CONFIG_MIPI_I3C_HCI=m CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set CONFIG_SPI_MASTER=y CONFIG_SPI_MEM=y @@ -4200,6 +4242,7 @@ CONFIG_PTP_1588_CLOCK_INES=m CONFIG_PTP_1588_CLOCK_KVM=m CONFIG_PTP_1588_CLOCK_IDT82P33=m CONFIG_PTP_1588_CLOCK_IDTCM=m +# CONFIG_PTP_1588_CLOCK_FC3W is not set # CONFIG_PTP_1588_CLOCK_MOCK is not set CONFIG_PTP_1588_CLOCK_OCP=m # end of PTP clock support @@ -4210,7 +4253,9 @@ CONFIG_PINMUX=y CONFIG_GENERIC_PINMUX_FUNCTIONS=y CONFIG_PINCONF=y CONFIG_GENERIC_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set CONFIG_PINCTRL_AS3722=m +# CONFIG_PINCTRL_AW9523 is not set # CONFIG_PINCTRL_CY8C95X0 is not set CONFIG_PINCTRL_MAX77620=y # CONFIG_PINCTRL_MCP23S08 is not set @@ -4232,6 +4277,8 @@ CONFIG_GPIOLIB_FASTPATH_LIMIT=512 CONFIG_OF_GPIO=y CONFIG_GPIOLIB_IRQCHIP=y CONFIG_OF_GPIO_MM_GPIOCHIP=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y CONFIG_GPIO_CDEV=y CONFIG_GPIO_CDEV_V1=y CONFIG_GPIO_GENERIC=y @@ -4285,6 +4332,7 @@ CONFIG_GPIO_TPIC2810=m CONFIG_GPIO_ADP5520=m CONFIG_GPIO_BD71815=m CONFIG_GPIO_BD71828=m +# CONFIG_GPIO_CROS_EC is not set CONFIG_GPIO_DLN2=m CONFIG_GPIO_MAX77620=y CONFIG_GPIO_MAX77650=m @@ -4339,6 +4387,7 @@ CONFIG_W1_MASTER_DS2490=m CONFIG_W1_MASTER_DS2482=m CONFIG_W1_MASTER_GPIO=m CONFIG_W1_MASTER_SGI=m +# CONFIG_W1_MASTER_UART is not set # end of 1-wire Bus Masters # @@ -4463,10 +4512,12 @@ CONFIG_SENSORS_AHT10=m CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m CONFIG_SENSORS_AS370=m CONFIG_SENSORS_ASC7621=m +# CONFIG_SENSORS_ASUS_ROG_RYUJIN is not set CONFIG_SENSORS_AXI_FAN_CONTROL=m # CONFIG_SENSORS_ARM_SCMI is not set CONFIG_SENSORS_ARM_SCPI=m CONFIG_SENSORS_ATXP1=m +# CONFIG_SENSORS_CHIPCAP2 is not set # CONFIG_SENSORS_CORSAIR_CPRO is not set CONFIG_SENSORS_CORSAIR_PSU=m CONFIG_SENSORS_DRIVETEMP=m @@ -4504,6 +4555,7 @@ CONFIG_SENSORS_LTC4222=m CONFIG_SENSORS_LTC4245=m CONFIG_SENSORS_LTC4260=m CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_LTC4282 is not set CONFIG_SENSORS_MAX1111=m CONFIG_SENSORS_MAX127=m CONFIG_SENSORS_MAX16065=m @@ -4553,6 +4605,7 @@ CONFIG_SENSORS_NCT7802=m CONFIG_SENSORS_NCT7904=m CONFIG_SENSORS_NPCM7XX=m CONFIG_SENSORS_NZXT_KRAKEN2=m +# CONFIG_SENSORS_NZXT_KRAKEN3 is not set CONFIG_SENSORS_NZXT_SMART2=m CONFIG_SENSORS_OCC_P8_I2C=m CONFIG_SENSORS_OCC=m @@ -4596,6 +4649,7 @@ CONFIG_SENSORS_MP2888=m CONFIG_SENSORS_MP5023=m # CONFIG_SENSORS_MP5990 is not set # CONFIG_SENSORS_MPQ7932 is not set +# CONFIG_SENSORS_MPQ8785 is not set CONFIG_SENSORS_PIM4328=m # CONFIG_SENSORS_PLI1209BC is not set CONFIG_SENSORS_PM6764TR=m @@ -4612,6 +4666,7 @@ CONFIG_SENSORS_XDPE152=m CONFIG_SENSORS_XDPE122=m # CONFIG_SENSORS_XDPE122_REGULATOR is not set CONFIG_SENSORS_ZL6100=m +# CONFIG_SENSORS_PT5161L is not set CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_SBTSI=m CONFIG_SENSORS_SBRMI=m @@ -4672,7 +4727,6 @@ CONFIG_THERMAL_STATISTICS=y CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y CONFIG_THERMAL_OF=y -CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set @@ -4707,6 +4761,7 @@ CONFIG_WATCHDOG_SYSFS=y # CONFIG_SOFT_WATCHDOG=m CONFIG_BD957XMUF_WATCHDOG=m +# CONFIG_CROS_EC_WATCHDOG is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_XILINX_WATCHDOG is not set # CONFIG_XILINX_WINDOW_WATCHDOG is not set @@ -5464,8 +5519,6 @@ CONFIG_VIDEOBUF2_VMALLOC=m CONFIG_VIDEOBUF2_DMA_SG=m # end of Media drivers -CONFIG_MEDIA_HIDE_ANCILLARY_SUBDRV=y - # # Media ancillary drivers # @@ -5576,23 +5629,108 @@ CONFIG_VIDEO_LM3646=m # end of Flash devices # -# audio, video and radio I2C drivers auto-selected by 'Autoselect ancillary drivers' +# Audio decoders, processors and mixers # +# CONFIG_VIDEO_CS3308 is not set +# CONFIG_VIDEO_CS5345 is not set CONFIG_VIDEO_CS53L32A=m CONFIG_VIDEO_MSP3400=m CONFIG_VIDEO_SONY_BTF_MPX=m +# CONFIG_VIDEO_TDA1997X is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_TVAUDIO is not set CONFIG_VIDEO_UDA1342=m +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_WM8739 is not set CONFIG_VIDEO_WM8775=m +# end of Audio decoders, processors and mixers + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set +# end of RDS decoders + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV748X is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_ISL7998X is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_ML86V7667 is not set +# CONFIG_VIDEO_SAA7110 is not set CONFIG_VIDEO_SAA711X=m +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TC358746 is not set +# CONFIG_VIDEO_TVP514X is not set CONFIG_VIDEO_TVP5150=m +# CONFIG_VIDEO_TVP7002 is not set CONFIG_VIDEO_TW2804=m +# CONFIG_VIDEO_TW9900 is not set CONFIG_VIDEO_TW9903=m CONFIG_VIDEO_TW9906=m +# CONFIG_VIDEO_TW9910 is not set +# CONFIG_VIDEO_VPX3220 is not set # # Video and audio decoders # +# CONFIG_VIDEO_SAA717X is not set CONFIG_VIDEO_CX25840=m +# end of Video decoders + +# +# Video encoders +# +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_THS8200 is not set +# end of Video encoders + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set +# end of Video improvement chips + +# +# Audio/Video compression chips +# +# CONFIG_VIDEO_SAA6752HS is not set +# end of Audio/Video compression chips + +# +# SDR tuner chips +# +# CONFIG_SDR_MAX2175 is not set +# end of SDR tuner chips + +# +# Miscellaneous helper chips +# +# CONFIG_VIDEO_I2C is not set +# CONFIG_VIDEO_M52790 is not set +# CONFIG_VIDEO_ST_MIPID02 is not set +# CONFIG_VIDEO_THS7303 is not set +# end of Miscellaneous helper chips # # Video serializers and deserializers @@ -5602,10 +5740,6 @@ CONFIG_VIDEO_CX25840=m # CONFIG_VIDEO_DS90UB960 is not set # end of Video serializers and deserializers -# -# SPI I2C drivers auto-selected by 'Autoselect ancillary drivers' -# - # # Media SPI Adapters # @@ -5616,7 +5750,7 @@ CONFIG_VIDEO_GS1662=m CONFIG_MEDIA_TUNER=m # -# Tuner drivers auto-selected by 'Autoselect ancillary drivers' +# Customize TV tuners # CONFIG_MEDIA_TUNER_E4000=m CONFIG_MEDIA_TUNER_FC0011=m @@ -5624,15 +5758,19 @@ CONFIG_MEDIA_TUNER_FC0012=m CONFIG_MEDIA_TUNER_FC0013=m CONFIG_MEDIA_TUNER_FC2580=m CONFIG_MEDIA_TUNER_IT913X=m +# CONFIG_MEDIA_TUNER_M88RS6000T is not set CONFIG_MEDIA_TUNER_MAX2165=m CONFIG_MEDIA_TUNER_MC44S803=m CONFIG_MEDIA_TUNER_MSI001=m CONFIG_MEDIA_TUNER_MT2060=m CONFIG_MEDIA_TUNER_MT2063=m CONFIG_MEDIA_TUNER_MT20XX=m +# CONFIG_MEDIA_TUNER_MT2131 is not set CONFIG_MEDIA_TUNER_MT2266=m +# CONFIG_MEDIA_TUNER_MXL301RF is not set CONFIG_MEDIA_TUNER_MXL5005S=m CONFIG_MEDIA_TUNER_MXL5007T=m +# CONFIG_MEDIA_TUNER_QM1D1B0004 is not set CONFIG_MEDIA_TUNER_QM1D1C0042=m CONFIG_MEDIA_TUNER_QT1010=m CONFIG_MEDIA_TUNER_R820T=m @@ -5651,19 +5789,23 @@ CONFIG_MEDIA_TUNER_TUA9001=m CONFIG_MEDIA_TUNER_XC2028=m CONFIG_MEDIA_TUNER_XC4000=m CONFIG_MEDIA_TUNER_XC5000=m +# end of Customize TV tuners # -# DVB Frontend drivers auto-selected by 'Autoselect ancillary drivers' +# Customise DVB Frontends # # # Multistandard (satellite) frontends # CONFIG_DVB_M88DS3103=m +# CONFIG_DVB_MXL5XX is not set CONFIG_DVB_STB0899=m CONFIG_DVB_STB6100=m CONFIG_DVB_STV090x=m +# CONFIG_DVB_STV0910 is not set CONFIG_DVB_STV6110x=m +# CONFIG_DVB_STV6111 is not set # # Multistandard (cable + terrestrial) frontends @@ -5677,10 +5819,13 @@ CONFIG_DVB_TDA18271C2DD=m # # DVB-S (satellite) frontends # +# CONFIG_DVB_CX24110 is not set CONFIG_DVB_CX24116=m +# CONFIG_DVB_CX24117 is not set CONFIG_DVB_CX24120=m CONFIG_DVB_CX24123=m CONFIG_DVB_DS3000=m +# CONFIG_DVB_MB86A16 is not set CONFIG_DVB_MT312=m CONFIG_DVB_S5H1420=m CONFIG_DVB_SI21XX=m @@ -5692,10 +5837,14 @@ CONFIG_DVB_STV6110=m CONFIG_DVB_TDA10071=m CONFIG_DVB_TDA10086=m CONFIG_DVB_TDA8083=m +# CONFIG_DVB_TDA8261 is not set CONFIG_DVB_TDA826X=m CONFIG_DVB_TS2020=m +# CONFIG_DVB_TUA6100 is not set CONFIG_DVB_TUNER_CX24113=m CONFIG_DVB_TUNER_ITD1000=m +# CONFIG_DVB_VES1X93 is not set +# CONFIG_DVB_ZL10036 is not set CONFIG_DVB_ZL10039=m # @@ -5711,24 +5860,31 @@ CONFIG_DVB_DIB3000MB=m CONFIG_DVB_DIB3000MC=m CONFIG_DVB_DIB7000M=m CONFIG_DVB_DIB7000P=m +# CONFIG_DVB_DIB9000 is not set CONFIG_DVB_DRXD=m CONFIG_DVB_EC100=m CONFIG_DVB_GP8PSK_FE=m +# CONFIG_DVB_L64781 is not set CONFIG_DVB_MT352=m CONFIG_DVB_NXT6000=m CONFIG_DVB_RTL2830=m CONFIG_DVB_RTL2832=m CONFIG_DVB_RTL2832_SDR=m +# CONFIG_DVB_S5H1432 is not set CONFIG_DVB_SI2168=m +# CONFIG_DVB_SP887X is not set +# CONFIG_DVB_STV0367 is not set CONFIG_DVB_TDA10048=m CONFIG_DVB_TDA1004X=m CONFIG_DVB_ZD1301_DEMOD=m CONFIG_DVB_ZL10353=m +# CONFIG_DVB_CXD2880 is not set # # DVB-C (cable) frontends # CONFIG_DVB_STV0297=m +# CONFIG_DVB_TDA10021 is not set CONFIG_DVB_TDA10023=m CONFIG_DVB_VES1820=m @@ -5745,6 +5901,8 @@ CONFIG_DVB_LGDT3306A=m CONFIG_DVB_LGDT330X=m CONFIG_DVB_MXL692=m CONFIG_DVB_NXT200X=m +# CONFIG_DVB_OR51132 is not set +# CONFIG_DVB_OR51211 is not set CONFIG_DVB_S5H1409=m CONFIG_DVB_S5H1411=m @@ -5758,6 +5916,7 @@ CONFIG_DVB_S921=m # # ISDB-S (satellite) & ISDB-T (terrestrial) frontends # +# CONFIG_DVB_MN88443X is not set CONFIG_DVB_TC90522=m # @@ -5772,20 +5931,30 @@ CONFIG_DVB_TUNER_DIB0090=m # CONFIG_DVB_A8293=m CONFIG_DVB_AF9033=m +# CONFIG_DVB_ASCOT2E is not set CONFIG_DVB_ATBM8830=m +# CONFIG_DVB_HELENE is not set +# CONFIG_DVB_HORUS3A is not set +# CONFIG_DVB_ISL6405 is not set CONFIG_DVB_ISL6421=m CONFIG_DVB_ISL6423=m CONFIG_DVB_IX2505V=m +# CONFIG_DVB_LGS8GL5 is not set CONFIG_DVB_LGS8GXX=m +# CONFIG_DVB_LNBH25 is not set +# CONFIG_DVB_LNBH29 is not set CONFIG_DVB_LNBP21=m CONFIG_DVB_LNBP22=m CONFIG_DVB_M88RS2000=m +# CONFIG_DVB_TDA665x is not set CONFIG_DVB_DRX39XYJ=m # # Common Interface (EN50221) controller drivers # +# CONFIG_DVB_CXD2099 is not set CONFIG_DVB_SP2=m +# end of Customise DVB Frontends # # Tools to develop new frontends @@ -5797,8 +5966,7 @@ CONFIG_DVB_DUMMY_FE=m # Graphics support # CONFIG_APERTURE_HELPERS=y -CONFIG_VIDEO_CMDLINE=y -CONFIG_VIDEO_NOMODESET=y +CONFIG_VIDEO=y # CONFIG_AUXDISPLAY is not set CONFIG_DRM=y CONFIG_DRM_MIPI_DBI=m @@ -5806,8 +5974,11 @@ CONFIG_DRM_MIPI_DSI=y # CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_KUNIT_TEST is not set CONFIG_DRM_KMS_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set # CONFIG_DRM_LOAD_EDID_FIRMWARE is not set CONFIG_DRM_DP_AUX_BUS=m CONFIG_DRM_DISPLAY_HELPER=y @@ -5874,15 +6045,15 @@ CONFIG_DRM_PANEL_ARM_VERSATILE=m # CONFIG_DRM_PANEL_AUO_A030JTN01 is not set CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m CONFIG_DRM_PANEL_BOE_HIMAX8279D=m +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m -CONFIG_DRM_PANEL_DSI_CM=m -CONFIG_DRM_PANEL_LVDS=m -CONFIG_DRM_PANEL_SIMPLE=m -CONFIG_DRM_PANEL_EDP=m # CONFIG_DRM_PANEL_EBBG_FT8719 is not set CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_DSI_CM=m +CONFIG_DRM_PANEL_LVDS=m +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set CONFIG_DRM_PANEL_ILITEK_IL9322=m CONFIG_DRM_PANEL_ILITEK_ILI9341=m @@ -5892,17 +6063,17 @@ CONFIG_DRM_PANEL_ILITEK_ILI9881C=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m CONFIG_DRM_PANEL_INNOLUX_P079ZCA=m # CONFIG_DRM_PANEL_JADARD_JD9365DA_H3 is not set -CONFIG_DRM_PANEL_JDI_LT070ME05000=m # CONFIG_DRM_PANEL_JDI_LPM102A188A is not set +CONFIG_DRM_PANEL_JDI_LT070ME05000=m CONFIG_DRM_PANEL_JDI_R63452=m CONFIG_DRM_PANEL_KHADAS_TS050=m CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m # CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829=m -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set CONFIG_DRM_PANEL_LG_LB035Q02=m # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set +# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set CONFIG_DRM_PANEL_NEC_NL8048HL11=m # CONFIG_DRM_PANEL_NEWVISION_NV3051D is not set CONFIG_DRM_PANEL_NEWVISION_NV3052C=m @@ -5911,8 +6082,8 @@ CONFIG_DRM_PANEL_NOVATEK_NT35510=m CONFIG_DRM_PANEL_NOVATEK_NT35950=m # CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set CONFIG_DRM_PANEL_NOVATEK_NT36672A=m +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set CONFIG_DRM_PANEL_NOVATEK_NT39016=m -# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO=m # CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m @@ -5923,15 +6094,16 @@ CONFIG_DRM_PANEL_RAYDIUM_RM67191=m CONFIG_DRM_PANEL_RAYDIUM_RM68200=m # CONFIG_DRM_PANEL_RAYDIUM_RM692E5 is not set CONFIG_DRM_PANEL_RONBO_RB070D30=m +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m CONFIG_DRM_PANEL_SAMSUNG_DB7430=m +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set CONFIG_DRM_PANEL_SAMSUNG_S6D16D0=m CONFIG_DRM_PANEL_SAMSUNG_S6D27A1=m # CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2=m CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m # CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set -CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m # CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set CONFIG_DRM_PANEL_SAMSUNG_SOFEF00=m CONFIG_DRM_PANEL_SEIKO_43WVF1G=m @@ -5942,19 +6114,21 @@ CONFIG_DRM_PANEL_SHARP_LS060T1SX01=m CONFIG_DRM_PANEL_SITRONIX_ST7701=m # CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set # CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set -# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set CONFIG_DRM_PANEL_SONY_ACX565AKM=m # CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m # CONFIG_DRM_PANEL_STARTEK_KD070FHFID015 is not set +CONFIG_DRM_PANEL_EDP=m +CONFIG_DRM_PANEL_SIMPLE=m +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set CONFIG_DRM_PANEL_TDO_TL070WSH30=m CONFIG_DRM_PANEL_TPO_TD028TTEC1=m CONFIG_DRM_PANEL_TPO_TD043MTEA1=m CONFIG_DRM_PANEL_TPO_TPG110=m CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m +# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set # CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set # CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set -# CONFIG_DRM_PANEL_VISIONOX_R66451 is not set CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m CONFIG_DRM_PANEL_XINPENG_XPP055C272=m # end of Display Panels @@ -6129,6 +6303,7 @@ CONFIG_LCD_CLASS_DEVICE=m CONFIG_LCD_OTM3225A=m CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD253 is not set +# CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LM3533=m CONFIG_BACKLIGHT_PWM=m @@ -6184,6 +6359,7 @@ CONFIG_SND_DMAENGINE_PCM=m CONFIG_SND_HWDEP=m CONFIG_SND_SEQ_DEVICE=m CONFIG_SND_RAWMIDI=m +# CONFIG_SND_CORE_TEST is not set CONFIG_SND_COMPRESS_OFFLOAD=m CONFIG_SND_JACK=y CONFIG_SND_JACK_INPUT_DEV=y @@ -6409,6 +6585,7 @@ CONFIG_SND_SOC_BD28623=m # CONFIG_SND_SOC_BT_SCO is not set # CONFIG_SND_SOC_CHV3_CODEC is not set CONFIG_SND_SOC_CROS_EC_CODEC=m +# CONFIG_SND_SOC_CS_AMP_LIB_TEST is not set # CONFIG_SND_SOC_CS35L32 is not set # CONFIG_SND_SOC_CS35L33 is not set # CONFIG_SND_SOC_CS35L34 is not set @@ -6790,6 +6967,7 @@ CONFIG_USB_OTG=y CONFIG_USB_OTG_FSM=m CONFIG_USB_LEDS_TRIGGER_USBPORT=y CONFIG_USB_AUTOSUSPEND_DELAY=2 +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 CONFIG_USB_MON=m # @@ -7017,6 +7195,7 @@ CONFIG_USB_ULPI_VIEWPORT=y # end of USB Physical Layer drivers CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set # CONFIG_USB_GADGET_DEBUG_FILES is not set # CONFIG_USB_GADGET_DEBUG_FS is not set CONFIG_USB_GADGET_VBUS_DRAW=2 @@ -7146,6 +7325,7 @@ CONFIG_TYPEC_HD3SS3220=m CONFIG_TYPEC_MUX_FSA4480=m # CONFIG_TYPEC_MUX_GPIO_SBU is not set CONFIG_TYPEC_MUX_PI3USB30532=m +# CONFIG_TYPEC_MUX_IT5205 is not set # CONFIG_TYPEC_MUX_NB7VPQ904M is not set # CONFIG_TYPEC_MUX_PTN36502 is not set # CONFIG_TYPEC_MUX_WCD939X_USBSS is not set @@ -7194,6 +7374,7 @@ CONFIG_MMC_DW_PLTFM=y # CONFIG_MMC_DW_BLUEFIELD is not set CONFIG_MMC_DW_EXYNOS=y CONFIG_MMC_DW_HI3798CV200=m +# CONFIG_MMC_DW_HI3798MV200 is not set CONFIG_MMC_DW_K3=y # CONFIG_MMC_DW_PCI is not set CONFIG_MMC_DW_ROCKCHIP=y @@ -7235,8 +7416,6 @@ CONFIG_LEDS_LM3692X=m CONFIG_LEDS_GPIO=y # CONFIG_LEDS_LP3944 is not set # CONFIG_LEDS_LP3952 is not set -# CONFIG_LEDS_LP50XX is not set -# CONFIG_LEDS_LP55XX_COMMON is not set # CONFIG_LEDS_LP8860 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -7513,6 +7692,7 @@ CONFIG_VFIO_PCI_CORE=m CONFIG_VFIO_PCI_MMAP=y CONFIG_VFIO_PCI_INTX=y CONFIG_VFIO_PCI=m +# CONFIG_NVGRACE_GPU_VFIO_PCI is not set # end of VFIO support for PCI devices # @@ -7652,7 +7832,6 @@ CONFIG_VIDEO_ROCKCHIP_VDEC=m # StarFive media platform drivers # # CONFIG_STAGING_MEDIA_DEPRECATED is not set -# CONFIG_STAGING_BOARD is not set # CONFIG_LTE_GDM724X is not set CONFIG_FB_TFT=m CONFIG_FB_TFT_AGM1264K_FL=m @@ -7878,6 +8057,7 @@ CONFIG_LITEX_SOC_CONTROLLER=m # Qualcomm SoC drivers # CONFIG_QCOM_QMI_HELPERS=m +# CONFIG_QCOM_PBS is not set # end of Qualcomm SoC drivers CONFIG_ROCKCHIP_GRF=y @@ -7999,6 +8179,7 @@ CONFIG_BMC150_ACCEL=m CONFIG_BMC150_ACCEL_I2C=m CONFIG_BMC150_ACCEL_SPI=m CONFIG_BMI088_ACCEL=m +CONFIG_BMI088_ACCEL_I2C=m CONFIG_BMI088_ACCEL_SPI=m CONFIG_DA280=m CONFIG_DA311=m @@ -8064,6 +8245,7 @@ CONFIG_AD7887=m CONFIG_AD7923=m CONFIG_AD7949=m CONFIG_AD799X=m +# CONFIG_AD9467 is not set # CONFIG_ADI_AXI_ADC is not set # CONFIG_CC10001_ADC is not set CONFIG_DLN2_ADC=m @@ -8090,6 +8272,7 @@ CONFIG_LTC2496=m # CONFIG_MCP3564 is not set # CONFIG_MCP3911 is not set # CONFIG_NAU7802 is not set +# CONFIG_PAC1934 is not set # CONFIG_QCOM_SPMI_IADC is not set # CONFIG_QCOM_SPMI_VADC is not set # CONFIG_QCOM_SPMI_ADC5 is not set @@ -8107,6 +8290,7 @@ CONFIG_TI_ADC161S626=m CONFIG_TI_ADS1015=m # CONFIG_TI_ADS7924 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1298 is not set CONFIG_TI_ADS7950=m CONFIG_TI_ADS8344=m CONFIG_TI_ADS8688=m @@ -8274,6 +8458,7 @@ CONFIG_ADMV8818=m # CONFIG_ADF4350 is not set CONFIG_ADF4371=m # CONFIG_ADF4377 is not set +# CONFIG_ADMFM2000 is not set CONFIG_ADMV1013=m # CONFIG_ADMV1014 is not set # CONFIG_ADMV4420 is not set @@ -8433,6 +8618,7 @@ CONFIG_ZOPT2201=m # # Magnetometer sensors # +# CONFIG_AF8133J is not set CONFIG_AK8974=m CONFIG_AK8975=m CONFIG_AK09911=m @@ -8468,6 +8654,7 @@ CONFIG_HID_SENSOR_INCLINOMETER_3D=m CONFIG_HID_SENSOR_DEVICE_ROTATION=m # end of Inclinometer sensors +# CONFIG_IIO_GTS_KUNIT_TEST is not set # CONFIG_IIO_FORMAT_KUNIT_TEST is not set # @@ -8593,6 +8780,7 @@ CONFIG_MAX31865=m # CONFIG_NTB is not set CONFIG_PWM=y CONFIG_PWM_SYSFS=y +# CONFIG_PWM_DEBUG is not set CONFIG_PWM_ATMEL_TCB=m # CONFIG_PWM_CLK is not set CONFIG_PWM_CROS_EC=m @@ -8623,7 +8811,9 @@ CONFIG_PARTITION_PERCPU=y # CONFIG_IPACK_BUS is not set CONFIG_ARCH_HAS_RESET_CONTROLLER=y CONFIG_RESET_CONTROLLER=y +# CONFIG_RESET_GPIO is not set CONFIG_RESET_SCMI=y +# CONFIG_RESET_SIMPLE is not set # CONFIG_RESET_TI_SYSCON is not set # CONFIG_RESET_TI_TPS380X is not set @@ -8662,6 +8852,7 @@ CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=m CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y CONFIG_PHY_ROCKCHIP_PCIE=y +# CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX is not set CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y CONFIG_PHY_ROCKCHIP_TYPEC=y CONFIG_PHY_ROCKCHIP_USB=y @@ -8689,6 +8880,7 @@ CONFIG_HISI_PCIE_PMU=m # CONFIG_HNS3_PMU is not set CONFIG_DWC_PCIE_PMU=y # CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU is not set +# CONFIG_CXL_PMU is not set # end of Performance monitor support CONFIG_RAS=y @@ -8872,6 +9064,7 @@ CONFIG_AUTOFS_FS=m CONFIG_FUSE_FS=y CONFIG_CUSE=m CONFIG_VIRTIO_FS=m +CONFIG_FUSE_PASSTHROUGH=y CONFIG_OVERLAY_FS=y # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -8915,11 +9108,11 @@ CONFIG_FAT_DEFAULT_UTF8=y CONFIG_FAT_KUNIT_TEST=m CONFIG_EXFAT_FS=m CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" -# CONFIG_NTFS_FS is not set CONFIG_NTFS3_FS=m # CONFIG_NTFS3_64BIT_CLUSTER is not set CONFIG_NTFS3_LZX_XPRESS=y CONFIG_NTFS3_FS_POSIX_ACL=y +# CONFIG_NTFS_FS is not set # end of DOS/FAT/EXFAT/NT Filesystems # @@ -9247,12 +9440,7 @@ CONFIG_LSM="lockdown,yama,integrity,apparmor" # # Memory initialization # -CONFIG_CC_HAS_AUTO_VAR_INIT_PATTERN=y -CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO_BARE=y -CONFIG_CC_HAS_AUTO_VAR_INIT_ZERO=y CONFIG_INIT_STACK_NONE=y -# CONFIG_INIT_STACK_ALL_PATTERN is not set -# CONFIG_INIT_STACK_ALL_ZERO is not set CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y # CONFIG_INIT_ON_FREE_DEFAULT_ON is not set CONFIG_CC_HAS_ZERO_CALL_USED_REGS=y @@ -9287,6 +9475,7 @@ CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_SIG=y CONFIG_CRYPTO_SIG2=y CONFIG_CRYPTO_SKCIPHER=y CONFIG_CRYPTO_SKCIPHER2=y @@ -9558,7 +9747,6 @@ CONFIG_GENERIC_NET_UTILS=y CONFIG_CORDIC=m # CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y -CONFIG_GENERIC_PCI_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y CONFIG_ARCH_USE_SYM_ANNOTATIONS=y @@ -9689,6 +9877,7 @@ CONFIG_CMA_ALIGNMENT=8 # CONFIG_DMA_API_DEBUG is not set # CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y +# CONFIG_FORCE_NR_CPUS is not set CONFIG_CPU_RMAP=y CONFIG_DQL=y CONFIG_GLOB=y @@ -9749,25 +9938,35 @@ CONFIG_PRINTK_TIME=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set CONFIG_DYNAMIC_DEBUG=y CONFIG_DYNAMIC_DEBUG_CORE=y CONFIG_SYMBOLIC_ERRNAME=y CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options -# CONFIG_DEBUG_KERNEL is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y # # Compile-time checks and compiler options # CONFIG_AS_HAS_NON_CONST_ULEB128=y +CONFIG_DEBUG_INFO_NONE=y +# CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set # CONFIG_HEADERS_INSTALL is not set # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set CONFIG_ARCH_WANT_FRAME_POINTERS=y CONFIG_FRAME_POINTER=y +# CONFIG_VMLINUX_MAP is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options # @@ -9782,35 +9981,52 @@ CONFIG_DEBUG_FS_ALLOW_ALL=y # CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set # CONFIG_DEBUG_FS_ALLOW_NONE is not set CONFIG_HAVE_ARCH_KGDB=y -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_KGDB is not set +CONFIG_ARCH_HAS_UBSAN=y # CONFIG_UBSAN is not set +CONFIG_HAVE_ARCH_KCSAN=y CONFIG_HAVE_KCSAN_COMPILER=y +# CONFIG_KCSAN is not set # end of Generic Kernel Debugging Instruments # # Networking Debugging # +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +# CONFIG_NET_NS_REFCNT_TRACKER is not set +# CONFIG_DEBUG_NET is not set # end of Networking Debugging # # Memory Debugging # # CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set CONFIG_SLUB_DEBUG=y # CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_PAGE_OWNER is not set # CONFIG_PAGE_TABLE_CHECK is not set # CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_PAGE_REF is not set # CONFIG_DEBUG_RODATA_TEST is not set CONFIG_ARCH_HAS_DEBUG_WX=y # CONFIG_DEBUG_WX is not set CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set # CONFIG_PER_VMA_LOCK_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set # CONFIG_SHRINKER_DEBUG is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_SCHED_STACK_END_CHECK is not set CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_VM_PGTABLE is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_PER_CPU_MAPS is not set CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_SW_TAGS=y CONFIG_HAVE_ARCH_KASAN_HW_TAGS=y @@ -9823,49 +10039,87 @@ CONFIG_HAVE_ARCH_KFENCE=y # CONFIG_KFENCE is not set # end of Memory Debugging +# CONFIG_DEBUG_SHIRQ is not set + # # Debug Oops, Lockups and Hangs # # CONFIG_PANIC_ON_OOPS is not set CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=0 +# CONFIG_SOFTLOCKUP_DETECTOR is not set CONFIG_HAVE_HARDLOCKUP_DETECTOR_BUDDY=y +# CONFIG_HARDLOCKUP_DETECTOR is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_WQ_WATCHDOG is not set +# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set CONFIG_TEST_LOCKUP=m # end of Debug Oops, Lockups and Hangs # # Scheduler Debugging # +CONFIG_SCHED_DEBUG=y CONFIG_SCHED_INFO=y +# CONFIG_SCHEDSTATS is not set # end of Scheduler Debugging # CONFIG_DEBUG_TIMEKEEPING is not set +# CONFIG_DEBUG_PREEMPT is not set # # Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_LOCK_DEBUGGING_SUPPORT=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set # CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set # end of Lock Debugging (spinlocks, mutexes, etc...) # CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set # # Debug kernel data structures # +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set # CONFIG_DEBUG_CLOSURES is not set +# CONFIG_DEBUG_MAPLE_TREE is not set # end of Debug kernel data structures # # RCU Debugging # +# CONFIG_RCU_SCALE_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=60 CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 # CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_RCU_TRACE=y +# CONFIG_RCU_EQS_DEBUG is not set # end of RCU Debugging +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_LATENCYTOP is not set +# CONFIG_DEBUG_CGROUP_REF is not set CONFIG_NOP_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y @@ -9938,10 +10192,11 @@ CONFIG_KUNIT=m # CONFIG_KUNIT_EXAMPLE_TEST is not set # CONFIG_KUNIT_ALL_TESTS is not set CONFIG_KUNIT_DEFAULT_ENABLED=y +# CONFIG_NOTIFIER_ERROR_INJECTION is not set CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_DHRY is not set # CONFIG_LKDTM is not set @@ -9951,12 +10206,18 @@ CONFIG_RUNTIME_TESTING_MENU=y # CONFIG_TEST_SORT is not set CONFIG_TEST_DIV64=m # CONFIG_TEST_IOV_ITER is not set +# CONFIG_KPROBES_SANITY_TEST is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_TEST_REF_TRACKER is not set +# CONFIG_RBTREE_TEST is not set CONFIG_REED_SOLOMON_TEST=m +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_PERCPU_TEST is not set # CONFIG_ATOMIC64_SELFTEST is not set CONFIG_ASYNC_RAID6_TEST=m # CONFIG_TEST_HEXDUMP is not set -# CONFIG_STRING_SELFTEST is not set -# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_STRING_KUNIT_TEST is not set +# CONFIG_STRING_HELPERS_KUNIT_TEST is not set # CONFIG_TEST_KSTRTOX is not set # CONFIG_TEST_PRINTF is not set CONFIG_TEST_SCANF=m @@ -9988,7 +10249,6 @@ CONFIG_CMDLINE_KUNIT_TEST=m CONFIG_SLUB_KUNIT_TEST=m CONFIG_RATIONAL_KUNIT_TEST=m CONFIG_MEMCPY_KUNIT_TEST=m -# CONFIG_MEMCPY_SLOW_KUNIT_TEST is not set # CONFIG_IS_SIGNED_TYPE_KUNIT_TEST is not set # CONFIG_OVERFLOW_KUNIT_TEST is not set # CONFIG_STACKINIT_KUNIT_TEST is not set @@ -10003,6 +10263,7 @@ CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_TEST_MEMCAT_P=m # CONFIG_TEST_MEMINIT is not set # CONFIG_TEST_FREE_PAGES is not set +# CONFIG_TEST_OBJPOOL is not set CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y # end of Kernel Testing and Coverage diff --git a/config/kernel/linux-sunxi64-current.config b/config/kernel/linux-sunxi64-current.config index e8d0610b32ef..32537f818b0d 100644 --- a/config/kernel/linux-sunxi64-current.config +++ b/config/kernel/linux-sunxi64-current.config @@ -5446,6 +5446,7 @@ CONFIG_SND_SOC_MTK_BTCVSD=m # Allwinner SoC Audio support # CONFIG_SND_SUN4I_CODEC=y +CONFIG_SND_SUN50IW9_CODEC=m CONFIG_SND_SUN8I_CODEC=y CONFIG_SND_SUN8I_CODEC_ANALOG=y CONFIG_SND_SUN50I_CODEC_ANALOG=y @@ -5455,6 +5456,17 @@ CONFIG_SND_SUN50I_DMIC=m CONFIG_SND_SUN9I_HDMI_AUDIO=m CONFIG_SND_SUN8I_ADDA_PR_REGMAP=y # end of Allwinner SoC Audio support +CONFIG_SND_SOC_SUNXI_MACH=m +CONFIG_SND_SOC_SUNXI_AHUB_DAM=m +CONFIG_SND_SOC_SUNXI_INTERNALCODEC=m +CONFIG_SND_SOC_SUNXI_SUN50IW9_CODEC=m + +# +# Allwinner SoC Audio support V2 +# +CONFIG_SND_SOC_SUNXI_AAUDIO=m +CONFIG_SND_SOC_SUNXI_AHUB=m +# end of Allwinner SoC Audio support V2 CONFIG_SND_SOC_XILINX_I2S=m CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m diff --git a/config/kernel/linux-sunxi64-edge.config b/config/kernel/linux-sunxi64-edge.config index 8b6f28eaadde..484c934caa13 100644 --- a/config/kernel/linux-sunxi64-edge.config +++ b/config/kernel/linux-sunxi64-edge.config @@ -5468,6 +5468,7 @@ CONFIG_SND_SOC_MTK_BTCVSD=m # Allwinner SoC Audio support # CONFIG_SND_SUN4I_CODEC=y +CONFIG_SND_SUN50IW9_CODEC=m CONFIG_SND_SUN8I_CODEC=y CONFIG_SND_SUN8I_CODEC_ANALOG=y CONFIG_SND_SUN50I_CODEC_ANALOG=y @@ -5478,6 +5479,18 @@ CONFIG_SND_SUN9I_HDMI_AUDIO=m CONFIG_SND_SUN8I_ADDA_PR_REGMAP=y # end of Allwinner SoC Audio support +CONFIG_SND_SOC_SUNXI_MACH=m +CONFIG_SND_SOC_SUNXI_AHUB_DAM=m +CONFIG_SND_SOC_SUNXI_INTERNALCODEC=m +CONFIG_SND_SOC_SUNXI_SUN50IW9_CODEC=m + +# +# Allwinner SoC Audio support V2 +# +CONFIG_SND_SOC_SUNXI_AAUDIO=m +CONFIG_SND_SOC_SUNXI_AHUB=m +# end of Allwinner SoC Audio support V2 + CONFIG_SND_SOC_XILINX_I2S=m CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m CONFIG_SND_SOC_XILINX_SPDIF=m diff --git a/config/sources/families/include/meson64_common.inc b/config/sources/families/include/meson64_common.inc index 6b6ca61448a2..9928fe8341be 100644 --- a/config/sources/families/include/meson64_common.inc +++ b/config/sources/families/include/meson64_common.inc @@ -45,7 +45,7 @@ case $BRANCH in declare -g KERNEL_MAJOR_MINOR="6.6" ;; edge) - declare -g KERNEL_MAJOR_MINOR="6.8" + declare -g KERNEL_MAJOR_MINOR="6.9" ;; esac diff --git a/config/sources/families/include/meson_common.inc b/config/sources/families/include/meson_common.inc index ed8384ab9f31..c08a27f45741 100644 --- a/config/sources/families/include/meson_common.inc +++ b/config/sources/families/include/meson_common.inc @@ -51,7 +51,7 @@ case $BRANCH in ;; edge) - declare -g KERNEL_MAJOR_MINOR="6.8" + declare -g KERNEL_MAJOR_MINOR="6.9" ;; esac diff --git a/config/sources/families/include/rockchip64_common.inc b/config/sources/families/include/rockchip64_common.inc index a6fe349b9edf..cb06959501a9 100644 --- a/config/sources/families/include/rockchip64_common.inc +++ b/config/sources/families/include/rockchip64_common.inc @@ -32,7 +32,7 @@ case $BRANCH in ;; edge) - declare -g KERNEL_MAJOR_MINOR="6.8" + declare -g KERNEL_MAJOR_MINOR="6.9" declare -g LINUXFAMILY=rockchip64 declare -g LINUXCONFIG='linux-rockchip64-'$BRANCH ;; diff --git a/config/sources/families/rockchip.conf b/config/sources/families/rockchip.conf index e06326aaf89d..78521f63eb6e 100644 --- a/config/sources/families/rockchip.conf +++ b/config/sources/families/rockchip.conf @@ -56,7 +56,7 @@ case $BRANCH in edge) - declare -g KERNEL_MAJOR_MINOR="6.8" # Major and minor versions of this kernel. + declare -g KERNEL_MAJOR_MINOR="6.9" # Major and minor versions of this kernel. ;; esac diff --git a/lib/functions/compilation/patch/drivers_network.sh b/lib/functions/compilation/patch/drivers_network.sh index 3f2785e75ff3..2983d52ca27b 100644 --- a/lib/functions/compilation/patch/drivers_network.sh +++ b/lib/functions/compilation/patch/drivers_network.sh @@ -448,6 +448,11 @@ driver_uwe5622() { process_patch_file "${SRC}/patch/misc/wireless-uwe5622/wireless-uwe5622-Fix-compilation-with-6.7-kernel.patch" "applying" process_patch_file "${SRC}/patch/misc/wireless-uwe5622/wireless-uwe5622-reduce-system-load.patch" "applying" + + if linux-version compare "${version}" ge 6.9; then + process_patch_file "${SRC}/patch/misc/wireless-uwe5622/uwe5622-v6.9.patch" "applying" + fi + fi } @@ -525,6 +530,10 @@ driver_rtl8723cs() { process_patch_file "${SRC}/patch/misc/wireless-rtl8723cs/8723cs-Port-to-6.8.patch" "applying" fi + if linux-version compare "${version}" ge 6.9; then + process_patch_file "${SRC}/patch/misc/wireless-rtl8723cs/8723cs-Port-to-6.9.patch" "applying" + fi + } ### The vendor's RTL8723DS driver is still required for RockPI-S support because diff --git a/lib/functions/rootfs/distro-agnostic.sh b/lib/functions/rootfs/distro-agnostic.sh index 6b6f26b510b3..d9a54f5d939e 100644 --- a/lib/functions/rootfs/distro-agnostic.sh +++ b/lib/functions/rootfs/distro-agnostic.sh @@ -413,11 +413,6 @@ function install_distribution_agnostic() { # @TODO: rpardini: still needed? people might want working Samba disable_systemd_service_sdcard nmbd - # move sshd activation from ssh.service to ssh.socket (more realiable, avoids possible race condition on first boot) supplementary to ffee50a8a6b99bb4f35af90895e019eced7ff71b and 67250321918e59582b8f1003d331f4b1db253b21 - display_alert "Moving SSH activation from service to socket" "systemd" "info" - disable_systemd_service_sdcard ssh - chroot_sdcard systemctl enable ssh.socket - # disable low-level kernel messages for non betas if [[ -z $BETA ]]; then sed -i "s/^#kernel.printk*/kernel.printk/" "${SDCARD}"/etc/sysctl.conf diff --git a/lib/tools/common/patching_utils.py b/lib/tools/common/patching_utils.py index 69daea7c4f4c..d75cc80c27fa 100755 --- a/lib/tools/common/patching_utils.py +++ b/lib/tools/common/patching_utils.py @@ -28,6 +28,19 @@ REGEX_PATCH_FILENAMES = r"^patching file \"(.+)\"" log: logging.Logger = logging.getLogger("patching_utils") +# Magic strings and regex for rewriting patches' "index xxx....yyyy" lines +index_zero = f"{'0' * 12}" +index_from_zero = f"index {'0' * 12}..{'1' * 12}" +index_not_zero = f"index {'1' * 12}..{'2' * 12}" +index_rewrite_regexp: re.Pattern = re.compile(r"index ([0-9a-f]{12})\.\.([0-9a-f]{12})") + + +# Callback used for rewriting index lines. +def rewrite_indexes_callback(x: re.Match): # Preserve zero from's for new file creations. + if x.group(1) == index_zero: + return index_from_zero + return index_not_zero + class PatchRootDir: def __init__(self, abs_dir, root_type, patch_type, root_dir): @@ -808,7 +821,7 @@ def export_commit_as_patch(repo: git.Repo, commit: str): '--zero-commit', # do not use the git revision, instead 000000...0000 '--stat=120', # 'wider' stat output; default is 80 '--stat-graph-width=10', # shorten the diffgraph graph part, it's too long - '--abbrev=12', # force index length to 12 + '--abbrev=12', # force index length to 12 - essential for the regex below to work "-1", "--stdout", commit ], cwd=repo.working_tree_dir, @@ -823,7 +836,17 @@ def export_commit_as_patch(repo: git.Repo, commit: str): raise Exception(f"Failed to export commit {commit} to patch: {stderr_output}") if stdout_output == "": raise Exception(f"Failed to export commit {commit} to patch: no output") - return stdout_output + + # Now, massage the output. We don't want the "index 08c33ec7e9f1..528741fcc0ec 100644" lines changing every time. + # We do need to preserve "0000000000.." ones as that indicates new file creation. + # Use a regular expression and a callback to decide. Check the top of this file for the regex and callback. + rewritten_indexes = re.sub(index_rewrite_regexp, rewrite_indexes_callback, stdout_output) + + # If rewritten is same as original this didn't work, surely. + if rewritten_indexes == stdout_output: + raise Exception(f"Failed to rewrite indexes in patch output: {stdout_output}") + + return rewritten_indexes # Hack diff --git a/packages/bsp/common/lib/systemd/system/armbian-firstrun.service b/packages/bsp/common/lib/systemd/system/armbian-firstrun.service index 64a390950b7c..fb94b03823fa 100644 --- a/packages/bsp/common/lib/systemd/system/armbian-firstrun.service +++ b/packages/bsp/common/lib/systemd/system/armbian-firstrun.service @@ -5,6 +5,7 @@ [Unit] Description=Armbian first run tasks Before=getty.target system-getty.slice +After=ssh.service [Service] Type=simple diff --git a/patch/kernel/archive/meson-6.8/0030-tools-Makefile-delete-missing-cgroup_clean.patch b/patch/kernel/archive/meson-6.8/0030-tools-Makefile-delete-missing-cgroup_clean.patch deleted file mode 100644 index 295c38d575fa..000000000000 --- a/patch/kernel/archive/meson-6.8/0030-tools-Makefile-delete-missing-cgroup_clean.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: amazingfate -Date: Wed, 24 Jan 2024 18:03:52 +0800 -Subject: tools/Makefile: delete missing cgroup_clean - ---- - tools/Makefile | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/tools/Makefile b/tools/Makefile -index 37e9f6804832..9903abe51d5f 100644 ---- a/tools/Makefile -+++ b/tools/Makefile -@@ -169,7 +169,7 @@ acpi_clean: - cpupower_clean: - $(call descend,power/cpupower,clean) - --cgroup_clean counter_clean hv_clean firewire_clean bootconfig_clean spi_clean usb_clean virtio_clean mm_clean wmi_clean bpf_clean iio_clean gpio_clean objtool_clean leds_clean pci_clean firmware_clean debugging_clean tracing_clean: -+counter_clean hv_clean firewire_clean bootconfig_clean spi_clean usb_clean virtio_clean mm_clean wmi_clean bpf_clean iio_clean gpio_clean objtool_clean leds_clean pci_clean firmware_clean debugging_clean tracing_clean: - $(call descend,$(@:_clean=),clean) - - libapi_clean: -@@ -209,7 +209,7 @@ freefall_clean: - build_clean: - $(call descend,build,clean) - --clean: acpi_clean cgroup_clean counter_clean cpupower_clean hv_clean firewire_clean \ -+clean: acpi_clean counter_clean cpupower_clean hv_clean firewire_clean \ - perf_clean selftests_clean turbostat_clean bootconfig_clean spi_clean usb_clean virtio_clean \ - mm_clean bpf_clean iio_clean x86_energy_perf_policy_clean tmon_clean \ - freefall_clean build_clean libbpf_clean libsubcmd_clean \ --- -Armbian - diff --git a/patch/kernel/archive/meson-6.8/generic-0001-m8-m8b-m8m2-Support-HDMI.patch b/patch/kernel/archive/meson-6.8/generic-0001-m8-m8b-m8m2-Support-HDMI.patch deleted file mode 100644 index 3408e53f8d5b..000000000000 --- a/patch/kernel/archive/meson-6.8/generic-0001-m8-m8b-m8m2-Support-HDMI.patch +++ /dev/null @@ -1,4399 +0,0 @@ -From 4367c45014e0ada25b438017df26140eeb795260 Mon Sep 17 00:00:00 2001 -From: Martin Blumenstingl -Date: Sat, 18 Nov 2023 01:22:02 +0800 -Subject: [PATCH 1/3] meson8/meson8b/meson8m2: Support HDMI - -The following codes are come from https://github.com/xdarklight/linux/commits/meson-mx-integration-5.18-20220516. - -Special thank to Martin Blumenstingl. - ---- - .../bindings/display/amlogic,meson-vpu.yaml | 16 + - .../phy/amlogic,meson-cvbs-dac-phy.yaml | 81 + - arch/arm/boot/dts/amlogic/meson.dtsi | 13 + - arch/arm/boot/dts/amlogic/meson8.dtsi | 168 +- - arch/arm/boot/dts/amlogic/meson8b.dtsi | 171 +- - arch/arm/boot/dts/amlogic/meson8m2.dtsi | 4 + - drivers/gpu/drm/meson/Kconfig | 9 + - drivers/gpu/drm/meson/Makefile | 1 + - drivers/gpu/drm/meson/meson_drv.c | 313 +++- - drivers/gpu/drm/meson/meson_drv.h | 49 +- - drivers/gpu/drm/meson/meson_encoder_cvbs.c | 61 +- - drivers/gpu/drm/meson/meson_encoder_hdmi.c | 69 +- - drivers/gpu/drm/meson/meson_plane.c | 37 +- - drivers/gpu/drm/meson/meson_transwitch_hdmi.c | 1579 +++++++++++++++++ - drivers/gpu/drm/meson/meson_transwitch_hdmi.h | 536 ++++++ - drivers/gpu/drm/meson/meson_vclk.c | 146 ++ - drivers/gpu/drm/meson/meson_venc.c | 44 +- - drivers/gpu/drm/meson/meson_viu.c | 18 +- - drivers/phy/amlogic/Kconfig | 10 + - drivers/phy/amlogic/Makefile | 1 + - drivers/phy/amlogic/phy-meson-cvbs-dac.c | 375 ++++ - 21 files changed, 3576 insertions(+), 125 deletions(-) - create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml - create mode 100644 drivers/gpu/drm/meson/meson_transwitch_hdmi.c - create mode 100644 drivers/gpu/drm/meson/meson_transwitch_hdmi.h - create mode 100644 drivers/phy/amlogic/phy-meson-cvbs-dac.c - -diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml -index cb0a90f0..96c32747 100644 ---- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml -+++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml -@@ -66,8 +66,12 @@ properties: - - const: amlogic,meson-gx-vpu - - enum: - - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2) -+ - amlogic,meson8-vpu -+ - amlogic,meson8b-vpu -+ - amlogic,meson8m2-vpu - - reg: -+ minItems: 1 - maxItems: 2 - - reg-names: -@@ -82,6 +86,15 @@ properties: - description: should point to a canvas provider node - $ref: /schemas/types.yaml#/definitions/phandle - -+ phys: -+ maxItems: 1 -+ description: -+ PHY specifier for the CVBS DAC -+ -+ phy-names: -+ items: -+ - const: cvbs-dac -+ - power-domains: - maxItems: 1 - description: phandle to the associated power domain -@@ -130,6 +143,9 @@ examples: - #size-cells = <0>; - amlogic,canvas = <&canvas>; - -+ phys = <&cvbs_dac_phy>; -+ phy-names = "cvbs-dac"; -+ - /* CVBS VDAC output port */ - port@0 { - reg = <0>; -diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml -new file mode 100644 -index 00000000..d73cb12c ---- /dev/null -+++ b/Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml -@@ -0,0 +1,81 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: "http://devicetree.org/schemas/phy/amlogic,meson-cvbs-dac-phy.yaml#" -+$schema: "http://devicetree.org/meta-schemas/core.yaml#" -+ -+title: Amlogic Meson Composite Video Baseband Signal DAC -+ -+maintainers: -+ - Martin Blumenstingl -+ -+description: |+ -+ The CVBS DAC node should be the child of a syscon node with the -+ required property: -+ -+ compatible = "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" -+ -+ Refer to the bindings described in -+ Documentation/devicetree/bindings/mfd/syscon.yaml -+ -+properties: -+ $nodename: -+ pattern: "^video-dac@[0-9a-f]+$" -+ -+ compatible: -+ oneOf: -+ - items: -+ - enum: -+ - amlogic,meson8-cvbs-dac -+ - amlogic,meson-gxbb-cvbs-dac -+ - amlogic,meson-gxl-cvbs-dac -+ - amlogic,meson-g12a-cvbs-dac -+ - const: amlogic,meson-cvbs-dac -+ - const: amlogic,meson-cvbs-dac -+ -+ reg: -+ maxItems: 1 -+ -+ clocks: -+ minItems: 1 -+ -+ nvmem-cells: -+ minItems: 1 -+ -+ nvmem-cell-names: -+ items: -+ - const: cvbs_trimming -+ -+ "#phy-cells": -+ const: 0 -+ -+required: -+ - compatible -+ - reg -+ - clocks -+ - "#phy-cells" -+ -+additionalProperties: false -+ -+examples: -+ - | -+ video-dac@2f4 { -+ compatible = "amlogic,meson8-cvbs-dac", "amlogic,meson-cvbs-dac"; -+ reg = <0x2f4 0x8>; -+ -+ #phy-cells = <0>; -+ -+ clocks = <&vdac_clock>; -+ -+ nvmem-cells = <&cvbs_trimming>; -+ nvmem-cell-names = "cvbs_trimming"; -+ }; -+ - | -+ video-dac@2ec { -+ compatible = "amlogic,meson-g12a-cvbs-dac", "amlogic,meson-cvbs-dac"; -+ reg = <0x2ec 0x8>; -+ -+ #phy-cells = <0>; -+ -+ clocks = <&vdac_clock>; -+ }; -diff --git a/arch/arm/boot/dts/amlogic/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi -index 8e3860d5..9a56cdf7 100644 ---- a/arch/arm/boot/dts/amlogic/meson.dtsi -+++ b/arch/arm/boot/dts/amlogic/meson.dtsi -@@ -35,6 +35,19 @@ hhi: system-controller@4000 { - "simple-mfd", - "syscon"; - reg = <0x4000 0x400>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x4000 0x400>; -+ -+ -+ cvbs_dac: video-dac@2f4 { -+ compatible = "amlogic,meson-cvbs-dac"; -+ reg = <0x2f4 0x8>; -+ -+ #phy-cells = <0>; -+ -+ status = "disabled"; -+ }; - }; - - aiu: audio-controller@5400 { -diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi -index 59932fbf..6c27d520 100644 ---- a/arch/arm/boot/dts/amlogic/meson8.dtsi -+++ b/arch/arm/boot/dts/amlogic/meson8.dtsi -@@ -314,6 +314,113 @@ mali: gpu@c0000 { - operating-points-v2 = <&gpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; -+ -+ hdmi_tx: hdmi-tx@42000 { -+ compatible = "amlogic,meson8-hdmi-tx"; -+ reg = <0x42000 0xc>; -+ interrupts = ; -+ phys = <&hdmi_tx_phy>; -+ phy-names = "hdmi"; -+ clocks = <&clkc CLKID_HDMI_PCLK>, -+ <&clkc CLKID_HDMI_SYS>; -+ clock-names = "pclk", "sys"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ #sound-dai-cells = <1>; -+ sound-name-prefix = "HDMITX"; -+ -+ status = "disabled"; -+ -+ /* VPU VENC Input */ -+ hdmi_tx_venc_port: port@0 { -+ reg = <0>; -+ -+ hdmi_tx_in: endpoint { -+ remote-endpoint = <&hdmi_tx_out>; -+ }; -+ }; -+ -+ /* TMDS Output */ -+ hdmi_tx_tmds_port: port@1 { -+ reg = <1>; -+ }; -+ }; -+ -+ vpu: vpu@100000 { -+ compatible = "amlogic,meson8-vpu"; -+ -+ reg = <0x100000 0x10000>; -+ reg-names = "vpu"; -+ -+ interrupts = ; -+ -+ amlogic,canvas = <&canvas>; -+ -+ /* -+ * The VCLK{,2}_IN path always needs to derived from -+ * the CLKID_VID_PLL_FINAL_DIV so other clocks like -+ * MPLL1 are not used (MPLL1 is reserved for audio -+ * purposes). -+ */ -+ assigned-clocks = <&clkc CLKID_VCLK_IN_SEL>, -+ <&clkc CLKID_VCLK2_IN_SEL>; -+ assigned-clock-parents = <&clkc CLKID_VID_PLL_FINAL_DIV>, -+ <&clkc CLKID_VID_PLL_FINAL_DIV>; -+ -+ clocks = <&clkc CLKID_VPU_INTR>, -+ <&clkc CLKID_HDMI_INTR_SYNC>, -+ <&clkc CLKID_GCLK_VENCI_INT>, -+ <&clkc CLKID_HDMI_PLL_HDMI_OUT>, -+ <&clkc CLKID_HDMI_TX_PIXEL>, -+ <&clkc CLKID_CTS_ENCP>, -+ <&clkc CLKID_CTS_ENCI>, -+ <&clkc CLKID_CTS_ENCT>, -+ <&clkc CLKID_CTS_ENCL>, -+ <&clkc CLKID_CTS_VDAC0>; -+ clock-names = "vpu_intr", -+ "hdmi_intr_sync", -+ "venci_int", -+ "tmds", -+ "hdmi_tx_pixel", -+ "cts_encp", -+ "cts_enci", -+ "cts_enct", -+ "cts_encl", -+ "cts_vdac0"; -+ -+ resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>; -+ reset-names = "vid_pll_pre", -+ "vid_pll_post", -+ "vid_pll_soft_pre", -+ "vid_pll_soft_post"; -+ -+ phys = <&cvbs_dac>; -+ phy-names = "cvbs-dac"; -+ -+ power-domains = <&pwrc PWRC_MESON8_VPU_ID>; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* CVBS VDAC output port */ -+ cvbs_vdac_port: port@0 { -+ reg = <0>; -+ }; -+ -+ /* HDMI-TX output port */ -+ hdmi_tx_port: port@1 { -+ reg = <1>; -+ -+ hdmi_tx_out: endpoint { -+ remote-endpoint = <&hdmi_tx_in>; -+ }; -+ }; -+ }; - }; - }; /* end of / */ - -@@ -363,6 +470,14 @@ gpio_ao: ao-bank@14 { - gpio-ranges = <&pinctrl_aobus 0 0 16>; - }; - -+ hdmi_cec_ao_pins: hdmi-cec-ao { -+ mux { -+ groups = "hdmi_cec_ao"; -+ function = "hdmi_cec_ao"; -+ bias-pull-up; -+ }; -+ }; -+ - i2s_am_clk_pins: i2s-am-clk-out { - mux { - groups = "i2s_am_clk_out_ao"; -@@ -427,6 +542,15 @@ mux { - }; - }; - }; -+ -+ cec_AO: cec@100 { -+ compatible = "amlogic,meson-gx-ao-cec"; // FIXME -+ reg = <0x100 0x14>; -+ interrupts = ; -+ // TODO: 32768HZ clock -+ hdmi-phandle = <&hdmi_tx>; -+ status = "disabled"; -+ }; - }; - - &ao_arc_rproc { -@@ -479,6 +603,22 @@ gpio: banks@80b0 { - gpio-ranges = <&pinctrl_cbus 0 0 120>; - }; - -+ hdmi_hpd_pins: hdmi-hpd { -+ mux { -+ groups = "hdmi_hpd"; -+ function = "hdmi"; -+ bias-disable; -+ }; -+ }; -+ -+ hdmi_i2c_pins: hdmi-i2c { -+ mux { -+ groups = "hdmi_sda", "hdmi_scl"; -+ function = "hdmi"; -+ bias-disable; -+ }; -+ }; -+ - sd_a_pins: sd-a { - mux { - groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", -@@ -601,6 +741,17 @@ smp-sram@1ff80 { - }; - }; - -+&cvbs_dac { -+ compatible = "amlogic,meson8-cvbs-dac", "amlogic,meson-cvbs-dac"; -+ -+ clocks = <&clkc CLKID_CTS_VDAC0>; -+ -+ nvmem-cells = <&cvbs_trimming>; -+ nvmem-cell-names = "cvbs_trimming"; -+ -+ status = "okay"; -+}; -+ - &efuse { - compatible = "amlogic,meson8-efuse"; - clocks = <&clkc CLKID_EFUSE>; -@@ -610,6 +761,10 @@ temperature_calib: calib@1f4 { - /* only the upper two bytes are relevant */ - reg = <0x1f4 0x4>; - }; -+ -+ cvbs_trimming: calib@1f8 { -+ reg = <0x1f8 0x2>; -+ }; - }; - - ðmac { -@@ -625,16 +780,18 @@ &gpio_intc { - }; - - &hhi { -- clkc: clock-controller { -+ clkc: clock-controller@0 { - compatible = "amlogic,meson8-clkc"; -+ reg = <0x0 0x39c>; - clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; - clock-names = "xtal", "ddr_pll"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -- pwrc: power-controller { -+ pwrc: power-controller@100 { - compatible = "amlogic,meson8-pwrc"; -+ reg = <0x100 0x10>; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&pmu>; - clocks = <&clkc CLKID_VPU>; -@@ -642,6 +799,13 @@ pwrc: power-controller { - assigned-clocks = <&clkc CLKID_VPU>; - assigned-clock-rates = <364285714>; - }; -+ -+ hdmi_tx_phy: hdmi-phy@3a0 { -+ compatible = "amlogic,meson8-hdmi-tx-phy"; -+ clocks = <&clkc CLKID_HDMI_PLL_HDMI_OUT>; -+ reg = <0x3a0 0xc>; -+ #phy-cells = <0>; -+ }; - }; - - &hwrng { -diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi -index 5198f517..da9216ee 100644 ---- a/arch/arm/boot/dts/amlogic/meson8b.dtsi -+++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi -@@ -276,6 +276,116 @@ mali: gpu@c0000 { - operating-points-v2 = <&gpu_opp_table>; - #cooling-cells = <2>; /* min followed by max */ - }; -+ -+ hdmi_tx: hdmi-tx@42000 { -+ compatible = "amlogic,meson8b-hdmi-tx"; -+ reg = <0x42000 0xc>; -+ interrupts = ; -+ phys = <&hdmi_tx_phy>; -+ phy-names = "hdmi"; -+ clocks = <&clkc CLKID_HDMI_PCLK>, -+ <&clkc CLKID_HDMI_SYS>; -+ clock-names = "pclk", "sys"; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ #sound-dai-cells = <1>; -+ sound-name-prefix = "HDMITX"; -+ -+ status = "disabled"; -+ -+ /* VPU VENC Input */ -+ hdmi_tx_venc_port: port@0 { -+ reg = <0>; -+ -+ hdmi_tx_in: endpoint { -+ remote-endpoint = <&hdmi_tx_out>; -+ }; -+ }; -+ -+ /* TMDS Output */ -+ hdmi_tx_tmds_port: port@1 { -+ reg = <1>; -+ }; -+ }; -+ -+ vpu: vpu@100000 { -+ compatible = "amlogic,meson8b-vpu"; -+ -+ reg = <0x100000 0x10000>; -+ reg-names = "vpu"; -+ -+ interrupts = ; -+ -+ amlogic,canvas = <&canvas>; -+ -+ /* -+ * The VCLK{,2}_IN path always needs to derived from -+ * the CLKID_VID_PLL_FINAL_DIV so other clocks like -+ * MPLL1 are not used (MPLL1 is reserved for audio -+ * purposes). -+ */ -+ assigned-clocks = <&clkc CLKID_VCLK_IN_SEL>, -+ <&clkc CLKID_VCLK2_IN_SEL>; -+ assigned-clock-parents = <&clkc CLKID_VID_PLL_FINAL_DIV>, -+ <&clkc CLKID_VID_PLL_FINAL_DIV>; -+ -+ clocks = <&clkc CLKID_VPU_INTR>, -+ <&clkc CLKID_HDMI_INTR_SYNC>, -+ <&clkc CLKID_GCLK_VENCI_INT>, -+ <&clkc CLKID_HDMI_PLL_HDMI_OUT>, -+ <&clkc CLKID_HDMI_TX_PIXEL>, -+ <&clkc CLKID_CTS_ENCP>, -+ <&clkc CLKID_CTS_ENCI>, -+ <&clkc CLKID_CTS_ENCT>, -+ <&clkc CLKID_CTS_ENCL>, -+ <&clkc CLKID_CTS_VDAC0>; -+ clock-names = "vpu_intr", -+ "hdmi_intr_sync", -+ "venci_int", -+ "tmds", -+ "hdmi_tx_pixel", -+ "cts_encp", -+ "cts_enci", -+ "cts_enct", -+ "cts_encl", -+ "cts_vdac0"; -+ -+ resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>, -+ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>; -+ reset-names = "vid_pll_pre", -+ "vid_pll_post", -+ "vid_pll_soft_pre", -+ "vid_pll_soft_post"; -+ -+ phys = <&cvbs_dac>; -+ phy-names = "cvbs-dac"; -+ -+ power-domains = <&pwrc PWRC_MESON8_VPU_ID>; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ #sound-dai-cells = <0>; -+ sound-name-prefix = "HDMITX"; -+ -+ /* CVBS VDAC output port */ -+ cvbs_vdac_port: port@0 { -+ reg = <0>; -+ }; -+ -+ /* HDMI-TX output port */ -+ hdmi_tx_port: port@1 { -+ reg = <1>; -+ -+ hdmi_tx_out: endpoint { -+ remote-endpoint = <&hdmi_tx_in>; -+ }; -+ }; -+ }; - }; - }; /* end of / */ - -@@ -325,6 +435,14 @@ gpio_ao: ao-bank@14 { - gpio-ranges = <&pinctrl_aobus 0 0 16>; - }; - -+ hdmi_cec_ao_pins: hdmi-cec-ao { -+ mux { -+ groups = "hdmi_cec_1"; -+ function = "hdmi_cec"; -+ bias-pull-up; -+ }; -+ }; -+ - i2s_am_clk_pins: i2s-am-clk-out { - mux { - groups = "i2s_am_clk_out"; -@@ -381,6 +499,15 @@ mux { - }; - }; - }; -+ -+ cec_AO: cec@100 { -+ compatible = "amlogic,meson-gx-ao-cec"; // FIXME -+ reg = <0x100 0x14>; -+ interrupts = ; -+ // TODO: 32768HZ clock -+ hdmi-phandle = <&hdmi_tx>; -+ status = "disabled"; -+ }; - }; - - &ao_arc_rproc { -@@ -471,6 +598,22 @@ mux { - }; - }; - -+ hdmi_hpd_pins: hdmi-hpd { -+ mux { -+ groups = "hdmi_hpd"; -+ function = "hdmi"; -+ bias-disable; -+ }; -+ }; -+ -+ hdmi_i2c_pins: hdmi-i2c { -+ mux { -+ groups = "hdmi_sda", "hdmi_scl"; -+ function = "hdmi"; -+ bias-disable; -+ }; -+ }; -+ - i2c_a_pins: i2c-a { - mux { - groups = "i2c_sda_a", "i2c_sck_a"; -@@ -547,6 +690,16 @@ smp-sram@1ff80 { - }; - }; - -+&cvbs_dac { -+ compatible = "amlogic,meson8-cvbs-dac", "amlogic,meson-cvbs-dac"; -+ -+ clocks = <&clkc CLKID_CTS_VDAC0>; -+ -+ nvmem-cells = <&cvbs_trimming>; -+ nvmem-cell-names = "cvbs_trimming"; -+ -+ status = "okay"; -+}; - - &efuse { - compatible = "amlogic,meson8b-efuse"; -@@ -557,6 +710,10 @@ temperature_calib: calib@1f4 { - /* only the upper two bytes are relevant */ - reg = <0x1f4 0x4>; - }; -+ -+ cvbs_trimming: calib@1f8 { -+ reg = <0x1f8 0x2>; -+ }; - }; - - ðmac { -@@ -586,16 +743,18 @@ &gpio_intc { - }; - - &hhi { -- clkc: clock-controller { -+ clkc: clock-controller@0 { - compatible = "amlogic,meson8b-clkc"; -+ reg = <0x0 0x39c>; - clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; - clock-names = "xtal", "ddr_pll"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - -- pwrc: power-controller { -+ pwrc: power-controller@100 { - compatible = "amlogic,meson8b-pwrc"; -+ reg = <0x100 0x10>; - #power-domain-cells = <1>; - amlogic,ao-sysctrl = <&pmu>; - resets = <&reset RESET_DBLK>, -@@ -617,6 +776,14 @@ pwrc: power-controller { - assigned-clocks = <&clkc CLKID_VPU>; - assigned-clock-rates = <182142857>; - }; -+ -+ hdmi_tx_phy: hdmi-phy@3a0 { -+ compatible = "amlogic,meson8b-hdmi-tx-phy", -+ "amlogic,meson8-hdmi-tx-phy"; -+ clocks = <&clkc CLKID_HDMI_PLL_HDMI_OUT>; -+ reg = <0x3a0 0xc>; -+ #phy-cells = <0>; -+ }; - }; - - &hwrng { -diff --git a/arch/arm/boot/dts/amlogic/meson8m2.dtsi b/arch/arm/boot/dts/amlogic/meson8m2.dtsi -index 6725dd9f..fcb2ad97 100644 ---- a/arch/arm/boot/dts/amlogic/meson8m2.dtsi -+++ b/arch/arm/boot/dts/amlogic/meson8m2.dtsi -@@ -96,6 +96,10 @@ &usb1_phy { - compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; - }; - -+&vpu { -+ compatible = "amlogic,meson8m2-vpu"; -+}; -+ - &wdt { - compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; - }; -diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig -index 615fdd0c..eff3e34b 100644 ---- a/drivers/gpu/drm/meson/Kconfig -+++ b/drivers/gpu/drm/meson/Kconfig -@@ -10,6 +10,7 @@ config DRM_MESON - select REGMAP_MMIO - select MESON_CANVAS - select CEC_CORE if CEC_NOTIFIER -+ imply PHY_MESON_CVBS_DAC - - config DRM_MESON_DW_HDMI - tristate "HDMI Synopsys Controller support for Amlogic Meson Display" -@@ -24,3 +25,11 @@ config DRM_MESON_DW_MIPI_DSI - default y if DRM_MESON - select DRM_DW_MIPI_DSI - select GENERIC_PHY_MIPI_DPHY -+ -+config DRM_MESON_TRANSWITCH_HDMI -+ tristate "Amlogic Meson8/8b/8m2 TranSwitch HDMI 1.4 Controller support" -+ depends on ARM || COMPILE_TEST -+ depends on DRM_MESON -+ default y if DRM_MESON -+ select REGMAP_MMIO -+ select SND_SOC_HDMI_CODEC if SND_SOC -diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile -index 43071bdb..c44cb6c5 100644 ---- a/drivers/gpu/drm/meson/Makefile -+++ b/drivers/gpu/drm/meson/Makefile -@@ -7,3 +7,4 @@ meson-drm-y += meson_encoder_hdmi.o meson_encoder_dsi.o - obj-$(CONFIG_DRM_MESON) += meson-drm.o - obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o - obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o -+obj-$(CONFIG_DRM_MESON_TRANSWITCH_HDMI) += meson_transwitch_hdmi.o -diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c -index cb674966..e8134e4c 100644 ---- a/drivers/gpu/drm/meson/meson_drv.c -+++ b/drivers/gpu/drm/meson/meson_drv.c -@@ -12,6 +12,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -133,30 +134,147 @@ static struct regmap_config meson_regmap_config = { - .max_register = 0x1000, - }; - -+static int meson_cvbs_dac_phy_init(struct meson_drm *priv) -+{ -+ struct platform_device *pdev; -+ const char *platform_id_name; -+ -+ priv->cvbs_dac = devm_phy_optional_get(priv->dev, "cvbs-dac"); -+ if (IS_ERR(priv->cvbs_dac)) -+ return dev_err_probe(priv->dev, PTR_ERR(priv->cvbs_dac), -+ "Failed to get the 'cvbs-dac' PHY\n"); -+ else if (priv->cvbs_dac) -+ return 0; -+ -+ switch (priv->compat) { -+ case VPU_COMPATIBLE_GXBB: -+ platform_id_name = "meson-gxbb-cvbs-dac"; -+ break; -+ case VPU_COMPATIBLE_GXL: -+ case VPU_COMPATIBLE_GXM: -+ platform_id_name = "meson-gxl-cvbs-dac"; -+ break; -+ case VPU_COMPATIBLE_G12A: -+ platform_id_name = "meson-g12a-cvbs-dac"; -+ break; -+ default: -+ return dev_err_probe(priv->dev, -EINVAL, -+ "No CVBS DAC platform ID found\n"); -+ } -+ -+ pdev = platform_device_register_data(priv->dev, platform_id_name, -+ PLATFORM_DEVID_AUTO, NULL, 0); -+ if (IS_ERR(pdev)) -+ return dev_err_probe(priv->dev, PTR_ERR(pdev), -+ "Failed to register fallback CVBS DAC PHY platform device\n"); -+ -+ priv->cvbs_dac = platform_get_drvdata(pdev); -+ if (IS_ERR(priv->cvbs_dac)) { -+ platform_device_unregister(pdev); -+ return dev_err_probe(priv->dev, PTR_ERR(priv->cvbs_dac), -+ "Failed to get the 'cvbs-dac' PHY from it's platform device\n"); -+ } -+ -+ dev_warn(priv->dev, "Using fallback for old .dtbs without CVBS DAC\n"); -+ -+ priv->cvbs_dac_pdev = pdev; -+ -+ return 0; -+} -+ -+static void meson_cvbs_dac_phy_exit(struct meson_drm *priv) -+{ -+ platform_device_unregister(priv->cvbs_dac_pdev); -+} -+ - static void meson_vpu_init(struct meson_drm *priv) - { -- u32 value; -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ writel(0x0, priv->io_base + _REG(VPU_MEM_PD_REG0)); -+ writel(0x0, priv->io_base + _REG(VPU_MEM_PD_REG1)); -+ } else { -+ u32 value; -+ -+ /* -+ * Slave dc0 and dc5 connected to master port 1. -+ * By default other slaves are connected to master port 0. -+ */ -+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) | -+ VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1); -+ writel_relaxed(value, -+ priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); -+ -+ /* Slave dc0 connected to master port 1 */ -+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1); -+ writel_relaxed(value, -+ priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); -+ -+ /* Slave dc4 and dc7 connected to master port 1 */ -+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) | -+ VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1); -+ writel_relaxed(value, -+ priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); -+ -+ /* Slave dc1 connected to master port 1 */ -+ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1); -+ writel_relaxed(value, -+ priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); -+ } -+} -+ -+static int meson_video_clock_init(struct meson_drm *priv) -+{ -+ int ret; -+ -+ ret = clk_bulk_prepare(VPU_VID_CLK_NUM, priv->vid_clks); -+ if (ret) -+ return dev_err_probe(priv->dev, ret, -+ "Failed to prepare the video clocks\n"); -+ -+ ret = clk_bulk_prepare(priv->num_intr_clks, priv->intr_clks); -+ if (ret) -+ return dev_err_probe(priv->dev, ret, -+ "Failed to prepare the interrupt clocks\n"); -+ -+ return 0; -+} -+ -+static void meson_video_clock_exit(struct meson_drm *priv) -+{ -+ if (priv->clk_dac_enabled) -+ clk_disable(priv->clk_dac); -+ -+ if (priv->clk_venc_enabled) -+ clk_disable(priv->clk_venc); -+ -+ clk_bulk_unprepare(priv->num_intr_clks, priv->intr_clks); -+ clk_bulk_unprepare(VPU_VID_CLK_NUM, priv->vid_clks); -+} -+ -+static void meson_fbdev_setup(struct meson_drm *priv) -+{ -+ unsigned int preferred_bpp; - - /* -- * Slave dc0 and dc5 connected to master port 1. -- * By default other slaves are connected to master port 0. -+ * All SoC generations before GXBB don't have a way to configure the -+ * alpha value for DRM_FORMAT_XRGB8888 and DRM_FORMAT_XBGR8888. These -+ * formats have an X component instead of an alpha component. On -+ * Meson8/8b/8m2 there is no way to configure the alpha value to use -+ * instead of the X component. This results in the fact that the -+ * formats with X component are only supported on GXBB and newer. Use -+ * 24 bits per pixel and therefore DRM_FORMAT_RGB888 to get a -+ * working framebuffer console. - */ -- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) | -- VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1); -- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); -- -- /* Slave dc0 connected to master port 1 */ -- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1); -- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); -- -- /* Slave dc4 and dc7 connected to master port 1 */ -- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) | -- VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1); -- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); -- -- /* Slave dc1 connected to master port 1 */ -- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1); -- writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) -+ preferred_bpp = 24; -+ else -+ preferred_bpp = 32; -+ -+ drm_fbdev_dma_setup(priv->drm, preferred_bpp); - } - - struct meson_drm_soc_attr { -@@ -165,13 +283,29 @@ struct meson_drm_soc_attr { - }; - - static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = { -- /* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */ -+ /* The maximum frequency of HDMI PHY on Meson8 and Meson8m2 is ~3GHz */ -+ { -+ .limits = { -+ .max_hdmi_phy_freq = 2976000, -+ }, -+ .attrs = (const struct soc_device_attribute []) { -+ { .soc_id = "Meson8 (S802)", }, -+ { .soc_id = "Meson8m2 (S812)", }, -+ { /* sentinel */ }, -+ } -+ }, -+ /* -+ * GXL S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz. -+ * Meson8b (S805) only supports "1200p@60 max resolution" according to -+ * the public datasheet. -+ */ - { - .limits = { - .max_hdmi_phy_freq = 1650000, - }, - .attrs = (const struct soc_device_attribute []) { - { .soc_id = "GXL (S805*)", }, -+ { .soc_id = "Meson8b (S805)", }, - { /* sentinel */ } - } - }, -@@ -212,67 +346,123 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - priv->compat = match->compat; - priv->afbcd.ops = match->afbcd_ops; - -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ priv->vid_pll_resets[VPU_RESET_VID_PLL_PRE].id = "vid_pll_pre"; -+ priv->vid_pll_resets[VPU_RESET_VID_PLL_POST].id = "vid_pll_post"; -+ priv->vid_pll_resets[VPU_RESET_VID_PLL_SOFT_PRE].id = "vid_pll_soft_pre"; -+ priv->vid_pll_resets[VPU_RESET_VID_PLL_SOFT_POST].id = "vid_pll_soft_post"; -+ -+ ret = devm_reset_control_bulk_get_exclusive(dev, -+ VPU_RESET_VID_PLL_NUM, -+ priv->vid_pll_resets); -+ if (ret) -+ goto free_drm; -+ -+ priv->intr_clks[0].id = "vpu_intr"; -+ priv->intr_clks[1].id = "hdmi_intr_sync"; -+ priv->intr_clks[2].id = "venci_int"; -+ priv->num_intr_clks = 3; -+ -+ ret = devm_clk_bulk_get(dev, priv->num_intr_clks, -+ priv->intr_clks); -+ if (ret) -+ goto free_drm; -+ -+ priv->vid_clks[VPU_VID_CLK_TMDS].id = "tmds"; -+ priv->vid_clks[VPU_VID_CLK_HDMI_TX_PIXEL].id = "hdmi_tx_pixel"; -+ priv->vid_clks[VPU_VID_CLK_CTS_ENCP].id = "cts_encp"; -+ priv->vid_clks[VPU_VID_CLK_CTS_ENCI].id = "cts_enci"; -+ priv->vid_clks[VPU_VID_CLK_CTS_ENCT].id = "cts_enct"; -+ priv->vid_clks[VPU_VID_CLK_CTS_ENCL].id = "cts_encl"; -+ priv->vid_clks[VPU_VID_CLK_CTS_VDAC0].id = "cts_vdac0"; -+ -+ ret = devm_clk_bulk_get(dev, VPU_VID_CLK_NUM, priv->vid_clks); -+ if (ret) -+ goto free_drm; -+ } else { -+ priv->intr_clks[0].id = "vpu_intr"; -+ priv->num_intr_clks = 1; -+ -+ ret = devm_clk_bulk_get_optional(dev, priv->num_intr_clks, -+ priv->intr_clks); -+ if (ret) -+ goto free_drm; -+ } -+ -+ ret = meson_video_clock_init(priv); -+ if (ret) -+ goto free_drm; -+ - regs = devm_platform_ioremap_resource_byname(pdev, "vpu"); - if (IS_ERR(regs)) { - ret = PTR_ERR(regs); -- goto free_drm; -+ goto video_clock_exit; - } - - priv->io_base = regs; - -+ /* -+ * The HHI resource is optional because it contains the clocks and CVBS -+ * encoder registers. These are managed by separate drivers though. -+ */ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi"); -- if (!res) { -- ret = -EINVAL; -- goto free_drm; -- } -- /* Simply ioremap since it may be a shared register zone */ -- regs = devm_ioremap(dev, res->start, resource_size(res)); -- if (!regs) { -- ret = -EADDRNOTAVAIL; -- goto free_drm; -- } -+ if (res) { -+ /* Simply ioremap since it may be a shared register zone */ -+ regs = devm_ioremap(dev, res->start, resource_size(res)); -+ if (!regs) { -+ ret = -EADDRNOTAVAIL; -+ goto video_clock_exit; -+ } - -- priv->hhi = devm_regmap_init_mmio(dev, regs, -- &meson_regmap_config); -- if (IS_ERR(priv->hhi)) { -- dev_err(&pdev->dev, "Couldn't create the HHI regmap\n"); -- ret = PTR_ERR(priv->hhi); -- goto free_drm; -+ priv->hhi = devm_regmap_init_mmio(dev, regs, -+ &meson_regmap_config); -+ if (IS_ERR(priv->hhi)) { -+ dev_err(&pdev->dev, -+ "Couldn't create the HHI regmap\n"); -+ ret = PTR_ERR(priv->hhi); -+ goto video_clock_exit; -+ } - } - - priv->canvas = meson_canvas_get(dev); - if (IS_ERR(priv->canvas)) { - ret = PTR_ERR(priv->canvas); -- goto free_drm; -+ goto video_clock_exit; - } - - ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1); - if (ret) -- goto free_drm; -+ goto video_clock_exit; - ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0); - if (ret) { - meson_canvas_free(priv->canvas, priv->canvas_id_osd1); -- goto free_drm; -+ goto video_clock_exit; - } - ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1); - if (ret) { - meson_canvas_free(priv->canvas, priv->canvas_id_osd1); - meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0); -- goto free_drm; -+ goto video_clock_exit; - } - ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2); - if (ret) { - meson_canvas_free(priv->canvas, priv->canvas_id_osd1); - meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0); - meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1); -- goto free_drm; -+ goto video_clock_exit; - } - -+ ret = meson_cvbs_dac_phy_init(priv); -+ if (ret) -+ goto free_drm; -+ - priv->vsync_irq = platform_get_irq(pdev, 0); - - ret = drm_vblank_init(drm, 1); - if (ret) -- goto free_drm; -+ goto exit_cvbs_dac_phy; - - /* Assign limits per soc revision/package */ - for (i = 0 ; i < ARRAY_SIZE(meson_drm_soc_attrs) ; ++i) { -@@ -288,11 +478,11 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - */ - ret = drm_aperture_remove_framebuffers(&meson_driver); - if (ret) -- goto free_drm; -+ goto exit_cvbs_dac_phy; - - ret = drmm_mode_config_init(drm); - if (ret) -- goto free_drm; -+ goto exit_cvbs_dac_phy; - drm->mode_config.max_width = 3840; - drm->mode_config.max_height = 2160; - drm->mode_config.funcs = &meson_mode_config_funcs; -@@ -307,7 +497,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - if (priv->afbcd.ops) { - ret = priv->afbcd.ops->init(priv); - if (ret) -- goto free_drm; -+ goto exit_cvbs_dac_phy; - } - - /* Encoder Initialization */ -@@ -362,7 +552,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - if (ret) - goto uninstall_irq; - -- drm_fbdev_dma_setup(drm, 32); -+ meson_fbdev_setup(priv); - - return 0; - -@@ -371,6 +561,10 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) - exit_afbcd: - if (priv->afbcd.ops) - priv->afbcd.ops->exit(priv); -+exit_cvbs_dac_phy: -+ meson_cvbs_dac_phy_exit(priv); -+video_clock_exit: -+ meson_video_clock_exit(priv); - free_drm: - drm_dev_put(drm); - -@@ -415,6 +609,10 @@ static void meson_drv_unbind(struct device *dev) - - if (priv->afbcd.ops) - priv->afbcd.ops->exit(priv); -+ -+ meson_cvbs_dac_phy_exit(priv); -+ -+ meson_video_clock_exit(priv); - } - - static const struct component_master_ops meson_drv_master_ops = { -@@ -429,6 +627,8 @@ static int __maybe_unused meson_drv_pm_suspend(struct device *dev) - if (!priv) - return 0; - -+ // TODO: video clock suspend -+ - return drm_mode_config_helper_suspend(priv->drm); - } - -@@ -439,6 +639,7 @@ static int __maybe_unused meson_drv_pm_resume(struct device *dev) - if (!priv) - return 0; - -+ meson_video_clock_init(priv); - meson_vpu_init(priv); - meson_venc_init(priv); - meson_vpp_init(priv); -@@ -521,6 +722,18 @@ static void meson_drv_remove(struct platform_device *pdev) - component_master_del(&pdev->dev, &meson_drv_master_ops); - } - -+static struct meson_drm_match_data meson_drm_m8_data = { -+ .compat = VPU_COMPATIBLE_M8, -+}; -+ -+static struct meson_drm_match_data meson_drm_m8b_data = { -+ .compat = VPU_COMPATIBLE_M8B, -+}; -+ -+static struct meson_drm_match_data meson_drm_m8m2_data = { -+ .compat = VPU_COMPATIBLE_M8M2, -+}; -+ - static struct meson_drm_match_data meson_drm_gxbb_data = { - .compat = VPU_COMPATIBLE_GXBB, - }; -@@ -540,6 +753,12 @@ static struct meson_drm_match_data meson_drm_g12a_data = { - }; - - static const struct of_device_id dt_match[] = { -+ { .compatible = "amlogic,meson8-vpu", -+ .data = (void *)&meson_drm_m8_data }, -+ { .compatible = "amlogic,meson8b-vpu", -+ .data = (void *)&meson_drm_m8b_data }, -+ { .compatible = "amlogic,meson8m2-vpu", -+ .data = (void *)&meson_drm_m8m2_data }, - { .compatible = "amlogic,meson-gxbb-vpu", - .data = (void *)&meson_drm_gxbb_data }, - { .compatible = "amlogic,meson-gxl-vpu", -diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h -index 3f9345c1..59f80fcc 100644 ---- a/drivers/gpu/drm/meson/meson_drv.h -+++ b/drivers/gpu/drm/meson/meson_drv.h -@@ -7,21 +7,28 @@ - #ifndef __MESON_DRV_H - #define __MESON_DRV_H - -+#include - #include - #include - #include -+#include - - struct drm_crtc; - struct drm_device; - struct drm_plane; - struct meson_drm; - struct meson_afbcd_ops; -+struct phy; -+struct platform_device; - - enum vpu_compatible { -- VPU_COMPATIBLE_GXBB = 0, -- VPU_COMPATIBLE_GXL = 1, -- VPU_COMPATIBLE_GXM = 2, -- VPU_COMPATIBLE_G12A = 3, -+ VPU_COMPATIBLE_M8 = 0, -+ VPU_COMPATIBLE_M8B = 1, -+ VPU_COMPATIBLE_M8M2 = 2, -+ VPU_COMPATIBLE_GXBB = 3, -+ VPU_COMPATIBLE_GXL = 4, -+ VPU_COMPATIBLE_GXM = 5, -+ VPU_COMPATIBLE_G12A = 6, - }; - - enum { -@@ -40,6 +47,25 @@ struct meson_drm_soc_limits { - unsigned int max_hdmi_phy_freq; - }; - -+enum vpu_bulk_clk_id { -+ VPU_VID_CLK_TMDS = 0, -+ VPU_VID_CLK_HDMI_TX_PIXEL, -+ VPU_VID_CLK_CTS_ENCP, -+ VPU_VID_CLK_CTS_ENCI, -+ VPU_VID_CLK_CTS_ENCT, -+ VPU_VID_CLK_CTS_ENCL, -+ VPU_VID_CLK_CTS_VDAC0, -+ VPU_VID_CLK_NUM -+}; -+ -+enum vpu_bulk_vid_pll_reset_id { -+ VPU_RESET_VID_PLL_PRE = 0, -+ VPU_RESET_VID_PLL_POST, -+ VPU_RESET_VID_PLL_SOFT_PRE, -+ VPU_RESET_VID_PLL_SOFT_POST, -+ VPU_RESET_VID_PLL_NUM -+}; -+ - struct meson_drm { - struct device *dev; - enum vpu_compatible compat; -@@ -61,6 +87,21 @@ struct meson_drm { - - const struct meson_drm_soc_limits *limits; - -+ struct phy *cvbs_dac; -+ bool cvbs_dac_enabled; -+ struct platform_device *cvbs_dac_pdev; -+ -+ struct clk_bulk_data intr_clks[3]; -+ unsigned int num_intr_clks; -+ bool intr_clks_enabled; -+ struct clk_bulk_data vid_clks[VPU_VID_CLK_NUM]; -+ bool vid_clk_rate_exclusive[VPU_VID_CLK_NUM]; -+ struct clk *clk_venc; -+ bool clk_venc_enabled; -+ struct clk *clk_dac; -+ bool clk_dac_enabled; -+ struct reset_control_bulk_data vid_pll_resets[VPU_RESET_VID_PLL_NUM]; -+ - /* Components Data */ - struct { - bool osd1_enabled; -diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/meson/meson_encoder_cvbs.c -index 34074504..44c09f8b 100644 ---- a/drivers/gpu/drm/meson/meson_encoder_cvbs.c -+++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c -@@ -11,6 +11,7 @@ - - #include - #include -+#include - - #include - #include -@@ -24,12 +25,6 @@ - #include "meson_vclk.h" - #include "meson_encoder_cvbs.h" - --/* HHI VDAC Registers */ --#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ --#define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbd offset in data sheet */ --#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ --#define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */ -- - struct meson_encoder_cvbs { - struct drm_encoder encoder; - struct drm_bridge bridge; -@@ -87,11 +82,28 @@ static int meson_encoder_cvbs_attach(struct drm_bridge *bridge, - { - struct meson_encoder_cvbs *meson_encoder_cvbs = - bridge_to_meson_encoder_cvbs(bridge); -+ int ret; -+ -+ ret = phy_init(meson_encoder_cvbs->priv->cvbs_dac); -+ if (ret) -+ return ret; - - return drm_bridge_attach(bridge->encoder, meson_encoder_cvbs->next_bridge, - &meson_encoder_cvbs->bridge, flags); - } - -+static void meson_encoder_cvbs_detach(struct drm_bridge *bridge) -+{ -+ struct meson_encoder_cvbs *meson_encoder_cvbs = -+ bridge_to_meson_encoder_cvbs(bridge); -+ int ret; -+ -+ ret = phy_exit(meson_encoder_cvbs->priv->cvbs_dac); -+ if (ret) -+ dev_err(meson_encoder_cvbs->priv->dev, -+ "Failed to exit the CVBS DAC\n"); -+} -+ - static int meson_encoder_cvbs_get_modes(struct drm_bridge *bridge, - struct drm_connector *connector) - { -@@ -148,6 +160,7 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge, - struct drm_connector_state *conn_state; - struct drm_crtc_state *crtc_state; - struct drm_connector *connector; -+ int ret; - - connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); - if (WARN_ON(!connector)) -@@ -177,16 +190,13 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge, - writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0, - priv->io_base + _REG(VENC_VDAC_DACSEL0)); - -- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) { -- regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0); -- } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || -- meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) { -- regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0); -- } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { -- regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); -+ if (!priv->cvbs_dac_enabled) { -+ ret = phy_power_on(priv->cvbs_dac); -+ if (ret) -+ dev_err(priv->dev, -+ "Failed to power on the CVBS DAC\n"); -+ else -+ priv->cvbs_dac_enabled = true; - } - } - -@@ -196,19 +206,22 @@ static void meson_encoder_cvbs_atomic_disable(struct drm_bridge *bridge, - struct meson_encoder_cvbs *meson_encoder_cvbs = - bridge_to_meson_encoder_cvbs(bridge); - struct meson_drm *priv = meson_encoder_cvbs->priv; -+ int ret; - -- /* Disable CVBS VDAC */ -- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { -- regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); -- } else { -- regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); -- } -+ if (!priv->cvbs_dac_enabled) -+ return; -+ -+ ret = phy_power_off(priv->cvbs_dac); -+ if (ret) -+ dev_err(priv->dev, -+ "Failed to power off the CVBS DAC\n"); -+ else -+ priv->cvbs_dac_enabled = false; - } - - static const struct drm_bridge_funcs meson_encoder_cvbs_bridge_funcs = { - .attach = meson_encoder_cvbs_attach, -+ .detach = meson_encoder_cvbs_detach, - .mode_valid = meson_encoder_cvbs_mode_valid, - .get_modes = meson_encoder_cvbs_get_modes, - .atomic_enable = meson_encoder_cvbs_atomic_enable, -diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c -index c4686568..583f2924 100644 ---- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c -+++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c -@@ -190,13 +190,13 @@ static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge, - { - struct meson_encoder_hdmi *encoder_hdmi = bridge_to_meson_encoder_hdmi(bridge); - struct drm_atomic_state *state = bridge_state->base.state; -- unsigned int ycrcb_map = VPU_HDMI_OUTPUT_CBYCR; - struct meson_drm *priv = encoder_hdmi->priv; - struct drm_connector_state *conn_state; - const struct drm_display_mode *mode; - struct drm_crtc_state *crtc_state; - struct drm_connector *connector; - bool yuv420_mode = false; -+ unsigned int ycrcb_map; - int vic; - - connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); -@@ -217,7 +217,14 @@ static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge, - - dev_dbg(priv->dev, "\"%s\" vic %d\n", mode->name, vic); - -- if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) { -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_RGB888_1X24) -+ ycrcb_map = VPU_HDMI_OUTPUT_YCBCR; -+ else -+ ycrcb_map = VPU_HDMI_OUTPUT_CRYCB; -+ } else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) { - ycrcb_map = VPU_HDMI_OUTPUT_CRYCB; - yuv420_mode = true; - } else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16) -@@ -229,17 +236,22 @@ static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge, - /* VCLK Set clock */ - meson_encoder_hdmi_set_vclk(encoder_hdmi, mode); - -- if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) -- /* Setup YUV420 to HDMI-TX, no 10bit diphering */ -- writel_relaxed(2 | (2 << 2), -- priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); -- else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16) -- /* Setup YUV422 to HDMI-TX, no 10bit diphering */ -- writel_relaxed(1 | (2 << 2), -- priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); -- else -- /* Setup YUV444 to HDMI-TX, no 10bit diphering */ -- writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); -+ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) -+ /* Setup YUV420 to HDMI-TX, no 10bit diphering */ -+ writel_relaxed(2 | (2 << 2), -+ priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); -+ else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16) -+ /* Setup YUV422 to HDMI-TX, no 10bit diphering */ -+ writel_relaxed(1 | (2 << 2), -+ priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); -+ else -+ /* Setup YUV444 to HDMI-TX, no 10bit diphering */ -+ writel_relaxed(0, -+ priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); -+ } - - dev_dbg(priv->dev, "%s\n", priv->venc.hdmi_use_enci ? "VENCI" : "VENCP"); - -@@ -262,7 +274,11 @@ static void meson_encoder_hdmi_atomic_disable(struct drm_bridge *bridge, - writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); - } - --static const u32 meson_encoder_hdmi_out_bus_fmts[] = { -+static const u32 meson8_encoder_hdmi_out_bus_fmts[] = { -+ MEDIA_BUS_FMT_YUV8_1X24, -+}; -+ -+static const u32 meson_gx_encoder_hdmi_out_bus_fmts[] = { - MEDIA_BUS_FMT_YUV8_1X24, - MEDIA_BUS_FMT_UYVY8_1X16, - MEDIA_BUS_FMT_UYYVYY8_0_5X24, -@@ -276,13 +292,27 @@ meson_encoder_hdmi_get_inp_bus_fmts(struct drm_bridge *bridge, - u32 output_fmt, - unsigned int *num_input_fmts) - { -+ struct meson_encoder_hdmi *encoder_hdmi = bridge_to_meson_encoder_hdmi(bridge); -+ struct meson_drm *priv = encoder_hdmi->priv; -+ unsigned int num_out_bus_fmts; -+ const u32 *out_bus_fmts; - u32 *input_fmts = NULL; - int i; - -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ num_out_bus_fmts = ARRAY_SIZE(meson8_encoder_hdmi_out_bus_fmts); -+ out_bus_fmts = meson8_encoder_hdmi_out_bus_fmts; -+ } else { -+ num_out_bus_fmts = ARRAY_SIZE(meson_gx_encoder_hdmi_out_bus_fmts); -+ out_bus_fmts = meson_gx_encoder_hdmi_out_bus_fmts; -+ } -+ - *num_input_fmts = 0; - -- for (i = 0 ; i < ARRAY_SIZE(meson_encoder_hdmi_out_bus_fmts) ; ++i) { -- if (output_fmt == meson_encoder_hdmi_out_bus_fmts[i]) { -+ for (i = 0 ; i < num_out_bus_fmts ; ++i) { -+ if (output_fmt == out_bus_fmts[i]) { - *num_input_fmts = 1; - input_fmts = kcalloc(*num_input_fmts, - sizeof(*input_fmts), -@@ -436,8 +466,11 @@ int meson_encoder_hdmi_init(struct meson_drm *priv) - - drm_connector_attach_max_bpc_property(meson_encoder_hdmi->connector, 8, 8); - -- /* Handle this here until handled by drm_bridge_connector_init() */ -- meson_encoder_hdmi->connector->ycbcr_420_allowed = true; -+ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) -+ /* Handle this here until handled by drm_bridge_connector_init() */ -+ meson_encoder_hdmi->connector->ycbcr_420_allowed = true; - - pdev = of_find_device_by_node(remote); - of_node_put(remote); -diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c -index 815dfe30..27e39577 100644 ---- a/drivers/gpu/drm/meson/meson_plane.c -+++ b/drivers/gpu/drm/meson/meson_plane.c -@@ -200,8 +200,11 @@ static void meson_plane_atomic_update(struct drm_plane *plane, - priv->viu.osd1_ctrl_stat2 &= ~OSD_DPATH_MALI_AFBCD; - } - -- /* On GXBB, Use the old non-HDR RGB2YUV converter */ -- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) -+ /* On GXBB and earlier, Use the old non-HDR RGB2YUV converter */ -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) - priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB; - - if (priv->viu.osd1_afbcd && -@@ -471,7 +474,20 @@ static const struct drm_plane_funcs meson_plane_funcs = { - .format_mod_supported = meson_plane_format_mod_supported, - }; - --static const uint32_t supported_drm_formats[] = { -+/* -+ * X components (for example in DRM_FORMAT_XRGB8888 and DRM_FORMAT_XBGR8888) -+ * are not supported because these older SoC's are lacking the OSD_REPLACE_EN -+ * bit to replace the X alpha component with a static value, leaving the alpha -+ * component in an undefined state. -+ */ -+static const uint32_t supported_drm_formats_m8[] = { -+ DRM_FORMAT_ARGB8888, -+ DRM_FORMAT_ABGR8888, -+ DRM_FORMAT_RGB888, -+ DRM_FORMAT_RGB565, -+}; -+ -+static const uint32_t supported_drm_formats_gx[] = { - DRM_FORMAT_ARGB8888, - DRM_FORMAT_ABGR8888, - DRM_FORMAT_XRGB8888, -@@ -533,6 +549,8 @@ int meson_plane_create(struct meson_drm *priv) - { - struct meson_plane *meson_plane; - struct drm_plane *plane; -+ unsigned int num_drm_formats; -+ const uint32_t *drm_formats; - const uint64_t *format_modifiers = format_modifiers_default; - - meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane), -@@ -548,10 +566,19 @@ int meson_plane_create(struct meson_drm *priv) - else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) - format_modifiers = format_modifiers_afbc_g12a; - -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ drm_formats = supported_drm_formats_m8; -+ num_drm_formats = ARRAY_SIZE(supported_drm_formats_m8); -+ } else { -+ drm_formats = supported_drm_formats_gx; -+ num_drm_formats = ARRAY_SIZE(supported_drm_formats_gx); -+ } -+ - drm_universal_plane_init(priv->drm, plane, 0xFF, - &meson_plane_funcs, -- supported_drm_formats, -- ARRAY_SIZE(supported_drm_formats), -+ drm_formats, num_drm_formats, - format_modifiers, - DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane"); - -diff --git a/drivers/gpu/drm/meson/meson_transwitch_hdmi.c b/drivers/gpu/drm/meson/meson_transwitch_hdmi.c -new file mode 100644 -index 00000000..e88bdba7 ---- /dev/null -+++ b/drivers/gpu/drm/meson/meson_transwitch_hdmi.c -@@ -0,0 +1,1579 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2021 Martin Blumenstingl -+ * -+ * All registers and magic values are taken from Amlogic's GPL kernel sources: -+ * Copyright (C) 2010 Amlogic, Inc. -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#include -+ -+#include -+ -+#include "meson_transwitch_hdmi.h" -+ -+#define HDMI_ADDR_PORT 0x0 -+#define HDMI_DATA_PORT 0x4 -+#define HDMI_CTRL_PORT 0x8 -+ #define HDMI_CTRL_PORT_APB3_ERR_EN BIT(15) -+ -+struct meson_txc_hdmi { -+ struct device *dev; -+ -+ struct regmap *regmap; -+ -+ struct clk *pclk; -+ struct clk *sys_clk; -+ -+ struct phy *phy; -+ bool phy_is_on; -+ -+ struct mutex codec_mutex; -+ enum drm_connector_status last_connector_status; -+ hdmi_codec_plugged_cb codec_plugged_cb; -+ struct device *codec_dev; -+ -+ struct platform_device *hdmi_codec_pdev; -+ -+ struct drm_connector *current_connector; -+ -+ struct drm_bridge bridge; -+ struct drm_bridge *next_bridge; -+ -+ bool sink_is_hdmi; -+}; -+ -+#define bridge_to_meson_txc_hdmi(x) container_of(x, struct meson_txc_hdmi, bridge) -+ -+static const struct regmap_range meson_txc_hdmi_regmap_ranges[] = { -+ regmap_reg_range(0x0000, 0x07ff), -+ regmap_reg_range(0x8000, 0x800c), -+}; -+ -+static const struct regmap_access_table meson_txc_hdmi_regmap_access = { -+ .yes_ranges = meson_txc_hdmi_regmap_ranges, -+ .n_yes_ranges = ARRAY_SIZE(meson_txc_hdmi_regmap_ranges), -+}; -+ -+static int meson_txc_hdmi_reg_read(void *context, unsigned int addr, -+ unsigned int *data) -+{ -+ void __iomem *base = context; -+ -+ writel(addr, base + HDMI_ADDR_PORT); -+ writel(addr, base + HDMI_ADDR_PORT); -+ -+ *data = readl(base + HDMI_DATA_PORT); -+ -+ return 0; -+} -+ -+static int meson_txc_hdmi_reg_write(void *context, unsigned int addr, -+ unsigned int data) -+{ -+ void __iomem *base = context; -+ -+ writel(addr, base + HDMI_ADDR_PORT); -+ writel(addr, base + HDMI_ADDR_PORT); -+ -+ writel(data, base + HDMI_DATA_PORT); -+ -+ return 0; -+} -+ -+static const struct regmap_config meson_txc_hdmi_regmap_config = { -+ .reg_bits = 16, -+ .val_bits = 16, -+ .reg_stride = 1, -+ .reg_read = meson_txc_hdmi_reg_read, -+ .reg_write = meson_txc_hdmi_reg_write, -+ .rd_table = &meson_txc_hdmi_regmap_access, -+ .wr_table = &meson_txc_hdmi_regmap_access, -+ .max_register = HDMI_OTHER_RX_PACKET_INTR_CLR, -+ .fast_io = true, -+}; -+ -+static void meson_txc_hdmi_write_infoframe(struct regmap *regmap, -+ unsigned int tx_pkt_reg, u8 *buf, -+ unsigned int len, bool enable) -+{ -+ unsigned int i; -+ -+ /* Write the data bytes by starting at register offset 1 */ -+ for (i = HDMI_INFOFRAME_HEADER_SIZE; i < len; i++) -+ regmap_write(regmap, -+ tx_pkt_reg + i - HDMI_INFOFRAME_HEADER_SIZE + 1, -+ buf[i]); -+ -+ /* Zero all remaining data bytes */ -+ for (; i < 0x1c; i++) -+ regmap_write(regmap, tx_pkt_reg + i, 0x00); -+ -+ /* Write the header (which we skipped above) */ -+ regmap_write(regmap, tx_pkt_reg + 0x00, buf[3]); -+ regmap_write(regmap, tx_pkt_reg + 0x1c, buf[0]); -+ regmap_write(regmap, tx_pkt_reg + 0x1d, buf[1]); -+ regmap_write(regmap, tx_pkt_reg + 0x1e, buf[2]); -+ -+ regmap_write(regmap, tx_pkt_reg + 0x1f, enable ? 0xff : 0x00); -+} -+ -+static void meson_txc_hdmi_disable_infoframe(struct meson_txc_hdmi *priv, -+ unsigned int tx_pkt_reg) -+{ -+ u8 buf[HDMI_INFOFRAME_HEADER_SIZE] = { 0 }; -+ -+ meson_txc_hdmi_write_infoframe(priv->regmap, tx_pkt_reg, buf, -+ HDMI_INFOFRAME_HEADER_SIZE, false); -+} -+ -+static void meson_txc_hdmi_sys5_reset_assert(struct meson_txc_hdmi *priv) -+{ -+ /* A comment in the vendor driver says: bit5,6 is converted */ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN); -+ usleep_range(10, 20); -+ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN); -+ usleep_range(10, 20); -+ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, -+ TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2 | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1 | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0); -+ usleep_range(10, 20); -+} -+ -+static void meson_txc_hdmi_sys5_reset_deassert(struct meson_txc_hdmi *priv) -+{ -+ /* Release the resets except tmds_clk */ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, -+ TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN); -+ usleep_range(10, 20); -+ -+ /* Release the tmds_clk reset as well */ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, 0x0); -+ usleep_range(10, 20); -+ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST); -+ usleep_range(10, 20); -+ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN); -+ usleep_range(10, 20); -+} -+ -+static void meson_txc_hdmi_config_hdcp_registers(struct meson_txc_hdmi *priv) -+{ -+ regmap_write(priv->regmap, TX_HDCP_CONFIG0, -+ FIELD_PREP(TX_HDCP_CONFIG0_ROM_ENCRYPT_OFF, 0x3)); -+ regmap_write(priv->regmap, TX_HDCP_MEM_CONFIG, 0x0); -+ regmap_write(priv->regmap, TX_HDCP_ENCRYPT_BYTE, 0x0); -+ -+ regmap_write(priv->regmap, TX_HDCP_MODE, TX_HDCP_MODE_CLEAR_AVMUTE); -+ -+ regmap_write(priv->regmap, TX_HDCP_MODE, TX_HDCP_MODE_ESS_CONFIG); -+} -+ -+static u8 meson_txc_hdmi_bus_fmt_to_color_depth(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ /* 8 bit */ -+ return 0x0; -+ -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ /* 10 bit */ -+ return 0x1; -+ -+ case MEDIA_BUS_FMT_RGB121212_1X36: -+ case MEDIA_BUS_FMT_YUV12_1X36: -+ case MEDIA_BUS_FMT_UYVY12_1X24: -+ /* 12 bit */ -+ return 0x2; -+ -+ case MEDIA_BUS_FMT_RGB161616_1X48: -+ case MEDIA_BUS_FMT_YUV16_1X48: -+ /* 16 bit */ -+ return 0x3; -+ -+ default: -+ /* unknown, default to 8 bit */ -+ return 0x0; -+ } -+} -+ -+static u8 meson_txc_hdmi_bus_fmt_to_color_format(unsigned int bus_format) -+{ -+ switch (bus_format) { -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_YUV12_1X36: -+ case MEDIA_BUS_FMT_YUV16_1X48: -+ /* Documented as YCbCr444 */ -+ return 0x1; -+ -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ case MEDIA_BUS_FMT_UYVY12_1X24: -+ /* Documented as YCbCr422 */ -+ return 0x3; -+ -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ case MEDIA_BUS_FMT_RGB121212_1X36: -+ case MEDIA_BUS_FMT_RGB161616_1X48: -+ default: -+ /* Documented as RGB444 */ -+ return 0x0; -+ } -+} -+ -+static void meson_txc_hdmi_config_color_space(struct meson_txc_hdmi *priv, -+ unsigned int input_bus_format, -+ unsigned int output_bus_format, -+ enum hdmi_quantization_range quant_range, -+ enum hdmi_colorimetry colorimetry) -+{ -+ unsigned int regval; -+ -+ regmap_write(priv->regmap, TX_VIDEO_DTV_MODE, -+ FIELD_PREP(TX_VIDEO_DTV_MODE_COLOR_DEPTH, -+ meson_txc_hdmi_bus_fmt_to_color_depth(output_bus_format))); -+ -+ regmap_write(priv->regmap, TX_VIDEO_DTV_OPTION_L, -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_FORMAT, -+ meson_txc_hdmi_bus_fmt_to_color_format(output_bus_format)) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_FORMAT, -+ meson_txc_hdmi_bus_fmt_to_color_format(input_bus_format)) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_DEPTH, -+ meson_txc_hdmi_bus_fmt_to_color_depth(output_bus_format)) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_DEPTH, -+ meson_txc_hdmi_bus_fmt_to_color_depth(input_bus_format))); -+ -+ if (quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) -+ regval = FIELD_PREP(TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE, -+ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE, -+ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235); -+ else -+ regval = FIELD_PREP(TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE, -+ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255) | -+ FIELD_PREP(TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE, -+ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255); -+ -+ regmap_write(priv->regmap, TX_VIDEO_DTV_OPTION_H, regval); -+ -+ if (colorimetry == HDMI_COLORIMETRY_ITU_601) { -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B0, 0x2f); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B1, 0x1d); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R0, 0x8b); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R1, 0x4c); -+ -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB0, 0x18); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB1, 0x58); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR0, 0xd0); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR1, 0xb6); -+ } else { -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B0, 0x7b); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B1, 0x12); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R0, 0x6c); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R1, 0x36); -+ -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB0, 0xf2); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB1, 0x2f); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR0, 0xd4); -+ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR1, 0x77); -+ } -+} -+ -+static void meson_txc_hdmi_config_serializer_clock(struct meson_txc_hdmi *priv, -+ enum hdmi_colorimetry colorimetry) -+{ -+ /* Serializer Internal clock setting */ -+ if (colorimetry == HDMI_COLORIMETRY_ITU_601) -+ regmap_write(priv->regmap, TX_SYS1_PLL, 0x24); -+ else -+ regmap_write(priv->regmap, TX_SYS1_PLL, 0x22); -+ -+#if 0 -+ // TODO: not ported yet -+ if ((param->VIC==HDMI_1080p60)&&(param->color_depth==COLOR_30BIT)&&(hdmi_rd_reg(0x018)==0x22)) { -+ regmap_write(priv->regmap, TX_SYS1_PLL, 0x12); -+ } -+#endif -+} -+ -+static void meson_txc_hdmi_reconfig_packet_setting(struct meson_txc_hdmi *priv, -+ u8 cea_mode) -+{ -+ u8 alloc_active2, alloc_eof1, alloc_sof1, alloc_sof2; -+ -+ regmap_write(priv->regmap, TX_PACKET_CONTROL_1, -+ FIELD_PREP(TX_PACKET_CONTROL_1_PACKET_START_LATENCY, 58)); -+ regmap_write(priv->regmap, TX_PACKET_CONTROL_2, -+ TX_PACKET_CONTROL_2_HORIZONTAL_GC_PACKET_TRANSPORT_EN); -+ -+ switch (cea_mode) { -+ case 31: -+ /* 1920x1080p50 */ -+ alloc_active2 = 0x12; -+ alloc_eof1 = 0x10; -+ alloc_sof1 = 0xb6; -+ alloc_sof2 = 0x11; -+ break; -+ case 93: -+ /* 3840x2160p24 */ -+ alloc_active2 = 0x12; -+ alloc_eof1 = 0x47; -+ alloc_sof1 = 0xf8; -+ alloc_sof2 = 0x52; -+ break; -+ case 94: -+ /* 3840x2160p25 */ -+ alloc_active2 = 0x12; -+ alloc_eof1 = 0x44; -+ alloc_sof1 = 0xda; -+ alloc_sof2 = 0x52; -+ break; -+ case 95: -+ /* 3840x2160p30 */ -+ alloc_active2 = 0x0f; -+ alloc_eof1 = 0x3a; -+ alloc_sof1 = 0x60; -+ alloc_sof2 = 0x52; -+ break; -+ case 98: -+ /* 4096x2160p24 */ -+ alloc_active2 = 0x12; -+ alloc_eof1 = 0x47; -+ alloc_sof1 = 0xf8; -+ alloc_sof2 = 0x52; -+ break; -+ default: -+ /* Disable the special packet settings only */ -+ regmap_write(priv->regmap, TX_PACKET_ALLOC_ACTIVE_1, 0x00); -+ return; -+ } -+ -+ /* -+ * The vendor driver says: manually configure these register to get -+ * stable video timings. -+ */ -+ regmap_write(priv->regmap, TX_PACKET_ALLOC_ACTIVE_1, 0x01); -+ regmap_write(priv->regmap, TX_PACKET_ALLOC_ACTIVE_2, alloc_active2); -+ regmap_write(priv->regmap, TX_PACKET_ALLOC_EOF_1, alloc_eof1); -+ regmap_write(priv->regmap, TX_PACKET_ALLOC_EOF_2, 0x12); -+ regmap_write(priv->regmap, TX_CORE_ALLOC_VSYNC_0, 0x01); -+ regmap_write(priv->regmap, TX_CORE_ALLOC_VSYNC_1, 0x00); -+ regmap_write(priv->regmap, TX_CORE_ALLOC_VSYNC_2, 0x0a); -+ regmap_write(priv->regmap, TX_PACKET_ALLOC_SOF_1, alloc_sof1); -+ regmap_write(priv->regmap, TX_PACKET_ALLOC_SOF_2, alloc_sof2); -+ regmap_update_bits(priv->regmap, TX_PACKET_CONTROL_1, -+ TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING, -+ TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING); -+} -+ -+static void meson_txc_hdmi_set_avi_infoframe(struct meson_txc_hdmi *priv, -+ struct drm_connector *conn, -+ const struct drm_display_mode *mode, -+ const struct drm_connector_state *conn_state, -+ unsigned int output_bus_format, -+ enum hdmi_quantization_range quant_range, -+ enum hdmi_colorimetry colorimetry) -+{ -+ u8 buf[HDMI_INFOFRAME_SIZE(AVI)], *video_code; -+ struct hdmi_avi_infoframe frame; -+ int ret; -+ -+ ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, conn, mode); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to setup AVI infoframe: %d\n", ret); -+ return; -+ } -+ -+ switch (output_bus_format) { -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ case MEDIA_BUS_FMT_YUV12_1X36: -+ case MEDIA_BUS_FMT_YUV16_1X48: -+ frame.colorspace = HDMI_COLORSPACE_YUV444; -+ break; -+ -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ case MEDIA_BUS_FMT_UYVY12_1X24: -+ frame.colorspace = HDMI_COLORSPACE_YUV422; -+ break; -+ -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ case MEDIA_BUS_FMT_RGB121212_1X36: -+ case MEDIA_BUS_FMT_RGB161616_1X48: -+ default: -+ frame.colorspace = HDMI_COLORSPACE_RGB; -+ break; -+ } -+ -+ drm_hdmi_avi_infoframe_colorimetry(&frame, conn_state); -+ drm_hdmi_avi_infoframe_quant_range(&frame, conn, mode, quant_range); -+ drm_hdmi_avi_infoframe_bars(&frame, conn_state); -+ -+ ret = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf)); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to pack AVI infoframe: %d\n", ret); -+ return; -+ } -+ -+ video_code = &buf[HDMI_INFOFRAME_HEADER_SIZE + 3]; -+ if (*video_code > 108) { -+ regmap_write(priv->regmap, TX_PKT_REG_EXCEPT0_BASE_ADDR, -+ *video_code); -+ *video_code = 0x00; -+ } else { -+ regmap_write(priv->regmap, TX_PKT_REG_EXCEPT0_BASE_ADDR, -+ 0x00); -+ } -+ -+ meson_txc_hdmi_write_infoframe(priv->regmap, -+ TX_PKT_REG_AVI_INFO_BASE_ADDR, buf, -+ sizeof(buf), true); -+} -+ -+static void meson_txc_hdmi_set_vendor_infoframe(struct meson_txc_hdmi *priv, -+ struct drm_connector *conn, -+ const struct drm_display_mode *mode) -+{ -+ u8 buf[HDMI_INFOFRAME_HEADER_SIZE + 6]; -+ struct hdmi_vendor_infoframe frame; -+ int ret; -+ -+ ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame, conn, mode); -+ if (ret) { -+ drm_dbg(priv->bridge.dev, -+ "Failed to setup vendor infoframe: %d\n", ret); -+ return; -+ } -+ -+ ret = hdmi_vendor_infoframe_pack(&frame, buf, sizeof(buf)); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to pack vendor infoframe: %d\n", ret); -+ return; -+ } -+ -+ meson_txc_hdmi_write_infoframe(priv->regmap, -+ TX_PKT_REG_VEND_INFO_BASE_ADDR, buf, -+ sizeof(buf), true); -+} -+ -+static void meson_txc_hdmi_set_spd_infoframe(struct meson_txc_hdmi *priv) -+{ -+ u8 buf[HDMI_INFOFRAME_SIZE(SPD)]; -+ struct hdmi_spd_infoframe frame; -+ int ret; -+ -+ ret = hdmi_spd_infoframe_init(&frame, "Amlogic", "Meson TXC HDMI"); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to setup SPD infoframe: %d\n", ret); -+ return; -+ } -+ -+ ret = hdmi_spd_infoframe_pack(&frame, buf, sizeof(buf)); -+ if (ret < 0) { -+ drm_err(priv->bridge.dev, -+ "Failed to pack SDP infoframe: %d\n", ret); -+ return; -+ } -+ -+ meson_txc_hdmi_write_infoframe(priv->regmap, -+ TX_PKT_REG_SPD_INFO_BASE_ADDR, buf, -+ sizeof(buf), true); -+} -+ -+static void meson_txc_hdmi_handle_plugged_change(struct meson_txc_hdmi *priv) -+{ -+ bool plugged; -+ -+ plugged = priv->last_connector_status == connector_status_connected; -+ -+ if (priv->codec_dev && priv->codec_plugged_cb) -+ priv->codec_plugged_cb(priv->codec_dev, plugged); -+} -+ -+static int meson_txc_hdmi_bridge_attach(struct drm_bridge *bridge, -+ enum drm_bridge_attach_flags flags) -+{ -+ struct meson_txc_hdmi *priv = bridge->driver_private; -+ -+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { -+ drm_err(bridge->dev, -+ "DRM_BRIDGE_ATTACH_NO_CONNECTOR flag is not set but needed\n"); -+ return -EINVAL; -+ } -+ -+ return drm_bridge_attach(bridge->encoder, priv->next_bridge, bridge, -+ flags); -+} -+ -+/* Can return a maximum of 11 possible output formats for a mode/connector */ -+#define MAX_OUTPUT_SEL_FORMATS 11 -+ -+static u32 * -+meson_txc_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ unsigned int *num_output_fmts) -+{ -+ struct drm_connector *conn = conn_state->connector; -+ struct drm_display_info *info = &conn->display_info; -+ u8 max_bpc = conn_state->max_requested_bpc; -+ unsigned int i = 0; -+ u32 *output_fmts; -+ -+ *num_output_fmts = 0; -+ -+ output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), -+ GFP_KERNEL); -+ if (!output_fmts) -+ return NULL; -+ -+ /* If we are the only bridge, avoid negotiating with ourselves */ -+ if (list_is_singular(&bridge->encoder->bridge_chain)) { -+ *num_output_fmts = 1; -+ output_fmts[0] = MEDIA_BUS_FMT_FIXED; -+ -+ return output_fmts; -+ } -+ -+ /* -+ * Order bus formats from 16bit to 8bit and from YUV422 to RGB -+ * if supported. In any case the default RGB888 format is added -+ */ -+ -+ if (max_bpc >= 16 && info->bpc == 16) { -+ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; -+ -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; -+ } -+ -+ if (max_bpc >= 12 && info->bpc >= 12) { -+ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) -+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; -+ -+ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; -+ -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; -+ } -+ -+ if (max_bpc >= 10 && info->bpc >= 10) { -+ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) -+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; -+ -+ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; -+ -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; -+ } -+ -+ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) -+ output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; -+ -+ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) -+ output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; -+ -+ /* Default 8bit RGB fallback */ -+ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ -+ *num_output_fmts = i; -+ -+ return output_fmts; -+} -+ -+/* Can return a maximum of 3 possible input formats for an output format */ -+#define MAX_INPUT_SEL_FORMATS 3 -+ -+static u32 * -+meson_txc_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, -+ struct drm_bridge_state *bridge_state, -+ struct drm_crtc_state *crtc_state, -+ struct drm_connector_state *conn_state, -+ u32 output_fmt, -+ unsigned int *num_input_fmts) -+{ -+ u32 *input_fmts; -+ unsigned int i = 0; -+ -+ *num_input_fmts = 0; -+ -+ input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), -+ GFP_KERNEL); -+ if (!input_fmts) -+ return NULL; -+ -+ switch (output_fmt) { -+ /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ -+ case MEDIA_BUS_FMT_FIXED: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ break; -+ -+ /* 8bit */ -+ case MEDIA_BUS_FMT_RGB888_1X24: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; -+ break; -+ case MEDIA_BUS_FMT_YUV8_1X24: -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ break; -+ case MEDIA_BUS_FMT_UYVY8_1X16: -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; -+ break; -+ -+ /* 10bit */ -+ case MEDIA_BUS_FMT_RGB101010_1X30: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; -+ break; -+ case MEDIA_BUS_FMT_YUV10_1X30: -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; -+ break; -+ case MEDIA_BUS_FMT_UYVY10_1X20: -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; -+ break; -+ -+ /* 12bit */ -+ case MEDIA_BUS_FMT_RGB121212_1X36: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; -+ break; -+ case MEDIA_BUS_FMT_YUV12_1X36: -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; -+ break; -+ case MEDIA_BUS_FMT_UYVY12_1X24: -+ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; -+ break; -+ -+ /* 16bit */ -+ case MEDIA_BUS_FMT_RGB161616_1X48: -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; -+ break; -+ case MEDIA_BUS_FMT_YUV16_1X48: -+ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; -+ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; -+ break; -+ } -+ -+ *num_input_fmts = i; -+ -+ if (*num_input_fmts == 0) { -+ kfree(input_fmts); -+ input_fmts = NULL; -+ } -+ -+ return input_fmts; -+} -+ -+static void meson_txc_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, -+ struct drm_bridge_state *old_bridge_state) -+{ -+ struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge); -+ struct drm_atomic_state *state = old_bridge_state->base.state; -+ enum hdmi_quantization_range quant_range; -+ struct drm_connector_state *conn_state; -+ struct drm_bridge_state *bridge_state; -+ const struct drm_display_mode *mode; -+ enum hdmi_colorimetry colorimetry; -+ struct drm_crtc_state *crtc_state; -+ struct drm_connector *connector; -+ unsigned int i; -+ u8 cea_mode; -+ -+ bridge_state = drm_atomic_get_new_bridge_state(state, bridge); -+ -+ connector = drm_atomic_get_new_connector_for_encoder(state, -+ bridge->encoder); -+ if (WARN_ON(!connector)) -+ return; -+ -+ conn_state = drm_atomic_get_new_connector_state(state, connector); -+ if (WARN_ON(!conn_state)) -+ return; -+ -+ crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); -+ if (WARN_ON(!crtc_state)) -+ return; -+ -+ priv->current_connector = connector; -+ -+ mode = &crtc_state->adjusted_mode; -+ -+ cea_mode = drm_match_cea_mode(mode); -+ -+ if (priv->sink_is_hdmi) { -+ quant_range = drm_default_rgb_quant_range(mode); -+ -+ switch (cea_mode) { -+ case 2 ... 3: -+ case 6 ... 7: -+ case 17 ... 18: -+ case 21 ... 22: -+ colorimetry = HDMI_COLORIMETRY_ITU_601; -+ break; -+ -+ default: -+ colorimetry = HDMI_COLORIMETRY_ITU_709; -+ break; -+ } -+ -+ meson_txc_hdmi_set_avi_infoframe(priv, connector, mode, -+ conn_state, -+ bridge_state->output_bus_cfg.format, -+ quant_range, colorimetry); -+ meson_txc_hdmi_set_vendor_infoframe(priv, connector, mode); -+ meson_txc_hdmi_set_spd_infoframe(priv); -+ } else { -+ quant_range = HDMI_QUANTIZATION_RANGE_FULL; -+ colorimetry = HDMI_COLORIMETRY_NONE; -+ } -+ -+ meson_txc_hdmi_sys5_reset_assert(priv); -+ -+ meson_txc_hdmi_config_hdcp_registers(priv); -+ -+ if (cea_mode == 39) -+ regmap_write(priv->regmap, TX_VIDEO_DTV_TIMING, 0x0); -+ else -+ regmap_write(priv->regmap, TX_VIDEO_DTV_TIMING, -+ TX_VIDEO_DTV_TIMING_DISABLE_VIC39_CORRECTION); -+ -+ regmap_write(priv->regmap, TX_CORE_DATA_CAPTURE_2, -+ TX_CORE_DATA_CAPTURE_2_INTERNAL_PACKET_ENABLE); -+ regmap_write(priv->regmap, TX_CORE_DATA_MONITOR_1, -+ TX_CORE_DATA_MONITOR_1_LANE0 | -+ FIELD_PREP(TX_CORE_DATA_MONITOR_1_SELECT_LANE0, 0x7)); -+ regmap_write(priv->regmap, TX_CORE_DATA_MONITOR_2, -+ FIELD_PREP(TX_CORE_DATA_MONITOR_2_MONITOR_SELECT, 0x2)); -+ -+ if (priv->sink_is_hdmi) -+ regmap_write(priv->regmap, TX_TMDS_MODE, -+ TX_TMDS_MODE_FORCED_HDMI | -+ TX_TMDS_MODE_HDMI_CONFIG); -+ else -+ regmap_write(priv->regmap, TX_TMDS_MODE, -+ TX_TMDS_MODE_FORCED_HDMI); -+ -+ regmap_write(priv->regmap, TX_SYS4_CONNECT_SEL_1, 0x0); -+ -+ /* -+ * Set tmds_clk pattern to be "0000011111" before being sent to AFE -+ * clock channel. -+ */ -+ regmap_write(priv->regmap, TX_SYS4_CK_INV_VIDEO, -+ TX_SYS4_CK_INV_VIDEO_TMDS_CLK_PATTERN); -+ -+ regmap_write(priv->regmap, TX_SYS5_FIFO_CONFIG, -+ TX_SYS5_FIFO_CONFIG_CLK_CHANNEL3_OUTPUT_ENABLE | -+ TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_ENABLE | -+ TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_ENABLE | -+ TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_ENABLE); -+ -+ meson_txc_hdmi_config_color_space(priv, -+ bridge_state->input_bus_cfg.format, -+ bridge_state->output_bus_cfg.format, -+ quant_range, colorimetry); -+ -+ meson_txc_hdmi_sys5_reset_deassert(priv); -+ -+ meson_txc_hdmi_config_serializer_clock(priv, colorimetry); -+ meson_txc_hdmi_reconfig_packet_setting(priv, cea_mode); -+ -+ /* all resets need to be applied twice */ -+ for (i = 0; i < 2; i++) { -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, -+ TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2 | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1 | -+ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0); -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN | -+ TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST | -+ TX_SYS5_TX_SOFT_RESET_2_TX_DDC_HDCP_RSTN | -+ TX_SYS5_TX_SOFT_RESET_2_TX_DDC_EDID_RSTN | -+ TX_SYS5_TX_SOFT_RESET_2_TX_DIG_RESET_N_CH3); -+ usleep_range(5000, 10000); -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, 0x00); -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, 0x00); -+ usleep_range(5000, 10000); -+ } -+ -+ if (!priv->phy_is_on) { -+ int ret; -+ -+ ret = phy_power_on(priv->phy); -+ if (ret) -+ drm_err(bridge->dev, "Failed to turn on PHY\n"); -+ else -+ priv->phy_is_on = true; -+ } -+} -+ -+static void meson_txc_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, -+ struct drm_bridge_state *old_bridge_state) -+{ -+ struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge); -+ -+ priv->current_connector = NULL; -+ -+ if (priv->phy_is_on) { -+ int ret; -+ -+ ret = phy_power_off(priv->phy); -+ if (ret) -+ drm_err(bridge->dev, "Failed to turn off PHY\n"); -+ else -+ priv->phy_is_on = false; -+ } -+ -+ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_AUDIO_INFO_BASE_ADDR); -+ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_AVI_INFO_BASE_ADDR); -+ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_EXCEPT0_BASE_ADDR); -+ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_VEND_INFO_BASE_ADDR); -+} -+ -+static enum drm_mode_status -+meson_txc_hdmi_bridge_mode_valid(struct drm_bridge *bridge, -+ const struct drm_display_info *info, -+ const struct drm_display_mode *mode) -+{ -+ return MODE_OK; -+} -+ -+static enum drm_connector_status meson_txc_hdmi_bridge_detect(struct drm_bridge *bridge) -+{ -+ struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge); -+ enum drm_connector_status status; -+ unsigned int val; -+ -+ regmap_read(priv->regmap, TX_HDCP_ST_EDID_STATUS, &val); -+ if (val & TX_HDCP_ST_EDID_STATUS_HPD_STATUS) -+ status = connector_status_connected; -+ else -+ status = connector_status_disconnected; -+ -+ mutex_lock(&priv->codec_mutex); -+ if (priv->last_connector_status != status) { -+ priv->last_connector_status = status; -+ meson_txc_hdmi_handle_plugged_change(priv); -+ } -+ mutex_unlock(&priv->codec_mutex); -+ -+ return status; -+} -+ -+static int meson_txc_hdmi_get_edid_block(void *data, u8 *buf, unsigned int block, -+ size_t len) -+{ -+ unsigned int i, regval, start = block * EDID_LENGTH; -+ struct meson_txc_hdmi *priv = data; -+ int ret; -+ -+ /* Start the DDC transaction */ -+ regmap_update_bits(priv->regmap, TX_HDCP_EDID_CONFIG, -+ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG, 0); -+ regmap_update_bits(priv->regmap, TX_HDCP_EDID_CONFIG, -+ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG, -+ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG); -+ -+ ret = regmap_read_poll_timeout(priv->regmap, -+ TX_HDCP_ST_EDID_STATUS, -+ regval, -+ (regval & TX_HDCP_ST_EDID_STATUS_EDID_DATA_READY), -+ 1000, 200000); -+ -+ regmap_update_bits(priv->regmap, TX_HDCP_EDID_CONFIG, -+ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG, 0); -+ -+ if (ret) -+ return ret; -+ -+ for (i = 0; i < len; i++) { -+ regmap_read(priv->regmap, TX_RX_EDID_OFFSET + start + i, -+ ®val); -+ buf[i] = regval; -+ } -+ -+ return 0; -+} -+ -+static struct edid *meson_txc_hdmi_bridge_get_edid(struct drm_bridge *bridge, -+ struct drm_connector *connector) -+{ -+ struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge); -+ struct edid *edid; -+ -+ edid = drm_do_get_edid(connector, meson_txc_hdmi_get_edid_block, priv); -+ if (!edid) { -+ drm_dbg(priv->bridge.dev, "Failed to get EDID\n"); -+ return NULL; -+ } -+ -+ priv->sink_is_hdmi = drm_detect_hdmi_monitor(edid); -+ -+ return edid; -+} -+ -+static const struct drm_bridge_funcs meson_txc_hdmi_bridge_funcs = { -+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, -+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, -+ .atomic_reset = drm_atomic_helper_bridge_reset, -+ .attach = meson_txc_hdmi_bridge_attach, -+ .atomic_get_output_bus_fmts = meson_txc_hdmi_bridge_atomic_get_output_bus_fmts, -+ .atomic_get_input_bus_fmts = meson_txc_hdmi_bridge_atomic_get_input_bus_fmts, -+ .atomic_enable = meson_txc_hdmi_bridge_atomic_enable, -+ .atomic_disable = meson_txc_hdmi_bridge_atomic_disable, -+ .mode_valid = meson_txc_hdmi_bridge_mode_valid, -+ .detect = meson_txc_hdmi_bridge_detect, -+ .get_edid = meson_txc_hdmi_bridge_get_edid, -+}; -+ -+static int meson_txc_hdmi_parse_dt(struct meson_txc_hdmi *priv) -+{ -+ struct device_node *endpoint, *remote; -+ -+ endpoint = of_graph_get_endpoint_by_regs(priv->dev->of_node, 1, -1); -+ if (!endpoint) { -+ dev_err(priv->dev, "Missing endpoint in port@1\n"); -+ return -ENODEV; -+ } -+ -+ remote = of_graph_get_remote_port_parent(endpoint); -+ of_node_put(endpoint); -+ if (!remote) { -+ dev_err(priv->dev, "Endpoint in port@1 unconnected\n"); -+ return -ENODEV; -+ } -+ -+ if (!of_device_is_available(remote)) { -+ dev_err(priv->dev, "port@1 remote device is disabled\n"); -+ of_node_put(remote); -+ return -ENODEV; -+ } -+ -+ priv->next_bridge = of_drm_find_bridge(remote); -+ of_node_put(remote); -+ if (!priv->next_bridge) -+ return -EPROBE_DEFER; -+ -+ return 0; -+} -+ -+static int meson_txc_hdmi_hw_init(struct meson_txc_hdmi *priv) -+{ -+ unsigned long ddc_i2c_bus_clk_hz = 500 * 1000; -+ unsigned long sys_clk_hz = 24 * 1000 * 1000; -+ int ret; -+ -+ ret = phy_init(priv->phy); -+ if (ret) { -+ dev_err(priv->dev, "Failed to initialize the PHY: %d\n", ret); -+ return ret; -+ } -+ -+ ret = clk_set_rate(priv->sys_clk, sys_clk_hz); -+ if (ret) { -+ dev_err(priv->dev, "Failed to set HDMI system clock to 24MHz\n"); -+ goto err_phy_exit; -+ } -+ -+ ret = clk_prepare_enable(priv->sys_clk); -+ if (ret) { -+ dev_err(priv->dev, "Failed to enable the sys clk\n"); -+ goto err_phy_exit; -+ } -+ -+ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_POWER_ON, -+ HDMI_OTHER_CTRL1_POWER_ON); -+ -+ regmap_write(priv->regmap, TX_HDMI_PHY_CONFIG0, -+ TX_HDMI_PHY_CONFIG0_HDMI_COMMON_B7_B0); -+ -+ regmap_write(priv->regmap, TX_HDCP_MODE, 0x40); -+ -+ /* -+ * The vendor driver comments that this is a setting for "Band-gap and -+ * main-bias". 0x1d = power-up, 0x00 = power-down. -+ */ -+ regmap_write(priv->regmap, TX_SYS1_AFE_TEST, 0x1d); -+ -+ meson_txc_hdmi_config_serializer_clock(priv, HDMI_COLORIMETRY_NONE); -+ -+ /* -+ * The vendor driver has a comment with the following information for -+ * the magic value: -+ * bit[2:0]=011: CK channel output TMDS CLOCK -+ * bit[2:0]=101, ck channel output PHYCLCK -+ */ -+ regmap_write(priv->regmap, TX_SYS1_AFE_CONNECT, 0xfb); -+ -+ /* Termination resistor calib value */ -+ regmap_write(priv->regmap, TX_CORE_CALIB_VALUE, 0x0f); -+ -+ /* HPD glitch filter */ -+ regmap_write(priv->regmap, TX_HDCP_HPD_FILTER_L, 0xa0); -+ regmap_write(priv->regmap, TX_HDCP_HPD_FILTER_H, 0xa0); -+ -+ /* Disable MEM power-down */ -+ regmap_write(priv->regmap, TX_MEM_PD_REG0, 0x0); -+ -+ regmap_write(priv->regmap, TX_HDCP_CONFIG3, -+ FIELD_PREP(TX_HDCP_CONFIG3_DDC_I2C_BUS_CLOCK_TIME_DIVIDER, -+ (sys_clk_hz / ddc_i2c_bus_clk_hz) - 1)); -+ -+ /* Enable software controlled DDC transaction */ -+ regmap_write(priv->regmap, TX_HDCP_EDID_CONFIG, -+ TX_HDCP_EDID_CONFIG_FORCED_MEM_COPY_DONE | -+ TX_HDCP_EDID_CONFIG_MEM_COPY_DONE_CONFIG); -+ regmap_write(priv->regmap, TX_CORE_EDID_CONFIG_MORE, -+ TX_CORE_EDID_CONFIG_MORE_SYS_TRIGGER_CONFIG_SEMI_MANU); -+ -+ /* mask (= disable) all interrupts */ -+ regmap_write(priv->regmap, HDMI_OTHER_INTR_MASKN, 0x0); -+ -+ /* clear any pending interrupt */ -+ regmap_write(priv->regmap, HDMI_OTHER_INTR_STAT_CLR, -+ HDMI_OTHER_INTR_STAT_CLR_EDID_RISING | -+ HDMI_OTHER_INTR_STAT_CLR_HPD_FALLING | -+ HDMI_OTHER_INTR_STAT_CLR_HPD_RISING); -+ -+ return 0; -+ -+err_phy_exit: -+ phy_exit(priv->phy); -+ return 0; -+} -+ -+static void meson_txc_hdmi_hw_exit(struct meson_txc_hdmi *priv) -+{ -+ int ret; -+ -+ /* mask (= disable) all interrupts */ -+ regmap_write(priv->regmap, HDMI_OTHER_INTR_MASKN, -+ HDMI_OTHER_INTR_MASKN_TX_EDID_INT_RISE | -+ HDMI_OTHER_INTR_MASKN_TX_HPD_INT_FALL | -+ HDMI_OTHER_INTR_MASKN_TX_HPD_INT_RISE); -+ -+ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_POWER_ON, 0); -+ -+ clk_disable_unprepare(priv->sys_clk); -+ -+ ret = phy_exit(priv->phy); -+ if (ret) -+ dev_err(priv->dev, "Failed to exit the PHY: %d\n", ret); -+} -+ -+static u32 meson_txc_hdmi_hdmi_codec_calc_audio_n(struct hdmi_codec_params *hparms) -+{ -+ u32 audio_n; -+ -+ if ((hparms->sample_rate % 44100) == 0) -+ audio_n = (128 * hparms->sample_rate) / 900; -+ else -+ audio_n = (128 * hparms->sample_rate) / 1000; -+ -+ if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_EAC3 || -+ hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_DTS_HD) -+ audio_n *= 4; -+ -+ return audio_n; -+} -+ -+static u8 meson_txc_hdmi_hdmi_codec_coding_type(struct hdmi_codec_params *hparms) -+{ -+ switch (hparms->cea.coding_type) { -+ case HDMI_AUDIO_CODING_TYPE_MLP: -+ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_HBR_AUDIO_PACKET; -+ case HDMI_AUDIO_CODING_TYPE_DSD: -+ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_ONE_BIT_AUDIO; -+ case HDMI_AUDIO_CODING_TYPE_DST: -+ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_DST_AUDIO_PACKET; -+ default: -+ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_AUDIO_SAMPLE_PACKET; -+ } -+} -+ -+static int meson_txc_hdmi_hdmi_codec_hw_params(struct device *dev, void *data, -+ struct hdmi_codec_daifmt *fmt, -+ struct hdmi_codec_params *hparms) -+{ -+ u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)]; -+ struct meson_txc_hdmi *priv = data; -+ u16 audio_tx_format; -+ u32 audio_n; -+ int len, i; -+ -+ if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_MLP) { -+ /* -+ * TODO: fixed CTS is not supported yet, it needs special -+ * TX_SYS1_ACR_N_* settings -+ */ -+ return -EINVAL; -+ } -+ -+ switch (hparms->sample_width) { -+ case 16: -+ audio_tx_format = FIELD_PREP(TX_AUDIO_FORMAT_BIT_WIDTH_MASK, -+ TX_AUDIO_FORMAT_BIT_WIDTH_16); -+ break; -+ -+ case 20: -+ audio_tx_format = FIELD_PREP(TX_AUDIO_FORMAT_BIT_WIDTH_MASK, -+ TX_AUDIO_FORMAT_BIT_WIDTH_20); -+ break; -+ -+ case 24: -+ audio_tx_format = FIELD_PREP(TX_AUDIO_FORMAT_BIT_WIDTH_MASK, -+ TX_AUDIO_FORMAT_BIT_WIDTH_24); -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ switch (fmt->fmt) { -+ case HDMI_I2S: -+ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON, -+ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON); -+ -+ audio_tx_format |= TX_AUDIO_FORMAT_SPDIF_OR_I2S | -+ TX_AUDIO_FORMAT_I2S_ONE_BIT_OR_I2S | -+ FIELD_PREP(TX_AUDIO_FORMAT_I2S_FORMAT, 0x2); -+ -+ if (hparms->channels > 2) -+ audio_tx_format |= TX_AUDIO_FORMAT_I2S_2_OR_8_CH; -+ -+ regmap_write(priv->regmap, TX_AUDIO_FORMAT, -+ audio_tx_format); -+ -+ regmap_write(priv->regmap, TX_AUDIO_I2S, TX_AUDIO_I2S_ENABLE); -+ regmap_write(priv->regmap, TX_AUDIO_SPDIF, 0x0); -+ break; -+ -+ case HDMI_SPDIF: -+ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON, 0x0); -+ -+ if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_STREAM) -+ audio_tx_format |= TX_AUDIO_FORMAT_SPDIF_CHANNEL_STATUS_FROM_DATA_OR_REG; -+ -+ regmap_write(priv->regmap, TX_AUDIO_FORMAT, -+ audio_tx_format); -+ -+ regmap_write(priv->regmap, TX_AUDIO_I2S, 0x0); -+ regmap_write(priv->regmap, TX_AUDIO_SPDIF, TX_AUDIO_SPDIF_ENABLE); -+ break; -+ -+ default: -+ return -EINVAL; -+ } -+ -+ if (hparms->channels > 2) -+ regmap_write(priv->regmap, TX_AUDIO_HEADER, -+ TX_AUDIO_HEADER_AUDIO_SAMPLE_PACKET_HEADER_LAYOUT1); -+ else -+ regmap_write(priv->regmap, TX_AUDIO_HEADER, 0x0); -+ -+ regmap_write(priv->regmap, TX_AUDIO_SAMPLE, -+ FIELD_PREP(TX_AUDIO_SAMPLE_CHANNEL_VALID, -+ BIT(hparms->channels) - 1)); -+ -+ audio_n = meson_txc_hdmi_hdmi_codec_calc_audio_n(hparms); -+ -+ regmap_write(priv->regmap, TX_SYS1_ACR_N_0, -+ FIELD_PREP(TX_SYS1_ACR_N_0_N_BYTE0, -+ (audio_n >> 0) & 0xff)); -+ regmap_write(priv->regmap, TX_SYS1_ACR_N_1, -+ FIELD_PREP(TX_SYS1_ACR_N_1_N_BYTE1, -+ (audio_n >> 8) & 0xff)); -+ regmap_update_bits(priv->regmap, TX_SYS1_ACR_N_2, -+ TX_SYS1_ACR_N_2_N_UPPER_NIBBLE, -+ FIELD_PREP(TX_SYS1_ACR_N_2_N_UPPER_NIBBLE, -+ (audio_n >> 16) & 0xf)); -+ -+ regmap_write(priv->regmap, TX_SYS0_ACR_CTS_0, 0x0); -+ regmap_write(priv->regmap, TX_SYS0_ACR_CTS_1, 0x0); -+ regmap_write(priv->regmap, TX_SYS0_ACR_CTS_2, -+ TX_SYS0_ACR_CTS_2_FORCE_ARC_STABLE); -+ -+ regmap_write(priv->regmap, TX_AUDIO_CONTROL, -+ TX_AUDIO_CONTROL_AUTO_AUDIO_FIFO_CLEAR | -+ FIELD_PREP(TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_MASK, -+ meson_txc_hdmi_hdmi_codec_coding_type(hparms)) | -+ TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_FLAT); -+ -+ len = hdmi_audio_infoframe_pack(&hparms->cea, buf, sizeof(buf)); -+ if (len < 0) -+ return len; -+ -+ meson_txc_hdmi_write_infoframe(priv->regmap, -+ TX_PKT_REG_AUDIO_INFO_BASE_ADDR, -+ buf, len, true); -+ -+ for (i = 0; i < ARRAY_SIZE(hparms->iec.status); i++) { -+ unsigned char sub1, sub2; -+ -+ sub1 = sub2 = hparms->iec.status[i]; -+ -+ if (i == 2) { -+ sub1 |= FIELD_PREP(IEC958_AES2_CON_CHANNEL, 1); -+ sub2 |= FIELD_PREP(IEC958_AES2_CON_CHANNEL, 2); -+ } -+ -+ regmap_write(priv->regmap, TX_IEC60958_SUB1_OFFSET + i, sub1); -+ regmap_write(priv->regmap, TX_IEC60958_SUB2_OFFSET + i, sub2); -+ } -+ -+ return 0; -+} -+ -+static int meson_txc_hdmi_hdmi_codec_audio_startup(struct device *dev, -+ void *data) -+{ -+ struct meson_txc_hdmi *priv = data; -+ -+ regmap_update_bits(priv->regmap, TX_PACKET_CONTROL_2, -+ TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE, 0x0); -+ -+ /* reset audio master and sample */ -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN | -+ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN); -+ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, 0x0); -+ -+ regmap_write(priv->regmap, TX_AUDIO_CONTROL_MORE, -+ TX_AUDIO_CONTROL_MORE_ENABLE); -+ -+ regmap_write(priv->regmap, TX_AUDIO_FIFO, -+ FIELD_PREP(TX_AUDIO_FIFO_FIFO_DEPTH_MASK, -+ TX_AUDIO_FIFO_FIFO_DEPTH_512) | -+ FIELD_PREP(TX_AUDIO_FIFO_CRITICAL_THRESHOLD_MASK, -+ TX_AUDIO_FIFO_CRITICAL_THRESHOLD_DEPTH_DIV16) | -+ FIELD_PREP(TX_AUDIO_FIFO_NORMAL_THRESHOLD_MASK, -+ TX_AUDIO_FIFO_NORMAL_THRESHOLD_DEPTH_DIV8)); -+ -+ regmap_write(priv->regmap, TX_AUDIO_LIPSYNC, 0x0); -+ -+ regmap_write(priv->regmap, TX_SYS1_ACR_N_2, -+ FIELD_PREP(TX_SYS1_ACR_N_2_N_MEAS_TOLERANCE, 0x3)); -+ -+ return 0; -+} -+ -+static void meson_txc_hdmi_hdmi_codec_audio_shutdown(struct device *dev, -+ void *data) -+{ -+ struct meson_txc_hdmi *priv = data; -+ -+ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_AUDIO_INFO_BASE_ADDR); -+ -+ regmap_write(priv->regmap, TX_AUDIO_CONTROL_MORE, 0x0); -+ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, -+ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON, 0x0); -+ -+ regmap_update_bits(priv->regmap, TX_PACKET_CONTROL_2, -+ TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE, -+ TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE); -+} -+ -+static int meson_txc_hdmi_hdmi_codec_mute_stream(struct device *dev, -+ void *data, -+ bool enable, int direction) -+{ -+ struct meson_txc_hdmi *priv = data; -+ -+ regmap_write(priv->regmap, TX_AUDIO_PACK, -+ enable ? 0 : TX_AUDIO_PACK_AUDIO_SAMPLE_PACKETS_ENABLE); -+ -+ return 0; -+} -+ -+static int meson_txc_hdmi_hdmi_codec_get_eld(struct device *dev, void *data, -+ uint8_t *buf, size_t len) -+{ -+ struct meson_txc_hdmi *priv = data; -+ -+ if (priv->current_connector) -+ memcpy(buf, priv->current_connector->eld, -+ min_t(size_t, MAX_ELD_BYTES, len)); -+ else -+ memset(buf, 0, len); -+ -+ return 0; -+} -+ -+static int meson_txc_hdmi_hdmi_codec_get_dai_id(struct snd_soc_component *component, -+ struct device_node *endpoint) -+{ -+ struct of_endpoint of_ep; -+ int ret; -+ -+ ret = of_graph_parse_endpoint(endpoint, &of_ep); -+ if (ret < 0) -+ return ret; -+ -+ /* -+ * HDMI sound should be located as reg = <2> -+ * Then, it is sound port 0 -+ */ -+ if (of_ep.port == 2) -+ return 0; -+ -+ return -EINVAL; -+} -+ -+static int meson_txc_hdmi_hdmi_codec_hook_plugged_cb(struct device *dev, -+ void *data, -+ hdmi_codec_plugged_cb fn, -+ struct device *codec_dev) -+{ -+ struct meson_txc_hdmi *priv = data; -+ -+ mutex_lock(&priv->codec_mutex); -+ priv->codec_plugged_cb = fn; -+ priv->codec_dev = codec_dev; -+ meson_txc_hdmi_handle_plugged_change(priv); -+ mutex_unlock(&priv->codec_mutex); -+ -+ return 0; -+} -+ -+static struct hdmi_codec_ops meson_txc_hdmi_hdmi_codec_ops = { -+ .hw_params = meson_txc_hdmi_hdmi_codec_hw_params, -+ .audio_startup = meson_txc_hdmi_hdmi_codec_audio_startup, -+ .audio_shutdown = meson_txc_hdmi_hdmi_codec_audio_shutdown, -+ .mute_stream = meson_txc_hdmi_hdmi_codec_mute_stream, -+ .get_eld = meson_txc_hdmi_hdmi_codec_get_eld, -+ .get_dai_id = meson_txc_hdmi_hdmi_codec_get_dai_id, -+ .hook_plugged_cb = meson_txc_hdmi_hdmi_codec_hook_plugged_cb, -+}; -+ -+static int meson_txc_hdmi_hdmi_codec_init(struct meson_txc_hdmi *priv) -+{ -+ struct hdmi_codec_pdata pdata = { -+ .ops = &meson_txc_hdmi_hdmi_codec_ops, -+ .i2s = 1, -+ .spdif = 1, -+ .max_i2s_channels = 8, -+ .data = priv, -+ }; -+ -+ priv->hdmi_codec_pdev = platform_device_register_data(priv->dev, -+ HDMI_CODEC_DRV_NAME, -+ PLATFORM_DEVID_AUTO, -+ &pdata, sizeof(pdata)); -+ return PTR_ERR_OR_ZERO(priv->hdmi_codec_pdev); -+} -+ -+static int meson_txc_hdmi_bind(struct device *dev, struct device *master, -+ void *data) -+{ -+ struct platform_device *pdev = to_platform_device(dev); -+ struct meson_txc_hdmi *priv; -+ void __iomem *base; -+ u32 regval; -+ int ret; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ priv->dev = dev; -+ -+ mutex_init(&priv->codec_mutex); -+ -+ dev_set_drvdata(dev, priv); -+ -+ base = devm_platform_ioremap_resource(pdev, 0); -+ if (IS_ERR(base)) -+ return PTR_ERR(base); -+ -+ priv->regmap = devm_regmap_init(dev, NULL, base, -+ &meson_txc_hdmi_regmap_config); -+ if (IS_ERR(priv->regmap)) -+ return PTR_ERR(priv->regmap); -+ -+ priv->pclk = devm_clk_get(dev, "pclk"); -+ if (IS_ERR(priv->pclk)) { -+ ret = PTR_ERR(priv->pclk); -+ return dev_err_probe(dev, ret, "Failed to get the pclk\n"); -+ } -+ -+ priv->sys_clk = devm_clk_get(dev, "sys"); -+ if (IS_ERR(priv->sys_clk)) { -+ ret = PTR_ERR(priv->sys_clk); -+ return dev_err_probe(dev, ret, -+ "Failed to get the sys clock\n"); -+ } -+ -+ priv->phy = devm_phy_get(dev, "hdmi"); -+ if (IS_ERR(priv->phy)) { -+ ret = PTR_ERR(priv->phy); -+ return dev_err_probe(dev, ret, "Failed to get the HDMI PHY\n"); -+ } -+ -+ ret = meson_txc_hdmi_parse_dt(priv); -+ if (ret) -+ return ret; -+ -+ ret = clk_prepare_enable(priv->pclk); -+ if (ret) { -+ dev_err_probe(dev, ret, "Failed to enable the pclk\n"); -+ return ret; -+ } -+ -+ regval = readl(base + HDMI_CTRL_PORT); -+ regval |= HDMI_CTRL_PORT_APB3_ERR_EN; -+ writel(regval, base + HDMI_CTRL_PORT); -+ -+ ret = meson_txc_hdmi_hw_init(priv); -+ if (ret) -+ goto err_disable_clk; -+ -+ ret = meson_txc_hdmi_hdmi_codec_init(priv); -+ if (ret) -+ goto err_hw_exit; -+ -+ priv->bridge.driver_private = priv; -+ priv->bridge.funcs = &meson_txc_hdmi_bridge_funcs; -+ priv->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID; -+ priv->bridge.of_node = dev->of_node; -+ priv->bridge.interlace_allowed = true; -+ -+ drm_bridge_add(&priv->bridge); -+ -+ return 0; -+ -+err_hw_exit: -+ meson_txc_hdmi_hw_exit(priv); -+err_disable_clk: -+ clk_disable_unprepare(priv->pclk); -+ return ret; -+} -+ -+static void meson_txc_hdmi_unbind(struct device *dev, struct device *master, -+ void *data) -+{ -+ struct meson_txc_hdmi *priv = dev_get_drvdata(dev); -+ -+ platform_device_unregister(priv->hdmi_codec_pdev); -+ -+ drm_bridge_remove(&priv->bridge); -+ -+ meson_txc_hdmi_hw_exit(priv); -+ -+ clk_disable_unprepare(priv->pclk); -+} -+ -+static const struct component_ops meson_txc_hdmi_component_ops = { -+ .bind = meson_txc_hdmi_bind, -+ .unbind = meson_txc_hdmi_unbind, -+}; -+ -+static int meson_txc_hdmi_probe(struct platform_device *pdev) -+{ -+ return component_add(&pdev->dev, &meson_txc_hdmi_component_ops); -+} -+ -+static int meson_txc_hdmi_remove(struct platform_device *pdev) -+{ -+ component_del(&pdev->dev, &meson_txc_hdmi_component_ops); -+ -+ return 0; -+} -+ -+static const struct of_device_id meson_txc_hdmi_of_table[] = { -+ { .compatible = "amlogic,meson8-hdmi-tx" }, -+ { .compatible = "amlogic,meson8b-hdmi-tx" }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, meson_txc_hdmi_of_table); -+ -+static struct platform_driver meson_txc_hdmi_platform_driver = { -+ .probe = meson_txc_hdmi_probe, -+ .remove = meson_txc_hdmi_remove, -+ .driver = { -+ .name = "meson-transwitch-hdmi", -+ .of_match_table = meson_txc_hdmi_of_table, -+ }, -+}; -+module_platform_driver(meson_txc_hdmi_platform_driver); -+ -+MODULE_AUTHOR("Martin Blumenstingl "); -+MODULE_DESCRIPTION("Amlogic Meson8 and Meson8b TranSwitch HDMI 1.4 TX driver"); -+MODULE_LICENSE("GPL v2"); -diff --git a/drivers/gpu/drm/meson/meson_transwitch_hdmi.h b/drivers/gpu/drm/meson/meson_transwitch_hdmi.h -new file mode 100644 -index 00000000..14929475 ---- /dev/null -+++ b/drivers/gpu/drm/meson/meson_transwitch_hdmi.h -@@ -0,0 +1,536 @@ -+// SPDX-License-Identifier: GPL-2.0+ -+/* -+ * Copyright (C) 2021 Martin Blumenstingl -+ * -+ * All registers and magic values are taken from Amlogic's GPL kernel sources: -+ * Copyright (C) 2010 Amlogic, Inc. -+ */ -+ -+#include -+#include -+ -+#ifndef __MESON_TRANSWITCH_HDMI_H__ -+#define __MESON_TRANSWITCH_HDMI_H__ -+ -+/* HDMI TX register */ -+ -+// System config 0 -+#define TX_SYS0_AFE_SIGNAL 0x0000 -+#define TX_SYS0_AFE_LOOP 0x0001 -+#define TX_SYS0_ACR_CTS_0 0x0002 -+ #define TX_SYS0_ACR_CTS_0_AUDIO_CTS_BYTE0 GENMASK(7, 0) -+#define TX_SYS0_ACR_CTS_1 0x0003 -+ #define TX_SYS0_ACR_CTS_1_AUDIO_CTS_BYTE1 GENMASK(7, 0) -+#define TX_SYS0_ACR_CTS_2 0x0004 -+ #define TX_SYS0_ACR_CTS_2_FORCE_ARC_STABLE BIT(5) -+#define TX_SYS0_BIST_CONTROL 0x0005 -+ #define TX_SYS0_BIST_CONTROL_AFE_BIST_ENABLE BIT(7) -+ #define TX_SYS0_BIST_CONTROL_TMDS_SHIFT_PATTERN_SELECT BIT(6) -+ #define TX_SYS0_BIST_CONTROL_TMDS_PRBS_PATTERN_SELECT GENMASK(5, 4) -+ #define TX_SYS0_BIST_CONTROL_TMDS_REPEAT_BIST_PATTERN GENMASK(2, 0) -+ -+#define TX_SYS0_BIST_DATA_0 0x0006 -+#define TX_SYS0_BIST_DATA_1 0x0007 -+#define TX_SYS0_BIST_DATA_2 0x0008 -+#define TX_SYS0_BIST_DATA_3 0x0009 -+#define TX_SYS0_BIST_DATA_4 0x000A -+#define TX_SYS0_BIST_DATA_5 0x000B -+#define TX_SYS0_BIST_DATA_6 0x000C -+#define TX_SYS0_BIST_DATA_7 0x000D -+#define TX_SYS0_BIST_DATA_8 0x000E -+#define TX_SYS0_BIST_DATA_9 0x000F -+ -+// system config 1 -+#define TX_HDMI_PHY_CONFIG0 0x0010 -+ #define TX_HDMI_PHY_CONFIG0_HDMI_COMMON_B7_B0 GENMASK(7, 0) -+#define TX_HDMI_PHY_CONFIG1 0x0010 -+ #define TX_HDMI_PHY_CONFIG1_HDMI_COMMON_B11_B8 GENMASK(3, 0) -+ #define TX_HDMI_PHY_CONFIG1_HDMI_CTL_REG_B3_B0 GENMASK(7, 4) -+#define TX_HDMI_PHY_CONFIG2 0x0012 -+ #define TX_HDMI_PHY_CONFIG_HDMI_CTL_REG_B11_B4 GENMASK(7, 0) -+#define TX_HDMI_PHY_CONFIG3 0x0013 -+ #define TX_HDMI_PHY_CONFIG3_HDMI_L2H_CTL GENMASK(3, 0) -+ #define TX_HDMI_PHY_CONFIG3_HDMI_MDR_PU GENMASK(7, 4) -+#define TX_HDMI_PHY_CONFIG4 0x0014 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_LF_PD BIT(0) -+ #define TX_HDMI_PHY_CONFIG4_HDMI_PHY_CLK_EN BIT(1) -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE GENMASK(3, 2) -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_NORMAL 0x0 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_CLK_CH3_EQUAL_CH0 0x1 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_ALTERNATE_HIGH_LOW 0x2 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_ALTERNATE_LOW_HIGH 0x3 -+ #define TX_HDMI_PHY_CONFIG4_HDMI_PREM_CTL GENMASK(7, 4) -+#define TX_HDMI_PHY_CONFIG5 0x0015 -+ #define TX_HDMI_PHY_CONFIG5_HDMI_VCM_CTL GENMASK(7, 5) -+ #define TX_HDMI_PHY_CONFIG5_HDMI_PREFCTL GENMASK(2, 0) -+#define TX_HDMI_PHY_CONFIG6 0x0016 -+ #define TX_HDMI_PHY_CONFIG6_HDMI_RTERM_CTL GENMASK(3, 0) -+ #define TX_HDMI_PHY_CONFIG6_HDMI_SWING_CTL GENMASK(7, 4) -+#define TX_SYS1_AFE_TEST 0x0017 -+#define TX_SYS1_PLL 0x0018 -+#define TX_SYS1_TUNE 0x0019 -+#define TX_SYS1_AFE_CONNECT 0x001A -+ -+#define TX_SYS1_ACR_N_0 0x001C -+ #define TX_SYS1_ACR_N_0_N_BYTE0 GENMASK(7, 0) -+#define TX_SYS1_ACR_N_1 0x001D -+ #define TX_SYS1_ACR_N_1_N_BYTE1 GENMASK(7, 0) -+#define TX_SYS1_ACR_N_2 0x001E -+ #define TX_SYS1_ACR_N_2_N_MEAS_TOLERANCE GENMASK(7, 4) -+ #define TX_SYS1_ACR_N_2_N_UPPER_NIBBLE GENMASK(3, 0) -+#define TX_SYS1_PRBS_DATA 0x001F -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE GENMASK(1, 0) -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE_11 0x0 -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE_15 0x1 -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE_7 0x2 -+ #define TX_SYS1_PRBS_DATA_PRBS_MODE_31 0x3 -+ -+// HDCP CONFIG -+#define TX_HDCP_ECC_CONFIG 0x0024 -+#define TX_HDCP_CRC_CONFIG 0x0025 -+#define TX_HDCP_EDID_CONFIG 0x0026 -+ #define TX_HDCP_EDID_CONFIG_FORCED_SYS_TRIGGER BIT(7) -+ #define TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG BIT(6) -+ #define TX_HDCP_EDID_CONFIG_MEM_ACC_SEQ_MODE BIT(5) -+ #define TX_HDCP_EDID_CONFIG_MEM_ACC_SEQ_START BIT(4) -+ #define TX_HDCP_EDID_CONFIG_FORCED_MEM_COPY_DONE BIT(3) -+ #define TX_HDCP_EDID_CONFIG_MEM_COPY_DONE_CONFIG BIT(2) -+ #define TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG_SEMI_MANU BIT(1) -+ -+#define TX_HDCP_MEM_CONFIG 0x0027 -+ #define TX_HDCP_MEM_CONFIG_READ_DECRYPT BIT(3) -+ -+#define TX_HDCP_HPD_FILTER_L 0x0028 -+#define TX_HDCP_HPD_FILTER_H 0x0029 -+#define TX_HDCP_ENCRYPT_BYTE 0x002A -+#define TX_HDCP_CONFIG0 0x002B -+ #define TX_HDCP_CONFIG0_ROM_ENCRYPT_OFF GENMASK(4, 3) -+ -+#define TX_HDCP_CONFIG1 0x002C -+#define TX_HDCP_CONFIG2 0x002D -+#define TX_HDCP_CONFIG3 0x002E -+ #define TX_HDCP_CONFIG3_DDC_I2C_BUS_CLOCK_TIME_DIVIDER GENMASK(7, 0) -+ -+#define TX_HDCP_MODE 0x002F -+ #define TX_HDCP_MODE_CP_DESIRED BIT(7) -+ #define TX_HDCP_MODE_ESS_CONFIG BIT(6) -+ #define TX_HDCP_MODE_SET_AVMUTE BIT(5) -+ #define TX_HDCP_MODE_CLEAR_AVMUTE BIT(4) -+ #define TX_HDCP_MODE_HDCP_1_1 BIT(3) -+ #define TX_HDCP_MODE_VSYNC_HSYNC_FORCED_POLARITY_SELECT BIT(2) -+ #define TX_HDCP_MODE_FORCED_VSYNC_POLARITY BIT(1) -+ #define TX_HDCP_MODE_FORCED_HSYNC_POLARITY BIT(0) -+ -+// Video config, part 1 -+#define TX_VIDEO_ACTIVE_PIXELS_0 0x0030 -+#define TX_VIDEO_ACTIVE_PIXELS_1 0x0031 -+#define TX_VIDEO_FRONT_PIXELS 0x0032 -+#define TX_VIDEO_HSYNC_PIXELS 0x0033 -+#define TX_VIDEO_BACK_PIXELS 0x0034 -+#define TX_VIDEO_ACTIVE_LINES_0 0x0035 -+#define TX_VIDEO_ACTIVE_LINES_1 0x0036 -+#define TX_VIDEO_EOF_LINES 0x0037 -+#define TX_VIDEO_VSYNC_LINES 0x0038 -+#define TX_VIDEO_SOF_LINES 0x0039 -+#define TX_VIDEO_DTV_TIMING 0x003A -+ #define TX_VIDEO_DTV_TIMING_FORCE_DTV_TIMING_AUTO BIT(7) -+ #define TX_VIDEO_DTV_TIMING_FORCE_VIDEO_SCAN BIT(6) -+ #define TX_VIDEO_DTV_TIMING_FORCE_VIDEO_FIELD BIT(5) -+ #define TX_VIDEO_DTV_TIMING_DISABLE_VIC39_CORRECTION BIT(4) -+ -+#define TX_VIDEO_DTV_MODE 0x003B -+ #define TX_VIDEO_DTV_MODE_FORCED_DEFAULT_PHASE BIT(7) -+ #define TX_VIDEO_DTV_MODE_COLOR_DEPTH GENMASK(1, 0) -+ -+#define TX_VIDEO_DTV_FORMAT0 0x003C -+#define TX_VIDEO_DTV_FORMAT1 0x003D -+#define TX_VIDEO_PIXEL_PACK 0x003F -+// video config, part 2 -+#define TX_VIDEO_CSC_COEFF_B0 0x0040 -+#define TX_VIDEO_CSC_COEFF_B1 0x0041 -+#define TX_VIDEO_CSC_COEFF_R0 0x0042 -+#define TX_VIDEO_CSC_COEFF_R1 0x0043 -+#define TX_VIDEO_CSC_COEFF_CB0 0x0044 -+#define TX_VIDEO_CSC_COEFF_CB1 0x0045 -+#define TX_VIDEO_CSC_COEFF_CR0 0x0046 -+#define TX_VIDEO_CSC_COEFF_CR1 0x0047 -+#define TX_VIDEO_DTV_OPTION_L 0x0048 -+ #define TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_FORMAT GENMASK(7, 6) -+ #define TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_FORMAT GENMASK(5, 4) -+ #define TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_DEPTH GENMASK(3, 2) -+ #define TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_DEPTH GENMASK(1, 0) -+ -+#define TX_VIDEO_DTV_OPTION_H 0x0049 -+ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235 0x0 -+ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_240 0x1 -+ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_1_254 0x2 -+ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255 0x3 -+ #define TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE GENMASK(3, 2) -+ #define TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE GENMASK(1, 0) -+ -+#define TX_VIDEO_DTV_FILTER 0x004A -+#define TX_VIDEO_DTV_DITHER 0x004B -+#define TX_VIDEO_DTV_DEDITHER 0x004C -+#define TX_VIDEO_PROC_CONFIG0 0x004E -+#define TX_VIDEO_PROC_CONFIG1 0x004F -+ -+// Audio config -+#define TX_AUDIO_FORMAT 0x0058 -+ #define TX_AUDIO_FORMAT_SPDIF_OR_I2S BIT(7) -+ #define TX_AUDIO_FORMAT_I2S_2_OR_8_CH BIT(6) -+ #define TX_AUDIO_FORMAT_I2S_FORMAT GENMASK(5, 4) -+ #define TX_AUDIO_FORMAT_BIT_WIDTH_MASK GENMASK(3, 2) -+ #define TX_AUDIO_FORMAT_BIT_WIDTH_16 0x1 -+ #define TX_AUDIO_FORMAT_BIT_WIDTH_20 0x2 -+ #define TX_AUDIO_FORMAT_BIT_WIDTH_24 0x3 -+ #define TX_AUDIO_FORMAT_WS_POLARITY BIT(1) -+ #define TX_AUDIO_FORMAT_I2S_ONE_BIT_OR_I2S BIT(0) -+ #define TX_AUDIO_FORMAT_SPDIF_CHANNEL_STATUS_FROM_DATA_OR_REG BIT(0) -+ -+#define TX_AUDIO_SPDIF 0x0059 -+ #define TX_AUDIO_SPDIF_ENABLE BIT(0) -+#define TX_AUDIO_I2S 0x005A -+ #define TX_AUDIO_I2S_ENABLE BIT(0) -+#define TX_AUDIO_FIFO 0x005B -+ #define TX_AUDIO_FIFO_FIFO_DEPTH_MASK GENMASK(7, 4) -+ #define TX_AUDIO_FIFO_FIFO_DEPTH_512 0x4 -+ #define TX_AUDIO_FIFO_CRITICAL_THRESHOLD_MASK GENMASK(3, 2) -+ #define TX_AUDIO_FIFO_CRITICAL_THRESHOLD_DEPTH_DIV16 0x2 -+ #define TX_AUDIO_FIFO_NORMAL_THRESHOLD_MASK GENMASK(1, 0) -+ #define TX_AUDIO_FIFO_NORMAL_THRESHOLD_DEPTH_DIV8 0x1 -+#define TX_AUDIO_LIPSYNC 0x005C -+ #define TX_AUDIO_LIPSYNC_NORMALIZED_LIPSYNC_PARAM GENMASK(7, 0) -+#define TX_AUDIO_CONTROL 0x005D -+ #define TX_AUDIO_CONTROL_FORCED_AUDIO_FIFO_CLEAR BIT(7) -+ #define TX_AUDIO_CONTROL_AUTO_AUDIO_FIFO_CLEAR BIT(6) -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_MASK GENMASK(5, 4) -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_AUDIO_SAMPLE_PACKET 0x0 -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_ONE_BIT_AUDIO 0x1 -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_HBR_AUDIO_PACKET 0x2 -+ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_DST_AUDIO_PACKET 0x3 -+ #define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_VALID BIT(2) -+ #define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_USER BIT(1) -+ #define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_FLAT BIT(0) -+#define TX_AUDIO_HEADER 0x005E -+ #define TX_AUDIO_HEADER_AUDIO_SAMPLE_PACKET_HEADER_LAYOUT1 BIT(7) -+ #define TX_AUDIO_HEADER_SET_NORMAL_DOUBLE_IN_DST_PACKET_HEADER BIT(6) -+#define TX_AUDIO_SAMPLE 0x005F -+ #define TX_AUDIO_SAMPLE_CHANNEL_VALID GENMASK(7, 0) -+#define TX_AUDIO_VALID 0x0060 -+#define TX_AUDIO_USER 0x0061 -+#define TX_AUDIO_PACK 0x0062 -+ #define TX_AUDIO_PACK_AUDIO_SAMPLE_PACKETS_ENABLE BIT(0) -+#define TX_AUDIO_CONTROL_MORE 0x0064 -+ #define TX_AUDIO_CONTROL_MORE_ENABLE BIT(0) -+ -+// tmds config -+#define TX_TMDS_MODE 0x0068 -+ #define TX_TMDS_MODE_FORCED_HDMI BIT(7) -+ #define TX_TMDS_MODE_HDMI_CONFIG BIT(6) -+ #define TX_TMDS_MODE_BIT_SWAP BIT(3) -+ #define TX_TMDS_MODE_CHANNEL_SWAP GENMASK(2, 0) -+ -+#define TX_TMDS_CONFIG0 0x006C -+#define TX_TMDS_CONFIG1 0x006D -+ -+// packet config -+#define TX_PACKET_ALLOC_ACTIVE_1 0x0078 -+#define TX_PACKET_ALLOC_ACTIVE_2 0x0079 -+#define TX_PACKET_ALLOC_EOF_1 0x007A -+#define TX_PACKET_ALLOC_EOF_2 0x007B -+#define TX_PACKET_ALLOC_SOF_1 0x007C -+#define TX_PACKET_ALLOC_SOF_2 0x007D -+#define TX_PACKET_CONTROL_1 0x007E -+ #define TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING BIT(7) -+ #define TX_PACKET_CONTROL_1_PACKET_ALLOC_MODE BIT(6) -+ #define TX_PACKET_CONTROL_1_PACKET_START_LATENCY GENMASK(5, 0) -+ -+#define TX_PACKET_CONTROL_2 0x007F -+ #define TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE BIT(3) -+ #define TX_PACKET_CONTROL_2_HORIZONTAL_GC_PACKET_TRANSPORT_EN BIT(1) -+ -+#define TX_CORE_EDID_CONFIG_MORE 0x0080 -+ #define TX_CORE_EDID_CONFIG_MORE_KEEP_EDID_ERROR BIT(1) -+ #define TX_CORE_EDID_CONFIG_MORE_SYS_TRIGGER_CONFIG_SEMI_MANU BIT(0) -+ -+#define TX_CORE_ALLOC_VSYNC_0 0x0081 -+#define TX_CORE_ALLOC_VSYNC_1 0x0082 -+#define TX_CORE_ALLOC_VSYNC_2 0x0083 -+#define TX_MEM_PD_REG0 0x0084 -+ -+// core config -+#define TX_CORE_DATA_CAPTURE_1 0x00F0 -+#define TX_CORE_DATA_CAPTURE_2 0x00F1 -+ #define TX_CORE_DATA_CAPTURE_2_AUDIO_SOURCE_SELECT GENMASK(7, 6) -+ #define TX_CORE_DATA_CAPTURE_2_EXTERNAL_PACKET_ENABLE BIT(5) -+ #define TX_CORE_DATA_CAPTURE_2_INTERNAL_PACKET_ENABLE BIT(4) -+ #define TX_CORE_DATA_CAPTURE_2_AFE_FIFO_SRC_LANE1 GENMASK(3, 2) -+ #define TX_CORE_DATA_CAPTURE_2_AFE_FIFO_SRC_LANE0 GENMASK(1, 0) -+ -+#define TX_CORE_DATA_MONITOR_1 0x00F2 -+ #define TX_CORE_DATA_MONITOR_1_LANE1 BIT(7) -+ #define TX_CORE_DATA_MONITOR_1_SELECT_LANE1 GENMASK(6, 4) -+ #define TX_CORE_DATA_MONITOR_1_LANE0 BIT(3) -+ #define TX_CORE_DATA_MONITOR_1_SELECT_LANE0 GENMASK(2, 0) -+ -+#define TX_CORE_DATA_MONITOR_2 0x00F3 -+ #define TX_CORE_DATA_MONITOR_2_MONITOR_SELECT GENMASK(2, 0) -+ -+#define TX_CORE_CALIB_MODE 0x00F4 -+#define TX_CORE_CALIB_SAMPLE_DELAY 0x00F5 -+#define TX_CORE_CALIB_VALUE_AUTO 0x00F6 -+#define TX_CORE_CALIB_VALUE 0x00F7 -+ -+// system config 4 -+#define TX_SYS4_TX_CKI_DDR 0x00A0 -+#define TX_SYS4_TX_CKO_DDR 0x00A1 -+#define TX_SYS4_RX_CKI_DDR 0x00A2 -+#define TX_SYS4_RX_CKO_DDR 0x00A3 -+#define TX_SYS4_CONNECT_SEL_0 0x00A4 -+#define TX_SYS4_CONNECT_SEL_1 0x00A5 -+ #define TX_SYS4_CONNECT_SEL_1_TX_CONNECT_SEL_UPPER_CHANNEL_DATA BIT(6) -+ -+#define TX_SYS4_CONNECT_SEL_2 0x00A6 -+#define TX_SYS4_CONNECT_SEL_3 0x00A7 -+#define TX_SYS4_CK_INV_VIDEO 0x00A8 -+ #define TX_SYS4_CK_INV_VIDEO_TMDS_CLK_PATTERN BIT(4) -+#define TX_SYS4_CK_INV_AUDIO 0x00A9 -+#define TX_SYS4_CK_INV_AFE 0x00AA -+#define TX_SYS4_CK_INV_CH01 0x00AB -+#define TX_SYS4_CK_INV_CH2 0x00AC -+#define TX_SYS4_CK_CEC 0x00AD -+#define TX_SYS4_CK_SOURCE_1 0x00AE -+#define TX_SYS4_CK_SOURCE_2 0x00AF -+ -+#define TX_IEC60958_SUB1_OFFSET 0x00B0 -+#define TX_IEC60958_SUB2_OFFSET 0x00C8 -+ -+// system config 5 -+#define TX_SYS5_TX_SOFT_RESET_1 0x00E0 -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN BIT(7) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN BIT(6) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN BIT(5) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN BIT(4) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN BIT(3) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2 BIT(2) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1 BIT(1) -+ #define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0 BIT(0) -+ -+#define TX_SYS5_TX_SOFT_RESET_2 0x00E1 -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN BIT(7) -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN BIT(6) -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN BIT(5) -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN BIT(4) -+ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST BIT(3) -+ #define TX_SYS5_TX_SOFT_RESET_2_TX_DDC_HDCP_RSTN BIT(2) -+ #define TX_SYS5_TX_SOFT_RESET_2_TX_DDC_EDID_RSTN BIT(1) -+ #define TX_SYS5_TX_SOFT_RESET_2_TX_DIG_RESET_N_CH3 BIT(0) -+ -+#define TX_SYS5_RX_SOFT_RESET_1 0x00E2 -+#define TX_SYS5_RX_SOFT_RESET_2 0x00E3 -+#define TX_SYS5_RX_SOFT_RESET_3 0x00E4 -+#define TX_SYS5_SSTL_BIDIR_IN 0x00E5 -+#define TX_SYS5_SSTL_IN 0x00E6 -+#define TX_SYS5_SSTL_DIFF_IN 0x00E7 -+#define TX_SYS5_FIFO_CONFIG 0x00E8 -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_BYPASS BIT(6) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_BYPASS BIT(5) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_BYPASS BIT(4) -+ #define TX_SYS5_FIFO_CONFIG_CLK_CHANNEL3_OUTPUT_ENABLE BIT(3) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_ENABLE BIT(2) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_ENABLE BIT(1) -+ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_ENABLE BIT(0) -+ -+#define TX_SYS5_FIFO_SAMP01_CFG 0x00E9 -+#define TX_SYS5_FIFO_SAMP23_CFG 0x00EA -+#define TX_SYS5_CONNECT_FIFO_CFG 0x00EB -+#define TX_SYS5_IO_CALIB_CONTROL 0x00EC -+#define TX_SYS5_SSTL_BIDIR_OUT 0x00ED -+#define TX_SYS5_SSTL_OUT 0x00EE -+#define TX_SYS5_SSTL_DIFF_OUT 0x00EF -+ -+// HDCP shadow register -+#define TX_HDCP_SHW_BKSV_0 0x0100 -+#define TX_HDCP_SHW_BKSV_1 0x0101 -+#define TX_HDCP_SHW_BKSV_2 0x0102 -+#define TX_HDCP_SHW_BKSV_3 0x0103 -+#define TX_HDCP_SHW_BKSV_4 0x0104 -+#define TX_HDCP_SHW_RI1_0 0x0108 -+#define TX_HDCP_SHW_RI1_1 0x0109 -+#define TX_HDCP_SHW_PJ1 0x010A -+#define TX_HDCP_SHW_AKSV_0 0x0110 -+#define TX_HDCP_SHW_AKSV_1 0x0111 -+#define TX_HDCP_SHW_AKSV_2 0x0112 -+#define TX_HDCP_SHW_AKSV_3 0x0113 -+#define TX_HDCP_SHW_AKSV_4 0x0114 -+#define TX_HDCP_SHW_AINFO 0x0115 -+#define TX_HDCP_SHW_AN_0 0x0118 -+#define TX_HDCP_SHW_AN_1 0x0119 -+#define TX_HDCP_SHW_AN_2 0x011A -+#define TX_HDCP_SHW_AN_3 0x011B -+#define TX_HDCP_SHW_AN_4 0x011C -+#define TX_HDCP_SHW_AN_5 0x011D -+#define TX_HDCP_SHW_AN_6 0x011E -+#define TX_HDCP_SHW_AN_7 0x011F -+#define TX_HDCP_SHW_V1_H0_0 0x0120 -+#define TX_HDCP_SHW_V1_H0_1 0x0121 -+#define TX_HDCP_SHW_V1_H0_2 0x0122 -+#define TX_HDCP_SHW_V1_H0_3 0x0123 -+#define TX_HDCP_SHW_V1_H1_0 0x0124 -+#define TX_HDCP_SHW_V1_H1_1 0x0125 -+#define TX_HDCP_SHW_V1_H1_2 0x0126 -+#define TX_HDCP_SHW_V1_H1_3 0x0127 -+#define TX_HDCP_SHW_V1_H2_0 0x0128 -+#define TX_HDCP_SHW_V1_H2_1 0x0129 -+#define TX_HDCP_SHW_V1_H2_2 0x012A -+#define TX_HDCP_SHW_V1_H2_3 0x012B -+#define TX_HDCP_SHW_V1_H3_0 0x012C -+#define TX_HDCP_SHW_V1_H3_1 0x012D -+#define TX_HDCP_SHW_V1_H3_2 0x012E -+#define TX_HDCP_SHW_V1_H3_3 0x012F -+#define TX_HDCP_SHW_V1_H4_0 0x0130 -+#define TX_HDCP_SHW_V1_H4_1 0x0131 -+#define TX_HDCP_SHW_V1_H4_2 0x0132 -+#define TX_HDCP_SHW_V1_H4_3 0x0133 -+#define TX_HDCP_SHW_BCAPS 0x0140 -+#define TX_HDCP_SHW_BSTATUS_0 0x0141 -+#define TX_HDCP_SHW_BSTATUS_1 0x0142 -+#define TX_HDCP_SHW_KSV_FIFO 0x0143 -+ -+// system status 0 -+#define TX_SYSST0_CONNECT_FIFO 0x0180 -+#define TX_SYSST0_PLL_MONITOR 0x0181 -+#define TX_SYSST0_AFE_FIFO 0x0182 -+#define TX_SYSST0_ROM_STATUS 0x018F -+ -+// hdcp status -+#define TX_HDCP_ST_AUTHENTICATION 0x0190 -+#define TX_HDCP_ST_FRAME_COUNT 0x0191 -+#define TX_HDCP_ST_STATUS_0 0x0192 -+#define TX_HDCP_ST_STATUS_1 0x0193 -+#define TX_HDCP_ST_STATUS_2 0x0194 -+#define TX_HDCP_ST_STATUS_3 0x0195 -+#define TX_HDCP_ST_EDID_STATUS 0x0196 -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS GENMASK(7, 6) -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_NO_SINK_ATTACHED 0x0 -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_READING_EDID 0x1 -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_DVI_MODE 0x2 -+ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_HDMI_MODE 0x3 -+ #define TX_HDCP_ST_EDID_STATUS_EDID_DATA_READY BIT(4) -+ #define TX_HDCP_ST_EDID_STATUS_HPD_STATUS BIT(1) -+ -+#define TX_HDCP_ST_MEM_STATUS 0x0197 -+#define TX_HDCP_ST_ST_MODE 0x019F -+ -+// video status -+#define TX_VIDEO_ST_ACTIVE_PIXELS_1 0x01A0 -+#define TX_VIDEO_ST_ACTIVE_PIXELS_2 0x01A1 -+#define TX_VIDEO_ST_FRONT_PIXELS 0x01A2 -+#define TX_VIDEO_ST_HSYNC_PIXELS 0x01A3 -+#define TX_VIDEO_ST_BACK_PIXELS 0x01A4 -+#define TX_VIDEO_ST_ACTIVE_LINES_1 0x01A5 -+#define TX_VIDEO_ST_ACTIVE_LINES_2 0x01A6 -+#define TX_VIDEO_ST_EOF_LINES 0x01A7 -+#define TX_VIDEO_ST_VSYNC_LINES 0x01A8 -+#define TX_VIDEO_ST_SOF_LINES 0x01A9 -+#define TX_VIDEO_ST_DTV_TIMING 0x01AA -+#define TX_VIDEO_ST_DTV_MODE 0x01AB -+// audio status -+#define TX_VIDEO_ST_AUDIO_STATUS 0x01AC -+#define TX_AFE_STATUS_0 0x01AE -+#define TX_AFE_STATUS_1 0x01AF -+ -+#define TX_IEC60958_ST_SUB1_OFFSET 0x01B0 -+#define TX_IEC60958_ST_SUB2_OFFSET 0x01C8 -+ -+// system status 1 -+#define TX_SYSST1_CALIB_BIT_RESULT_0 0x01E0 -+#define TX_SYSST1_CALIB_BIT_RESULT_1 0x01E1 -+//HDMI_STATUS_OUT[7:0] -+#define TX_HDMI_PHY_READBACK_0 0x01E2 -+//HDMI_COMP_OUT[4] -+//HDMI_STATUS_OUT[11:8] -+#define TX_HDMI_PHY_READBACK_1 0x01E3 -+#define TX_SYSST1_CALIB_BIT_RESULT_4 0x01E4 -+#define TX_SYSST1_CALIB_BIT_RESULT_5 0x01E5 -+#define TX_SYSST1_CALIB_BIT_RESULT_6 0x01E6 -+#define TX_SYSST1_CALIB_BIT_RESULT_7 0x01E7 -+#define TX_SYSST1_CALIB_BUS_RESULT_0 0x01E8 -+#define TX_SYSST1_CALIB_BUS_RESULT_1 0x01E9 -+#define TX_SYSST1_CALIB_BUS_RESULT_2 0x01EA -+#define TX_SYSST1_CALIB_BUS_RESULT_3 0x01EB -+#define TX_SYSST1_CALIB_BUS_RESULT_4 0x01EC -+#define TX_SYSST1_CALIB_BUS_RESULT_5 0x01ED -+#define TX_SYSST1_CALIB_BUS_RESULT_6 0x01EE -+#define TX_SYSST1_CALIB_BUS_RESULT_7 0x01EF -+ -+// Packet status -+#define TX_PACKET_ST_REQUEST_STATUS_1 0x01F0 -+#define TX_PACKET_ST_REQUEST_STATUS_2 0x01F1 -+#define TX_PACKET_ST_REQUEST_MISSED_1 0x01F2 -+#define TX_PACKET_ST_REQUEST_MISSED_2 0x01F3 -+#define TX_PACKET_ST_ENCODE_STATUS_0 0x01F4 -+#define TX_PACKET_ST_ENCODE_STATUS_1 0x01F5 -+#define TX_PACKET_ST_ENCODE_STATUS_2 0x01F6 -+#define TX_PACKET_ST_TIMER_STATUS 0x01F7 -+ -+// tmds status -+#define TX_TMDS_ST_CLOCK_METER_1 0x01F8 -+#define TX_TMDS_ST_CLOCK_METER_2 0x01F9 -+#define TX_TMDS_ST_CLOCK_METER_3 0x01FA -+#define TX_TMDS_ST_TMDS_STATUS_1 0x01FC -+#define TX_TMDS_ST_TMDS_STATUS_2 0x01FD -+#define TX_TMDS_ST_TMDS_STATUS_3 0x01FE -+#define TX_TMDS_ST_TMDS_STATUS_4 0x01FF -+ -+// Packet register -+#define TX_PKT_REG_SPD_INFO_BASE_ADDR 0x0200 -+#define TX_PKT_REG_VEND_INFO_BASE_ADDR 0x0220 -+#define TX_PKT_REG_MPEG_INFO_BASE_ADDR 0x0240 -+#define TX_PKT_REG_AVI_INFO_BASE_ADDR 0x0260 -+#define TX_PKT_REG_AUDIO_INFO_BASE_ADDR 0x0280 -+#define TX_PKT_REG_ACP_INFO_BASE_ADDR 0x02A0 -+#define TX_PKT_REG_ISRC1_BASE_ADDR 0x02C0 -+#define TX_PKT_REG_ISRC2_BASE_ADDR 0x02E0 -+#define TX_PKT_REG_EXCEPT0_BASE_ADDR 0x0300 -+#define TX_PKT_REG_EXCEPT1_BASE_ADDR 0x0320 -+#define TX_PKT_REG_EXCEPT2_BASE_ADDR 0x0340 -+#define TX_PKT_REG_EXCEPT3_BASE_ADDR 0x0360 -+#define TX_PKT_REG_EXCEPT4_BASE_ADDR 0x0380 -+#define TX_PKT_REG_GAMUT_P0_BASE_ADDR 0x03A0 -+#define TX_PKT_REG_GAMUT_P1_1_BASE_ADDR 0x03C0 -+#define TX_PKT_REG_GAMUT_P1_2_BASE_ADDR 0x03E0 -+ -+#define TX_RX_EDID_OFFSET 0x0600 -+ -+/* HDMI OTHER registers */ -+ -+#define HDMI_OTHER_CTRL0 0x8000 -+#define HDMI_OTHER_CTRL1 0x8001 -+ #define HDMI_OTHER_CTRL1_POWER_ON BIT(15) -+ #define HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON BIT(13) -+ -+#define HDMI_OTHER_STATUS0 0x8002 -+#define HDMI_OTHER_CTRL2 0x8003 -+#define HDMI_OTHER_INTR_MASKN 0x8004 -+ #define HDMI_OTHER_INTR_MASKN_TX_EDID_INT_RISE BIT(2) -+ #define HDMI_OTHER_INTR_MASKN_TX_HPD_INT_FALL BIT(1) -+ #define HDMI_OTHER_INTR_MASKN_TX_HPD_INT_RISE BIT(0) -+ -+#define HDMI_OTHER_INTR_STAT 0x8005 -+ #define HDMI_OTHER_INTR_STAT_EDID_RISING BIT(2) -+ #define HDMI_OTHER_INTR_STAT_HPD_FALLING BIT(1) -+ #define HDMI_OTHER_INTR_STAT_HPD_RISING BIT(0) -+ -+#define HDMI_OTHER_INTR_STAT_CLR 0x8006 -+ #define HDMI_OTHER_INTR_STAT_CLR_EDID_RISING BIT(2) -+ #define HDMI_OTHER_INTR_STAT_CLR_HPD_FALLING BIT(1) -+ #define HDMI_OTHER_INTR_STAT_CLR_HPD_RISING BIT(0) -+ -+#define HDMI_OTHER_AVI_INTR_MASKN0 0x8008 -+#define HDMI_OTHER_AVI_INTR_MASKN1 0x8009 -+#define HDMI_OTHER_RX_AINFO_INTR_MASKN0 0x800a -+#define HDMI_OTHER_RX_AINFO_INTR_MASKN1 0x800b -+#define HDMI_OTHER_RX_PACKET_INTR_CLR 0x800c -+ -+#endif /* __MESON_TRANSWITCH_HDMI_H__ */ -diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c -index 2a82119e..a2c1bf1a 100644 ---- a/drivers/gpu/drm/meson/meson_vclk.c -+++ b/drivers/gpu/drm/meson/meson_vclk.c -@@ -732,6 +732,11 @@ meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq) - return MODE_CLOCK_HIGH; - } - -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) -+ return MODE_OK; -+ - if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od)) - return MODE_OK; - -@@ -784,6 +789,11 @@ meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_freq, - return MODE_CLOCK_HIGH; - } - -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) -+ return MODE_OK; -+ - for (i = 0 ; params[i].pixel_freq ; ++i) { - DRM_DEBUG_DRIVER("i = %d pixel_freq = %d alt = %d\n", - i, params[i].pixel_freq, -@@ -1024,6 +1034,128 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq, - regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN); - } - -+static int meson_vclk_set_rate_exclusive(struct meson_drm *priv, -+ enum vpu_bulk_clk_id clk_id, -+ unsigned int rate_khz) -+{ -+ struct clk *clk = priv->vid_clks[clk_id].clk; -+ int ret; -+ -+ ret = clk_set_rate_exclusive(clk, rate_khz * 1000UL); -+ if (ret) -+ return ret; -+ -+ priv->vid_clk_rate_exclusive[clk_id] = true; -+ -+ return 0; -+} -+ -+static void meson_vclk_disable_ccf(struct meson_drm *priv) -+{ -+ unsigned int i; -+ -+ /* allow all clocks to be changed in _enable again */ -+ for (i = 0; i < VPU_VID_CLK_NUM; i++) { -+ if (!priv->vid_clk_rate_exclusive[i]) -+ continue; -+ -+ clk_rate_exclusive_put(priv->vid_clks[i].clk); -+ priv->vid_clk_rate_exclusive[i] = false; -+ } -+ -+ if (priv->clk_dac_enabled) { -+ clk_disable(priv->clk_dac); -+ priv->clk_dac_enabled = false; -+ } -+ -+ if (priv->clk_venc_enabled) { -+ clk_disable(priv->clk_venc); -+ priv->clk_venc_enabled = false; -+ } -+} -+ -+static int meson_vclk_enable_ccf(struct meson_drm *priv, unsigned int target, -+ bool hdmi_use_enci, unsigned int phy_freq, -+ unsigned int dac_freq, unsigned int venc_freq) -+{ -+ enum vpu_bulk_clk_id venc_clk_id, dac_clk_id; -+ int ret; -+ -+ if (target == MESON_VCLK_TARGET_CVBS || hdmi_use_enci) -+ venc_clk_id = VPU_VID_CLK_CTS_ENCI; -+ else -+ venc_clk_id = VPU_VID_CLK_CTS_ENCP; -+ -+ if (target == MESON_VCLK_TARGET_CVBS) -+ dac_clk_id = VPU_VID_CLK_CTS_VDAC0; -+ else -+ dac_clk_id = VPU_VID_CLK_HDMI_TX_PIXEL; -+ -+ /* -+ * The TMDS clock also updates the PLL. Protect the PLL rate so all -+ * following clocks are derived from the PLL setting which matches the -+ * TMDS clock. -+ */ -+ ret = meson_vclk_set_rate_exclusive(priv, VPU_VID_CLK_TMDS, phy_freq); -+ if (ret) { -+ dev_err(priv->dev, "Failed to set TMDS clock to %ukHz: %d\n", -+ phy_freq, ret); -+ goto out_enable_clocks; -+ } -+ -+ /* -+ * The DAC clock may be derived from a parent of the VENC clock so we -+ * must protect the VENC clock from changing it's rate. This works -+ * because the DAC freq can be divided by the VENC clock. -+ */ -+ ret = meson_vclk_set_rate_exclusive(priv, venc_clk_id, venc_freq); -+ if (ret) { -+ dev_warn(priv->dev, -+ "Failed to set VENC clock to %ukHz while TMDS clock is %ukHz: %d\n", -+ venc_freq, phy_freq, ret); -+ goto out_enable_clocks; -+ } -+ -+ priv->clk_venc = priv->vid_clks[venc_clk_id].clk; -+ -+ /* -+ * after changing any of the VID_PLL_* clocks (which can happen when -+ * update the VENC clock rate) we need to assert and then de-assert the -+ * VID_DIVIDER_CNTL_* reset lines. -+ */ -+ reset_control_bulk_assert(VPU_RESET_VID_PLL_NUM, priv->vid_pll_resets); -+ reset_control_bulk_deassert(VPU_RESET_VID_PLL_NUM, priv->vid_pll_resets); -+ -+ ret = meson_vclk_set_rate_exclusive(priv, dac_clk_id, dac_freq); -+ if (ret) { -+ dev_warn(priv->dev, -+ "Failed to set pixel clock to %ukHz while TMDS clock is %ukHz: %d\n", -+ dac_freq, phy_freq, ret); -+ goto out_enable_clocks; -+ } -+ -+ priv->clk_dac = priv->vid_clks[dac_clk_id].clk; -+ -+out_enable_clocks: -+ ret = clk_enable(priv->clk_venc); -+ if (ret) -+ dev_err(priv->dev, -+ "Failed to re-enable the VENC clock at %ukHz: %d\n", -+ venc_freq, ret); -+ else -+ priv->clk_venc_enabled = true; -+ -+ ret = clk_enable(priv->clk_dac); -+ if (ret) -+ dev_err(priv->dev, -+ "Failed to re-enable the pixel clock at %ukHz: %d\n", -+ dac_freq, ret); -+ else -+ priv->clk_dac_enabled = true; -+ -+ return ret; -+} -+ - void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int phy_freq, unsigned int vclk_freq, - unsigned int venc_freq, unsigned int dac_freq, -@@ -1034,6 +1166,20 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, - unsigned int hdmi_tx_div; - unsigned int venc_div; - -+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || -+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ /* CVBS video clocks are generated off a 1296MHz base clock */ -+ if (target == MESON_VCLK_TARGET_CVBS) -+ phy_freq = 1296000; -+ -+ dev_err(priv->dev, "%s(target: %u, phy: %u, dac: %u, venc: %u, hdmi_use_enci: %u)\n", __func__, target, phy_freq, dac_freq, venc_freq, hdmi_use_enci); -+ meson_vclk_disable_ccf(priv); -+ meson_vclk_enable_ccf(priv, target, hdmi_use_enci, phy_freq, -+ dac_freq, venc_freq); -+ return; -+ } -+ - if (target == MESON_VCLK_TARGET_CVBS) { - meson_venci_cvbs_clock_config(priv); - return; -diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c -index 3bf0d6e4..d834359c 100644 ---- a/drivers/gpu/drm/meson/meson_venc.c -+++ b/drivers/gpu/drm/meson/meson_venc.c -@@ -62,10 +62,6 @@ - - /* HHI Registers */ - #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ --#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ --#define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbb offset in data sheet */ --#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ --#define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbc offset in data sheet */ - #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */ - - struct meson_cvbs_enci_mode meson_cvbs_enci_pal = { -@@ -1957,31 +1953,47 @@ void meson_venc_enable_vsync(struct meson_drm *priv) - writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN, - priv->io_base + _REG(VENC_INTCTRL)); - } -- regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); -+ -+ if (priv->intr_clks[0].clk) { -+ if (!priv->intr_clks_enabled) { -+ int ret; -+ -+ ret = clk_bulk_enable(priv->num_intr_clks, -+ priv->intr_clks); -+ if (ret) -+ dev_err(priv->dev, -+ "Failed to enable the interrupt clocks\n"); -+ else -+ priv->intr_clks_enabled = true; -+ } -+ } else { -+ regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); -+ } - } - - void meson_venc_disable_vsync(struct meson_drm *priv) - { -- regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0); -+ if (priv->intr_clks[0].clk) { -+ if (priv->intr_clks_enabled) { -+ clk_bulk_disable(priv->num_intr_clks, -+ priv->intr_clks); -+ priv->intr_clks_enabled = false; -+ } -+ } else { -+ regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0); -+ } -+ - writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL)); - } - - void meson_venc_init(struct meson_drm *priv) - { -- /* Disable CVBS VDAC */ -- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { -- regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 8); -- } else { -- regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); -- regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); -- } -- - /* Power Down Dacs */ - writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING)); - - /* Disable HDMI PHY */ -- regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); -+ if (priv->hhi) -+ regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); - - /* Disable HDMI */ - writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI | -diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c -index cd399b0b..bdfa342c 100644 ---- a/drivers/gpu/drm/meson/meson_viu.c -+++ b/drivers/gpu/drm/meson/meson_viu.c -@@ -448,13 +448,17 @@ void meson_viu_init(struct meson_drm *priv) - writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); - writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT)); - -- /* Set OSD alpha replace value */ -- writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, -- 0xff << OSD_REPLACE_SHIFT, -- priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); -- writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, -- 0xff << OSD_REPLACE_SHIFT, -- priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); -+ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && -+ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { -+ /* Set OSD alpha replace value */ -+ writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, -+ 0xff << OSD_REPLACE_SHIFT, -+ priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); -+ writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, -+ 0xff << OSD_REPLACE_SHIFT, -+ priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); -+ } - - /* Disable VD1 AFBC */ - /* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 and afbc vd1 set=0*/ -diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig -index ce7ba3eb..671435b6 100644 ---- a/drivers/phy/amlogic/Kconfig -+++ b/drivers/phy/amlogic/Kconfig -@@ -25,6 +25,16 @@ config PHY_MESON8B_USB2 - Meson8b and GXBB SoCs. - If unsure, say N. - -+config PHY_MESON_CVBS_DAC -+ tristate "Amlogic Meson CVBS DAC PHY driver" -+ depends on ARCH_MESON || COMPILE_TEST -+ depends on OF -+ select MFD_SYSCON -+ help -+ Enable this to support the CVBS DAC (PHY) found in Amlogic -+ Meson SoCs. -+ If unsure, say N. -+ - config PHY_MESON_GXL_USB2 - tristate "Meson GXL and GXM USB2 PHY drivers" - default ARCH_MESON -diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile -index 91e3b979..f6c38f73 100644 ---- a/drivers/phy/amlogic/Makefile -+++ b/drivers/phy/amlogic/Makefile -@@ -1,6 +1,7 @@ - # SPDX-License-Identifier: GPL-2.0-only - obj-$(CONFIG_PHY_MESON8_HDMI_TX) += phy-meson8-hdmi-tx.o - obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o -+obj-$(CONFIG_PHY_MESON_CVBS_DAC) += phy-meson-cvbs-dac.o - obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o - obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o - obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o -diff --git a/drivers/phy/amlogic/phy-meson-cvbs-dac.c b/drivers/phy/amlogic/phy-meson-cvbs-dac.c -new file mode 100644 -index 00000000..96549e63 ---- /dev/null -+++ b/drivers/phy/amlogic/phy-meson-cvbs-dac.c -@@ -0,0 +1,375 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Copyright (C) 2016 BayLibre, SAS -+ * Copyright (C) 2021 Martin Blumenstingl -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+#include -+ -+#define HHI_VDAC_CNTL0_MESON8 0x2F4 /* 0xbd offset in data sheet */ -+#define HHI_VDAC_CNTL1_MESON8 0x2F8 /* 0xbe offset in data sheet */ -+ -+#define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbd offset in data sheet */ -+#define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */ -+ -+enum phy_meson_cvbs_dac_reg { -+ MESON_CDAC_CTRL_RESV1, -+ MESON_CDAC_CTRL_RESV2, -+ MESON_CDAC_VREF_ADJ, -+ MESON_CDAC_RL_ADJ, -+ MESON_CDAC_CLK_PHASE_SEL, -+ MESON_CDAC_DRIVER_ADJ, -+ MESON_CDAC_EXT_VREF_EN, -+ MESON_CDAC_BIAS_C, -+ MESON_VDAC_CNTL0_RESERVED, -+ MESON_CDAC_GSW, -+ MESON_CDAC_PWD, -+ MESON_VDAC_CNTL1_RESERVED, -+ MESON_CVBS_DAC_NUM_REGS -+}; -+ -+struct phy_meson_cvbs_dac_data { -+ const struct reg_field *reg_fields; -+ u8 cdac_ctrl_resv2_enable_val; -+ u8 cdac_vref_adj_enable_val; -+ u8 cdac_rl_adj_enable_val; -+ bool disable_ignore_cdac_pwd; -+ bool needs_cvbs_trimming_nvmem_cell; -+}; -+ -+struct phy_meson_cvbs_dac_priv { -+ struct regmap_field *regs[MESON_CVBS_DAC_NUM_REGS]; -+ const struct phy_meson_cvbs_dac_data *data; -+ u8 cdac_gsw_enable_val; -+}; -+ -+static const struct reg_field phy_meson8_cvbs_dac_reg_fields[] = { -+ [MESON_CDAC_CTRL_RESV1] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 0, 7), -+ [MESON_CDAC_CTRL_RESV2] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 8, 15), -+ [MESON_CDAC_VREF_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 16, 20), -+ [MESON_CDAC_RL_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 21, 23), -+ [MESON_CDAC_CLK_PHASE_SEL] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 24, 24), -+ [MESON_CDAC_DRIVER_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 25, 25), -+ [MESON_CDAC_EXT_VREF_EN] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 26, 26), -+ [MESON_CDAC_BIAS_C] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 27, 27), -+ [MESON_VDAC_CNTL0_RESERVED] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 28, 31), -+ [MESON_CDAC_GSW] = REG_FIELD(HHI_VDAC_CNTL1_MESON8, 0, 2), -+ [MESON_CDAC_PWD] = REG_FIELD(HHI_VDAC_CNTL1_MESON8, 3, 3), -+ [MESON_VDAC_CNTL1_RESERVED] = REG_FIELD(HHI_VDAC_CNTL1_MESON8, 4, 31), -+}; -+ -+static const struct reg_field phy_meson_g12a_cvbs_dac_reg_fields[] = { -+ [MESON_CDAC_CTRL_RESV1] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 0, 7), -+ [MESON_CDAC_CTRL_RESV2] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 8, 15), -+ [MESON_CDAC_VREF_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 16, 20), -+ [MESON_CDAC_RL_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 21, 23), -+ [MESON_CDAC_CLK_PHASE_SEL] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 24, 24), -+ [MESON_CDAC_DRIVER_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 25, 25), -+ [MESON_CDAC_EXT_VREF_EN] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 26, 26), -+ [MESON_CDAC_BIAS_C] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 27, 27), -+ [MESON_VDAC_CNTL0_RESERVED] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 28, 31), -+ [MESON_CDAC_GSW] = REG_FIELD(HHI_VDAC_CNTL1_G12A, 0, 2), -+ [MESON_CDAC_PWD] = REG_FIELD(HHI_VDAC_CNTL1_G12A, 3, 3), -+ [MESON_VDAC_CNTL1_RESERVED] = REG_FIELD(HHI_VDAC_CNTL1_G12A, 4, 31), -+}; -+ -+static const struct phy_meson_cvbs_dac_data phy_meson8_cvbs_dac_data = { -+ .reg_fields = phy_meson8_cvbs_dac_reg_fields, -+ .cdac_ctrl_resv2_enable_val = 0x0, -+ .cdac_vref_adj_enable_val = 0x0, -+ .cdac_rl_adj_enable_val = 0x0, -+ .disable_ignore_cdac_pwd = false, -+ .needs_cvbs_trimming_nvmem_cell = true, -+}; -+ -+static const struct phy_meson_cvbs_dac_data phy_meson_gxbb_cvbs_dac_data = { -+ .reg_fields = phy_meson8_cvbs_dac_reg_fields, -+ .cdac_ctrl_resv2_enable_val = 0x0, -+ .cdac_vref_adj_enable_val = 0x0, -+ .cdac_rl_adj_enable_val = 0x0, -+ .disable_ignore_cdac_pwd = false, -+ .needs_cvbs_trimming_nvmem_cell = false, -+}; -+ -+static const struct phy_meson_cvbs_dac_data phy_meson_gxl_cvbs_dac_data = { -+ .reg_fields = phy_meson8_cvbs_dac_reg_fields, -+ .cdac_ctrl_resv2_enable_val = 0x0, -+ .cdac_vref_adj_enable_val = 0xf, -+ .cdac_rl_adj_enable_val = 0x0, -+ .disable_ignore_cdac_pwd = false, -+ .needs_cvbs_trimming_nvmem_cell = false, -+}; -+ -+static const struct phy_meson_cvbs_dac_data phy_meson_g12a_cvbs_dac_data = { -+ .reg_fields = phy_meson_g12a_cvbs_dac_reg_fields, -+ .cdac_ctrl_resv2_enable_val = 0x60, -+ .cdac_vref_adj_enable_val = 0x10, -+ .cdac_rl_adj_enable_val = 0x4, -+ .disable_ignore_cdac_pwd = true, -+ .needs_cvbs_trimming_nvmem_cell = false, -+}; -+ -+static int phy_meson_cvbs_dac_power_on(struct phy *phy) -+{ -+ struct phy_meson_cvbs_dac_priv *priv = phy_get_drvdata(phy); -+ -+ regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV1], 0x1); -+ regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV2], -+ priv->data->cdac_ctrl_resv2_enable_val); -+ regmap_field_write(priv->regs[MESON_CDAC_VREF_ADJ], -+ priv->data->cdac_vref_adj_enable_val); -+ regmap_field_write(priv->regs[MESON_CDAC_RL_ADJ], -+ priv->data->cdac_rl_adj_enable_val); -+ regmap_field_write(priv->regs[MESON_CDAC_GSW], -+ priv->cdac_gsw_enable_val); -+ regmap_field_write(priv->regs[MESON_CDAC_PWD], 0x0); -+ -+ return 0; -+} -+ -+static int phy_meson_cvbs_dac_power_off(struct phy *phy) -+{ -+ struct phy_meson_cvbs_dac_priv *priv = phy_get_drvdata(phy); -+ -+ regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV1], 0x0); -+ regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV2], 0x0); -+ regmap_field_write(priv->regs[MESON_CDAC_VREF_ADJ], 0x0); -+ regmap_field_write(priv->regs[MESON_CDAC_RL_ADJ], 0x0); -+ regmap_field_write(priv->regs[MESON_CDAC_GSW], 0x0); -+ -+ if (priv->data->disable_ignore_cdac_pwd) -+ regmap_field_write(priv->regs[MESON_CDAC_PWD], 0x0); -+ else -+ regmap_field_write(priv->regs[MESON_CDAC_PWD], 0x1); -+ -+ return 0; -+} -+ -+static int phy_meson_cvbs_dac_init(struct phy *phy) -+{ -+ struct phy_meson_cvbs_dac_priv *priv = phy_get_drvdata(phy); -+ -+ regmap_field_write(priv->regs[MESON_CDAC_CLK_PHASE_SEL], 0x0); -+ regmap_field_write(priv->regs[MESON_CDAC_DRIVER_ADJ], 0x0); -+ regmap_field_write(priv->regs[MESON_CDAC_EXT_VREF_EN], 0x0); -+ regmap_field_write(priv->regs[MESON_CDAC_BIAS_C], 0x0); -+ regmap_field_write(priv->regs[MESON_VDAC_CNTL0_RESERVED], 0x0); -+ regmap_field_write(priv->regs[MESON_VDAC_CNTL1_RESERVED], 0x0); -+ -+ return phy_meson_cvbs_dac_power_off(phy); -+} -+ -+static const struct phy_ops phy_meson_cvbs_dac_ops = { -+ .init = phy_meson_cvbs_dac_init, -+ .power_on = phy_meson_cvbs_dac_power_on, -+ .power_off = phy_meson_cvbs_dac_power_off, -+ .owner = THIS_MODULE, -+}; -+ -+static u8 phy_meson_cvbs_trimming_version(u8 trimming1) -+{ -+ if ((trimming1 & 0xf0) == 0xa0) -+ return 5; -+ else if ((trimming1 & 0xf0) == 0x40) -+ return 2; -+ else if ((trimming1 & 0xc0) == 0x80) -+ return 1; -+ else if ((trimming1 & 0xc0) == 0x00) -+ return 0; -+ else -+ return 0xff; -+} -+ -+static int phy_meson_cvbs_read_trimming(struct device *dev, -+ struct phy_meson_cvbs_dac_priv *priv) -+{ -+ struct nvmem_cell *cell; -+ u8 *trimming; -+ size_t len; -+ -+ cell = devm_nvmem_cell_get(dev, "cvbs_trimming"); -+ if (IS_ERR(cell)) -+ return dev_err_probe(dev, PTR_ERR(cell), -+ "Failed to get the 'cvbs_trimming' nvmem-cell\n"); -+ -+ trimming = nvmem_cell_read(cell, &len); -+ if (IS_ERR(trimming)) { -+ /* -+ * TrustZone firmware may block access to the CVBS trimming -+ * data stored in the eFuse. On those devices the trimming data -+ * is stored in the u-boot environment. However, the known -+ * examples of trimming data in the u-boot environment are all -+ * zero. -+ */ -+ dev_dbg(dev, -+ "Failed to read the 'cvbs_trimming' nvmem-cell - falling back to a default value\n"); -+ priv->cdac_gsw_enable_val = 0x0; -+ return 0; -+ } -+ -+ if (len != 2) { -+ kfree(trimming); -+ return dev_err_probe(dev, -EINVAL, -+ "Read the 'cvbs_trimming' nvmem-cell with invalid length\n"); -+ } -+ -+ switch (phy_meson_cvbs_trimming_version(trimming[1])) { -+ case 1: -+ case 2: -+ case 5: -+ priv->cdac_gsw_enable_val = trimming[0] & 0x7; -+ break; -+ default: -+ priv->cdac_gsw_enable_val = 0x0; -+ break; -+ } -+ -+ kfree(trimming); -+ -+ return 0; -+} -+ -+static int phy_meson_cvbs_dac_probe(struct platform_device *pdev) -+{ -+ struct device_node *np = pdev->dev.of_node; -+ struct phy_meson_cvbs_dac_priv *priv; -+ struct phy_provider *phy_provider; -+ struct device *dev = &pdev->dev; -+ struct regmap *hhi; -+ struct phy *phy; -+ int ret; -+ -+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); -+ if (!priv) -+ return -ENOMEM; -+ -+ if (np) { -+ priv->data = device_get_match_data(dev); -+ if (!priv->data) -+ return dev_err_probe(dev, -EINVAL, -+ "Could not find the OF match data\n"); -+ -+ hhi = syscon_node_to_regmap(np->parent); -+ if (IS_ERR(hhi)) -+ return dev_err_probe(dev, PTR_ERR(hhi), -+ "Failed to get the parent syscon\n"); -+ } else { -+ const struct platform_device_id *pdev_id; -+ -+ pdev_id = platform_get_device_id(pdev); -+ if (!pdev_id) -+ return dev_err_probe(dev, -EINVAL, -+ "Failed to find platform device ID\n"); -+ -+ priv->data = (void *)pdev_id->driver_data; -+ if (!priv->data) -+ return dev_err_probe(dev, -EINVAL, -+ "Could not find the platform driver data\n"); -+ -+ hhi = syscon_regmap_lookup_by_compatible("amlogic,meson-gx-hhi-sysctrl"); -+ if (IS_ERR(hhi)) -+ return dev_err_probe(dev, PTR_ERR(hhi), -+ "Failed to get the \"amlogic,meson-gx-hhi-sysctrl\" syscon\n"); -+ } -+ -+ if (priv->data->needs_cvbs_trimming_nvmem_cell) { -+ ret = phy_meson_cvbs_read_trimming(dev, priv); -+ if (ret) -+ return ret; -+ } -+ -+ ret = devm_regmap_field_bulk_alloc(dev, hhi, priv->regs, -+ priv->data->reg_fields, -+ MESON_CVBS_DAC_NUM_REGS); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "Failed to create regmap fields\n"); -+ -+ phy = devm_phy_create(dev, np, &phy_meson_cvbs_dac_ops); -+ if (IS_ERR(phy)) -+ return PTR_ERR(phy); -+ -+ phy_set_drvdata(phy, priv); -+ -+ if (np) { -+ phy_provider = devm_of_phy_provider_register(dev, -+ of_phy_simple_xlate); -+ ret = PTR_ERR_OR_ZERO(phy_provider); -+ if (ret) -+ return dev_err_probe(dev, ret, -+ "Failed to register PHY provider\n"); -+ } -+ -+ platform_set_drvdata(pdev, phy); -+ -+ return 0; -+} -+ -+static const struct of_device_id phy_meson_cvbs_dac_of_match[] = { -+ { -+ .compatible = "amlogic,meson8-cvbs-dac", -+ .data = &phy_meson8_cvbs_dac_data, -+ }, -+ { -+ .compatible = "amlogic,meson-gxbb-cvbs-dac", -+ .data = &phy_meson_gxbb_cvbs_dac_data, -+ }, -+ { -+ .compatible = "amlogic,meson-gxl-cvbs-dac", -+ .data = &phy_meson_gxl_cvbs_dac_data, -+ }, -+ { -+ .compatible = "amlogic,meson-g12a-cvbs-dac", -+ .data = &phy_meson_g12a_cvbs_dac_data, -+ }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(of, phy_meson_cvbs_dac_of_match); -+ -+/* -+ * The platform_device_id table is used for backwards compatibility with old -+ * .dtbs which don't have a CVBS DAC node (where the VPU DRM driver registers -+ * this as a platform device. Support for additional SoCs should only be added -+ * to the of_device_id table above. -+ */ -+static const struct platform_device_id phy_meson_cvbs_dac_device_ids[] = { -+ { -+ .name = "meson-gxbb-cvbs-dac", -+ .driver_data = (kernel_ulong_t)&phy_meson_gxbb_cvbs_dac_data, -+ }, -+ { -+ .name = "meson-gxl-cvbs-dac", -+ .driver_data = (kernel_ulong_t)&phy_meson_gxl_cvbs_dac_data, -+ }, -+ { -+ .name = "meson-g12a-cvbs-dac", -+ .driver_data = (kernel_ulong_t)&phy_meson_g12a_cvbs_dac_data, -+ }, -+ { /* sentinel */ } -+}; -+MODULE_DEVICE_TABLE(platform, phy_meson_cvbs_dac_device_ids); -+ -+static struct platform_driver phy_meson_cvbs_dac_driver = { -+ .driver = { -+ .name = "phy-meson-cvbs-dac", -+ .of_match_table = phy_meson_cvbs_dac_of_match, -+ }, -+ .id_table = phy_meson_cvbs_dac_device_ids, -+ .probe = phy_meson_cvbs_dac_probe, -+}; -+module_platform_driver(phy_meson_cvbs_dac_driver); -+ -+MODULE_AUTHOR("Martin Blumenstingl "); -+MODULE_DESCRIPTION("Amlogic Meson CVBS DAC driver"); -+MODULE_LICENSE("GPL v2"); --- -2.34.1 - diff --git a/patch/kernel/archive/meson-6.8/generic-0002-m8-m8b-m8m2-drm-forcefully-enable-XRGB-format.patch b/patch/kernel/archive/meson-6.8/generic-0002-m8-m8b-m8m2-drm-forcefully-enable-XRGB-format.patch deleted file mode 100644 index 7114e0dd81c6..000000000000 --- a/patch/kernel/archive/meson-6.8/generic-0002-m8-m8b-m8m2-drm-forcefully-enable-XRGB-format.patch +++ /dev/null @@ -1,27 +0,0 @@ -From d11b44bf44111b9f1d5497e92826df46ff065dbd Mon Sep 17 00:00:00 2001 -From: hzy -Date: Sat, 18 Nov 2023 01:22:03 +0800 -Subject: [PATCH 2/3] meson8/meson8b/meson8m2: drm: Forcefully enable XRGB - format - -Signed-off-by: hzy ---- - drivers/gpu/drm/meson/meson_plane.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c -index 27e39577..027b2fe7 100644 ---- a/drivers/gpu/drm/meson/meson_plane.c -+++ b/drivers/gpu/drm/meson/meson_plane.c -@@ -483,6 +483,8 @@ static const struct drm_plane_funcs meson_plane_funcs = { - static const uint32_t supported_drm_formats_m8[] = { - DRM_FORMAT_ARGB8888, - DRM_FORMAT_ABGR8888, -+ DRM_FORMAT_XRGB8888, -+ DRM_FORMAT_XBGR8888, - DRM_FORMAT_RGB888, - DRM_FORMAT_RGB565, - }; --- -2.34.1 - diff --git a/patch/kernel/archive/meson-6.8/generic-0003-drm-meson-Support-meson-8-8b-hdmi-tx-components.patch b/patch/kernel/archive/meson-6.8/generic-0003-drm-meson-Support-meson-8-8b-hdmi-tx-components.patch deleted file mode 100644 index fdf63bf9c9af..000000000000 --- a/patch/kernel/archive/meson-6.8/generic-0003-drm-meson-Support-meson-8-8b-hdmi-tx-components.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 99a889c050d71d663aba1ba2a706348be72ca787 Mon Sep 17 00:00:00 2001 -From: hzy -Date: Fri, 17 Nov 2023 22:54:18 +0800 -Subject: [PATCH 3/3] drm/meson: Support meson{8,8b}-hdmi-tx components - -Signed-off-by: hzy ---- - drivers/gpu/drm/meson/meson_drv.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c -index e8134e4c..c3e8fef9 100644 ---- a/drivers/gpu/drm/meson/meson_drv.c -+++ b/drivers/gpu/drm/meson/meson_drv.c -@@ -668,6 +668,8 @@ static void meson_drv_shutdown(struct platform_device *pdev) - * private structure for HHI registers. - */ - static const struct of_device_id components_dev_match[] = { -+ { .compatible = "amlogic,meson8-hdmi-tx" }, -+ { .compatible = "amlogic,meson8b-hdmi-tx" }, - { .compatible = "amlogic,meson-gxbb-dw-hdmi" }, - { .compatible = "amlogic,meson-gxl-dw-hdmi" }, - { .compatible = "amlogic,meson-gxm-dw-hdmi" }, --- -2.34.1 - diff --git a/patch/kernel/archive/meson-6.9/0007-dt-bindings-phy-meson8b-usb2-Add-support-for-reading.patch b/patch/kernel/archive/meson-6.9/0007-dt-bindings-phy-meson8b-usb2-Add-support-for-reading.patch new file mode 100644 index 000000000000..48bed5118090 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0007-dt-bindings-phy-meson8b-usb2-Add-support-for-reading.patch @@ -0,0 +1,47 @@ +From 85409ae3c08b4b1aedc80d35f0afd6832cfe5d1f Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Wed, 16 Jun 2021 20:34:01 +0200 +Subject: [PATCH 07/96] dt-bindings: phy: meson8b-usb2: Add support for reading + the ID signal + +The first USB PHY on Amlogic Meson8/8b/8m2/GXBB SoCs is OTG capable. +This means that the USB "ID" signal is routed to the PHY. Add support +for the gpio-controller and #gpio-cells properties so the value of +the "ID" signal can be read as a GPIO (from the PHY) for example by +an "gpio-usb-b-connector". + +Signed-off-by: Martin Blumenstingl +--- + .../bindings/phy/amlogic,meson8b-usb2-phy.yaml | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml +index df68bfe5f..be722a235 100644 +--- a/Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml ++++ b/Documentation/devicetree/bindings/phy/amlogic,meson8b-usb2-phy.yaml +@@ -6,6 +6,10 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# + + title: Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY + ++description: | ++ OTG capable PHYs have the USB "ID" signal routed to them. ++ This can be read out via the PHY-provided GPIO controller. ++ + maintainers: + - Martin Blumenstingl + +@@ -31,6 +35,11 @@ properties: + - const: usb_general + - const: usb + ++ '#gpio-cells': ++ const: 2 ++ ++ gpio-controller: true ++ + resets: + minItems: 1 + +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0008-phy-amlogic-meson8b-usb2-Add-support-for-reading-the.patch b/patch/kernel/archive/meson-6.9/0008-phy-amlogic-meson8b-usb2-Add-support-for-reading-the.patch new file mode 100644 index 000000000000..42f56c905595 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0008-phy-amlogic-meson8b-usb2-Add-support-for-reading-the.patch @@ -0,0 +1,103 @@ +From fa852523a5da72615695668ef4d354b6af2cae83 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sun, 3 May 2020 21:40:27 +0200 +Subject: [PATCH 08/96] phy: amlogic: meson8b-usb2: Add support for reading the + "ID" signal + +The first USB PHY on Amlogic Meson8/8b/8m2/GXBB SoCs is OTG capable. +This means that the USB "ID" signal is routed to the PHY. Add support +for the gpio-controller and #gpio-cells properties so the value of +the "ID" signal can be read as a GPIO (from the PHY) for example by +the usb-conn-gpio driver. + +The registers also have a bit for the VBUS signal. That either is not +wired in hardware inside the SoC silicon or not wired on the boards +(e.g. Odroid-C1), which is why it's value is not exposed for now. + +Signed-off-by: Martin Blumenstingl +--- + drivers/phy/amlogic/phy-meson8b-usb2.c | 42 +++++++++++++++++++++++++- + 1 file changed, 41 insertions(+), 1 deletion(-) + +diff --git a/drivers/phy/amlogic/phy-meson8b-usb2.c b/drivers/phy/amlogic/phy-meson8b-usb2.c +index d63147c41..d3d0bd367 100644 +--- a/drivers/phy/amlogic/phy-meson8b-usb2.c ++++ b/drivers/phy/amlogic/phy-meson8b-usb2.c +@@ -7,6 +7,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -127,6 +128,7 @@ struct phy_meson8b_usb2_priv { + struct clk *clk_usb_general; + struct clk *clk_usb; + struct reset_control *reset; ++ struct gpio_chip gpiochip; + const struct phy_meson8b_usb2_match_data *match; + }; + +@@ -236,12 +238,44 @@ static const struct phy_ops phy_meson8b_usb2_ops = { + .owner = THIS_MODULE, + }; + ++static int phy_meson8b_usb2_id_gpio_get_direction(struct gpio_chip *gc, ++ unsigned int offset) ++{ ++ return GPIO_LINE_DIRECTION_IN; ++} ++ ++static int phy_meson8b_usb2_id_gpio_get_value(struct gpio_chip *gc, ++ unsigned int offset) ++{ ++ struct phy_meson8b_usb2_priv *priv = gpiochip_get_data(gc); ++ unsigned int val; ++ ++ regmap_read(priv->regmap, REG_ADP_BC, &val); ++ ++ return (val & REG_ADP_BC_ID_DIG) ? 1 : 0; ++} ++ ++static int phy_meson8b_usb2_id_gpiochip_add(struct device *dev, ++ struct phy_meson8b_usb2_priv *priv) ++{ ++ priv->gpiochip.label = dev_name(dev); ++ priv->gpiochip.parent = dev; ++ priv->gpiochip.get_direction = phy_meson8b_usb2_id_gpio_get_direction; ++ priv->gpiochip.get = phy_meson8b_usb2_id_gpio_get_value; ++ priv->gpiochip.of_gpio_n_cells = 2; ++ priv->gpiochip.base = -1; ++ priv->gpiochip.ngpio = 1; ++ ++ return devm_gpiochip_add_data(dev, &priv->gpiochip, priv); ++} ++ + static int phy_meson8b_usb2_probe(struct platform_device *pdev) + { + struct phy_meson8b_usb2_priv *priv; +- struct phy *phy; + struct phy_provider *phy_provider; + void __iomem *base; ++ struct phy *phy; ++ int ret; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) +@@ -280,6 +314,12 @@ static int phy_meson8b_usb2_probe(struct platform_device *pdev) + return -EINVAL; + } + ++ if (device_property_read_bool(&pdev->dev, "gpio-controller")) { ++ ret = phy_meson8b_usb2_id_gpiochip_add(&pdev->dev, priv); ++ if (ret) ++ return ret; ++ } ++ + phy = devm_phy_create(&pdev->dev, NULL, &phy_meson8b_usb2_ops); + if (IS_ERR(phy)) { + return dev_err_probe(&pdev->dev, PTR_ERR(phy), +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0009-usb-common-usb-conn-gpio-Fall-back-to-polling-the-GP.patch b/patch/kernel/archive/meson-6.9/0009-usb-common-usb-conn-gpio-Fall-back-to-polling-the-GP.patch new file mode 100644 index 000000000000..86b8a1da5bfd --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0009-usb-common-usb-conn-gpio-Fall-back-to-polling-the-GP.patch @@ -0,0 +1,147 @@ +From 8d8783f1098d154b6beb13fb694cf932dbf43e43 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Wed, 16 Jun 2021 21:07:50 +0200 +Subject: [PATCH 09/96] usb: common: usb-conn-gpio: Fall back to polling the + GPIO + +On some SoCs (for example: Amlogic Meson8/8b/8m2 and GXBB) the ID GPIO +cannot generate an interrupt. Fall back to polling the GPIO(s) in that +case. + +Signed-off-by: Martin Blumenstingl +--- + drivers/usb/common/usb-conn-gpio.c | 76 +++++++++++++++++++----------- + 1 file changed, 48 insertions(+), 28 deletions(-) + +diff --git a/drivers/usb/common/usb-conn-gpio.c b/drivers/usb/common/usb-conn-gpio.c +index 501e8bc97..b0b19e026 100644 +--- a/drivers/usb/common/usb-conn-gpio.c ++++ b/drivers/usb/common/usb-conn-gpio.c +@@ -23,6 +23,7 @@ + + #define USB_GPIO_DEB_MS 20 /* ms */ + #define USB_GPIO_DEB_US ((USB_GPIO_DEB_MS) * 1000) /* us */ ++#define USB_GPIO_POLL_MS 1000 + + #define USB_CONN_IRQF \ + (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT) +@@ -45,6 +46,23 @@ struct usb_conn_info { + bool initial_detection; + }; + ++static void usb_conn_queue_dwork(struct usb_conn_info *info, ++ unsigned long delay) ++{ ++ queue_delayed_work(system_power_efficient_wq, &info->dw_det, delay); ++} ++ ++static void usb_conn_gpio_start_polling(struct usb_conn_info *info) ++{ ++ usb_conn_queue_dwork(info, msecs_to_jiffies(USB_GPIO_POLL_MS)); ++} ++ ++static bool usb_conn_gpio_needs_polling(struct usb_conn_info *info) ++{ ++ /* We need to poll if one of the GPIOs cannot generate an IRQ. */ ++ return info->id_irq < 0 || info->vbus_irq < 0; ++} ++ + /* + * "DEVICE" = VBUS and "HOST" = !ID, so we have: + * Both "DEVICE" and "HOST" can't be set as active at the same time +@@ -88,7 +106,10 @@ static void usb_conn_detect_cable(struct work_struct *work) + usb_role_string(info->last_role), usb_role_string(role), id, vbus); + + if (!info->initial_detection && info->last_role == role) { +- dev_warn(info->dev, "repeated role: %s\n", usb_role_string(role)); ++ if (usb_conn_gpio_needs_polling(info)) ++ usb_conn_gpio_start_polling(info); ++ else ++ dev_warn(info->dev, "repeated role: %s\n", usb_role_string(role)); + return; + } + +@@ -114,12 +135,9 @@ static void usb_conn_detect_cable(struct work_struct *work) + regulator_is_enabled(info->vbus) ? "enabled" : "disabled"); + + power_supply_changed(info->charger); +-} + +-static void usb_conn_queue_dwork(struct usb_conn_info *info, +- unsigned long delay) +-{ +- queue_delayed_work(system_power_efficient_wq, &info->dw_det, delay); ++ if (usb_conn_gpio_needs_polling(info)) ++ usb_conn_gpio_start_polling(info); + } + + static irqreturn_t usb_conn_isr(int irq, void *dev_id) +@@ -226,34 +244,34 @@ static int usb_conn_probe(struct platform_device *pdev) + if (info->id_gpiod) { + info->id_irq = gpiod_to_irq(info->id_gpiod); + if (info->id_irq < 0) { +- dev_err(dev, "failed to get ID IRQ\n"); +- ret = info->id_irq; +- goto put_role_sw; +- } +- +- ret = devm_request_threaded_irq(dev, info->id_irq, NULL, +- usb_conn_isr, USB_CONN_IRQF, +- pdev->name, info); +- if (ret < 0) { +- dev_err(dev, "failed to request ID IRQ\n"); +- goto put_role_sw; ++ dev_info(dev, ++ "failed to get ID IRQ - falling back to polling\n"); ++ } else { ++ ret = devm_request_threaded_irq(dev, info->id_irq, ++ NULL, usb_conn_isr, ++ USB_CONN_IRQF, ++ pdev->name, info); ++ if (ret < 0) { ++ dev_err(dev, "failed to request ID IRQ\n"); ++ goto put_role_sw; ++ } + } + } + + if (info->vbus_gpiod) { + info->vbus_irq = gpiod_to_irq(info->vbus_gpiod); + if (info->vbus_irq < 0) { +- dev_err(dev, "failed to get VBUS IRQ\n"); +- ret = info->vbus_irq; +- goto put_role_sw; +- } +- +- ret = devm_request_threaded_irq(dev, info->vbus_irq, NULL, +- usb_conn_isr, USB_CONN_IRQF, +- pdev->name, info); +- if (ret < 0) { +- dev_err(dev, "failed to request VBUS IRQ\n"); +- goto put_role_sw; ++ dev_info(dev, ++ "failed to get VBUS IRQ - falling back to polling\n"); ++ } else { ++ ret = devm_request_threaded_irq(dev, info->vbus_irq, ++ NULL, usb_conn_isr, ++ USB_CONN_IRQF, ++ pdev->name, info); ++ if (ret < 0) { ++ dev_err(dev, "failed to request VBUS IRQ\n"); ++ goto put_role_sw; ++ } + } + } + +@@ -300,6 +318,8 @@ static int __maybe_unused usb_conn_suspend(struct device *dev) + if (info->vbus_gpiod) + disable_irq(info->vbus_irq); + ++ cancel_delayed_work_sync(&info->dw_det); ++ + pinctrl_pm_select_sleep_state(dev); + + return 0; +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0010-usb-dwc2-register-child-USB-connector-devices.patch b/patch/kernel/archive/meson-6.9/0010-usb-dwc2-register-child-USB-connector-devices.patch new file mode 100644 index 000000000000..244d7d5414b7 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0010-usb-dwc2-register-child-USB-connector-devices.patch @@ -0,0 +1,49 @@ +From d7166eaf19e263a1b6dd551f1b5c40b86524b4d6 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 4 Jul 2020 21:04:29 +0200 +Subject: [PATCH 10/96] usb: dwc2: register child (USB connector) devices + +Populate the child devices/nodes of the dwc2 controller. Typically these +are USB connectors with a compatible string (and additional properties) +like "gpio-usb-b-connector". + +Signed-off-by: Martin Blumenstingl +--- + drivers/usb/dwc2/platform.c | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c +index b1d48019e..d56c1ea5b 100644 +--- a/drivers/usb/dwc2/platform.c ++++ b/drivers/usb/dwc2/platform.c +@@ -12,6 +12,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -620,6 +621,19 @@ static int dwc2_driver_probe(struct platform_device *dev) + } + } + #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */ ++ ++ retval = devm_of_platform_populate(&dev->dev); ++ if (retval) { ++ dev_err(hsotg->dev, ++ "Failed to create child devices/connectors for %p\n", ++ dev->dev.of_node); ++ ++ if (hsotg->gadget_enabled) ++ dwc2_hsotg_remove(hsotg); ++ ++ goto error_debugfs; ++ } ++ + return 0; + + #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \ +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0011-ARM-dts-meson-Add-GPIO-controller-capabilities-to-th.patch b/patch/kernel/archive/meson-6.9/0011-ARM-dts-meson-Add-GPIO-controller-capabilities-to-th.patch new file mode 100644 index 000000000000..eb9b490ff18c --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0011-ARM-dts-meson-Add-GPIO-controller-capabilities-to-th.patch @@ -0,0 +1,30 @@ +From 8a559e2ff9aa875656c3c62df16dedc84f68c2b7 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Wed, 16 Jun 2021 20:38:07 +0200 +Subject: [PATCH 11/96] ARM: dts: meson: Add GPIO controller capabilities to + the first USB PHY + +This is needed for boards that implement OTG functionality to read out +the value of the "ID" signal (e.g. on Micro USB connectors). + +Signed-off-by: Martin Blumenstingl +--- + arch/arm/boot/dts/amlogic/meson.dtsi | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/arch/arm/boot/dts/amlogic/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi +index 8cb0fc78b..0e7756c95 100644 +--- a/arch/arm/boot/dts/amlogic/meson.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson.dtsi +@@ -124,6 +124,8 @@ usb0_phy: phy@8800 { + compatible = "amlogic,meson-mx-usb2-phy"; + #phy-cells = <0>; + reg = <0x8800 0x20>; ++ gpio-controller; ++ #gpio-cells = <2>; + status = "disabled"; + }; + +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0012-ARM-dts-meson8b-odroidc1-Enable-the-Micro-USB-OTG-co.patch b/patch/kernel/archive/meson-6.9/0012-ARM-dts-meson8b-odroidc1-Enable-the-Micro-USB-OTG-co.patch new file mode 100644 index 000000000000..440bfb3792b8 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0012-ARM-dts-meson8b-odroidc1-Enable-the-Micro-USB-OTG-co.patch @@ -0,0 +1,75 @@ +From ebc6d5206b98d516e34304a42898d7733301cc96 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 4 May 2020 00:16:00 +0200 +Subject: [PATCH 12/96] ARM: dts: meson8b: odroidc1: Enable the Micro USB OTG + connector + +Enable &usb0 which is routed to the Micro USB connector. The port +supports OTG modes and the role switch is implemented by reading out the +"ID" signal from &usb0_phy. + +Signed-off-by: Martin Blumenstingl +--- + .../arm/boot/dts/amlogic/meson8b-odroidc1.dts | 34 ++++++++++++++++++- + 1 file changed, 33 insertions(+), 1 deletion(-) + +diff --git a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts +index 941682844..eaf89638c 100644 +--- a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts ++++ b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts +@@ -93,6 +93,20 @@ rtc32k_xtal: rtc32k-xtal-clk { + #clock-cells = <0>; + }; + ++ usb0_vbus: regulator-usb0-vbus { ++ /* Richtek RT9715EGB */ ++ compatible = "regulator-fixed"; ++ ++ regulator-name = "USB0_VBUS"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ ++ vin-supply = <&p5v0>; ++ ++ gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>; ++ enable-active-high; ++ }; ++ + vcc_1v8: regulator-vcc-1v8 { + /* + * RICHTEK RT9179 configured for a fixed output voltage of +@@ -363,8 +377,18 @@ &uart_AO { + pinctrl-names = "default"; + }; + +-&usb1_phy { ++&usb0 { + status = "okay"; ++ ++ dr_mode = "otg"; ++ usb-role-switch; ++ ++ connector { ++ compatible = "gpio-usb-b-connector", "usb-b-connector"; ++ type = "micro"; ++ id-gpios = <&usb0_phy 0 GPIO_ACTIVE_HIGH>; ++ vbus-supply = <&usb0_vbus>; ++ }; + }; + + &usb1 { +@@ -381,3 +405,11 @@ hub@1 { + reset-gpio = <&gpio_ao GPIOAO_4 GPIO_ACTIVE_LOW>; + }; + }; ++ ++&usb0_phy { ++ status = "okay"; ++}; ++ ++&usb1_phy { ++ status = "okay"; ++}; +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0013-dt-bindings-phy-Add-bindings-for-the-Amlogic-Meson-C.patch b/patch/kernel/archive/meson-6.9/0013-dt-bindings-phy-Add-bindings-for-the-Amlogic-Meson-C.patch new file mode 100644 index 000000000000..4f10f7969e90 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0013-dt-bindings-phy-Add-bindings-for-the-Amlogic-Meson-C.patch @@ -0,0 +1,106 @@ +From 84f7776a36cf1b7bae65498c93dd7850efa0c12b Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 11 Oct 2021 23:37:19 +0200 +Subject: [PATCH 13/96] dt-bindings: phy: Add bindings for the Amlogic Meson + CVBS DAC + +Amlogic Meson SoCs embed a Composite Video Baseband Signal DAC. Add the +bindings for this IP. + +Signed-off-by: Martin Blumenstingl +--- + .../phy/amlogic,meson-cvbs-dac-phy.yaml | 82 +++++++++++++++++++ + 1 file changed, 82 insertions(+) + create mode 100644 Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml + +diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml +new file mode 100644 +index 000000000..906a69505 +--- /dev/null ++++ b/Documentation/devicetree/bindings/phy/amlogic,meson-cvbs-dac-phy.yaml +@@ -0,0 +1,82 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++%YAML 1.2 ++--- ++$id: http://devicetree.org/schemas/phy/amlogic,meson-cvbs-dac-phy.yaml# ++$schema: http://devicetree.org/meta-schemas/core.yaml# ++ ++title: Amlogic Meson Composite Video Baseband Signal DAC ++ ++maintainers: ++ - Martin Blumenstingl ++ ++description: |+ ++ The CVBS DAC node should be the child of a syscon node with the ++ required property: ++ ++ compatible = "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" ++ ++ Refer to the bindings described in ++ Documentation/devicetree/bindings/mfd/syscon.yaml ++ ++properties: ++ $nodename: ++ pattern: "^video-dac@[0-9a-f]+$" ++ ++ compatible: ++ oneOf: ++ - items: ++ - enum: ++ - amlogic,meson8-cvbs-dac ++ - amlogic,meson8b-cvbs-dac ++ - amlogic,meson-gxbb-cvbs-dac ++ - amlogic,meson-gxl-cvbs-dac ++ - amlogic,meson-g12a-cvbs-dac ++ - const: amlogic,meson-cvbs-dac ++ - const: amlogic,meson-cvbs-dac ++ ++ reg: ++ maxItems: 1 ++ ++ clocks: ++ minItems: 1 ++ ++ nvmem-cells: ++ minItems: 1 ++ ++ nvmem-cell-names: ++ items: ++ - const: cvbs_trimming ++ ++ "#phy-cells": ++ const: 0 ++ ++required: ++ - compatible ++ - reg ++ - clocks ++ - "#phy-cells" ++ ++additionalProperties: false ++ ++examples: ++ - | ++ video-dac@2f4 { ++ compatible = "amlogic,meson8-cvbs-dac", "amlogic,meson-cvbs-dac"; ++ reg = <0x2f4 0x8>; ++ ++ #phy-cells = <0>; ++ ++ clocks = <&vdac_clock>; ++ ++ nvmem-cells = <&cvbs_trimming>; ++ nvmem-cell-names = "cvbs_trimming"; ++ }; ++ - | ++ video-dac@2ec { ++ compatible = "amlogic,meson-g12a-cvbs-dac", "amlogic,meson-cvbs-dac"; ++ reg = <0x2ec 0x8>; ++ ++ #phy-cells = <0>; ++ ++ clocks = <&vdac_clock>; ++ }; +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0014-phy-amlogic-Add-a-new-driver-for-the-CVBS-DAC-CVBS-P.patch b/patch/kernel/archive/meson-6.9/0014-phy-amlogic-Add-a-new-driver-for-the-CVBS-DAC-CVBS-P.patch new file mode 100644 index 000000000000..d4fe5a44ae80 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0014-phy-amlogic-Add-a-new-driver-for-the-CVBS-DAC-CVBS-P.patch @@ -0,0 +1,447 @@ +From a8af3998b655e87d5a10380584d2e80a93129195 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 11 Oct 2021 23:05:25 +0200 +Subject: [PATCH 14/96] phy: amlogic: Add a new driver for the CVBS DAC (CVBS + PHY) + +Amlogic Meson SoCs embed a CVBS DAC which converts the signal from the +VPU to analog. The IP has evolved over time with the SoC generations: +- Meson8/8b/8m2 has per-chip calibrated data for the CDAC_GSW register +- GXBB is overall similar to Meson8/8b/8m2 except that it doesn't have + per-chip calibration data and uses 0x0 in CDAC_GSW always +- GXL/GXM are overall similar to GXBB but require a CDAC_VREF_ADJ value + of 0xf (of which the actual meaning is unknown) +- G12A/G12B/SM1 use different register offsets and different values for + CDAC_CTRL_RESV2, CDAC_VREF_ADJ and CDAC_RL_ADJ. Like other SoCs from + GXBB onwards they don't need any per-chip data. + +For backwards compatibility with old .dtbs the driver gets +platform_device_id's so the VPU driver can register the PHY as platform +device if not provided via .dtb. + +Signed-off-by: Martin Blumenstingl +--- + drivers/phy/amlogic/Kconfig | 10 + + drivers/phy/amlogic/Makefile | 1 + + drivers/phy/amlogic/phy-meson-cvbs-dac.c | 376 +++++++++++++++++++++++ + 3 files changed, 387 insertions(+) + create mode 100644 drivers/phy/amlogic/phy-meson-cvbs-dac.c + +diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig +index ce7ba3eb2..671435b60 100644 +--- a/drivers/phy/amlogic/Kconfig ++++ b/drivers/phy/amlogic/Kconfig +@@ -25,6 +25,16 @@ config PHY_MESON8B_USB2 + Meson8b and GXBB SoCs. + If unsure, say N. + ++config PHY_MESON_CVBS_DAC ++ tristate "Amlogic Meson CVBS DAC PHY driver" ++ depends on ARCH_MESON || COMPILE_TEST ++ depends on OF ++ select MFD_SYSCON ++ help ++ Enable this to support the CVBS DAC (PHY) found in Amlogic ++ Meson SoCs. ++ If unsure, say N. ++ + config PHY_MESON_GXL_USB2 + tristate "Meson GXL and GXM USB2 PHY drivers" + default ARCH_MESON +diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile +index 91e3b9790..f6c38f738 100644 +--- a/drivers/phy/amlogic/Makefile ++++ b/drivers/phy/amlogic/Makefile +@@ -1,6 +1,7 @@ + # SPDX-License-Identifier: GPL-2.0-only + obj-$(CONFIG_PHY_MESON8_HDMI_TX) += phy-meson8-hdmi-tx.o + obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o ++obj-$(CONFIG_PHY_MESON_CVBS_DAC) += phy-meson-cvbs-dac.o + obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o + obj-$(CONFIG_PHY_MESON_G12A_USB2) += phy-meson-g12a-usb2.o + obj-$(CONFIG_PHY_MESON_G12A_USB3_PCIE) += phy-meson-g12a-usb3-pcie.o +diff --git a/drivers/phy/amlogic/phy-meson-cvbs-dac.c b/drivers/phy/amlogic/phy-meson-cvbs-dac.c +new file mode 100644 +index 000000000..10edfb120 +--- /dev/null ++++ b/drivers/phy/amlogic/phy-meson-cvbs-dac.c +@@ -0,0 +1,376 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Copyright (C) 2016 BayLibre, SAS ++ * Copyright (C) 2021 Martin Blumenstingl ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define HHI_VDAC_CNTL0_MESON8 0x2F4 /* 0xbd offset in data sheet */ ++#define HHI_VDAC_CNTL1_MESON8 0x2F8 /* 0xbe offset in data sheet */ ++ ++#define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbd offset in data sheet */ ++#define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */ ++ ++enum phy_meson_cvbs_dac_reg { ++ MESON_CDAC_CTRL_RESV1, ++ MESON_CDAC_CTRL_RESV2, ++ MESON_CDAC_VREF_ADJ, ++ MESON_CDAC_RL_ADJ, ++ MESON_CDAC_CLK_PHASE_SEL, ++ MESON_CDAC_DRIVER_ADJ, ++ MESON_CDAC_EXT_VREF_EN, ++ MESON_CDAC_BIAS_C, ++ MESON_VDAC_CNTL0_RESERVED, ++ MESON_CDAC_GSW, ++ MESON_CDAC_PWD, ++ MESON_VDAC_CNTL1_RESERVED, ++ MESON_CVBS_DAC_NUM_REGS ++}; ++ ++struct phy_meson_cvbs_dac_data { ++ const struct reg_field *reg_fields; ++ u8 cdac_ctrl_resv2_enable_val; ++ u8 cdac_vref_adj_enable_val; ++ u8 cdac_rl_adj_enable_val; ++ u8 cdac_pwd_disable_val; ++ bool needs_cvbs_trimming_nvmem_cell; ++}; ++ ++struct phy_meson_cvbs_dac_priv { ++ struct regmap_field *regs[MESON_CVBS_DAC_NUM_REGS]; ++ const struct phy_meson_cvbs_dac_data *data; ++ u8 cdac_gsw_enable_val; ++}; ++ ++static const struct reg_field phy_meson8_cvbs_dac_reg_fields[] = { ++ [MESON_CDAC_CTRL_RESV1] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 0, 7), ++ [MESON_CDAC_CTRL_RESV2] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 8, 15), ++ [MESON_CDAC_VREF_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 16, 20), ++ [MESON_CDAC_RL_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 21, 23), ++ [MESON_CDAC_CLK_PHASE_SEL] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 24, 24), ++ [MESON_CDAC_DRIVER_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 25, 25), ++ [MESON_CDAC_EXT_VREF_EN] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 26, 26), ++ [MESON_CDAC_BIAS_C] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 27, 27), ++ [MESON_VDAC_CNTL0_RESERVED] = REG_FIELD(HHI_VDAC_CNTL0_MESON8, 28, 31), ++ [MESON_CDAC_GSW] = REG_FIELD(HHI_VDAC_CNTL1_MESON8, 0, 2), ++ [MESON_CDAC_PWD] = REG_FIELD(HHI_VDAC_CNTL1_MESON8, 3, 3), ++ [MESON_VDAC_CNTL1_RESERVED] = REG_FIELD(HHI_VDAC_CNTL1_MESON8, 4, 31), ++}; ++ ++static const struct reg_field phy_meson_g12a_cvbs_dac_reg_fields[] = { ++ [MESON_CDAC_CTRL_RESV1] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 0, 7), ++ [MESON_CDAC_CTRL_RESV2] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 8, 15), ++ [MESON_CDAC_VREF_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 16, 20), ++ [MESON_CDAC_RL_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 21, 23), ++ [MESON_CDAC_CLK_PHASE_SEL] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 24, 24), ++ [MESON_CDAC_DRIVER_ADJ] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 25, 25), ++ [MESON_CDAC_EXT_VREF_EN] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 26, 26), ++ [MESON_CDAC_BIAS_C] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 27, 27), ++ [MESON_VDAC_CNTL0_RESERVED] = REG_FIELD(HHI_VDAC_CNTL0_G12A, 28, 31), ++ [MESON_CDAC_GSW] = REG_FIELD(HHI_VDAC_CNTL1_G12A, 0, 2), ++ [MESON_CDAC_PWD] = REG_FIELD(HHI_VDAC_CNTL1_G12A, 3, 3), ++ [MESON_VDAC_CNTL1_RESERVED] = REG_FIELD(HHI_VDAC_CNTL1_G12A, 4, 31), ++}; ++ ++static const struct phy_meson_cvbs_dac_data phy_meson8_cvbs_dac_data = { ++ .reg_fields = phy_meson8_cvbs_dac_reg_fields, ++ .cdac_ctrl_resv2_enable_val = 0x0, ++ .cdac_vref_adj_enable_val = 0x0, ++ .cdac_rl_adj_enable_val = 0x0, ++ .cdac_pwd_disable_val = 0x1, ++ .needs_cvbs_trimming_nvmem_cell = true, ++}; ++ ++static const struct phy_meson_cvbs_dac_data phy_meson_gxbb_cvbs_dac_data = { ++ .reg_fields = phy_meson8_cvbs_dac_reg_fields, ++ .cdac_ctrl_resv2_enable_val = 0x0, ++ .cdac_vref_adj_enable_val = 0x0, ++ .cdac_rl_adj_enable_val = 0x0, ++ .cdac_pwd_disable_val = 0x1, ++ .needs_cvbs_trimming_nvmem_cell = false, ++}; ++ ++static const struct phy_meson_cvbs_dac_data phy_meson_gxl_cvbs_dac_data = { ++ .reg_fields = phy_meson8_cvbs_dac_reg_fields, ++ .cdac_ctrl_resv2_enable_val = 0x0, ++ .cdac_vref_adj_enable_val = 0xf, ++ .cdac_rl_adj_enable_val = 0x0, ++ .cdac_pwd_disable_val = 0x1, ++ .needs_cvbs_trimming_nvmem_cell = false, ++}; ++ ++static const struct phy_meson_cvbs_dac_data phy_meson_g12a_cvbs_dac_data = { ++ .reg_fields = phy_meson_g12a_cvbs_dac_reg_fields, ++ .cdac_ctrl_resv2_enable_val = 0x60, ++ .cdac_vref_adj_enable_val = 0x10, ++ .cdac_rl_adj_enable_val = 0x4, ++ .cdac_pwd_disable_val = 0x0, ++ .needs_cvbs_trimming_nvmem_cell = false, ++}; ++ ++static int phy_meson_cvbs_dac_power_on(struct phy *phy) ++{ ++ struct phy_meson_cvbs_dac_priv *priv = phy_get_drvdata(phy); ++ ++ regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV1], 0x1); ++ regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV2], ++ priv->data->cdac_ctrl_resv2_enable_val); ++ regmap_field_write(priv->regs[MESON_CDAC_VREF_ADJ], ++ priv->data->cdac_vref_adj_enable_val); ++ regmap_field_write(priv->regs[MESON_CDAC_RL_ADJ], ++ priv->data->cdac_rl_adj_enable_val); ++ regmap_field_write(priv->regs[MESON_CDAC_GSW], ++ priv->cdac_gsw_enable_val); ++ regmap_field_write(priv->regs[MESON_CDAC_PWD], 0x0); ++ ++ return 0; ++} ++ ++static int phy_meson_cvbs_dac_power_off(struct phy *phy) ++{ ++ struct phy_meson_cvbs_dac_priv *priv = phy_get_drvdata(phy); ++ ++ regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV1], 0x0); ++ regmap_field_write(priv->regs[MESON_CDAC_CTRL_RESV2], 0x0); ++ regmap_field_write(priv->regs[MESON_CDAC_VREF_ADJ], 0x0); ++ regmap_field_write(priv->regs[MESON_CDAC_RL_ADJ], 0x0); ++ regmap_field_write(priv->regs[MESON_CDAC_GSW], 0x0); ++ regmap_field_write(priv->regs[MESON_CDAC_PWD], ++ priv->data->cdac_pwd_disable_val); ++ ++ return 0; ++} ++ ++static int phy_meson_cvbs_dac_init(struct phy *phy) ++{ ++ struct phy_meson_cvbs_dac_priv *priv = phy_get_drvdata(phy); ++ ++ regmap_field_write(priv->regs[MESON_CDAC_CLK_PHASE_SEL], 0x0); ++ regmap_field_write(priv->regs[MESON_CDAC_DRIVER_ADJ], 0x0); ++ regmap_field_write(priv->regs[MESON_CDAC_EXT_VREF_EN], 0x0); ++ regmap_field_write(priv->regs[MESON_CDAC_BIAS_C], 0x0); ++ regmap_field_write(priv->regs[MESON_VDAC_CNTL0_RESERVED], 0x0); ++ regmap_field_write(priv->regs[MESON_VDAC_CNTL1_RESERVED], 0x0); ++ ++ return phy_meson_cvbs_dac_power_off(phy); ++} ++ ++static const struct phy_ops phy_meson_cvbs_dac_ops = { ++ .init = phy_meson_cvbs_dac_init, ++ .power_on = phy_meson_cvbs_dac_power_on, ++ .power_off = phy_meson_cvbs_dac_power_off, ++ .owner = THIS_MODULE, ++}; ++ ++static u8 phy_meson_cvbs_trimming_version(u8 trimming1) ++{ ++ if ((trimming1 & 0xf0) == 0xa0) ++ return 5; ++ else if ((trimming1 & 0xf0) == 0x40) ++ return 2; ++ else if ((trimming1 & 0xc0) == 0x80) ++ return 1; ++ else if ((trimming1 & 0xc0) == 0x00) ++ return 0; ++ else ++ return 0xff; ++} ++ ++static int phy_meson_cvbs_read_trimming(struct device *dev, ++ struct phy_meson_cvbs_dac_priv *priv) ++{ ++ struct nvmem_cell *cell; ++ u8 *trimming; ++ size_t len; ++ ++ cell = devm_nvmem_cell_get(dev, "cvbs_trimming"); ++ if (IS_ERR(cell)) ++ return dev_err_probe(dev, PTR_ERR(cell), ++ "Failed to get the 'cvbs_trimming' nvmem-cell\n"); ++ ++ trimming = nvmem_cell_read(cell, &len); ++ if (IS_ERR(trimming)) { ++ /* ++ * TrustZone firmware may block access to the CVBS trimming ++ * data stored in the eFuse. On those devices the trimming data ++ * is stored in the u-boot environment. However, the known ++ * examples of trimming data in the u-boot environment are all ++ * zero. ++ */ ++ dev_dbg(dev, ++ "Failed to read the 'cvbs_trimming' nvmem-cell - falling back to a default value\n"); ++ priv->cdac_gsw_enable_val = 0x0; ++ return 0; ++ } ++ ++ if (len != 2) { ++ kfree(trimming); ++ return dev_err_probe(dev, -EINVAL, ++ "Read the 'cvbs_trimming' nvmem-cell with invalid length\n"); ++ } ++ ++ switch (phy_meson_cvbs_trimming_version(trimming[1])) { ++ case 1: ++ case 2: ++ case 5: ++ priv->cdac_gsw_enable_val = trimming[0] & 0x7; ++ break; ++ default: ++ priv->cdac_gsw_enable_val = 0x0; ++ break; ++ } ++ ++ kfree(trimming); ++ ++ return 0; ++} ++ ++static int phy_meson_cvbs_dac_probe(struct platform_device *pdev) ++{ ++ struct device_node *np = pdev->dev.of_node; ++ struct phy_meson_cvbs_dac_priv *priv; ++ struct phy_provider *phy_provider; ++ struct device *dev = &pdev->dev; ++ struct regmap *hhi; ++ struct phy *phy; ++ int ret; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ if (np) { ++ priv->data = device_get_match_data(dev); ++ if (!priv->data) ++ return dev_err_probe(dev, -EINVAL, ++ "Could not find the OF match data\n"); ++ ++ hhi = syscon_node_to_regmap(np->parent); ++ if (IS_ERR(hhi)) ++ return dev_err_probe(dev, PTR_ERR(hhi), ++ "Failed to get the parent syscon\n"); ++ } else { ++ const struct platform_device_id *pdev_id; ++ ++ pdev_id = platform_get_device_id(pdev); ++ if (!pdev_id) ++ return dev_err_probe(dev, -EINVAL, ++ "Failed to find platform device ID\n"); ++ ++ priv->data = (void *)pdev_id->driver_data; ++ if (!priv->data) ++ return dev_err_probe(dev, -EINVAL, ++ "Could not find the platform driver data\n"); ++ ++ hhi = syscon_regmap_lookup_by_compatible("amlogic,meson-gx-hhi-sysctrl"); ++ if (IS_ERR(hhi)) ++ return dev_err_probe(dev, PTR_ERR(hhi), ++ "Failed to get the \"amlogic,meson-gx-hhi-sysctrl\" syscon\n"); ++ } ++ ++ if (priv->data->needs_cvbs_trimming_nvmem_cell) { ++ ret = phy_meson_cvbs_read_trimming(dev, priv); ++ if (ret) ++ return ret; ++ } ++ ++ ret = devm_regmap_field_bulk_alloc(dev, hhi, priv->regs, ++ priv->data->reg_fields, ++ MESON_CVBS_DAC_NUM_REGS); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "Failed to create regmap fields\n"); ++ ++ phy = devm_phy_create(dev, np, &phy_meson_cvbs_dac_ops); ++ if (IS_ERR(phy)) ++ return PTR_ERR(phy); ++ ++ phy_set_drvdata(phy, priv); ++ ++ if (np) { ++ phy_provider = devm_of_phy_provider_register(dev, ++ of_phy_simple_xlate); ++ ret = PTR_ERR_OR_ZERO(phy_provider); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "Failed to register PHY provider\n"); ++ } else { ++ platform_set_drvdata(pdev, phy); ++ } ++ ++ return 0; ++} ++ ++static const struct of_device_id phy_meson_cvbs_dac_of_match[] = { ++ { ++ .compatible = "amlogic,meson8-cvbs-dac", ++ .data = &phy_meson8_cvbs_dac_data, ++ }, ++ { ++ .compatible = "amlogic,meson8b-cvbs-dac", ++ .data = &phy_meson8_cvbs_dac_data, ++ }, ++ { ++ .compatible = "amlogic,meson-gxbb-cvbs-dac", ++ .data = &phy_meson_gxbb_cvbs_dac_data, ++ }, ++ { ++ .compatible = "amlogic,meson-gxl-cvbs-dac", ++ .data = &phy_meson_gxl_cvbs_dac_data, ++ }, ++ { ++ .compatible = "amlogic,meson-g12a-cvbs-dac", ++ .data = &phy_meson_g12a_cvbs_dac_data, ++ }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, phy_meson_cvbs_dac_of_match); ++ ++/* ++ * The platform_device_id table is used for backwards compatibility with old ++ * .dtbs which don't have a CVBS DAC node (where the VPU DRM driver registers ++ * this as a platform device. Support for additional SoCs should only be added ++ * to the of_device_id table above. ++ */ ++static const struct platform_device_id phy_meson_cvbs_dac_device_ids[] = { ++ { ++ .name = "meson-gxbb-cvbs-dac", ++ .driver_data = (kernel_ulong_t)&phy_meson_gxbb_cvbs_dac_data, ++ }, ++ { ++ .name = "meson-gxl-cvbs-dac", ++ .driver_data = (kernel_ulong_t)&phy_meson_gxl_cvbs_dac_data, ++ }, ++ { ++ .name = "meson-g12a-cvbs-dac", ++ .driver_data = (kernel_ulong_t)&phy_meson_g12a_cvbs_dac_data, ++ }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(platform, phy_meson_cvbs_dac_device_ids); ++ ++static struct platform_driver phy_meson_cvbs_dac_driver = { ++ .driver = { ++ .name = "phy-meson-cvbs-dac", ++ .of_match_table = phy_meson_cvbs_dac_of_match, ++ }, ++ .id_table = phy_meson_cvbs_dac_device_ids, ++ .probe = phy_meson_cvbs_dac_probe, ++}; ++module_platform_driver(phy_meson_cvbs_dac_driver); ++ ++MODULE_AUTHOR("Martin Blumenstingl "); ++MODULE_DESCRIPTION("Amlogic Meson CVBS DAC driver"); ++MODULE_LICENSE("GPL v2"); +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0015-dt-bindings-display-meson-vpu-Add-the-CVBS-DAC-prope.patch b/patch/kernel/archive/meson-6.9/0015-dt-bindings-display-meson-vpu-Add-the-CVBS-DAC-prope.patch new file mode 100644 index 000000000000..2334fe18f030 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0015-dt-bindings-display-meson-vpu-Add-the-CVBS-DAC-prope.patch @@ -0,0 +1,49 @@ +From 3b2d4e35f9726027f7fe3c0c10dae8e86169ba39 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Wed, 20 Oct 2021 22:19:25 +0200 +Subject: [PATCH 15/96] dt-bindings: display: meson-vpu: Add the CVBS DAC + properties + +The CVBS DAC converts the digital video signal to the (analog) composite +video baseband signal (CVBS). This DAC is part of the HHI registers. +Add the phy and phy-names property to describe the relation between the +VPU (which outputs the digital signal) and the CVBS DAC. + +Signed-off-by: Martin Blumenstingl +--- + .../bindings/display/amlogic,meson-vpu.yaml | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml +index cb0a90f02..c9ab01434 100644 +--- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml ++++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml +@@ -82,6 +82,15 @@ properties: + description: should point to a canvas provider node + $ref: /schemas/types.yaml#/definitions/phandle + ++ phys: ++ maxItems: 1 ++ description: ++ PHY specifier for the CVBS DAC ++ ++ phy-names: ++ items: ++ - const: cvbs-dac ++ + power-domains: + maxItems: 1 + description: phandle to the associated power domain +@@ -130,6 +139,9 @@ examples: + #size-cells = <0>; + amlogic,canvas = <&canvas>; + ++ phys = <&cvbs_dac_phy>; ++ phy-names = "cvbs-dac"; ++ + /* CVBS VDAC output port */ + port@0 { + reg = <0>; +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0016-drm-meson-Add-support-for-using-a-PHY-for-the-CVBS-D.patch b/patch/kernel/archive/meson-6.9/0016-drm-meson-Add-support-for-using-a-PHY-for-the-CVBS-D.patch new file mode 100644 index 000000000000..09cc670ba1a7 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0016-drm-meson-Add-support-for-using-a-PHY-for-the-CVBS-D.patch @@ -0,0 +1,317 @@ +From 8f9b70c8b353b2140e78d5aba6141b313d603e12 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 25 Apr 2020 22:06:53 +0200 +Subject: [PATCH 16/96] drm/meson: Add support for using a PHY for the CVBS DAC + +Currently the VPU driver hardcodes the initialization, power-on and +power-off sequences for the CVBS DAC. The registers for the CVBS DAC are +in the HHI register area. Also the CVBS DAC is a PHY so it can be +modelled as such. Add support for using a PHY as CVBS DAC to de-couple +the VPU driver from the HHI registers (at least for this part of the +implementation). +Register a platform device for the PHY (which creates a lookup entry to +compensate for the missing .dtb entry) which takes over all +HHI_VDAC_CNTL register management. + +Signed-off-by: Martin Blumenstingl +--- + drivers/gpu/drm/meson/Kconfig | 1 + + drivers/gpu/drm/meson/meson_drv.h | 6 + + drivers/gpu/drm/meson/meson_encoder_cvbs.c | 132 ++++++++++++++++----- + drivers/gpu/drm/meson/meson_venc.c | 13 -- + 4 files changed, 110 insertions(+), 42 deletions(-) + +diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig +index 615fdd0ce..47e920105 100644 +--- a/drivers/gpu/drm/meson/Kconfig ++++ b/drivers/gpu/drm/meson/Kconfig +@@ -10,6 +10,7 @@ config DRM_MESON + select REGMAP_MMIO + select MESON_CANVAS + select CEC_CORE if CEC_NOTIFIER ++ imply PHY_MESON_CVBS_DAC + + config DRM_MESON_DW_HDMI + tristate "HDMI Synopsys Controller support for Amlogic Meson Display" +diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h +index 3f9345c14..69be4c67f 100644 +--- a/drivers/gpu/drm/meson/meson_drv.h ++++ b/drivers/gpu/drm/meson/meson_drv.h +@@ -16,6 +16,8 @@ struct drm_device; + struct drm_plane; + struct meson_drm; + struct meson_afbcd_ops; ++struct phy; ++struct platform_device; + + enum vpu_compatible { + VPU_COMPATIBLE_GXBB = 0, +@@ -61,6 +63,10 @@ struct meson_drm { + + const struct meson_drm_soc_limits *limits; + ++ struct phy *cvbs_dac; ++ bool cvbs_dac_enabled; ++ struct platform_device *cvbs_dac_pdev; ++ + /* Components Data */ + struct { + bool osd1_enabled; +diff --git a/drivers/gpu/drm/meson/meson_encoder_cvbs.c b/drivers/gpu/drm/meson/meson_encoder_cvbs.c +index d1191de85..f849e0f85 100644 +--- a/drivers/gpu/drm/meson/meson_encoder_cvbs.c ++++ b/drivers/gpu/drm/meson/meson_encoder_cvbs.c +@@ -11,6 +11,8 @@ + + #include + #include ++#include ++#include + + #include + #include +@@ -24,12 +26,6 @@ + #include "meson_vclk.h" + #include "meson_encoder_cvbs.h" + +-/* HHI VDAC Registers */ +-#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ +-#define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbd offset in data sheet */ +-#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ +-#define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbe offset in data sheet */ +- + struct meson_encoder_cvbs { + struct drm_encoder encoder; + struct drm_bridge bridge; +@@ -87,11 +83,28 @@ static int meson_encoder_cvbs_attach(struct drm_bridge *bridge, + { + struct meson_encoder_cvbs *meson_encoder_cvbs = + bridge_to_meson_encoder_cvbs(bridge); ++ int ret; ++ ++ ret = phy_init(meson_encoder_cvbs->priv->cvbs_dac); ++ if (ret) ++ return ret; + + return drm_bridge_attach(bridge->encoder, meson_encoder_cvbs->next_bridge, + &meson_encoder_cvbs->bridge, flags); + } + ++static void meson_encoder_cvbs_detach(struct drm_bridge *bridge) ++{ ++ struct meson_encoder_cvbs *meson_encoder_cvbs = ++ bridge_to_meson_encoder_cvbs(bridge); ++ int ret; ++ ++ ret = phy_exit(meson_encoder_cvbs->priv->cvbs_dac); ++ if (ret) ++ dev_err(meson_encoder_cvbs->priv->dev, ++ "Failed to exit the CVBS DAC\n"); ++} ++ + static int meson_encoder_cvbs_get_modes(struct drm_bridge *bridge, + struct drm_connector *connector) + { +@@ -148,6 +161,7 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge, + struct drm_connector_state *conn_state; + struct drm_crtc_state *crtc_state; + struct drm_connector *connector; ++ int ret; + + connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); + if (WARN_ON(!connector)) +@@ -177,16 +191,13 @@ static void meson_encoder_cvbs_atomic_enable(struct drm_bridge *bridge, + writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0, + priv->io_base + _REG(VENC_VDAC_DACSEL0)); + +- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) { +- regmap_write(priv->hhi, HHI_VDAC_CNTL0, 1); +- regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0); +- } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) || +- meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) { +- regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0xf0001); +- regmap_write(priv->hhi, HHI_VDAC_CNTL1, 0); +- } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { +- regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0x906001); +- regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); ++ if (!priv->cvbs_dac_enabled) { ++ ret = phy_power_on(priv->cvbs_dac); ++ if (ret) ++ dev_err(priv->dev, ++ "Failed to power on the CVBS DAC\n"); ++ else ++ priv->cvbs_dac_enabled = true; + } + } + +@@ -196,19 +207,22 @@ static void meson_encoder_cvbs_atomic_disable(struct drm_bridge *bridge, + struct meson_encoder_cvbs *meson_encoder_cvbs = + bridge_to_meson_encoder_cvbs(bridge); + struct meson_drm *priv = meson_encoder_cvbs->priv; ++ int ret; + +- /* Disable CVBS VDAC */ +- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { +- regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); +- regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 0); +- } else { +- regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); +- regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); +- } ++ if (!priv->cvbs_dac_enabled) ++ return; ++ ++ ret = phy_power_off(priv->cvbs_dac); ++ if (ret) ++ dev_err(priv->dev, ++ "Failed to power off the CVBS DAC\n"); ++ else ++ priv->cvbs_dac_enabled = false; + } + + static const struct drm_bridge_funcs meson_encoder_cvbs_bridge_funcs = { + .attach = meson_encoder_cvbs_attach, ++ .detach = meson_encoder_cvbs_detach, + .mode_valid = meson_encoder_cvbs_mode_valid, + .get_modes = meson_encoder_cvbs_get_modes, + .atomic_enable = meson_encoder_cvbs_atomic_enable, +@@ -219,6 +233,54 @@ static const struct drm_bridge_funcs meson_encoder_cvbs_bridge_funcs = { + .atomic_reset = drm_atomic_helper_bridge_reset, + }; + ++static int meson_cvbs_dac_probe(struct meson_drm *priv) ++{ ++ struct platform_device *pdev; ++ const char *platform_id_name; ++ ++ priv->cvbs_dac = devm_phy_optional_get(priv->dev, "cvbs-dac"); ++ if (IS_ERR(priv->cvbs_dac)) ++ return dev_err_probe(priv->dev, PTR_ERR(priv->cvbs_dac), ++ "Failed to get the 'cvbs-dac' PHY\n"); ++ else if (priv->cvbs_dac) ++ return 0; ++ ++ switch (priv->compat) { ++ case VPU_COMPATIBLE_GXBB: ++ platform_id_name = "meson-gxbb-cvbs-dac"; ++ break; ++ case VPU_COMPATIBLE_GXL: ++ case VPU_COMPATIBLE_GXM: ++ platform_id_name = "meson-gxl-cvbs-dac"; ++ break; ++ case VPU_COMPATIBLE_G12A: ++ platform_id_name = "meson-g12a-cvbs-dac"; ++ break; ++ default: ++ return dev_err_probe(priv->dev, -EINVAL, ++ "No CVBS DAC platform ID found\n"); ++ } ++ ++ pdev = platform_device_register_data(priv->dev, platform_id_name, ++ PLATFORM_DEVID_AUTO, NULL, 0); ++ if (IS_ERR(pdev)) ++ return dev_err_probe(priv->dev, PTR_ERR(pdev), ++ "Failed to register fallback CVBS DAC PHY platform device\n"); ++ ++ priv->cvbs_dac = platform_get_drvdata(pdev); ++ if (IS_ERR(priv->cvbs_dac)) { ++ platform_device_unregister(pdev); ++ return dev_err_probe(priv->dev, PTR_ERR(priv->cvbs_dac), ++ "Failed to get the 'cvbs-dac' PHY from it's platform device\n"); ++ } ++ ++ dev_info(priv->dev, "Using fallback for old .dtbs without CVBS DAC\n"); ++ ++ priv->cvbs_dac_pdev = pdev; ++ ++ return 0; ++} ++ + int meson_encoder_cvbs_probe(struct meson_drm *priv) + { + struct drm_device *drm = priv->drm; +@@ -255,6 +317,10 @@ int meson_encoder_cvbs_probe(struct meson_drm *priv) + + meson_encoder_cvbs->priv = priv; + ++ ret = meson_cvbs_dac_probe(priv); ++ if (ret) ++ return ret; ++ + /* Encoder */ + ret = drm_simple_encoder_init(priv->drm, &meson_encoder_cvbs->encoder, + DRM_MODE_ENCODER_TVDAC); +@@ -268,21 +334,27 @@ int meson_encoder_cvbs_probe(struct meson_drm *priv) + ret = drm_bridge_attach(&meson_encoder_cvbs->encoder, &meson_encoder_cvbs->bridge, NULL, + DRM_BRIDGE_ATTACH_NO_CONNECTOR); + if (ret) { +- dev_err(priv->dev, "Failed to attach bridge: %d\n", ret); +- return ret; ++ dev_err_probe(priv->dev, ret, "Failed to attach bridge\n"); ++ goto err_unregister_cvbs_dac_pdev; + } + + /* Initialize & attach Bridge Connector */ + connector = drm_bridge_connector_init(priv->drm, &meson_encoder_cvbs->encoder); +- if (IS_ERR(connector)) +- return dev_err_probe(priv->dev, PTR_ERR(connector), +- "Unable to create CVBS bridge connector\n"); ++ if (IS_ERR(connector)) { ++ ret = dev_err_probe(priv->dev, PTR_ERR(connector), ++ "Unable to create CVBS bridge connector\n"); ++ goto err_unregister_cvbs_dac_pdev; ++ } + + drm_connector_attach_encoder(connector, &meson_encoder_cvbs->encoder); + + priv->encoders[MESON_ENC_CVBS] = meson_encoder_cvbs; + + return 0; ++ ++err_unregister_cvbs_dac_pdev: ++ platform_device_unregister(priv->cvbs_dac_pdev); ++ return ret; + } + + void meson_encoder_cvbs_remove(struct meson_drm *priv) +@@ -293,4 +365,6 @@ void meson_encoder_cvbs_remove(struct meson_drm *priv) + meson_encoder_cvbs = priv->encoders[MESON_ENC_CVBS]; + drm_bridge_remove(&meson_encoder_cvbs->bridge); + } ++ ++ platform_device_unregister(priv->cvbs_dac_pdev); + } +diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c +index 3bf0d6e4f..5efd7a298 100644 +--- a/drivers/gpu/drm/meson/meson_venc.c ++++ b/drivers/gpu/drm/meson/meson_venc.c +@@ -62,10 +62,6 @@ + + /* HHI Registers */ + #define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */ +-#define HHI_VDAC_CNTL0 0x2F4 /* 0xbd offset in data sheet */ +-#define HHI_VDAC_CNTL0_G12A 0x2EC /* 0xbb offset in data sheet */ +-#define HHI_VDAC_CNTL1 0x2F8 /* 0xbe offset in data sheet */ +-#define HHI_VDAC_CNTL1_G12A 0x2F0 /* 0xbc offset in data sheet */ + #define HHI_HDMI_PHY_CNTL0 0x3a0 /* 0xe8 offset in data sheet */ + + struct meson_cvbs_enci_mode meson_cvbs_enci_pal = { +@@ -1968,15 +1964,6 @@ void meson_venc_disable_vsync(struct meson_drm *priv) + + void meson_venc_init(struct meson_drm *priv) + { +- /* Disable CVBS VDAC */ +- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { +- regmap_write(priv->hhi, HHI_VDAC_CNTL0_G12A, 0); +- regmap_write(priv->hhi, HHI_VDAC_CNTL1_G12A, 8); +- } else { +- regmap_write(priv->hhi, HHI_VDAC_CNTL0, 0); +- regmap_write(priv->hhi, HHI_VDAC_CNTL1, 8); +- } +- + /* Power Down Dacs */ + writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING)); + +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0018-dt-bindings-clock-meson8b-Add-the-RMII-reference-clo.patch b/patch/kernel/archive/meson-6.9/0018-dt-bindings-clock-meson8b-Add-the-RMII-reference-clo.patch new file mode 100644 index 000000000000..88dba3105ada --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0018-dt-bindings-clock-meson8b-Add-the-RMII-reference-clo.patch @@ -0,0 +1,31 @@ +From 182a6e3ae155fe2a0d9f4380c8f46b531d8e867b Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Fri, 1 May 2020 23:16:07 +0200 +Subject: [PATCH 18/96] dt-bindings: clock: meson8b: Add the RMII reference + clock input + +Amlogic Meson8 SoCs need an external 50MHz RMII reference clock. This is +either provided by the Ethernet PHY or an external oscillator. Add the +documentation for this clock input. + +Signed-off-by: Martin Blumenstingl +--- + .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +index cc51e4746..a2602b5d5 100644 +--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt ++++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +@@ -16,6 +16,8 @@ Required Properties: + * "xtal": the 24MHz system oscillator + * "ddr_pll": the DDR PLL clock + * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN) ++ * "rmii_clk": (if present) the 50MHz RMII reference clock (from the PHY or ++ an external oscillator + + Parent node should have the following properties : + - compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0019-dt-bindings-clock-meson8b-Add-the-Meson8-Ethernet-RM.patch b/patch/kernel/archive/meson-6.9/0019-dt-bindings-clock-meson8b-Add-the-Meson8-Ethernet-RM.patch new file mode 100644 index 000000000000..a53bfa7f0224 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0019-dt-bindings-clock-meson8b-Add-the-Meson8-Ethernet-RM.patch @@ -0,0 +1,31 @@ +From 2b1a5a4937e6de3aeba31fdd96946ff66d3c1608 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Fri, 1 May 2020 23:23:49 +0200 +Subject: [PATCH 19/96] dt-bindings: clock: meson8b: Add the Meson8 Ethernet + (RMII) clocks + +Export CLKID_ETH_CLK (and it's parents) because it is used as input for +the Ethernet controller on Meson8 SoCs. + +Signed-off-by: Martin Blumenstingl +--- + include/dt-bindings/clock/meson8b-clkc.h | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h +index 385bf243c..a09b686af 100644 +--- a/include/dt-bindings/clock/meson8b-clkc.h ++++ b/include/dt-bindings/clock/meson8b-clkc.h +@@ -221,5 +221,9 @@ + #define CLKID_VCLK2_EN 215 + #define CLKID_VID_PLL_LVDS_EN 216 + #define CLKID_HDMI_PLL_DCO_IN 217 ++#define CLKID_ETH_CLK_SEL 218 ++#define CLKID_ETH_CLK_DIV 219 ++#define CLKID_ETH_CLK_PHASE 220 ++#define CLKID_ETH_CLK 221 + + #endif /* __MESON8B_CLKC_H */ +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0020-clk-meson-meson8b-Add-the-Ethernet-RMII-clock-tree-o.patch b/patch/kernel/archive/meson-6.9/0020-clk-meson-meson8b-Add-the-Ethernet-RMII-clock-tree-o.patch new file mode 100644 index 000000000000..872d7855ed1c --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0020-clk-meson-meson8b-Add-the-Ethernet-RMII-clock-tree-o.patch @@ -0,0 +1,166 @@ +From 1336f3b73beada616ef72126e736598e4503fbe0 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Fri, 1 May 2020 23:25:13 +0200 +Subject: [PATCH 20/96] clk: meson: meson8b: Add the Ethernet (RMII) clock tree + on Meson8 +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Add the Ethernet clock tree on Meson8 which consists of: +- an input mux - the only known input is the RMII reference clock signal + which is an input on one of the SoC's pads +- a divider +- 0° or 180° phase change +- a gate to enable/disable the clock + +Add these clocks only for Meson8 because they're only known to be used +there. + +Signed-off-by: Martin Blumenstingl +--- + drivers/clk/meson/Kconfig | 1 + + drivers/clk/meson/meson8b.c | 81 +++++++++++++++++++++++++++++++++++++ + drivers/clk/meson/meson8b.h | 1 + + 3 files changed, 83 insertions(+) + +diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig +index 29ffd14d2..03e99ee3c 100644 +--- a/drivers/clk/meson/Kconfig ++++ b/drivers/clk/meson/Kconfig +@@ -55,6 +55,7 @@ config COMMON_CLK_MESON8B + select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS + select COMMON_CLK_MESON_MPLL ++ select COMMON_CLK_MESON_PHASE + select COMMON_CLK_MESON_PLL + select MFD_SYSCON + select RESET_CONTROLLER +diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c +index b7417ac26..8128e0864 100644 +--- a/drivers/clk/meson/meson8b.c ++++ b/drivers/clk/meson/meson8b.c +@@ -19,6 +19,7 @@ + #include "meson8b.h" + #include "clk-regmap.h" + #include "meson-clkc-utils.h" ++#include "clk-phase.h" + #include "clk-pll.h" + #include "clk-mpll.h" + +@@ -2682,6 +2683,78 @@ static struct clk_regmap meson8b_cts_i958 = { + }, + }; + ++static u32 meson8_eth_clk_mux_table[] = { 7 }; ++ ++static struct clk_regmap meson8_eth_clk_sel = { ++ .data = &(struct clk_regmap_mux_data) { ++ .offset = HHI_ETH_CLK_CNTL, ++ .mask = 0x7, ++ .shift = 9, ++ .table = meson8_eth_clk_mux_table, ++ }, ++ .hw.init = &(struct clk_init_data) { ++ .name = "eth_clk_sel", ++ .ops = &clk_regmap_mux_ops, ++ .parent_data = &(const struct clk_parent_data) { ++ /* TODO: all other parents are unknown */ ++ .fw_name = "rmii_clk", ++ }, ++ .num_parents = 1, ++ }, ++}; ++ ++static struct clk_regmap meson8_eth_clk_div = { ++ .data = &(struct clk_regmap_div_data) { ++ .offset = HHI_ETH_CLK_CNTL, ++ .shift = 0, ++ .width = 8, ++ }, ++ .hw.init = &(struct clk_init_data) { ++ .name = "eth_clk_div", ++ .ops = &clk_regmap_divider_ops, ++ .parent_hws = (const struct clk_hw *[]) { ++ &meson8_eth_clk_sel.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static struct clk_regmap meson8_eth_clk_phase = { ++ .data = &(struct meson_clk_phase_data) { ++ .ph = { ++ .reg_off = HHI_ETH_CLK_CNTL, ++ .shift = 14, ++ .width = 1, ++ }, ++ }, ++ .hw.init = &(struct clk_init_data){ ++ .name = "eth_clk_inverted", ++ .ops = &meson_clk_phase_ops, ++ .parent_hws = (const struct clk_hw *[]) { ++ &meson8_eth_clk_div.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ ++static struct clk_regmap meson8_eth_clk_gate = { ++ .data = &(struct clk_regmap_gate_data) { ++ .offset = HHI_ETH_CLK_CNTL, ++ .bit_idx = 8, ++ }, ++ .hw.init = &(struct clk_init_data){ ++ .name = "eth_clk_en", ++ .ops = &clk_regmap_gate_ops, ++ .parent_hws = (const struct clk_hw *[]) { ++ &meson8_eth_clk_phase.hw ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ }, ++}; ++ + #define MESON_GATE(_name, _reg, _bit) \ + MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw) + +@@ -2978,6 +3051,10 @@ static struct clk_hw *meson8_hw_clks[] = { + [CLKID_CTS_I958] = &meson8b_cts_i958.hw, + [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, + [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, ++ [CLKID_ETH_CLK_SEL] = &meson8_eth_clk_sel.hw, ++ [CLKID_ETH_CLK_DIV] = &meson8_eth_clk_div.hw, ++ [CLKID_ETH_CLK_PHASE] = &meson8_eth_clk_phase.hw, ++ [CLKID_ETH_CLK] = &meson8_eth_clk_gate.hw, + }; + + static struct clk_hw *meson8b_hw_clks[] = { +@@ -3606,6 +3683,10 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { + &meson8b_cts_mclk_i958, + &meson8b_cts_i958, + &meson8b_vid_pll_lvds_en, ++ &meson8_eth_clk_sel, ++ &meson8_eth_clk_div, ++ &meson8_eth_clk_phase, ++ &meson8_eth_clk_gate, + }; + + static const struct meson8b_clk_reset_line { +diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h +index a5b6e67ee..dfec963d4 100644 +--- a/drivers/clk/meson/meson8b.h ++++ b/drivers/clk/meson/meson8b.h +@@ -43,6 +43,7 @@ + #define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */ + #define HHI_VPU_CLK_CNTL 0x1bc /* 0x6f offset in data sheet */ + #define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */ ++#define HHI_ETH_CLK_CNTL 0x1d8 /* 0x76 offset in data sheet */ + #define HHI_VDEC_CLK_CNTL 0x1e0 /* 0x78 offset in data sheet */ + #define HHI_VDEC2_CLK_CNTL 0x1e4 /* 0x79 offset in data sheet */ + #define HHI_VDEC3_CLK_CNTL 0x1e8 /* 0x7a offset in data sheet */ +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0021-dt-bindings-net-dwmac-meson-Add-the-Ethernet-clock-i.patch b/patch/kernel/archive/meson-6.9/0021-dt-bindings-net-dwmac-meson-Add-the-Ethernet-clock-i.patch new file mode 100644 index 000000000000..ef790577de25 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0021-dt-bindings-net-dwmac-meson-Add-the-Ethernet-clock-i.patch @@ -0,0 +1,52 @@ +From a2f6824d3140baec1ba1b0748b0b3ee08f083185 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Fri, 1 May 2020 23:37:35 +0200 +Subject: [PATCH 21/96] dt-bindings: net: dwmac-meson: Add the Ethernet clock + input for Meson6/8 + +The additional DWMAC register on Amlogic Meson6 and Meson8 SoCs take a +clock input (which is provided by the HHI clock controller). For RMII +mode this clock is derived from the RMII reference clock. Document this +clock input so the clock can be enabled when needed. + +Signed-off-by: Martin Blumenstingl +--- + .../bindings/net/amlogic,meson-dwmac.yaml | 22 +++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml +index ee7a65b52..ea4b75ef6 100644 +--- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml ++++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml +@@ -127,6 +127,28 @@ allOf: + - 2800 + - 3000 + ++ - if: ++ properties: ++ compatible: ++ contains: ++ enum: ++ - amlogic,meson6-dwmac ++ then: ++ properties: ++ clocks: ++ minItems: 1 ++ maxItems: 2 ++ items: ++ - description: GMAC main clock ++ - description: The RMII reference clock ++ ++ clock-names: ++ minItems: 1 ++ maxItems: 2 ++ items: ++ - const: stmmaceth ++ - const: ethernet ++ + properties: + compatible: + additionalItems: true +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0022-net-stmmac-dwmac-meson-Rename-the-SPEED_100-macro.patch b/patch/kernel/archive/meson-6.9/0022-net-stmmac-dwmac-meson-Rename-the-SPEED_100-macro.patch new file mode 100644 index 000000000000..c44a2a262142 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0022-net-stmmac-dwmac-meson-Rename-the-SPEED_100-macro.patch @@ -0,0 +1,44 @@ +From 237a072d8b71eecddce1f9ec7dda2ae7a46f27bf Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 25 Dec 2021 04:07:05 +0100 +Subject: [PATCH 22/96] net: stmmac: dwmac-meson: Rename the SPEED_100 macro + +The SPEED_100 macro is part of the PREG_ETHERNET_ADDR0 register. Rename +it accordingly to make this relationship clear. +While here also add a comment what the SPEED_100 bit actually does. + +Signed-off-by: Martin Blumenstingl +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c | 7 ++++--- + 1 file changed, 4 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c +index a16bfa908..919c41e15 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c +@@ -15,7 +15,8 @@ + + #include "stmmac_platform.h" + +-#define ETHMAC_SPEED_100 BIT(1) ++/* divides the input clock by 20 (= 0x0) or 2 (= 0x1) */ ++#define PREG_ETHERNET_ADDR0_SPEED_100 BIT(1) + + struct meson_dwmac { + struct device *dev; +@@ -31,10 +32,10 @@ static void meson6_dwmac_fix_mac_speed(void *priv, unsigned int speed, unsigned + + switch (speed) { + case SPEED_10: +- val &= ~ETHMAC_SPEED_100; ++ val &= ~PREG_ETHERNET_ADDR0_SPEED_100; + break; + case SPEED_100: +- val |= ETHMAC_SPEED_100; ++ val |= PREG_ETHERNET_ADDR0_SPEED_100; + break; + } + +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0023-net-stmmac-dwmac-meson-Manage-the-ethernet-clock.patch b/patch/kernel/archive/meson-6.9/0023-net-stmmac-dwmac-meson-Manage-the-ethernet-clock.patch new file mode 100644 index 000000000000..78c79f1d405b --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0023-net-stmmac-dwmac-meson-Manage-the-ethernet-clock.patch @@ -0,0 +1,117 @@ +From 6cfa3555ebbfd9cfab319352f436ae9d7f0ffdea Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 25 Dec 2021 04:22:53 +0100 +Subject: [PATCH 23/96] net: stmmac: dwmac-meson: Manage the "ethernet" clock + +Meson6 and Meson8 (both use the same glue registers on top of the DWMAC +IP) have a dedicated Ethernet clock. For RMII mode the SoC has an input +for an external RMII reference clock signal (which can be provided by +either the PHY or an external oscillator). This clock needs to run at +50MHz because the additional glue registers can divide by 2 - to achieve +25MHz for 100Mbit/s line speed, or 20 - to achieve 2.5MHz for 10Mbit/s +line speed. + +Set the correct frequency for this clock and enable it during init. Also +enable the ETHMAC_DIV_EN bit which enables the divider in the glue +registers, based on the Ethernet clock input. + +Signed-off-by: Martin Blumenstingl +--- + .../net/ethernet/stmicro/stmmac/dwmac-meson.c | 51 ++++++++++++++++++- + 1 file changed, 50 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c +index 919c41e15..2361734e3 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c +@@ -5,6 +5,7 @@ + * Copyright (C) 2014 Beniamino Galvani + */ + ++#include + #include + #include + #include +@@ -15,12 +16,15 @@ + + #include "stmmac_platform.h" + ++#define PREG_ETHERNET_ADDR0_DIV_EN BIT(0) ++ + /* divides the input clock by 20 (= 0x0) or 2 (= 0x1) */ + #define PREG_ETHERNET_ADDR0_SPEED_100 BIT(1) + + struct meson_dwmac { + struct device *dev; + void __iomem *reg; ++ struct clk *ethernet_clk; + }; + + static void meson6_dwmac_fix_mac_speed(void *priv, unsigned int speed, unsigned int mode) +@@ -42,6 +46,33 @@ static void meson6_dwmac_fix_mac_speed(void *priv, unsigned int speed, unsigned + writel(val, dwmac->reg); + } + ++static int meson6_dwmac_init(struct platform_device *pdev, void *priv) ++{ ++ struct meson_dwmac *dwmac = priv; ++ int ret; ++ ++ ret = clk_set_rate(dwmac->ethernet_clk, 50 * 1000 * 1000); ++ if (ret) ++ return ret; ++ ++ ret = clk_prepare_enable(dwmac->ethernet_clk); ++ if (ret) ++ return ret; ++ ++ writel(readl(dwmac->reg) | PREG_ETHERNET_ADDR0_DIV_EN, dwmac->reg); ++ ++ return 0; ++} ++ ++static void meson6_dwmac_exit(struct platform_device *pdev, void *priv) ++{ ++ struct meson_dwmac *dwmac = priv; ++ ++ writel(readl(dwmac->reg) & ~PREG_ETHERNET_ADDR0_DIV_EN, dwmac->reg); ++ ++ clk_disable_unprepare(dwmac->ethernet_clk); ++} ++ + static int meson6_dwmac_probe(struct platform_device *pdev) + { + struct plat_stmmacenet_data *plat_dat; +@@ -65,10 +96,28 @@ static int meson6_dwmac_probe(struct platform_device *pdev) + if (IS_ERR(dwmac->reg)) + return PTR_ERR(dwmac->reg); + ++ dwmac->ethernet_clk = devm_clk_get_optional(&pdev->dev, "ethernet"); ++ if (IS_ERR(dwmac->ethernet_clk)) ++ return PTR_ERR(dwmac->ethernet_clk); ++ + plat_dat->bsp_priv = dwmac; ++ plat_dat->init = meson6_dwmac_init; ++ plat_dat->exit = meson6_dwmac_exit; + plat_dat->fix_mac_speed = meson6_dwmac_fix_mac_speed; + +- return stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); ++ ret = meson6_dwmac_init(pdev, dwmac); ++ if (ret) ++ return ret; ++ ++ ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); ++ if (ret) ++ goto err_exit_dwmac; ++ ++ return 0; ++ ++err_exit_dwmac: ++ meson6_dwmac_exit(pdev, dwmac); ++ return ret; + } + + static const struct of_device_id meson6_dwmac_match[] = { +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0024-net-stmmac-dwmac-meson-Initialize-all-known-PREG_ETH.patch b/patch/kernel/archive/meson-6.9/0024-net-stmmac-dwmac-meson-Initialize-all-known-PREG_ETH.patch new file mode 100644 index 000000000000..1574f9eb2b97 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0024-net-stmmac-dwmac-meson-Initialize-all-known-PREG_ETH.patch @@ -0,0 +1,76 @@ +From 259fca64ab9ea66d43f6bd82584768fb0767789b Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 25 Dec 2021 04:18:30 +0100 +Subject: [PATCH 24/96] net: stmmac: dwmac-meson: Initialize all known + PREG_ETHERNET_ADDR0 bits + +Initialize all known PREG_ETHERNET_ADDR0 register bits to be less +dependent on the bootloader to set them up correctly. + +Signed-off-by: Martin Blumenstingl +--- + .../net/ethernet/stmicro/stmmac/dwmac-meson.c | 25 ++++++++++++++++--- + 1 file changed, 22 insertions(+), 3 deletions(-) + +diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c +index 2361734e3..b96aa4d39 100644 +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-meson.c +@@ -5,6 +5,7 @@ + * Copyright (C) 2014 Beniamino Galvani + */ + ++#include + #include + #include + #include +@@ -16,10 +17,20 @@ + + #include "stmmac_platform.h" + +-#define PREG_ETHERNET_ADDR0_DIV_EN BIT(0) ++#define PREG_ETHERNET_ADDR0_DIV_EN BIT(0) + + /* divides the input clock by 20 (= 0x0) or 2 (= 0x1) */ +-#define PREG_ETHERNET_ADDR0_SPEED_100 BIT(1) ++#define PREG_ETHERNET_ADDR0_SPEED_100 BIT(1) ++ ++/* 0x0 = little, 0x1 = big */ ++#define PREG_ETHERNET_ADDR0_DATA_ENDIANNESS BIT(2) ++ ++/* 0x0 = same order, 0x1: unknown */ ++#define PREG_ETHERNET_ADDR0_DESC_ENDIANNESS BIT(3) ++ ++#define PREG_ETHERNET_ADDR0_MII_MODE GENMASK(6, 4) ++#define PREG_ETHERNET_ADDR0_MII_MODE_RGMII 0x1 ++#define PREG_ETHERNET_ADDR0_MII_MODE_RMII 0x4 + + struct meson_dwmac { + struct device *dev; +@@ -49,6 +60,7 @@ static void meson6_dwmac_fix_mac_speed(void *priv, unsigned int speed, unsigned + static int meson6_dwmac_init(struct platform_device *pdev, void *priv) + { + struct meson_dwmac *dwmac = priv; ++ u32 val; + int ret; + + ret = clk_set_rate(dwmac->ethernet_clk, 50 * 1000 * 1000); +@@ -59,7 +71,14 @@ static int meson6_dwmac_init(struct platform_device *pdev, void *priv) + if (ret) + return ret; + +- writel(readl(dwmac->reg) | PREG_ETHERNET_ADDR0_DIV_EN, dwmac->reg); ++ val = readl(dwmac->reg); ++ val &= ~PREG_ETHERNET_ADDR0_DATA_ENDIANNESS; ++ val &= ~PREG_ETHERNET_ADDR0_DESC_ENDIANNESS; ++ val &= ~PREG_ETHERNET_ADDR0_MII_MODE; ++ val |= FIELD_PREP(PREG_ETHERNET_ADDR0_MII_MODE, ++ PREG_ETHERNET_ADDR0_MII_MODE_RMII); ++ val |= PREG_ETHERNET_ADDR0_DIV_EN; ++ writel(val, dwmac->reg); + + return 0; + } +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0025-ARM-dts-meson-meson8-Add-the-clock-input-to-the-Ethe.patch b/patch/kernel/archive/meson-6.9/0025-ARM-dts-meson-meson8-Add-the-clock-input-to-the-Ethe.patch new file mode 100644 index 000000000000..914dac6c1621 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0025-ARM-dts-meson-meson8-Add-the-clock-input-to-the-Ethe.patch @@ -0,0 +1,34 @@ +From e1e3ba72f71b31abadff7ce2443b3cdeafbdacf1 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Fri, 1 May 2020 23:47:47 +0200 +Subject: [PATCH 25/96] ARM: dts: meson: meson8: Add the clock input to the + Ethernet controller + +The Ethernet controller on Meson8 has an additional clock input from the +HHI clock controller. The clock signal provides the RMII reference clock +which is used to generate the internal 25MHz or 2.5MHz clocks depending +on the line speed. + +Signed-off-by: Martin Blumenstingl +--- + arch/arm/boot/dts/amlogic/meson8.dtsi | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi +index f57be9ae1..b2be52915 100644 +--- a/arch/arm/boot/dts/amlogic/meson8.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson8.dtsi +@@ -613,8 +613,8 @@ temperature_calib: calib@1f4 { + }; + + ðmac { +- clocks = <&clkc CLKID_ETH>; +- clock-names = "stmmaceth"; ++ clocks = <&clkc CLKID_ETH>, <&clkc CLKID_ETH_CLK>; ++ clock-names = "stmmaceth", "ethernet"; + + power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>; + }; +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0026-dt-bindings-clock-meson8b-add-the-rtc_32k-oscillator.patch b/patch/kernel/archive/meson-6.9/0026-dt-bindings-clock-meson8b-add-the-rtc_32k-oscillator.patch new file mode 100644 index 000000000000..11612b3958e6 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0026-dt-bindings-clock-meson8b-add-the-rtc_32k-oscillator.patch @@ -0,0 +1,30 @@ +From 0361c56921d2f1c27f35bb5ef2165e5550a26d68 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Fri, 1 Jan 2021 19:01:08 +0100 +Subject: [PATCH 26/96] dt-bindings: clock: meson8b: add the rtc_32k oscillator + input + +The CLK81 tree can be driven off the 32kHz oscillator connected to the +SoCs RTC32K_XI and RTC32K_XO pads. Add this clock as a valid input. + +Signed-off-by: Martin Blumenstingl +--- + .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +index a2602b5d5..855931509 100644 +--- a/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt ++++ b/Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +@@ -18,6 +18,8 @@ Required Properties: + * "clk_32k": (if present) the 32kHz clock signal from GPIOAO_6 (CLK_32K_IN) + * "rmii_clk": (if present) the 50MHz RMII reference clock (from the PHY or + an external oscillator ++ * "rtc_32k": the clock signal from the 32kHz oscillator connected to the ++ RTC32K_XI and RTC32K_XO pads + + Parent node should have the following properties : + - compatible: "amlogic,meson-hhi-sysctrl", "simple-mfd", "syscon" +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0027-clk-meson-meson8b-Add-the-mpeg_rtc_osc_sel-clock.patch b/patch/kernel/archive/meson-6.9/0027-clk-meson-meson8b-Add-the-mpeg_rtc_osc_sel-clock.patch new file mode 100644 index 000000000000..7060f796c83d --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0027-clk-meson-meson8b-Add-the-mpeg_rtc_osc_sel-clock.patch @@ -0,0 +1,108 @@ +From 439df3198ef064825150418f9c1244a9f2a20aac Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Fri, 1 Jan 2021 18:55:05 +0100 +Subject: [PATCH 27/96] clk: meson: meson8b: Add the mpeg_rtc_osc_sel clock + +The first input of the CLK81 clock tree uses the SoC's external +oscillators. By default it's the 24MHz XTAL from which most frequencies +in this SoC are derived. For power-saving purposes there's a mux to +switch the input between the 24MHz XTAL and the 32kHz RTC oscillator. +Add support for that mux add it to the CLK81 clock tree for a better +representation of how the hardware is actually designed. + +Signed-off-by: Martin Blumenstingl +--- + drivers/clk/meson/meson8b.c | 26 ++++++++++++++++++++++-- + include/dt-bindings/clock/meson8b-clkc.h | 1 + + 2 files changed, 25 insertions(+), 2 deletions(-) + +diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c +index 8128e0864..2f7a2adda 100644 +--- a/drivers/clk/meson/meson8b.c ++++ b/drivers/clk/meson/meson8b.c +@@ -611,7 +611,24 @@ static struct clk_regmap meson8b_mpll2 = { + }, + }; + +-static u32 mux_table_clk81[] = { 6, 5, 7 }; ++static struct clk_regmap meson8b_mpeg_rtc_osc_sel = { ++ .data = &(struct clk_regmap_mux_data){ ++ .offset = HHI_MPEG_CLK_CNTL, ++ .mask = 0x1, ++ .shift = 9, ++ }, ++ .hw.init = &(struct clk_init_data){ ++ .name = "mpeg_rtc_osc_sel", ++ .ops = &clk_regmap_mux_ro_ops, ++ .parent_data = (const struct clk_parent_data[]) { ++ { .fw_name = "xtal", .index = -1, }, ++ { .fw_name = "rtc_32k", .index = -1, }, ++ }, ++ .num_parents = 2, ++ }, ++}; ++ ++static u32 mux_table_clk81[] = { 0, 6, 5, 7 }; + static struct clk_regmap meson8b_mpeg_clk_sel = { + .data = &(struct clk_regmap_mux_data){ + .offset = HHI_MPEG_CLK_CNTL, +@@ -628,11 +645,12 @@ static struct clk_regmap meson8b_mpeg_clk_sel = { + * fclk_div4, fclk_div3, fclk_div5 + */ + .parent_hws = (const struct clk_hw *[]) { ++ &meson8b_mpeg_rtc_osc_sel.hw, + &meson8b_fclk_div3.hw, + &meson8b_fclk_div4.hw, + &meson8b_fclk_div5.hw, + }, +- .num_parents = 3, ++ .num_parents = 4, + }, + }; + +@@ -3055,6 +3073,7 @@ static struct clk_hw *meson8_hw_clks[] = { + [CLKID_ETH_CLK_DIV] = &meson8_eth_clk_div.hw, + [CLKID_ETH_CLK_PHASE] = &meson8_eth_clk_phase.hw, + [CLKID_ETH_CLK] = &meson8_eth_clk_gate.hw, ++ [CLKID_MPEG_RTC_OSC_SEL] = &meson8b_mpeg_rtc_osc_sel.hw, + }; + + static struct clk_hw *meson8b_hw_clks[] = { +@@ -3270,6 +3289,7 @@ static struct clk_hw *meson8b_hw_clks[] = { + [CLKID_CTS_I958] = &meson8b_cts_i958.hw, + [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, + [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, ++ [CLKID_MPEG_RTC_OSC_SEL] = &meson8b_mpeg_rtc_osc_sel.hw, + }; + + static struct clk_hw *meson8m2_hw_clks[] = { +@@ -3487,6 +3507,7 @@ static struct clk_hw *meson8m2_hw_clks[] = { + [CLKID_CTS_I958] = &meson8b_cts_i958.hw, + [CLKID_VID_PLL_LVDS_EN] = &meson8b_vid_pll_lvds_en.hw, + [CLKID_HDMI_PLL_DCO_IN] = &hdmi_pll_dco_in.hw, ++ [CLKID_MPEG_RTC_OSC_SEL] = &meson8b_mpeg_rtc_osc_sel.hw, + }; + + static struct clk_regmap *const meson8b_clk_regmaps[] = { +@@ -3687,6 +3708,7 @@ static struct clk_regmap *const meson8b_clk_regmaps[] = { + &meson8_eth_clk_div, + &meson8_eth_clk_phase, + &meson8_eth_clk_gate, ++ &meson8b_mpeg_rtc_osc_sel, + }; + + static const struct meson8b_clk_reset_line { +diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h +index a09b686af..fe6c02e04 100644 +--- a/include/dt-bindings/clock/meson8b-clkc.h ++++ b/include/dt-bindings/clock/meson8b-clkc.h +@@ -225,5 +225,6 @@ + #define CLKID_ETH_CLK_DIV 219 + #define CLKID_ETH_CLK_PHASE 220 + #define CLKID_ETH_CLK 221 ++#define CLKID_MPEG_RTC_OSC_SEL 222 + + #endif /* __MESON8B_CLKC_H */ +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0028-ARM-dts-meson-Add-address-cells-size-cells-and-range.patch b/patch/kernel/archive/meson-6.9/0028-ARM-dts-meson-Add-address-cells-size-cells-and-range.patch new file mode 100644 index 000000000000..0bae77dca43f --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0028-ARM-dts-meson-Add-address-cells-size-cells-and-range.patch @@ -0,0 +1,85 @@ +From b9f75c5b68a79dee3c4ca723a4ee92521118a92d Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 28 Aug 2021 18:50:10 +0200 +Subject: [PATCH 28/96] ARM: dts: meson: Add #address-cells, #size-cells and + ranges to hhi + +The HHI node has multiple child-nodes. Add #address-cells, #size-cells +and ranges properties to the hhi node itself so the child-nodes can get +their own offset and register sizes. Also add the reg property to the +clock and power domain controllers inside the hhi region. + +Signed-off-by: Martin Blumenstingl +--- + arch/arm/boot/dts/amlogic/meson.dtsi | 3 +++ + arch/arm/boot/dts/amlogic/meson8.dtsi | 6 ++++-- + arch/arm/boot/dts/amlogic/meson8b.dtsi | 6 ++++-- + 3 files changed, 11 insertions(+), 4 deletions(-) + +diff --git a/arch/arm/boot/dts/amlogic/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi +index 0e7756c95..d7f50fec8 100644 +--- a/arch/arm/boot/dts/amlogic/meson.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson.dtsi +@@ -35,6 +35,9 @@ hhi: system-controller@4000 { + "simple-mfd", + "syscon"; + reg = <0x4000 0x400>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0x0 0x4000 0x400>; + }; + + aiu: audio-controller@5400 { +diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi +index b2be52915..d925bdcc0 100644 +--- a/arch/arm/boot/dts/amlogic/meson8.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson8.dtsi +@@ -625,16 +625,18 @@ &gpio_intc { + }; + + &hhi { +- clkc: clock-controller { ++ clkc: clock-controller@0 { + compatible = "amlogic,meson8-clkc"; ++ reg = <0x0 0x39c>; + clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; + clock-names = "xtal", "ddr_pll"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +- pwrc: power-controller { ++ pwrc: power-controller@100 { + compatible = "amlogic,meson8-pwrc"; ++ reg = <0x100 0x10>; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&pmu>; + clocks = <&clkc CLKID_VPU>; +diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi +index 2d9d24d3a..5ffedca99 100644 +--- a/arch/arm/boot/dts/amlogic/meson8b.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi +@@ -586,16 +586,18 @@ &gpio_intc { + }; + + &hhi { +- clkc: clock-controller { ++ clkc: clock-controller@0 { + compatible = "amlogic,meson8b-clkc"; ++ reg = <0x0 0x39c>; + clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>; + clock-names = "xtal", "ddr_pll"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +- pwrc: power-controller { ++ pwrc: power-controller@100 { + compatible = "amlogic,meson8b-pwrc"; ++ reg = <0x100 0x10>; + #power-domain-cells = <1>; + amlogic,ao-sysctrl = <&pmu>; + resets = <&reset RESET_DBLK>, +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0029-dt-bindings-firmware-Document-the-Amlogic-Meson6-8-8.patch b/patch/kernel/archive/meson-6.9/0029-dt-bindings-firmware-Document-the-Amlogic-Meson6-8-8.patch new file mode 100644 index 000000000000..391b7c725c0b --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0029-dt-bindings-firmware-Document-the-Amlogic-Meson6-8-8.patch @@ -0,0 +1,77 @@ +From 5e640e96e1224868456fda4cc2c9e8cca273a79c Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 17 May 2021 22:50:25 +0200 +Subject: [PATCH 29/96] dt-bindings: firmware: Document the Amlogic + Meson6/8/8b/8m2 TrustZone + +Amlogic Meson6/8/8b/8m2 SoCs can optionally use a TrustZone secure +firmware. This prevents anything outside of the TEE (Trusted +Execution Environment aka TrustZone secure firmware) from accessing +certain functionality of these SoCs, such as (but not limited to): +Bringing up/down secondary SMP cores, accessing the eFuse and getting +the SoC misc version. +ARM SMCCC is used for communication with the TrustZone secure +firmware. + +Signed-off-by: Martin Blumenstingl +--- + .../amlogic,meson-mx-trustzone-firmware.yaml | 47 +++++++++++++++++++ + 1 file changed, 47 insertions(+) + create mode 100644 Documentation/devicetree/bindings/firmware/meson/amlogic,meson-mx-trustzone-firmware.yaml + +diff --git a/Documentation/devicetree/bindings/firmware/meson/amlogic,meson-mx-trustzone-firmware.yaml b/Documentation/devicetree/bindings/firmware/meson/amlogic,meson-mx-trustzone-firmware.yaml +new file mode 100644 +index 000000000..1e0e19a35 +--- /dev/null ++++ b/Documentation/devicetree/bindings/firmware/meson/amlogic,meson-mx-trustzone-firmware.yaml +@@ -0,0 +1,47 @@ ++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) ++# Copyright 2021 Martin Blumenstingl ++%YAML 1.2 ++--- ++$id: "http://devicetree.org/schemas/firmware/meson/amlogic,meson-mx-trustzone-firmware.yaml#" ++$schema: "http://devicetree.org/meta-schemas/core.yaml#" ++ ++title: Amlogic Meson6/8/8b/8m2 TrustZone secure firmware ++ ++description: | ++ Amlogic Meson6/8/8b/8m2 SoCs can optionally use a TrustZone secure ++ firmware. This prevents anything outside of the TEE (Trusted ++ Execution Environment aka TrustZone secure firmware) from accessing ++ certain functionality of these SoCs, such as (but not limited to): ++ Bringing up/down secondary SMP cores, accessing the eFuse and getting ++ the SoC misc version. ++ ARM SMCCC is used for communication with the TrustZone secure ++ firmware. ++ ++maintainers: ++ - Martin Blumenstingl ++ ++properties: ++ compatible: ++ oneOf: ++ - items: ++ - enum: ++ - amlogic,meson6-trustzone-firmware ++ - amlogic,meson8-trustzone-firmware ++ - amlogic,meson8b-trustzone-firmware ++ - amlogic,meson8m2-trustzone-firmware ++ - const: amlogic,meson-mx-trustzone-firmware ++ ++required: ++ - compatible ++ ++additionalProperties: false ++ ++examples: ++ - | ++ firmware { ++ trustzone-firmware { ++ compatible = "amlogic,meson8m2-trustzone-firmware", ++ "amlogic,meson-mx-trustzone-firmware"; ++ }; ++ }; ++... +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0030-dt-bindings-arm-cpus-Document-Meson8-TrustZone-firmw.patch b/patch/kernel/archive/meson-6.9/0030-dt-bindings-arm-cpus-Document-Meson8-TrustZone-firmw.patch new file mode 100644 index 000000000000..6a1b0e3ece21 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0030-dt-bindings-arm-cpus-Document-Meson8-TrustZone-firmw.patch @@ -0,0 +1,31 @@ +From f753ee1373a56cee5d6c2e7c107a85822828c983 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 18 Dec 2021 16:38:16 +0100 +Subject: [PATCH 30/96] dt-bindings: arm: cpus: Document Meson8 TrustZone + firmware enable-method + +Amlogic Meson8 SoCs can run a TrustZone firmware. This results in the +CPU registers not being accessible directly and instead require firmware +calls for booting the secondary cores or powering off a CPU. Add a new +compatible string for this enable-method. + +Signed-off-by: Martin Blumenstingl +--- + Documentation/devicetree/bindings/arm/cpus.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml +index cc5a21b47..ec7593e04 100644 +--- a/Documentation/devicetree/bindings/arm/cpus.yaml ++++ b/Documentation/devicetree/bindings/arm/cpus.yaml +@@ -216,6 +216,7 @@ properties: + - allwinner,sun9i-a80-smp + - allwinner,sun8i-a83t-smp + - amlogic,meson8-smp ++ - amlogic,meson8-trustzone-firmware-smp + - amlogic,meson8b-smp + - arm,realview-smp + - aspeed,ast2600-smp +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0031-ARM-meson-Add-support-for-the-TrustZone-firmware.patch b/patch/kernel/archive/meson-6.9/0031-ARM-meson-Add-support-for-the-TrustZone-firmware.patch new file mode 100644 index 000000000000..8ba503b3abd3 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0031-ARM-meson-Add-support-for-the-TrustZone-firmware.patch @@ -0,0 +1,439 @@ +From 5499854ac2d2227951eb9e0437a5897d038cca97 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 3 May 2021 00:34:53 +0200 +Subject: [PATCH 31/96] ARM: meson: Add support for the TrustZone firmware + +Amlogic Meson6/8/8b/8m2 SoCs can optionally use a TrustZone secure +firmware. This prevents anything outside of the TEE (Trusted +Execution Environment aka TrustZone secure firmware) from accessing +certain functionality of these SoCs, such as (but not limited to): +Bringing up/down secondary SMP cores, accessing the eFuse and getting +the SoC misc version. +ARM SMCCC is used for communication with the TrustZone secure +firmware. + +Signed-off-by: Martin Blumenstingl +--- + arch/arm/mach-meson/Makefile | 2 +- + arch/arm/mach-meson/meson.c | 4 + + arch/arm/mach-meson/tz_firmware.c | 250 ++++++++++++++++++ + arch/arm/mach-meson/tz_firmware.h | 76 ++++++ + .../linux/firmware/meson/meson_mx_trustzone.h | 37 +++ + 5 files changed, 368 insertions(+), 1 deletion(-) + create mode 100644 arch/arm/mach-meson/tz_firmware.c + create mode 100644 arch/arm/mach-meson/tz_firmware.h + create mode 100644 include/linux/firmware/meson/meson_mx_trustzone.h + +diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile +index 49cfbaee4..b8fe5f140 100644 +--- a/arch/arm/mach-meson/Makefile ++++ b/arch/arm/mach-meson/Makefile +@@ -1,3 +1,3 @@ + # SPDX-License-Identifier: GPL-2.0-only +-obj-$(CONFIG_ARCH_MESON) += meson.o ++obj-$(CONFIG_ARCH_MESON) += meson.o tz_firmware.o + obj-$(CONFIG_SMP) += platsmp.o +diff --git a/arch/arm/mach-meson/meson.c b/arch/arm/mach-meson/meson.c +index d3ae89dd8..45dae29a4 100644 +--- a/arch/arm/mach-meson/meson.c ++++ b/arch/arm/mach-meson/meson.c +@@ -5,6 +5,8 @@ + + #include + ++#include "tz_firmware.h" ++ + static const char * const meson_common_board_compat[] = { + "amlogic,meson6", + "amlogic,meson8", +@@ -17,4 +19,6 @@ DT_MACHINE_START(MESON, "Amlogic Meson platform") + .dt_compat = meson_common_board_compat, + .l2c_aux_val = 0, + .l2c_aux_mask = ~0, ++ .init_early = meson_mx_trustzone_firmware_init, ++ .reserve = meson_mx_trustzone_firmware_reserve_mem, + MACHINE_END +diff --git a/arch/arm/mach-meson/tz_firmware.c b/arch/arm/mach-meson/tz_firmware.c +new file mode 100644 +index 000000000..9cdad4144 +--- /dev/null ++++ b/arch/arm/mach-meson/tz_firmware.c +@@ -0,0 +1,250 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (C) 2021 Martin Blumenstingl ++ */ ++ ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++ ++#include "tz_firmware.h" ++ ++struct meson_mx_trustzone_firmware_memconfig { ++ unsigned char name[64]; ++ unsigned int start_phy_addr; ++ unsigned int end_phy_addr; ++} __packed; ++ ++static struct meson_mx_trustzone_firmware_memconfig meson_firmware_memconfig[2]; ++ ++static int meson_mx_trustzone_firmware_hal_api(unsigned int cmd, u32 *args) ++{ ++ struct arm_smccc_res res; ++ ++ arm_smccc_smc(MESON_CALL_TRUSTZONE_HAL_API, cmd, virt_to_phys(args), 0, ++ 0, 0, 0, 0, &res); ++ ++ return res.a0; ++} ++ ++static u32 meson_mx_trustzone_firmware_mon(unsigned int cmd, unsigned int arg0, ++ unsigned int arg1) ++{ ++ struct arm_smccc_res res; ++ ++ arm_smccc_smc(MESON_CALL_TRUSTZONE_MON, cmd, arg0, arg1, 0, 0, 0, 0, ++ &res); ++ ++ return res.a0; ++} ++ ++static int meson_mx_trustzone_firmware_set_cpu_boot_addr(int cpu, ++ unsigned long boot_addr){ ++ return meson_mx_trustzone_firmware_mon(MESON_TRUSTZONE_MON_CORE_BOOTADDR_INDEX, ++ cpu, boot_addr); ++} ++ ++static int meson_mx_trustzone_firmware_cpu_boot(int cpu) ++{ ++ u32 ret, corectrl; ++ ++ corectrl = meson_mx_trustzone_firmware_mon(MESON_TRUSTZONE_MON_CORE_RD_CTRL_INDEX, ++ 0, 0); ++ ++ corectrl |= BIT(cpu); ++ ++ ret = meson_mx_trustzone_firmware_mon(MESON_TRUSTZONE_MON_CORE_WR_CTRL_INDEX, ++ corectrl, 0); ++ if (ret != corectrl) ++ return -EINVAL; ++ ++ return 0; ++} ++ ++static void meson_mx_trustzone_firmware_l2x0_write_sec(unsigned long val, ++ unsigned int reg) ++{ ++ u32 fn; ++ ++ switch (reg) { ++ case L2X0_CTRL: ++ fn = MESON_TRUSTZONE_MON_L2X0_CTRL_INDEX; ++ break; ++ ++ case L2X0_AUX_CTRL: ++ fn = MESON_TRUSTZONE_MON_L2X0_AUXCTRL_INDEX; ++ break; ++ ++ case L310_TAG_LATENCY_CTRL: ++ fn = MESON_TRUSTZONE_MON_L2X0_TAGLATENCY_INDEX; ++ break; ++ ++ case L310_DATA_LATENCY_CTRL: ++ fn = MESON_TRUSTZONE_MON_L2X0_DATALATENCY_INDEX; ++ break; ++ ++ case L310_ADDR_FILTER_START: ++ fn = MESON_TRUSTZONE_MON_L2X0_FILTERSTART_INDEX; ++ break; ++ ++ case L310_ADDR_FILTER_END: ++ fn = MESON_TRUSTZONE_MON_L2X0_FILTEREND_INDEX; ++ break; ++ ++ case L2X0_DEBUG_CTRL: ++ fn = MESON_TRUSTZONE_MON_L2X0_DEBUG_INDEX; ++ break; ++ ++ case L310_PREFETCH_CTRL: ++ fn = MESON_TRUSTZONE_MON_L2X0_PREFETCH_INDEX; ++ break; ++ ++ case L310_POWER_CTRL: ++ fn = MESON_TRUSTZONE_MON_L2X0_POWER_INDEX; ++ break; ++ ++ default: ++ pr_warn("Amlogic Meson TrustZone - unsupported L2X0 register 0x%08x\n", ++ reg); ++ return; ++ } ++ ++ WARN_ON(meson_mx_trustzone_firmware_mon(fn, val, 0)); ++} ++ ++static int __maybe_unused meson_mx_trustzone_firmware_l2x0_init(void) ++{ ++ if (IS_ENABLED(CONFIG_CACHE_L2X0)) ++ outer_cache.write_sec = meson_mx_trustzone_firmware_l2x0_write_sec; ++ ++ return 0; ++} ++ ++static const struct firmware_ops meson_mx_trustzone_firmware_ops = { ++ .set_cpu_boot_addr = meson_mx_trustzone_firmware_set_cpu_boot_addr, ++ .cpu_boot = meson_mx_trustzone_firmware_cpu_boot, ++ .l2x0_init = meson_mx_trustzone_firmware_l2x0_init, ++}; ++ ++void __init meson_mx_trustzone_firmware_init(void) ++{ ++ if (!meson_mx_trustzone_firmware_available()) ++ return; ++ ++ pr_info("Running under Amlogic Meson TrustZone secure firmware.\n"); ++ ++ register_firmware_ops(&meson_mx_trustzone_firmware_ops); ++ ++ call_firmware_op(l2x0_init); ++} ++ ++static void __init meson_mx_trustzone_firmware_memconfig_init(void) ++{ ++ unsigned int i, size; ++ u32 args[2] = { ++ __pa_symbol(meson_firmware_memconfig), ++ ARRAY_SIZE(meson_firmware_memconfig), ++ }; ++ int ret; ++ ++ ret = meson_mx_trustzone_firmware_hal_api(MESON_TRUSTZONE_HAL_API_MEMCONFIG, ++ args); ++ if (ret) { ++ pr_err("Amlogic Meson TrustZone memconfig failed: %d\n", ret); ++ return; ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(meson_firmware_memconfig); i++) { ++ size = meson_firmware_memconfig[i].end_phy_addr - ++ meson_firmware_memconfig[i].start_phy_addr; ++ ++ pr_debug("\tAmlogic Meson TrustZone memblock[%d]: %s (%u bytes)\n", ++ i, meson_firmware_memconfig[i].name, size); ++ ++ ret = memblock_mark_nomap(meson_firmware_memconfig[i].start_phy_addr, ++ size); ++ if (ret) ++ pr_err("Failed to reserve %u bytes for Amlogic Meson TrustZone memblock[%d] (%s): %d\n", ++ size, i, meson_firmware_memconfig[i].name, ret); ++ } ++} ++ ++static void __init meson_mx_trustzone_firmware_monitor_memory_init(void) ++{ ++ u32 base, size; ++ int ret; ++ ++ base = meson_mx_trustzone_firmware_mon(MESON_TRUSTZONE_MON_MEM_BASE, ++ 0, 0); ++ WARN_ON(!base); ++ ++ size = meson_mx_trustzone_firmware_mon(MESON_TRUSTZONE_MON_MEM_TOTAL_SIZE, ++ 0, 0); ++ WARN_ON(!size); ++ ++ ret = memblock_mark_nomap(base, size); ++ if (ret) ++ pr_err("Failed to reserve %u bytes of Amlogic Meson TrustZone monitor memory: %d\n", ++ size, ret); ++} ++ ++void __init meson_mx_trustzone_firmware_reserve_mem(void) ++{ ++ if (!meson_mx_trustzone_firmware_available()) ++ return; ++ ++ meson_mx_trustzone_firmware_monitor_memory_init(); ++ meson_mx_trustzone_firmware_memconfig_init(); ++} ++ ++bool meson_mx_trustzone_firmware_available(void) ++{ ++ struct device_node *np; ++ ++ np = of_find_compatible_node(NULL, NULL, ++ "amlogic,meson-mx-trustzone-firmware"); ++ if (!np) ++ return false; ++ ++ of_node_put(np); ++ ++ return true; ++} ++EXPORT_SYMBOL_GPL(meson_mx_trustzone_firmware_available); ++ ++int meson_mx_trustzone_firmware_efuse_read(unsigned int offset, ++ unsigned int bytes, void *buf) ++{ ++ unsigned int read_bytes; ++ u32 args[5] = { ++ MESON_TRUSTZONE_HAL_API_EFUSE_CMD_READ, ++ offset, ++ bytes, ++ __pa_symbol(buf), ++ virt_to_phys(&read_bytes) ++ }; ++ int ret; ++ ++ ret = meson_mx_trustzone_firmware_hal_api(MESON_TRUSTZONE_HAL_API_EFUSE, ++ args); ++ if (ret) ++ return -EIO; ++ ++ if (read_bytes != bytes) ++ return -EINVAL; ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(meson_mx_trustzone_firmware_efuse_read); ++ ++u32 meson_mx_trustzone_read_soc_rev1(void) ++{ ++ return meson_mx_trustzone_firmware_mon(MESON_TRUSTZONE_MON_CORE_RD_SOC_REV1, ++ 0, 0); ++} ++EXPORT_SYMBOL_GPL(meson_mx_trustzone_read_soc_rev1); +diff --git a/arch/arm/mach-meson/tz_firmware.h b/arch/arm/mach-meson/tz_firmware.h +new file mode 100644 +index 000000000..a9da3c84a +--- /dev/null ++++ b/arch/arm/mach-meson/tz_firmware.h +@@ -0,0 +1,76 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Amlogic Meson6/8/8b/8m2 secure TrustZone firmware definitions. ++ * ++ * Based on meson-secure.c and meson-secure.h from the Amlogic vendor kernel: ++ * Copyright (C) 2002 ARM Ltd. ++ * Copyright (c) 2010, Code Aurora Forum. All rights reserved. ++ * Copyright (C) 2013 Amlogic, Inc. ++ * Author: Platform-SH@amlogic.com ++ * ++ * Copyright (C) 2021 Martin Blumenstingl ++ */ ++ ++/* Meson Secure Monitor/HAL APIs */ ++#define MESON_CALL_TRUSTZONE_API 0x1 ++#define MESON_CALL_TRUSTZONE_MON 0x4 ++#define MESON_CALL_TRUSTZONE_HAL_API 0x5 ++ ++/* Secure Monitor mode APIs */ ++#define MESON_TRUSTZONE_MON_TYPE_MASK 0xF00 ++#define MESON_TRUSTZONE_MON_FUNC_MASK 0x0FF ++ ++#define MESON_TRUSTZONE_MON_L2X0 0x100 ++#define MESON_TRUSTZONE_MON_L2X0_CTRL_INDEX 0x101 ++#define MESON_TRUSTZONE_MON_L2X0_AUXCTRL_INDEX 0x102 ++#define MESON_TRUSTZONE_MON_L2X0_PREFETCH_INDEX 0x103 ++#define MESON_TRUSTZONE_MON_L2X0_TAGLATENCY_INDEX 0x104 ++#define MESON_TRUSTZONE_MON_L2X0_DATALATENCY_INDEX 0x105 ++#define MESON_TRUSTZONE_MON_L2X0_FILTERSTART_INDEX 0x106 ++#define MESON_TRUSTZONE_MON_L2X0_FILTEREND_INDEX 0x107 ++#define MESON_TRUSTZONE_MON_L2X0_DEBUG_INDEX 0x108 ++#define MESON_TRUSTZONE_MON_L2X0_POWER_INDEX 0x109 ++ ++#define MESON_TRUSTZONE_MON_CORE 0x200 ++#define MESON_TRUSTZONE_MON_CORE_RD_CTRL_INDEX 0x201 ++#define MESON_TRUSTZONE_MON_CORE_WR_CTRL_INDEX 0x202 ++#define MESON_TRUSTZONE_MON_CORE_RD_STATUS0_INDEX 0x203 ++#define MESON_TRUSTZONE_MON_CORE_WR_STATUS0_INDEX 0x204 ++#define MESON_TRUSTZONE_MON_CORE_RD_STATUS1_INDEX 0x205 ++#define MESON_TRUSTZONE_MON_CORE_WR_STATUS1_INDEX 0x206 ++#define MESON_TRUSTZONE_MON_CORE_BOOTADDR_INDEX 0x207 ++#define MESON_TRUSTZONE_MON_CORE_DDR_INDEX 0x208 ++#define MESON_TRUSTZONE_MON_CORE_RD_SOC_REV1 0x209 ++#define MESON_TRUSTZONE_MON_CORE_RD_SOC_REV2 0x20A ++ ++#define MESON_TRUSTZONE_MON_SUSPEND_FIRMWARE 0x300 ++#define MESON_TRUSTZONE_MON_SAVE_CPU_GIC 0x400 ++ ++#define MESON_TRUSTZONE_MON_RTC 0x500 ++#define MESON_TRUSTZONE_MON_RTC_RD_REG_INDEX 0x501 ++#define MESON_TRUSTZONE_MON_RTC_WR_REG_INDEX 0x502 ++ ++#define MESON_TRUSTZONE_MON_REG 0x600 ++#define MESON_TRUSTZONE_MON_REG_RD_INDEX 0x601 ++#define MESON_TRUSTZONE_MON_REG_WR_INDEX 0x602 ++ ++#define MESON_TRUSTZONE_MON_MEM 0x700 ++#define MESON_TRUSTZONE_MON_MEM_BASE 0x701 ++#define MESON_TRUSTZONE_MON_MEM_TOTAL_SIZE 0x702 ++#define MESON_TRUSTZONE_MON_MEM_FLASH 0x703 ++#define MESON_TRUSTZONE_MON_MEM_FLASH_SIZE 0x704 ++#define MESON_TRUSTZONE_MON_MEM_GE2D 0x705 ++ ++/* Secure HAL APIs*/ ++#define MESON_TRUSTZONE_HAL_API_EFUSE 0x100 ++#define MESON_TRUSTZONE_HAL_API_EFUSE_CMD_READ 0x0 ++#define MESON_TRUSTZONE_HAL_API_EFUSE_CMD_WRITE 0x1 ++#define MESON_TRUSTZONE_HAL_API_EFUSE_CMD_VERIFY_IMG 0x3 ++ ++#define MESON_TRUSTZONE_HAL_API_STORAGE 0x200 ++ ++#define MESON_TRUSTZONE_HAL_API_MEMCONFIG 0x300 ++#define MESON_TRUSTZONE_HAL_API_MEMCONFIG_GE2D 0x301 ++ ++void __init meson_mx_trustzone_firmware_init(void); ++void __init meson_mx_trustzone_firmware_reserve_mem(void); +diff --git a/include/linux/firmware/meson/meson_mx_trustzone.h b/include/linux/firmware/meson/meson_mx_trustzone.h +new file mode 100644 +index 000000000..947463050 +--- /dev/null ++++ b/include/linux/firmware/meson/meson_mx_trustzone.h +@@ -0,0 +1,37 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Copyright (C) 2021 Martin Blumenstingl ++ */ ++ ++#include ++#include ++ ++#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_MESON) ++ ++bool meson_mx_trustzone_firmware_available(void); ++ ++int meson_mx_trustzone_firmware_efuse_read(unsigned int offset, ++ unsigned int bytes, void *buf); ++ ++u32 meson_mx_trustzone_read_soc_rev1(void); ++ ++#else ++ ++static inline bool meson_mx_trustzone_firmware_available(void) ++{ ++ return false; ++} ++ ++static inline int meson_mx_trustzone_firmware_efuse_read(unsigned int offset, ++ unsigned int bytes, ++ void *buf) ++{ ++ return -EINVAL; ++} ++ ++static inline u32 meson_mx_trustzone_read_soc_rev1(void) ++{ ++ return 0; ++} ++ ++#endif +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0032-ARM-meson-platsmp-Add-support-for-SoCs-running-on-Tr.patch b/patch/kernel/archive/meson-6.9/0032-ARM-meson-platsmp-Add-support-for-SoCs-running-on-Tr.patch new file mode 100644 index 000000000000..2a5ef2f3aec2 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0032-ARM-meson-platsmp-Add-support-for-SoCs-running-on-Tr.patch @@ -0,0 +1,75 @@ +From 342867fae2835ccac6edc355c6d115f9e69a4eeb Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 3 May 2021 08:36:16 +0200 +Subject: [PATCH 32/96] ARM: meson: platsmp: Add support for SoCs running on + TrustZone firmware + +When the SoC is running on the TrustZone firmware we cannot modify the +SMP related registers. Add a new set of SMP ops which use firmware calls +to set the startup (function) address and core control (on/off). + +Signed-off-by: Martin Blumenstingl +--- + arch/arm/mach-meson/platsmp.c | 33 +++++++++++++++++++++++++++++++++ + 1 file changed, 33 insertions(+) + +diff --git a/arch/arm/mach-meson/platsmp.c b/arch/arm/mach-meson/platsmp.c +index 32ac60b89..3e38066fc 100644 +--- a/arch/arm/mach-meson/platsmp.c ++++ b/arch/arm/mach-meson/platsmp.c +@@ -16,6 +16,7 @@ + + #include + #include ++#include + #include + #include + +@@ -291,6 +292,31 @@ static int meson8b_smp_boot_secondary(unsigned int cpu, + return 0; + } + ++static int meson8_smp_trustzone_firmware_boot_secondary(unsigned int cpu, ++ struct task_struct *idle) ++{ ++ unsigned int addr = __pa_symbol(secondary_startup); ++ int ret; ++ ++ ret = call_firmware_op(set_cpu_boot_addr, cpu, addr); ++ if (ret) { ++ pr_err("Failed to set aux core boot address for CPU%u using TrustZone secure firmware\n", ++ cpu); ++ return ret; ++ } ++ ++ ret = call_firmware_op(cpu_boot, cpu); ++ if (ret) { ++ pr_err("Failed to modify core control for CPU%u using TrustZone secure firmware\n", ++ cpu); ++ return ret; ++ } ++ ++ udelay(10); ++ ++ return 0; ++} ++ + #ifdef CONFIG_HOTPLUG_CPU + static void meson8_smp_cpu_die(unsigned int cpu) + { +@@ -428,5 +454,12 @@ static struct smp_operations meson8b_smp_ops __initdata = { + #endif + }; + ++static struct smp_operations meson8_smp_trustzone_firmware_ops __initdata = { ++ .smp_boot_secondary = meson8_smp_trustzone_firmware_boot_secondary, ++}; ++ + CPU_METHOD_OF_DECLARE(meson8_smp, "amlogic,meson8-smp", &meson8_smp_ops); + CPU_METHOD_OF_DECLARE(meson8b_smp, "amlogic,meson8b-smp", &meson8b_smp_ops); ++CPU_METHOD_OF_DECLARE(meson8_trustzone_firmware_smp, ++ "amlogic,meson8-trustzone-firmware-smp", ++ &meson8_smp_trustzone_firmware_ops); +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0033-soc-amlogic-meson-mx-socinfo-Add-support-for-the-Tru.patch b/patch/kernel/archive/meson-6.9/0033-soc-amlogic-meson-mx-socinfo-Add-support-for-the-Tru.patch new file mode 100644 index 000000000000..625ef52ba41b --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0033-soc-amlogic-meson-mx-socinfo-Add-support-for-the-Tru.patch @@ -0,0 +1,68 @@ +From 77011250fbd490a4b85363f62e7c4e639191a4ec Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sun, 16 May 2021 19:48:54 +0200 +Subject: [PATCH 33/96] soc: amlogic: meson-mx-socinfo: Add support for the + TrustZone firmware + +When the TrustZone firmware is enabled the SoC is configured so the boot +ROM cannot be read from the (untrusted) Linux kernel. Instead a firmware +call needs to be used to get the SoC's "misc" version. +Add support for the firmware call to retrieve the SoC's misc version if +the TrustZone firmware is loaded. + +Signed-off-by: Martin Blumenstingl +--- + drivers/soc/amlogic/meson-mx-socinfo.c | 23 +++++++++++++++-------- + 1 file changed, 15 insertions(+), 8 deletions(-) + +diff --git a/drivers/soc/amlogic/meson-mx-socinfo.c b/drivers/soc/amlogic/meson-mx-socinfo.c +index 92125dd65..25503bdd7 100644 +--- a/drivers/soc/amlogic/meson-mx-socinfo.c ++++ b/drivers/soc/amlogic/meson-mx-socinfo.c +@@ -4,6 +4,7 @@ + * SPDX-License-Identifier: GPL-2.0+ + */ + ++#include + #include + #include + #include +@@ -118,10 +119,12 @@ static int __init meson_mx_socinfo_init(void) + if (IS_ERR(assist_regmap)) + return PTR_ERR(assist_regmap); + +- bootrom_regmap = +- syscon_regmap_lookup_by_compatible("amlogic,meson-mx-bootrom"); +- if (IS_ERR(bootrom_regmap)) +- return PTR_ERR(bootrom_regmap); ++ if (!meson_mx_trustzone_firmware_available()) { ++ bootrom_regmap = ++ syscon_regmap_lookup_by_compatible("amlogic,meson-mx-bootrom"); ++ if (IS_ERR(bootrom_regmap)) ++ return PTR_ERR(bootrom_regmap); ++ } + + np = of_find_matching_node(NULL, meson_mx_socinfo_analog_top_ids); + if (np) { +@@ -141,10 +144,14 @@ static int __init meson_mx_socinfo_init(void) + if (ret < 0) + return ret; + +- ret = regmap_read(bootrom_regmap, MESON_MX_BOOTROM_MISC_VER, +- &misc_ver); +- if (ret < 0) +- return ret; ++ if (meson_mx_trustzone_firmware_available()) { ++ misc_ver = meson_mx_trustzone_read_soc_rev1(); ++ } else { ++ ret = regmap_read(bootrom_regmap, MESON_MX_BOOTROM_MISC_VER, ++ &misc_ver); ++ if (ret < 0) ++ return ret; ++ } + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0034-nvmem-meson-mx-efuse-Add-support-for-the-TrustZone-f.patch b/patch/kernel/archive/meson-6.9/0034-nvmem-meson-mx-efuse-Add-support-for-the-TrustZone-f.patch new file mode 100644 index 000000000000..4ae137b8af56 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0034-nvmem-meson-mx-efuse-Add-support-for-the-TrustZone-f.patch @@ -0,0 +1,73 @@ +From a6e38e2f0cc7be7d75ed8b9895e7bc7af99d0fe0 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 3 May 2021 00:35:22 +0200 +Subject: [PATCH 34/96] nvmem: meson-mx-efuse: Add support for the TrustZone + firmware interface + +Some boards have a TrustZone firmware which prevents us from accessing +(most of) the eFuse registers. On these boards we must use read the +eFuse through TrustZone firmware calls (using SMC). +Implement a .reg_read op using the Meson TrustZone firmware interface. + +Signed-off-by: Martin Blumenstingl +--- + drivers/nvmem/meson-mx-efuse.c | 29 ++++++++++++++++++++++++++++- + 1 file changed, 28 insertions(+), 1 deletion(-) + +diff --git a/drivers/nvmem/meson-mx-efuse.c b/drivers/nvmem/meson-mx-efuse.c +index 3ff04d5ca..1a08f5541 100644 +--- a/drivers/nvmem/meson-mx-efuse.c ++++ b/drivers/nvmem/meson-mx-efuse.c +@@ -9,6 +9,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -166,6 +167,28 @@ static int meson_mx_efuse_read(void *context, unsigned int offset, + return err; + } + ++static int meson_mx_efuse_read_trustzone_firmware(void *context, ++ unsigned int offset, ++ void *buf, size_t bytes) ++{ ++ struct meson_mx_efuse *efuse = context; ++ unsigned int tmp; ++ int i, ret; ++ ++ for (i = 0; i < bytes; i += efuse->config.word_size) { ++ ret = meson_mx_trustzone_firmware_efuse_read(offset + i, ++ sizeof(tmp), ++ &tmp); ++ if (ret) ++ return ret; ++ ++ memcpy(buf + i, &tmp, ++ min_t(size_t, bytes - i, efuse->config.word_size)); ++ } ++ ++ return 0; ++} ++ + static const struct meson_mx_efuse_platform_data meson6_efuse_data = { + .name = "meson6-efuse", + .word_size = 1, +@@ -215,7 +238,11 @@ static int meson_mx_efuse_probe(struct platform_device *pdev) + efuse->config.word_size = drvdata->word_size; + efuse->config.size = SZ_512; + efuse->config.read_only = true; +- efuse->config.reg_read = meson_mx_efuse_read; ++ ++ if (meson_mx_trustzone_firmware_available()) ++ efuse->config.reg_read = meson_mx_efuse_read_trustzone_firmware; ++ else ++ efuse->config.reg_read = meson_mx_efuse_read; + + efuse->core_clk = devm_clk_get(&pdev->dev, "core"); + if (IS_ERR(efuse->core_clk)) { +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0036-ARM-dts-meson8-Add-the-PWM_C-DV9-and-PWM_D-pins.patch b/patch/kernel/archive/meson-6.9/0036-ARM-dts-meson8-Add-the-PWM_C-DV9-and-PWM_D-pins.patch new file mode 100644 index 000000000000..65448734e1da --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0036-ARM-dts-meson8-Add-the-PWM_C-DV9-and-PWM_D-pins.patch @@ -0,0 +1,45 @@ +From 77298a6b2e7937abfefb0514469b03c223cb6414 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Thu, 22 Jul 2021 08:27:29 +0200 +Subject: [PATCH 36/96] ARM: dts: meson8: Add the PWM_C (DV9) and PWM_D pins + +There are some Meson8m2 boards which don't use a PMIC (like Ricoh +RN5T618) but use two PWM regulators for VCCK and VDDEE. Add the PWM_C +(DV9) and PWM_D pins so the pinctrl settings can be applied on those +boards. + +Signed-off-by: Martin Blumenstingl +--- + arch/arm/boot/dts/amlogic/meson8.dtsi | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi +index d925bdcc0..454c35530 100644 +--- a/arch/arm/boot/dts/amlogic/meson8.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson8.dtsi +@@ -479,6 +479,22 @@ gpio: banks@80b0 { + gpio-ranges = <&pinctrl_cbus 0 0 120>; + }; + ++ pwm_c_dv9_pins: pwm-c-dv9 { ++ mux { ++ groups = "pwm_c_dv9"; ++ function = "pwm_c"; ++ bias-disable; ++ }; ++ }; ++ ++ pwm_d_pins: pwm-d { ++ mux { ++ groups = "pwm_d"; ++ function = "pwm_d"; ++ bias-disable; ++ }; ++ }; ++ + sd_a_pins: sd-a { + mux { + groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0045-dt-bindings-display-meson-vpu-add-support-for-Meson8.patch b/patch/kernel/archive/meson-6.9/0045-dt-bindings-display-meson-vpu-add-support-for-Meson8.patch new file mode 100644 index 000000000000..ac5f7e47eaf7 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0045-dt-bindings-display-meson-vpu-add-support-for-Meson8.patch @@ -0,0 +1,33 @@ +From 875ed8762a46e7f0fd143b58a3002c3a76b805cd Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 25 Apr 2020 22:16:15 +0200 +Subject: [PATCH 45/96] dt-bindings: display: meson-vpu: add support for + Meson8/8b/8m2 - WiP + +WiP + +Signed-off-by: Martin Blumenstingl +--- + .../devicetree/bindings/display/amlogic,meson-vpu.yaml | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml +index c9ab01434..96c32747e 100644 +--- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml ++++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml +@@ -66,8 +66,12 @@ properties: + - const: amlogic,meson-gx-vpu + - enum: + - amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2) ++ - amlogic,meson8-vpu ++ - amlogic,meson8b-vpu ++ - amlogic,meson8m2-vpu + + reg: ++ minItems: 1 + maxItems: 2 + + reg-names: +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0046-drm-meson-add-Meson8-Meson8b-Meson8m2-specific-vpu_c.patch b/patch/kernel/archive/meson-6.9/0046-drm-meson-add-Meson8-Meson8b-Meson8m2-specific-vpu_c.patch new file mode 100644 index 000000000000..4c6c716ad05c --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0046-drm-meson-add-Meson8-Meson8b-Meson8m2-specific-vpu_c.patch @@ -0,0 +1,39 @@ +From f4fdd1b75e3ad64c9903a42aeeb9e45a1ad10780 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 25 Apr 2020 21:50:45 +0200 +Subject: [PATCH 46/96] drm/meson: add Meson8/Meson8b/Meson8m2 specific + vpu_compatible entries + +Add values for Meson8/Meson8b/Meson8m2 to enum vpu_compatible so quirks +for these earlier hardware generations can be added to the driver. + +Signed-off-by: Martin Blumenstingl +--- + drivers/gpu/drm/meson/meson_drv.h | 11 +++++++---- + 1 file changed, 7 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h +index 69be4c67f..8e1c01242 100644 +--- a/drivers/gpu/drm/meson/meson_drv.h ++++ b/drivers/gpu/drm/meson/meson_drv.h +@@ -20,10 +20,13 @@ struct phy; + struct platform_device; + + enum vpu_compatible { +- VPU_COMPATIBLE_GXBB = 0, +- VPU_COMPATIBLE_GXL = 1, +- VPU_COMPATIBLE_GXM = 2, +- VPU_COMPATIBLE_G12A = 3, ++ VPU_COMPATIBLE_M8 = 0, ++ VPU_COMPATIBLE_M8B = 1, ++ VPU_COMPATIBLE_M8M2 = 2, ++ VPU_COMPATIBLE_GXBB = 3, ++ VPU_COMPATIBLE_GXL = 4, ++ VPU_COMPATIBLE_GXM = 5, ++ VPU_COMPATIBLE_G12A = 6, + }; + + enum { +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0047-drm-meson-Use-24-bits-per-pixel-for-the-framebuffer-.patch b/patch/kernel/archive/meson-6.9/0047-drm-meson-Use-24-bits-per-pixel-for-the-framebuffer-.patch new file mode 100644 index 000000000000..e79607809fa5 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0047-drm-meson-Use-24-bits-per-pixel-for-the-framebuffer-.patch @@ -0,0 +1,67 @@ +From 31af191867e9272d80820cc452e3c209a24713fa Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sun, 26 Apr 2020 00:00:09 +0200 +Subject: [PATCH 47/96] drm/meson: Use 24 bits per pixel for the framebuffer on + Meson8/8b/8m2 + +All SoC generations before GXBB don't have a way to configure the +alpha value for DRM_FORMAT_XRGB8888 and DRM_FORMAT_XBGR8888. These +formats have an X component instead of an alpha component. On +Meson8/8b/8m2 there is no way to configure the alpha value to use +instead of the X component. This results in the fact that the +formats with X component are only supported on GXBB and newer. Use +24 bits per pixel and therefore DRM_FORMAT_RGB888 to get a +working framebuffer console. + +Signed-off-by: Martin Blumenstingl +--- + drivers/gpu/drm/meson/meson_drv.c | 26 +++++++++++++++++++++++++- + 1 file changed, 25 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c +index 17a5cca00..60298cf3b 100644 +--- a/drivers/gpu/drm/meson/meson_drv.c ++++ b/drivers/gpu/drm/meson/meson_drv.c +@@ -159,6 +159,30 @@ static void meson_vpu_init(struct meson_drm *priv) + writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); + } + ++static void meson_fbdev_setup(struct meson_drm *priv) ++{ ++ unsigned int preferred_bpp; ++ ++ /* ++ * All SoC generations before GXBB don't have a way to configure the ++ * alpha value for DRM_FORMAT_XRGB8888 and DRM_FORMAT_XBGR8888. These ++ * formats have an X component instead of an alpha component. On ++ * Meson8/8b/8m2 there is no way to configure the alpha value to use ++ * instead of the X component. This results in the fact that the ++ * formats with X component are only supported on GXBB and newer. Use ++ * 24 bits per pixel and therefore DRM_FORMAT_RGB888 to get a ++ * working framebuffer console. ++ */ ++ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) ++ preferred_bpp = 24; ++ else ++ preferred_bpp = 32; ++ ++ drm_fbdev_dma_setup(priv->drm, preferred_bpp); ++} ++ + struct meson_drm_soc_attr { + struct meson_drm_soc_limits limits; + const struct soc_device_attribute *attrs; +@@ -362,7 +386,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) + if (ret) + goto uninstall_irq; + +- drm_fbdev_dma_setup(drm, 32); ++ meson_fbdev_setup(priv); + + return 0; + +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0048-drm-meson-Use-a-separate-list-of-supported-formats-f.patch b/patch/kernel/archive/meson-6.9/0048-drm-meson-Use-a-separate-list-of-supported-formats-f.patch new file mode 100644 index 000000000000..48793142e77b --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0048-drm-meson-Use-a-separate-list-of-supported-formats-f.patch @@ -0,0 +1,84 @@ +From fc19ccbb10a7f76c8ad92571f306782c4afebe3c Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 25 Apr 2020 21:53:21 +0200 +Subject: [PATCH 48/96] drm/meson: Use a separate list of supported formats for + 32-bit SoCs + +The VIU_OSD1_CTRL_STAT2 and VIU_OSD2_CTRL_STAT2 registers on +Meson8/Meson8b/Meson8m2 don't have the following bits: +- replaced_alpha_en in bit [14] +- replaced_alpha in bits [13:6] + +This results in formats with X component (currently DRM_FORMAT_XRGB8888 +and DRM_FORMAT_XBGR8888 are supported on GXBB and later) are not +supported. Depending on the application this may work (kmscube for +example - which seems to properly set 0xff as alpha component), but +there's other examples (Kodi for example) where there are alpha blending +issues because the alpha value is not defined (and thus some random +value). + +Signed-off-by: Martin Blumenstingl +--- + drivers/gpu/drm/meson/meson_plane.c | 30 ++++++++++++++++++++++++++--- + 1 file changed, 27 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c +index 815dfe304..e71503609 100644 +--- a/drivers/gpu/drm/meson/meson_plane.c ++++ b/drivers/gpu/drm/meson/meson_plane.c +@@ -471,7 +471,20 @@ static const struct drm_plane_funcs meson_plane_funcs = { + .format_mod_supported = meson_plane_format_mod_supported, + }; + +-static const uint32_t supported_drm_formats[] = { ++/* ++ * X components (for example in DRM_FORMAT_XRGB8888 and DRM_FORMAT_XBGR8888) ++ * are not supported because these older SoC's are lacking the OSD_REPLACE_EN ++ * bit to replace the X alpha component with a static value, leaving the alpha ++ * component in an undefined state. ++ */ ++static const uint32_t supported_drm_formats_m8[] = { ++ DRM_FORMAT_ARGB8888, ++ DRM_FORMAT_ABGR8888, ++ DRM_FORMAT_RGB888, ++ DRM_FORMAT_RGB565, ++}; ++ ++static const uint32_t supported_drm_formats_gx[] = { + DRM_FORMAT_ARGB8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_XRGB8888, +@@ -533,6 +546,8 @@ int meson_plane_create(struct meson_drm *priv) + { + struct meson_plane *meson_plane; + struct drm_plane *plane; ++ unsigned int num_drm_formats; ++ const uint32_t *drm_formats; + const uint64_t *format_modifiers = format_modifiers_default; + + meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane), +@@ -548,10 +563,19 @@ int meson_plane_create(struct meson_drm *priv) + else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) + format_modifiers = format_modifiers_afbc_g12a; + ++ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { ++ drm_formats = supported_drm_formats_m8; ++ num_drm_formats = ARRAY_SIZE(supported_drm_formats_m8); ++ } else { ++ drm_formats = supported_drm_formats_gx; ++ num_drm_formats = ARRAY_SIZE(supported_drm_formats_gx); ++ } ++ + drm_universal_plane_init(priv->drm, plane, 0xFF, + &meson_plane_funcs, +- supported_drm_formats, +- ARRAY_SIZE(supported_drm_formats), ++ drm_formats, num_drm_formats, + format_modifiers, + DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane"); + +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0049-drm-meson-Skip-VIU_OSD1_CTRL_STAT2-alpha-replace-val.patch b/patch/kernel/archive/meson-6.9/0049-drm-meson-Skip-VIU_OSD1_CTRL_STAT2-alpha-replace-val.patch new file mode 100644 index 000000000000..34d9b1d1d82a --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0049-drm-meson-Skip-VIU_OSD1_CTRL_STAT2-alpha-replace-val.patch @@ -0,0 +1,52 @@ +From 4fec04a45ba08241d76deaa2640aad5be1743683 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Mon, 31 Jan 2022 23:02:59 +0100 +Subject: [PATCH 49/96] drm/meson: Skip VIU_OSD1_CTRL_STAT2 alpha replace value + initialization + +The VIU_OSD1_CTRL_STAT2 and VIU_OSD2_CTRL_STAT2 registers on +Meson8/Meson8b/Meson8m2 don't have the following bits: +- replaced_alpha_en in bit [14] +- replaced_alpha in bits [13:6] + +Don't initialize the replaced_alpha register bits in VIU_OSD1_CTRL_STAT2 +on Meson8/Meson8b/Meson8m2 because they are not implemented on those +SoCs. + +Signed-off-by: Martin Blumenstingl +--- + drivers/gpu/drm/meson/meson_viu.c | 18 +++++++++++------- + 1 file changed, 11 insertions(+), 7 deletions(-) + +diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c +index cd399b0b7..bdfa342c4 100644 +--- a/drivers/gpu/drm/meson/meson_viu.c ++++ b/drivers/gpu/drm/meson/meson_viu.c +@@ -448,13 +448,17 @@ void meson_viu_init(struct meson_drm *priv) + writel_relaxed(reg, priv->io_base + _REG(VIU_OSD1_FIFO_CTRL_STAT)); + writel_relaxed(reg, priv->io_base + _REG(VIU_OSD2_FIFO_CTRL_STAT)); + +- /* Set OSD alpha replace value */ +- writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, +- 0xff << OSD_REPLACE_SHIFT, +- priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); +- writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, +- 0xff << OSD_REPLACE_SHIFT, +- priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); ++ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && ++ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && ++ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { ++ /* Set OSD alpha replace value */ ++ writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, ++ 0xff << OSD_REPLACE_SHIFT, ++ priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); ++ writel_bits_relaxed(0xff << OSD_REPLACE_SHIFT, ++ 0xff << OSD_REPLACE_SHIFT, ++ priv->io_base + _REG(VIU_OSD2_CTRL_STAT2)); ++ } + + /* Disable VD1 AFBC */ + /* di_mif0_en=0 mif0_to_vpp_en=0 di_mad_en=0 and afbc vd1 set=0*/ +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0050-drm-meson-Enable-the-RGB-to-YUV-converter-on-Meson8-.patch b/patch/kernel/archive/meson-6.9/0050-drm-meson-Enable-the-RGB-to-YUV-converter-on-Meson8-.patch new file mode 100644 index 000000000000..e7fc3241f577 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0050-drm-meson-Enable-the-RGB-to-YUV-converter-on-Meson8-.patch @@ -0,0 +1,35 @@ +From a7583cc8a459b072fb3613f204143bcfccd18849 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 25 Apr 2020 22:00:57 +0200 +Subject: [PATCH 50/96] drm/meson: Enable the RGB to YUV converter on + Meson8/Meson8b/Meson8m2 + +Set VIU_OSD1_BLK0_CFG_W0[7] to 1 to enable RGB to YUV converter, just +like on GXBB. + +Signed-off-by: Martin Blumenstingl +--- + drivers/gpu/drm/meson/meson_plane.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c +index e71503609..27e395772 100644 +--- a/drivers/gpu/drm/meson/meson_plane.c ++++ b/drivers/gpu/drm/meson/meson_plane.c +@@ -200,8 +200,11 @@ static void meson_plane_atomic_update(struct drm_plane *plane, + priv->viu.osd1_ctrl_stat2 &= ~OSD_DPATH_MALI_AFBCD; + } + +- /* On GXBB, Use the old non-HDR RGB2YUV converter */ +- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) ++ /* On GXBB and earlier, Use the old non-HDR RGB2YUV converter */ ++ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) + priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB; + + if (priv->viu.osd1_afbcd && +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0051-drm-meson-Update-meson_vpu_init-to-work-with-Meson8-.patch b/patch/kernel/archive/meson-6.9/0051-drm-meson-Update-meson_vpu_init-to-work-with-Meson8-.patch new file mode 100644 index 000000000000..e9046f25782c --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0051-drm-meson-Update-meson_vpu_init-to-work-with-Meson8-.patch @@ -0,0 +1,85 @@ +From 8b09602979c279f579ced2d5234f878e8e9243bb Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 25 Apr 2020 22:03:27 +0200 +Subject: [PATCH 51/96] drm/meson: Update meson_vpu_init to work with + Meson8/Meson8b/Meson8m2 + +Don't modify the VPU_RDARB_MODE_* registers because they only exist on +GXBB and newer SoCs. Initialize the VPU_MEM_PD_REG0 and VPU_MEM_PD_REG1 +to 0x0 (meaning: enable everything), just like vendor u-boot does for +Meson8/Meson8b/Meson8m2. + +Signed-off-by: Martin Blumenstingl +--- + drivers/gpu/drm/meson/meson_drv.c | 55 ++++++++++++++++++------------- + 1 file changed, 33 insertions(+), 22 deletions(-) + +diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c +index 60298cf3b..ffc5eb588 100644 +--- a/drivers/gpu/drm/meson/meson_drv.c ++++ b/drivers/gpu/drm/meson/meson_drv.c +@@ -135,28 +135,39 @@ static struct regmap_config meson_regmap_config = { + + static void meson_vpu_init(struct meson_drm *priv) + { +- u32 value; +- +- /* +- * Slave dc0 and dc5 connected to master port 1. +- * By default other slaves are connected to master port 0. +- */ +- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) | +- VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1); +- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); +- +- /* Slave dc0 connected to master port 1 */ +- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1); +- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); +- +- /* Slave dc4 and dc7 connected to master port 1 */ +- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) | +- VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1); +- writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); +- +- /* Slave dc1 connected to master port 1 */ +- value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1); +- writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); ++ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { ++ writel(0x0, priv->io_base + _REG(VPU_MEM_PD_REG0)); ++ writel(0x0, priv->io_base + _REG(VPU_MEM_PD_REG1)); ++ } else { ++ u32 value; ++ ++ /* ++ * Slave dc0 and dc5 connected to master port 1. ++ * By default other slaves are connected to master port 0. ++ */ ++ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) | ++ VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1); ++ writel_relaxed(value, ++ priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); ++ ++ /* Slave dc0 connected to master port 1 */ ++ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1); ++ writel_relaxed(value, ++ priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); ++ ++ /* Slave dc4 and dc7 connected to master port 1 */ ++ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) | ++ VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1); ++ writel_relaxed(value, ++ priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); ++ ++ /* Slave dc1 connected to master port 1 */ ++ value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1); ++ writel_relaxed(value, ++ priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); ++ } + } + + static void meson_fbdev_setup(struct meson_drm *priv) +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0052-drm-meson-Describe-the-HDMI-PHY-frequency-limits-of-.patch b/patch/kernel/archive/meson-6.9/0052-drm-meson-Describe-the-HDMI-PHY-frequency-limits-of-.patch new file mode 100644 index 000000000000..adcdb5421ab2 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0052-drm-meson-Describe-the-HDMI-PHY-frequency-limits-of-.patch @@ -0,0 +1,57 @@ +From 7017db5123fbbccca0dde37e7a2f45172d50e56e Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Wed, 23 Dec 2020 21:18:35 +0100 +Subject: [PATCH 52/96] drm/meson: Describe the HDMI PHY frequency limits of + Meson8/8b/8m2 + +The maximum HDMI PLL frequency used by the vendor kernel is 2.976GHz. +For Meson8 and Meson8b (both "HDMI 1.4 4k" capable) the maximum HDMI PHY +frequency therefore is 2.976GHz. This makes sure we don't expose any +HDMI 2.0 modes. +Meson8b only supports up to 1080p according to it's datasheet. Limit the +Meson8b SoC's to 1.65GHz (similar to what's already there for GXL S805X +and S805Y). + +Signed-off-by: Martin Blumenstingl +--- + drivers/gpu/drm/meson/meson_drv.c | 18 +++++++++++++++++- + 1 file changed, 17 insertions(+), 1 deletion(-) + +diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c +index ffc5eb588..bbb8b8b50 100644 +--- a/drivers/gpu/drm/meson/meson_drv.c ++++ b/drivers/gpu/drm/meson/meson_drv.c +@@ -200,13 +200,29 @@ struct meson_drm_soc_attr { + }; + + static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = { +- /* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */ ++ /* The maximum frequency of HDMI PHY on Meson8 and Meson8m2 is ~3GHz */ ++ { ++ .limits = { ++ .max_hdmi_phy_freq = 2976000, ++ }, ++ .attrs = (const struct soc_device_attribute []) { ++ { .soc_id = "Meson8 (S802)", }, ++ { .soc_id = "Meson8m2 (S812)", }, ++ { /* sentinel */ }, ++ } ++ }, ++ /* ++ * GXL S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz. ++ * Meson8b (S805) only supports "1200p@60 max resolution" according to ++ * the public datasheet. ++ */ + { + .limits = { + .max_hdmi_phy_freq = 1650000, + }, + .attrs = (const struct soc_device_attribute []) { + { .soc_id = "GXL (S805*)", }, ++ { .soc_id = "Meson8b (S805)", }, + { /* sentinel */ } + } + }, +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0053-drm-meson-Update-the-HDMI-encoder-for-Meson8-8b-8m2.patch b/patch/kernel/archive/meson-6.9/0053-drm-meson-Update-the-HDMI-encoder-for-Meson8-8b-8m2.patch new file mode 100644 index 000000000000..c6b66ab05cef --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0053-drm-meson-Update-the-HDMI-encoder-for-Meson8-8b-8m2.patch @@ -0,0 +1,144 @@ +From e37f5e8c60f9ecad4b2286bec22e2989d267971b Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Wed, 6 Oct 2021 23:34:04 +0200 +Subject: [PATCH 53/96] drm/meson: Update the HDMI encoder for Meson8/8b/8m2 + +Meson8/8b/8m2 uses VPU_HDMI_OUTPUT_YCBCR for YUV444 while newer SoCs use +VPU_HDMI_OUTPUT_CBYCR. Also the 32-bit SoCs use VPU_HDMI_OUTPUT_CRYCB +for RGB. These are the only two known mappings for the 32-bit SoCs. + +The VPU_HDMI_FMT_CTRL register with it's YUV444 to YUV422/YUV420 +converter is not present on these older SoCs. Avoid writing this +reserved register on these 32-bit SoCs. + +MEDIA_BUS_FMT_RGB888_1X24 cannot be exposed as output format because the +RGB to YUV converter is always enabled in meson_plane_atomic_update() +(so there's currently no way to configure it). + +Signed-off-by: Martin Blumenstingl +--- + drivers/gpu/drm/meson/meson_encoder_hdmi.c | 66 ++++++++++++++++------ + 1 file changed, 49 insertions(+), 17 deletions(-) + +diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c +index 0593a1cde..d8aae0952 100644 +--- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c ++++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c +@@ -190,13 +190,13 @@ static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge, + { + struct meson_encoder_hdmi *encoder_hdmi = bridge_to_meson_encoder_hdmi(bridge); + struct drm_atomic_state *state = bridge_state->base.state; +- unsigned int ycrcb_map = VPU_HDMI_OUTPUT_CBYCR; + struct meson_drm *priv = encoder_hdmi->priv; + struct drm_connector_state *conn_state; + const struct drm_display_mode *mode; + struct drm_crtc_state *crtc_state; + struct drm_connector *connector; + bool yuv420_mode = false; ++ unsigned int ycrcb_map; + int vic; + + connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); +@@ -217,11 +217,21 @@ static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge, + + dev_dbg(priv->dev, "\"%s\" vic %d\n", mode->name, vic); + +- if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) { ++ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { ++ if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_RGB888_1X24) ++ ycrcb_map = VPU_HDMI_OUTPUT_YCBCR; ++ else ++ ycrcb_map = VPU_HDMI_OUTPUT_CRYCB; ++ } else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) { + ycrcb_map = VPU_HDMI_OUTPUT_CRYCB; + yuv420_mode = true; +- } else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16) ++ } else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16) { + ycrcb_map = VPU_HDMI_OUTPUT_CRYCB; ++ } else { ++ ycrcb_map = VPU_HDMI_OUTPUT_CBYCR; ++ } + + /* VENC + VENC-DVI Mode setup */ + meson_venc_hdmi_mode_set(priv, vic, ycrcb_map, yuv420_mode, mode); +@@ -229,17 +239,21 @@ static void meson_encoder_hdmi_atomic_enable(struct drm_bridge *bridge, + /* VCLK Set clock */ + meson_encoder_hdmi_set_vclk(encoder_hdmi, mode); + +- if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) +- /* Setup YUV420 to HDMI-TX, no 10bit diphering */ +- writel_relaxed(2 | (2 << 2), +- priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); +- else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16) +- /* Setup YUV422 to HDMI-TX, no 10bit diphering */ +- writel_relaxed(1 | (2 << 2), +- priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); +- else +- /* Setup YUV444 to HDMI-TX, no 10bit diphering */ +- writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); ++ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && ++ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && ++ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { ++ if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYYVYY8_0_5X24) ++ /* Setup YUV420 to HDMI-TX, no 10bit diphering */ ++ writel_relaxed(2 | (2 << 2), ++ priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); ++ else if (encoder_hdmi->output_bus_fmt == MEDIA_BUS_FMT_UYVY8_1X16) ++ /* Setup YUV422 to HDMI-TX, no 10bit diphering */ ++ writel_relaxed(1 | (2 << 2), ++ priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); ++ else ++ /* Setup YUV444 to HDMI-TX, no 10bit diphering */ ++ writel_relaxed(0, priv->io_base + _REG(VPU_HDMI_FMT_CTRL)); ++ } + + dev_dbg(priv->dev, "%s\n", priv->venc.hdmi_use_enci ? "VENCI" : "VENCP"); + +@@ -262,7 +276,11 @@ static void meson_encoder_hdmi_atomic_disable(struct drm_bridge *bridge, + writel_relaxed(0, priv->io_base + _REG(ENCP_VIDEO_EN)); + } + +-static const u32 meson_encoder_hdmi_out_bus_fmts[] = { ++static const u32 meson8_encoder_hdmi_out_bus_fmts[] = { ++ MEDIA_BUS_FMT_YUV8_1X24, ++}; ++ ++static const u32 meson_gx_encoder_hdmi_out_bus_fmts[] = { + MEDIA_BUS_FMT_YUV8_1X24, + MEDIA_BUS_FMT_UYVY8_1X16, + MEDIA_BUS_FMT_UYYVYY8_0_5X24, +@@ -276,13 +294,27 @@ meson_encoder_hdmi_get_inp_bus_fmts(struct drm_bridge *bridge, + u32 output_fmt, + unsigned int *num_input_fmts) + { ++ struct meson_encoder_hdmi *encoder_hdmi = bridge_to_meson_encoder_hdmi(bridge); ++ struct meson_drm *priv = encoder_hdmi->priv; ++ unsigned int num_out_bus_fmts; ++ const u32 *out_bus_fmts; + u32 *input_fmts = NULL; + int i; + ++ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { ++ num_out_bus_fmts = ARRAY_SIZE(meson8_encoder_hdmi_out_bus_fmts); ++ out_bus_fmts = meson8_encoder_hdmi_out_bus_fmts; ++ } else { ++ num_out_bus_fmts = ARRAY_SIZE(meson_gx_encoder_hdmi_out_bus_fmts); ++ out_bus_fmts = meson_gx_encoder_hdmi_out_bus_fmts; ++ } ++ + *num_input_fmts = 0; + +- for (i = 0 ; i < ARRAY_SIZE(meson_encoder_hdmi_out_bus_fmts) ; ++i) { +- if (output_fmt == meson_encoder_hdmi_out_bus_fmts[i]) { ++ for (i = 0 ; i < num_out_bus_fmts ; ++i) { ++ if (output_fmt == out_bus_fmts[i]) { + *num_input_fmts = 1; + input_fmts = kcalloc(*num_input_fmts, + sizeof(*input_fmts), +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0054-drm-meson-Only-set-ycbcr_420_allowed-on-64-bit-SoCs.patch b/patch/kernel/archive/meson-6.9/0054-drm-meson-Only-set-ycbcr_420_allowed-on-64-bit-SoCs.patch new file mode 100644 index 000000000000..414dfcc39616 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0054-drm-meson-Only-set-ycbcr_420_allowed-on-64-bit-SoCs.patch @@ -0,0 +1,34 @@ +From 7ba0841fd85b2f8fd11602ea92fb8887ecd3d81c Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Wed, 6 Oct 2021 23:37:44 +0200 +Subject: [PATCH 54/96] drm/meson: Only set ycbcr_420_allowed on 64-bit SoCs + +The 32-bit SoCs don't support YUV420 so we don't enable that +functionality there. + +Signed-off-by: Martin Blumenstingl +--- + drivers/gpu/drm/meson/meson_encoder_hdmi.c | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/drivers/gpu/drm/meson/meson_encoder_hdmi.c b/drivers/gpu/drm/meson/meson_encoder_hdmi.c +index d8aae0952..4a84d7d99 100644 +--- a/drivers/gpu/drm/meson/meson_encoder_hdmi.c ++++ b/drivers/gpu/drm/meson/meson_encoder_hdmi.c +@@ -481,8 +481,11 @@ int meson_encoder_hdmi_probe(struct meson_drm *priv) + + drm_connector_attach_max_bpc_property(meson_encoder_hdmi->connector, 8, 8); + +- /* Handle this here until handled by drm_bridge_connector_init() */ +- meson_encoder_hdmi->connector->ycbcr_420_allowed = true; ++ if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) && ++ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) && ++ !meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) ++ /* Handle this here until handled by drm_bridge_connector_init() */ ++ meson_encoder_hdmi->connector->ycbcr_420_allowed = true; + + pdev = of_find_device_by_node(remote); + of_node_put(remote); +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0055-drm-meson-Make-the-HHI-registers-optional-WIP.patch b/patch/kernel/archive/meson-6.9/0055-drm-meson-Make-the-HHI-registers-optional-WIP.patch new file mode 100644 index 000000000000..5d7856c00b73 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0055-drm-meson-Make-the-HHI-registers-optional-WIP.patch @@ -0,0 +1,100 @@ +From 39042addabb9910ec95e916fb619f5af8097f0c8 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Thu, 7 Oct 2021 19:09:49 +0200 +Subject: [PATCH 55/96] drm/meson: Make the HHI registers optional - WIP + +The HHI area contains the clock controller registers as well as the +registers for the CVBS DAC. Make the HHI registers optional because the +functionality provided by them can be handled by separate drivers +(especially on the 32-bit SoCs). + +Signed-off-by: Martin Blumenstingl +--- + drivers/gpu/drm/meson/meson_drv.c | 35 ++++++++++++++++-------------- + drivers/gpu/drm/meson/meson_venc.c | 11 +++++++--- + 2 files changed, 27 insertions(+), 19 deletions(-) + +diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c +index bbb8b8b50..104b53861 100644 +--- a/drivers/gpu/drm/meson/meson_drv.c ++++ b/drivers/gpu/drm/meson/meson_drv.c +@@ -271,24 +271,27 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) + + priv->io_base = regs; + ++ /* ++ * The HHI resource is optional because it contains the clocks and CVBS ++ * encoder registers. These are managed by separate drivers though. ++ */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi"); +- if (!res) { +- ret = -EINVAL; +- goto free_drm; +- } +- /* Simply ioremap since it may be a shared register zone */ +- regs = devm_ioremap(dev, res->start, resource_size(res)); +- if (!regs) { +- ret = -EADDRNOTAVAIL; +- goto free_drm; +- } ++ if (res) { ++ /* Simply ioremap since it may be a shared register zone */ ++ regs = devm_ioremap(dev, res->start, resource_size(res)); ++ if (!regs) { ++ ret = -EADDRNOTAVAIL; ++ goto free_drm; ++ } + +- priv->hhi = devm_regmap_init_mmio(dev, regs, +- &meson_regmap_config); +- if (IS_ERR(priv->hhi)) { +- dev_err(&pdev->dev, "Couldn't create the HHI regmap\n"); +- ret = PTR_ERR(priv->hhi); +- goto free_drm; ++ priv->hhi = devm_regmap_init_mmio(dev, regs, ++ &meson_regmap_config); ++ if (IS_ERR(priv->hhi)) { ++ dev_err(&pdev->dev, ++ "Couldn't create the HHI regmap\n"); ++ ret = PTR_ERR(priv->hhi); ++ goto free_drm; ++ } + } + + priv->canvas = meson_canvas_get(dev); +diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c +index 5efd7a298..805751b9e 100644 +--- a/drivers/gpu/drm/meson/meson_venc.c ++++ b/drivers/gpu/drm/meson/meson_venc.c +@@ -1953,12 +1953,16 @@ void meson_venc_enable_vsync(struct meson_drm *priv) + writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN, + priv->io_base + _REG(VENC_INTCTRL)); + } +- regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); ++ ++ if (priv->hhi) ++ regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); + } + + void meson_venc_disable_vsync(struct meson_drm *priv) + { +- regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0); ++ if (priv->hhi) ++ regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0); ++ + writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL)); + } + +@@ -1968,7 +1972,8 @@ void meson_venc_init(struct meson_drm *priv) + writel_relaxed(0xff, priv->io_base + _REG(VENC_VDAC_SETTING)); + + /* Disable HDMI PHY */ +- regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); ++ if (priv->hhi) ++ regmap_write(priv->hhi, HHI_HDMI_PHY_CNTL0, 0); + + /* Disable HDMI */ + writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI | +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0056-drm-meson-Add-support-for-the-Meson8-8b-8m2-TranSwit.patch b/patch/kernel/archive/meson-6.9/0056-drm-meson-Add-support-for-the-Meson8-8b-8m2-TranSwit.patch new file mode 100644 index 000000000000..1735f13b841d --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0056-drm-meson-Add-support-for-the-Meson8-8b-8m2-TranSwit.patch @@ -0,0 +1,2133 @@ +From 7aabe08f5ea4b120e2451904c8c2f7a497eabefe Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sun, 5 May 2019 02:29:42 +0200 +Subject: [PATCH 56/96] drm/meson: Add support for the Meson8/8b/8m2 TranSwitch + HDMI transmitter - WiP + +WiP + +Signed-off-by: Martin Blumenstingl +--- + drivers/gpu/drm/meson/Kconfig | 10 + + drivers/gpu/drm/meson/Makefile | 1 + + drivers/gpu/drm/meson/meson_transwitch_hdmi.c | 1537 +++++++++++++++++ + drivers/gpu/drm/meson/meson_transwitch_hdmi.h | 536 ++++++ + 4 files changed, 2084 insertions(+) + create mode 100644 drivers/gpu/drm/meson/meson_transwitch_hdmi.c + create mode 100644 drivers/gpu/drm/meson/meson_transwitch_hdmi.h + +diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig +index 47e920105..73ec1b314 100644 +--- a/drivers/gpu/drm/meson/Kconfig ++++ b/drivers/gpu/drm/meson/Kconfig +@@ -25,3 +25,13 @@ config DRM_MESON_DW_MIPI_DSI + default y if DRM_MESON + select DRM_DW_MIPI_DSI + select GENERIC_PHY_MIPI_DPHY ++ ++config DRM_MESON_TRANSWITCH_HDMI ++ tristate "Amlogic Meson8/8b/8m2 TranSwitch HDMI 1.4 Controller support" ++ depends on ARM || COMPILE_TEST ++ depends on DRM_MESON ++ default y if DRM_MESON ++ select DRM_DISPLAY_HDMI_HELPER ++ select DRM_DISPLAY_HELPER ++ select REGMAP_MMIO ++ select SND_SOC_HDMI_CODEC if SND_SOC +diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile +index 43071bdbd..c44cb6c52 100644 +--- a/drivers/gpu/drm/meson/Makefile ++++ b/drivers/gpu/drm/meson/Makefile +@@ -7,3 +7,4 @@ meson-drm-y += meson_encoder_hdmi.o meson_encoder_dsi.o + obj-$(CONFIG_DRM_MESON) += meson-drm.o + obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o + obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o ++obj-$(CONFIG_DRM_MESON_TRANSWITCH_HDMI) += meson_transwitch_hdmi.o +diff --git a/drivers/gpu/drm/meson/meson_transwitch_hdmi.c b/drivers/gpu/drm/meson/meson_transwitch_hdmi.c +new file mode 100644 +index 000000000..3a07ab763 +--- /dev/null ++++ b/drivers/gpu/drm/meson/meson_transwitch_hdmi.c +@@ -0,0 +1,1537 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2021 Martin Blumenstingl ++ * ++ * All registers and magic values are taken from Amlogic's GPL kernel sources: ++ * Copyright (C) 2010 Amlogic, Inc. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++ ++#include ++ ++#include "meson_transwitch_hdmi.h" ++ ++#define HDMI_ADDR_PORT 0x0 ++#define HDMI_DATA_PORT 0x4 ++#define HDMI_CTRL_PORT 0x8 ++ #define HDMI_CTRL_PORT_APB3_ERR_EN BIT(15) ++ ++struct meson_txc_hdmi { ++ struct device *dev; ++ ++ struct regmap *regmap; ++ ++ struct clk *pclk; ++ struct clk *sys_clk; ++ ++ struct phy *phy; ++ bool phy_is_on; ++ ++ struct mutex codec_mutex; ++ enum drm_connector_status last_connector_status; ++ hdmi_codec_plugged_cb codec_plugged_cb; ++ struct device *codec_dev; ++ ++ struct platform_device *hdmi_codec_pdev; ++ ++ struct drm_connector *current_connector; ++ ++ struct drm_bridge bridge; ++ struct drm_bridge *next_bridge; ++}; ++ ++#define bridge_to_meson_txc_hdmi(x) container_of(x, struct meson_txc_hdmi, bridge) ++ ++static const struct regmap_range meson_txc_hdmi_regmap_ranges[] = { ++ regmap_reg_range(0x0000, 0x07ff), ++ regmap_reg_range(0x8000, 0x800c), ++}; ++ ++static const struct regmap_access_table meson_txc_hdmi_regmap_access = { ++ .yes_ranges = meson_txc_hdmi_regmap_ranges, ++ .n_yes_ranges = ARRAY_SIZE(meson_txc_hdmi_regmap_ranges), ++}; ++ ++static int meson_txc_hdmi_reg_read(void *context, unsigned int addr, ++ unsigned int *data) ++{ ++ void __iomem *base = context; ++ ++ writel(addr, base + HDMI_ADDR_PORT); ++ writel(addr, base + HDMI_ADDR_PORT); ++ ++ *data = readl(base + HDMI_DATA_PORT); ++ ++ return 0; ++} ++ ++static int meson_txc_hdmi_reg_write(void *context, unsigned int addr, ++ unsigned int data) ++{ ++ void __iomem *base = context; ++ ++ writel(addr, base + HDMI_ADDR_PORT); ++ writel(addr, base + HDMI_ADDR_PORT); ++ ++ writel(data, base + HDMI_DATA_PORT); ++ ++ return 0; ++} ++ ++static const struct regmap_config meson_txc_hdmi_regmap_config = { ++ .reg_bits = 16, ++ .val_bits = 16, ++ .reg_stride = 1, ++ .reg_read = meson_txc_hdmi_reg_read, ++ .reg_write = meson_txc_hdmi_reg_write, ++ .rd_table = &meson_txc_hdmi_regmap_access, ++ .wr_table = &meson_txc_hdmi_regmap_access, ++ .max_register = HDMI_OTHER_RX_PACKET_INTR_CLR, ++ .fast_io = true, ++}; ++ ++static void meson_txc_hdmi_write_infoframe(struct regmap *regmap, ++ unsigned int tx_pkt_reg, u8 *buf, ++ unsigned int len, bool enable) ++{ ++ unsigned int i; ++ ++ /* Write the data bytes by starting at register offset 1 */ ++ for (i = HDMI_INFOFRAME_HEADER_SIZE; i < len; i++) ++ regmap_write(regmap, ++ tx_pkt_reg + i - HDMI_INFOFRAME_HEADER_SIZE + 1, ++ buf[i]); ++ ++ /* Zero all remaining data bytes */ ++ for (; i < 0x1c; i++) ++ regmap_write(regmap, tx_pkt_reg + i, 0x00); ++ ++ /* Write the header (which we skipped above) */ ++ regmap_write(regmap, tx_pkt_reg + 0x00, buf[3]); ++ regmap_write(regmap, tx_pkt_reg + 0x1c, buf[0]); ++ regmap_write(regmap, tx_pkt_reg + 0x1d, buf[1]); ++ regmap_write(regmap, tx_pkt_reg + 0x1e, buf[2]); ++ ++ regmap_write(regmap, tx_pkt_reg + 0x1f, enable ? 0xff : 0x00); ++} ++ ++static void meson_txc_hdmi_disable_infoframe(struct meson_txc_hdmi *priv, ++ unsigned int tx_pkt_reg) ++{ ++ u8 buf[HDMI_INFOFRAME_HEADER_SIZE] = { 0 }; ++ ++ meson_txc_hdmi_write_infoframe(priv->regmap, tx_pkt_reg, buf, ++ HDMI_INFOFRAME_HEADER_SIZE, false); ++} ++ ++static void meson_txc_hdmi_sys5_reset_assert(struct meson_txc_hdmi *priv) ++{ ++ /* A comment in the vendor driver says: bit5,6 is converted */ ++ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, ++ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN | ++ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN); ++ usleep_range(10, 20); ++ ++ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, ++ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | ++ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN); ++ usleep_range(10, 20); ++ ++ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, ++ TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN | ++ TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN | ++ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN | ++ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN | ++ TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN | ++ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2 | ++ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1 | ++ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0); ++ usleep_range(10, 20); ++} ++ ++static void meson_txc_hdmi_sys5_reset_deassert(struct meson_txc_hdmi *priv) ++{ ++ /* Release the resets except tmds_clk */ ++ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, ++ TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN); ++ usleep_range(10, 20); ++ ++ /* Release the tmds_clk reset as well */ ++ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, 0x0); ++ usleep_range(10, 20); ++ ++ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, ++ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | ++ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN | ++ TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST); ++ usleep_range(10, 20); ++ ++ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, ++ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | ++ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN); ++ usleep_range(10, 20); ++} ++ ++static void meson_txc_hdmi_config_hdcp_registers(struct meson_txc_hdmi *priv) ++{ ++ regmap_write(priv->regmap, TX_HDCP_CONFIG0, ++ FIELD_PREP(TX_HDCP_CONFIG0_ROM_ENCRYPT_OFF, 0x3)); ++ regmap_write(priv->regmap, TX_HDCP_MEM_CONFIG, 0x0); ++ regmap_write(priv->regmap, TX_HDCP_ENCRYPT_BYTE, 0x0); ++ ++ regmap_write(priv->regmap, TX_HDCP_MODE, TX_HDCP_MODE_CLEAR_AVMUTE); ++ ++ regmap_write(priv->regmap, TX_HDCP_MODE, TX_HDCP_MODE_ESS_CONFIG); ++} ++ ++static u8 meson_txc_hdmi_bus_fmt_to_color_depth(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ /* 8 bit */ ++ return 0x0; ++ ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ /* 10 bit */ ++ return 0x1; ++ ++ case MEDIA_BUS_FMT_RGB121212_1X36: ++ case MEDIA_BUS_FMT_YUV12_1X36: ++ case MEDIA_BUS_FMT_UYVY12_1X24: ++ /* 12 bit */ ++ return 0x2; ++ ++ case MEDIA_BUS_FMT_RGB161616_1X48: ++ case MEDIA_BUS_FMT_YUV16_1X48: ++ /* 16 bit */ ++ return 0x3; ++ ++ default: ++ /* unknown, default to 8 bit */ ++ return 0x0; ++ } ++} ++ ++static u8 meson_txc_hdmi_bus_fmt_to_color_format(unsigned int bus_format) ++{ ++ switch (bus_format) { ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ case MEDIA_BUS_FMT_YUV12_1X36: ++ case MEDIA_BUS_FMT_YUV16_1X48: ++ /* Documented as YCbCr444 */ ++ return 0x1; ++ ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ case MEDIA_BUS_FMT_UYVY12_1X24: ++ /* Documented as YCbCr422 */ ++ return 0x3; ++ ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ case MEDIA_BUS_FMT_RGB121212_1X36: ++ case MEDIA_BUS_FMT_RGB161616_1X48: ++ default: ++ /* Documented as RGB444 */ ++ return 0x0; ++ } ++} ++ ++static void meson_txc_hdmi_config_color_space(struct meson_txc_hdmi *priv, ++ unsigned int input_bus_format, ++ unsigned int output_bus_format, ++ enum hdmi_quantization_range quant_range, ++ enum hdmi_colorimetry colorimetry) ++{ ++ unsigned int regval; ++ ++ regmap_write(priv->regmap, TX_VIDEO_DTV_MODE, ++ FIELD_PREP(TX_VIDEO_DTV_MODE_COLOR_DEPTH, ++ meson_txc_hdmi_bus_fmt_to_color_depth(output_bus_format))); ++ ++ regmap_write(priv->regmap, TX_VIDEO_DTV_OPTION_L, ++ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_FORMAT, ++ meson_txc_hdmi_bus_fmt_to_color_format(output_bus_format)) | ++ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_FORMAT, ++ meson_txc_hdmi_bus_fmt_to_color_format(input_bus_format)) | ++ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_DEPTH, ++ meson_txc_hdmi_bus_fmt_to_color_depth(output_bus_format)) | ++ FIELD_PREP(TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_DEPTH, ++ meson_txc_hdmi_bus_fmt_to_color_depth(input_bus_format))); ++ ++ if (quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) ++ regval = FIELD_PREP(TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE, ++ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235) | ++ FIELD_PREP(TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE, ++ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235); ++ else ++ regval = FIELD_PREP(TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE, ++ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255) | ++ FIELD_PREP(TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE, ++ TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255); ++ ++ regmap_write(priv->regmap, TX_VIDEO_DTV_OPTION_H, regval); ++ ++ if (colorimetry == HDMI_COLORIMETRY_ITU_601) { ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B0, 0x2f); ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B1, 0x1d); ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R0, 0x8b); ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R1, 0x4c); ++ ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB0, 0x18); ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB1, 0x58); ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR0, 0xd0); ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR1, 0xb6); ++ } else { ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B0, 0x7b); ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_B1, 0x12); ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R0, 0x6c); ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_R1, 0x36); ++ ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB0, 0xf2); ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CB1, 0x2f); ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR0, 0xd4); ++ regmap_write(priv->regmap, TX_VIDEO_CSC_COEFF_CR1, 0x77); ++ } ++} ++ ++static void meson_txc_hdmi_config_serializer_clock(struct meson_txc_hdmi *priv, ++ enum hdmi_colorimetry colorimetry) ++{ ++ /* Serializer Internal clock setting */ ++ if (colorimetry == HDMI_COLORIMETRY_ITU_601) ++ regmap_write(priv->regmap, TX_SYS1_PLL, 0x24); ++ else ++ regmap_write(priv->regmap, TX_SYS1_PLL, 0x22); ++ ++#if 0 ++ // TODO: not ported yet ++ if ((param->VIC==HDMI_1080p60)&&(param->color_depth==COLOR_30BIT)&&(hdmi_rd_reg(0x018)==0x22)) { ++ regmap_write(priv->regmap, TX_SYS1_PLL, 0x12); ++ } ++#endif ++} ++ ++static void meson_txc_hdmi_reconfig_packet_setting(struct meson_txc_hdmi *priv, ++ u8 cea_mode) ++{ ++ u8 alloc_active2, alloc_eof1, alloc_sof1, alloc_sof2; ++ ++ regmap_write(priv->regmap, TX_PACKET_CONTROL_1, ++ FIELD_PREP(TX_PACKET_CONTROL_1_PACKET_START_LATENCY, 58)); ++ regmap_write(priv->regmap, TX_PACKET_CONTROL_2, ++ TX_PACKET_CONTROL_2_HORIZONTAL_GC_PACKET_TRANSPORT_EN); ++ ++ switch (cea_mode) { ++ case 31: ++ /* 1920x1080p50 */ ++ alloc_active2 = 0x12; ++ alloc_eof1 = 0x10; ++ alloc_sof1 = 0xb6; ++ alloc_sof2 = 0x11; ++ break; ++ case 93: ++ /* 3840x2160p24 */ ++ alloc_active2 = 0x12; ++ alloc_eof1 = 0x47; ++ alloc_sof1 = 0xf8; ++ alloc_sof2 = 0x52; ++ break; ++ case 94: ++ /* 3840x2160p25 */ ++ alloc_active2 = 0x12; ++ alloc_eof1 = 0x44; ++ alloc_sof1 = 0xda; ++ alloc_sof2 = 0x52; ++ break; ++ case 95: ++ /* 3840x2160p30 */ ++ alloc_active2 = 0x0f; ++ alloc_eof1 = 0x3a; ++ alloc_sof1 = 0x60; ++ alloc_sof2 = 0x52; ++ break; ++ case 98: ++ /* 4096x2160p24 */ ++ alloc_active2 = 0x12; ++ alloc_eof1 = 0x47; ++ alloc_sof1 = 0xf8; ++ alloc_sof2 = 0x52; ++ break; ++ default: ++ /* Disable the special packet settings only */ ++ regmap_write(priv->regmap, TX_PACKET_ALLOC_ACTIVE_1, 0x00); ++ return; ++ } ++ ++ /* ++ * The vendor driver says: manually configure these register to get ++ * stable video timings. ++ */ ++ regmap_write(priv->regmap, TX_PACKET_ALLOC_ACTIVE_1, 0x01); ++ regmap_write(priv->regmap, TX_PACKET_ALLOC_ACTIVE_2, alloc_active2); ++ regmap_write(priv->regmap, TX_PACKET_ALLOC_EOF_1, alloc_eof1); ++ regmap_write(priv->regmap, TX_PACKET_ALLOC_EOF_2, 0x12); ++ regmap_write(priv->regmap, TX_CORE_ALLOC_VSYNC_0, 0x01); ++ regmap_write(priv->regmap, TX_CORE_ALLOC_VSYNC_1, 0x00); ++ regmap_write(priv->regmap, TX_CORE_ALLOC_VSYNC_2, 0x0a); ++ regmap_write(priv->regmap, TX_PACKET_ALLOC_SOF_1, alloc_sof1); ++ regmap_write(priv->regmap, TX_PACKET_ALLOC_SOF_2, alloc_sof2); ++ regmap_update_bits(priv->regmap, TX_PACKET_CONTROL_1, ++ TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING, ++ TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING); ++} ++ ++static void meson_txc_hdmi_set_avi_infoframe(struct meson_txc_hdmi *priv, ++ struct drm_connector *conn, ++ const struct drm_display_mode *mode, ++ const struct drm_connector_state *conn_state, ++ unsigned int output_bus_format, ++ enum hdmi_quantization_range quant_range, ++ enum hdmi_colorimetry colorimetry) ++{ ++ u8 buf[HDMI_INFOFRAME_SIZE(AVI)], *video_code; ++ struct hdmi_avi_infoframe frame; ++ int ret; ++ ++ ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, conn, mode); ++ if (ret < 0) { ++ drm_err(priv->bridge.dev, ++ "Failed to setup AVI infoframe: %d\n", ret); ++ return; ++ } ++ ++ switch (output_bus_format) { ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ case MEDIA_BUS_FMT_YUV12_1X36: ++ case MEDIA_BUS_FMT_YUV16_1X48: ++ frame.colorspace = HDMI_COLORSPACE_YUV444; ++ break; ++ ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ case MEDIA_BUS_FMT_UYVY12_1X24: ++ frame.colorspace = HDMI_COLORSPACE_YUV422; ++ break; ++ ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ case MEDIA_BUS_FMT_RGB121212_1X36: ++ case MEDIA_BUS_FMT_RGB161616_1X48: ++ default: ++ frame.colorspace = HDMI_COLORSPACE_RGB; ++ break; ++ } ++ ++ drm_hdmi_avi_infoframe_colorimetry(&frame, conn_state); ++ drm_hdmi_avi_infoframe_quant_range(&frame, conn, mode, quant_range); ++ drm_hdmi_avi_infoframe_bars(&frame, conn_state); ++ ++ ret = hdmi_avi_infoframe_pack(&frame, buf, sizeof(buf)); ++ if (ret < 0) { ++ drm_err(priv->bridge.dev, ++ "Failed to pack AVI infoframe: %d\n", ret); ++ return; ++ } ++ ++ video_code = &buf[HDMI_INFOFRAME_HEADER_SIZE + 3]; ++ if (*video_code > 108) { ++ regmap_write(priv->regmap, TX_PKT_REG_EXCEPT0_BASE_ADDR, ++ *video_code); ++ *video_code = 0x00; ++ } else { ++ regmap_write(priv->regmap, TX_PKT_REG_EXCEPT0_BASE_ADDR, ++ 0x00); ++ } ++ ++ meson_txc_hdmi_write_infoframe(priv->regmap, ++ TX_PKT_REG_AVI_INFO_BASE_ADDR, buf, ++ sizeof(buf), true); ++} ++ ++static void meson_txc_hdmi_set_vendor_infoframe(struct meson_txc_hdmi *priv, ++ struct drm_connector *conn, ++ const struct drm_display_mode *mode) ++{ ++ u8 buf[HDMI_INFOFRAME_HEADER_SIZE + 6]; ++ struct hdmi_vendor_infoframe frame; ++ int ret; ++ ++ ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame, conn, mode); ++ if (ret) { ++ drm_dbg(priv->bridge.dev, ++ "Failed to setup vendor infoframe: %d\n", ret); ++ return; ++ } ++ ++ ret = hdmi_vendor_infoframe_pack(&frame, buf, sizeof(buf)); ++ if (ret < 0) { ++ drm_err(priv->bridge.dev, ++ "Failed to pack vendor infoframe: %d\n", ret); ++ return; ++ } ++ ++ meson_txc_hdmi_write_infoframe(priv->regmap, ++ TX_PKT_REG_VEND_INFO_BASE_ADDR, buf, ++ sizeof(buf), true); ++} ++ ++static void meson_txc_hdmi_set_spd_infoframe(struct meson_txc_hdmi *priv) ++{ ++ u8 buf[HDMI_INFOFRAME_SIZE(SPD)]; ++ struct hdmi_spd_infoframe frame; ++ int ret; ++ ++ ret = hdmi_spd_infoframe_init(&frame, "Amlogic", "Meson TXC HDMI"); ++ if (ret < 0) { ++ drm_err(priv->bridge.dev, ++ "Failed to setup SPD infoframe: %d\n", ret); ++ return; ++ } ++ ++ ret = hdmi_spd_infoframe_pack(&frame, buf, sizeof(buf)); ++ if (ret < 0) { ++ drm_err(priv->bridge.dev, ++ "Failed to pack SDP infoframe: %d\n", ret); ++ return; ++ } ++ ++ meson_txc_hdmi_write_infoframe(priv->regmap, ++ TX_PKT_REG_SPD_INFO_BASE_ADDR, buf, ++ sizeof(buf), true); ++} ++ ++static void meson_txc_hdmi_handle_plugged_change(struct meson_txc_hdmi *priv) ++{ ++ bool plugged; ++ ++ plugged = priv->last_connector_status == connector_status_connected; ++ ++ if (priv->codec_dev && priv->codec_plugged_cb) ++ priv->codec_plugged_cb(priv->codec_dev, plugged); ++} ++ ++static int meson_txc_hdmi_bridge_attach(struct drm_bridge *bridge, ++ enum drm_bridge_attach_flags flags) ++{ ++ struct meson_txc_hdmi *priv = bridge->driver_private; ++ ++ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { ++ drm_err(bridge->dev, ++ "DRM_BRIDGE_ATTACH_NO_CONNECTOR flag is not set but needed\n"); ++ return -EINVAL; ++ } ++ ++ return drm_bridge_attach(bridge->encoder, priv->next_bridge, bridge, ++ flags); ++} ++ ++/* Can return a maximum of 11 possible output formats for a mode/connector */ ++#define MAX_OUTPUT_SEL_FORMATS 11 ++ ++static u32 * ++meson_txc_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, ++ struct drm_bridge_state *bridge_state, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state, ++ unsigned int *num_output_fmts) ++{ ++ struct drm_connector *conn = conn_state->connector; ++ struct drm_display_info *info = &conn->display_info; ++ u8 max_bpc = conn_state->max_requested_bpc; ++ unsigned int i = 0; ++ u32 *output_fmts; ++ ++ *num_output_fmts = 0; ++ ++ output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), ++ GFP_KERNEL); ++ if (!output_fmts) ++ return NULL; ++ ++ /* If we are the only bridge, avoid negotiating with ourselves */ ++ if (list_is_singular(&bridge->encoder->bridge_chain)) { ++ *num_output_fmts = 1; ++ output_fmts[0] = MEDIA_BUS_FMT_FIXED; ++ ++ return output_fmts; ++ } ++ ++ /* ++ * Order bus formats from 16bit to 8bit and from YUV422 to RGB ++ * if supported. In any case the default RGB888 format is added ++ */ ++ ++ if (max_bpc >= 16 && info->bpc == 16) { ++ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) ++ output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; ++ ++ output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; ++ } ++ ++ if (max_bpc >= 12 && info->bpc >= 12) { ++ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) ++ output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; ++ ++ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) ++ output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; ++ ++ output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; ++ } ++ ++ if (max_bpc >= 10 && info->bpc >= 10) { ++ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) ++ output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; ++ ++ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) ++ output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; ++ ++ output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; ++ } ++ ++ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) ++ output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; ++ ++ if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) ++ output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; ++ ++ /* Default 8bit RGB fallback */ ++ output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; ++ ++ *num_output_fmts = i; ++ ++ return output_fmts; ++} ++ ++/* Can return a maximum of 3 possible input formats for an output format */ ++#define MAX_INPUT_SEL_FORMATS 3 ++ ++static u32 * ++meson_txc_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, ++ struct drm_bridge_state *bridge_state, ++ struct drm_crtc_state *crtc_state, ++ struct drm_connector_state *conn_state, ++ u32 output_fmt, ++ unsigned int *num_input_fmts) ++{ ++ u32 *input_fmts; ++ unsigned int i = 0; ++ ++ *num_input_fmts = 0; ++ ++ input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), ++ GFP_KERNEL); ++ if (!input_fmts) ++ return NULL; ++ ++ switch (output_fmt) { ++ /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ ++ case MEDIA_BUS_FMT_FIXED: ++ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; ++ break; ++ ++ /* 8bit */ ++ case MEDIA_BUS_FMT_RGB888_1X24: ++ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; ++ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; ++ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; ++ break; ++ case MEDIA_BUS_FMT_YUV8_1X24: ++ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; ++ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; ++ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; ++ break; ++ case MEDIA_BUS_FMT_UYVY8_1X16: ++ input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; ++ input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; ++ input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; ++ break; ++ ++ /* 10bit */ ++ case MEDIA_BUS_FMT_RGB101010_1X30: ++ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; ++ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; ++ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; ++ break; ++ case MEDIA_BUS_FMT_YUV10_1X30: ++ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; ++ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; ++ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; ++ break; ++ case MEDIA_BUS_FMT_UYVY10_1X20: ++ input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; ++ input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; ++ input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; ++ break; ++ ++ /* 12bit */ ++ case MEDIA_BUS_FMT_RGB121212_1X36: ++ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; ++ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; ++ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; ++ break; ++ case MEDIA_BUS_FMT_YUV12_1X36: ++ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; ++ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; ++ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; ++ break; ++ case MEDIA_BUS_FMT_UYVY12_1X24: ++ input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; ++ input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; ++ input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; ++ break; ++ ++ /* 16bit */ ++ case MEDIA_BUS_FMT_RGB161616_1X48: ++ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; ++ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; ++ break; ++ case MEDIA_BUS_FMT_YUV16_1X48: ++ input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; ++ input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; ++ break; ++ } ++ ++ *num_input_fmts = i; ++ ++ if (*num_input_fmts == 0) { ++ kfree(input_fmts); ++ input_fmts = NULL; ++ } ++ ++ return input_fmts; ++} ++ ++static void meson_txc_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, ++ struct drm_bridge_state *old_bridge_state) ++{ ++ struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge); ++ struct drm_atomic_state *state = old_bridge_state->base.state; ++ enum hdmi_quantization_range quant_range; ++ struct drm_connector_state *conn_state; ++ struct drm_bridge_state *bridge_state; ++ const struct drm_display_mode *mode; ++ enum hdmi_colorimetry colorimetry; ++ struct drm_crtc_state *crtc_state; ++ struct drm_connector *connector; ++ unsigned int i; ++ u8 cea_mode; ++ ++ bridge_state = drm_atomic_get_new_bridge_state(state, bridge); ++ ++ connector = drm_atomic_get_new_connector_for_encoder(state, ++ bridge->encoder); ++ if (WARN_ON(!connector)) ++ return; ++ ++ conn_state = drm_atomic_get_new_connector_state(state, connector); ++ if (WARN_ON(!conn_state)) ++ return; ++ ++ crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); ++ if (WARN_ON(!crtc_state)) ++ return; ++ ++ priv->current_connector = connector; ++ ++ mode = &crtc_state->adjusted_mode; ++ ++ cea_mode = drm_match_cea_mode(mode); ++ ++ if (connector->display_info.is_hdmi) { ++ quant_range = drm_default_rgb_quant_range(mode); ++ ++ switch (cea_mode) { ++ case 2 ... 3: ++ case 6 ... 7: ++ case 17 ... 18: ++ case 21 ... 22: ++ colorimetry = HDMI_COLORIMETRY_ITU_601; ++ break; ++ ++ default: ++ colorimetry = HDMI_COLORIMETRY_ITU_709; ++ break; ++ } ++ ++ meson_txc_hdmi_set_avi_infoframe(priv, connector, mode, ++ conn_state, ++ bridge_state->output_bus_cfg.format, ++ quant_range, colorimetry); ++ meson_txc_hdmi_set_vendor_infoframe(priv, connector, mode); ++ meson_txc_hdmi_set_spd_infoframe(priv); ++ } else { ++ quant_range = HDMI_QUANTIZATION_RANGE_FULL; ++ colorimetry = HDMI_COLORIMETRY_NONE; ++ } ++ ++ meson_txc_hdmi_sys5_reset_assert(priv); ++ ++ meson_txc_hdmi_config_hdcp_registers(priv); ++ ++ if (cea_mode == 39) ++ regmap_write(priv->regmap, TX_VIDEO_DTV_TIMING, 0x0); ++ else ++ regmap_write(priv->regmap, TX_VIDEO_DTV_TIMING, ++ TX_VIDEO_DTV_TIMING_DISABLE_VIC39_CORRECTION); ++ ++ regmap_write(priv->regmap, TX_CORE_DATA_CAPTURE_2, ++ TX_CORE_DATA_CAPTURE_2_INTERNAL_PACKET_ENABLE); ++ regmap_write(priv->regmap, TX_CORE_DATA_MONITOR_1, ++ TX_CORE_DATA_MONITOR_1_LANE0 | ++ FIELD_PREP(TX_CORE_DATA_MONITOR_1_SELECT_LANE0, 0x7)); ++ regmap_write(priv->regmap, TX_CORE_DATA_MONITOR_2, ++ FIELD_PREP(TX_CORE_DATA_MONITOR_2_MONITOR_SELECT, 0x2)); ++ ++ if (connector->display_info.is_hdmi) ++ regmap_write(priv->regmap, TX_TMDS_MODE, ++ TX_TMDS_MODE_FORCED_HDMI | ++ TX_TMDS_MODE_HDMI_CONFIG); ++ else ++ regmap_write(priv->regmap, TX_TMDS_MODE, ++ TX_TMDS_MODE_FORCED_HDMI); ++ ++ regmap_write(priv->regmap, TX_SYS4_CONNECT_SEL_1, 0x0); ++ ++ /* ++ * Set tmds_clk pattern to be "0000011111" before being sent to AFE ++ * clock channel. ++ */ ++ regmap_write(priv->regmap, TX_SYS4_CK_INV_VIDEO, ++ TX_SYS4_CK_INV_VIDEO_TMDS_CLK_PATTERN); ++ ++ regmap_write(priv->regmap, TX_SYS5_FIFO_CONFIG, ++ TX_SYS5_FIFO_CONFIG_CLK_CHANNEL3_OUTPUT_ENABLE | ++ TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_ENABLE | ++ TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_ENABLE | ++ TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_ENABLE); ++ ++ meson_txc_hdmi_config_color_space(priv, ++ bridge_state->input_bus_cfg.format, ++ bridge_state->output_bus_cfg.format, ++ quant_range, colorimetry); ++ ++ meson_txc_hdmi_sys5_reset_deassert(priv); ++ ++ meson_txc_hdmi_config_serializer_clock(priv, colorimetry); ++ meson_txc_hdmi_reconfig_packet_setting(priv, cea_mode); ++ ++ /* all resets need to be applied twice */ ++ for (i = 0; i < 2; i++) { ++ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, ++ TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN | ++ TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN | ++ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN | ++ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN | ++ TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN | ++ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2 | ++ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1 | ++ TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0); ++ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, ++ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN | ++ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN | ++ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN | ++ TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN | ++ TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST | ++ TX_SYS5_TX_SOFT_RESET_2_TX_DDC_HDCP_RSTN | ++ TX_SYS5_TX_SOFT_RESET_2_TX_DDC_EDID_RSTN | ++ TX_SYS5_TX_SOFT_RESET_2_TX_DIG_RESET_N_CH3); ++ usleep_range(5000, 10000); ++ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, 0x00); ++ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_2, 0x00); ++ usleep_range(5000, 10000); ++ } ++ ++ if (!priv->phy_is_on) { ++ int ret; ++ ++ ret = phy_power_on(priv->phy); ++ if (ret) ++ drm_err(bridge->dev, "Failed to turn on PHY\n"); ++ else ++ priv->phy_is_on = true; ++ } ++} ++ ++static void meson_txc_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, ++ struct drm_bridge_state *old_bridge_state) ++{ ++ struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge); ++ ++ priv->current_connector = NULL; ++ ++ if (priv->phy_is_on) { ++ int ret; ++ ++ ret = phy_power_off(priv->phy); ++ if (ret) ++ drm_err(bridge->dev, "Failed to turn off PHY\n"); ++ else ++ priv->phy_is_on = false; ++ } ++ ++ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_AUDIO_INFO_BASE_ADDR); ++ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_AVI_INFO_BASE_ADDR); ++ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_EXCEPT0_BASE_ADDR); ++ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_VEND_INFO_BASE_ADDR); ++} ++ ++static enum drm_mode_status ++meson_txc_hdmi_bridge_mode_valid(struct drm_bridge *bridge, ++ const struct drm_display_info *info, ++ const struct drm_display_mode *mode) ++{ ++ return MODE_OK; ++} ++ ++static enum drm_connector_status meson_txc_hdmi_bridge_detect(struct drm_bridge *bridge) ++{ ++ struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge); ++ enum drm_connector_status status; ++ unsigned int val; ++ ++ regmap_read(priv->regmap, TX_HDCP_ST_EDID_STATUS, &val); ++ if (val & TX_HDCP_ST_EDID_STATUS_HPD_STATUS) ++ status = connector_status_connected; ++ else ++ status = connector_status_disconnected; ++ ++ mutex_lock(&priv->codec_mutex); ++ if (priv->last_connector_status != status) { ++ priv->last_connector_status = status; ++ meson_txc_hdmi_handle_plugged_change(priv); ++ } ++ mutex_unlock(&priv->codec_mutex); ++ ++ return status; ++} ++ ++static int meson_txc_hdmi_get_edid_block(void *data, u8 *buf, unsigned int block, ++ size_t len) ++{ ++ unsigned int i, regval, start = block * EDID_LENGTH; ++ struct meson_txc_hdmi *priv = data; ++ int ret; ++ ++ /* Start the DDC transaction */ ++ regmap_update_bits(priv->regmap, TX_HDCP_EDID_CONFIG, ++ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG, 0); ++ regmap_update_bits(priv->regmap, TX_HDCP_EDID_CONFIG, ++ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG, ++ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG); ++ ++ ret = regmap_read_poll_timeout(priv->regmap, ++ TX_HDCP_ST_EDID_STATUS, ++ regval, ++ (regval & TX_HDCP_ST_EDID_STATUS_EDID_DATA_READY), ++ 1000, 200000); ++ ++ regmap_update_bits(priv->regmap, TX_HDCP_EDID_CONFIG, ++ TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG, 0); ++ ++ if (ret) ++ return ret; ++ ++ for (i = 0; i < len; i++) { ++ regmap_read(priv->regmap, TX_RX_EDID_OFFSET + start + i, ++ ®val); ++ buf[i] = regval; ++ } ++ ++ return 0; ++} ++ ++static const struct drm_edid *meson_txc_hdmi_bridge_edid_read(struct drm_bridge *bridge, ++ struct drm_connector *connector) ++{ ++ struct meson_txc_hdmi *priv = bridge_to_meson_txc_hdmi(bridge); ++ const struct drm_edid *drm_edid; ++ ++ drm_edid = drm_edid_read_custom(connector, ++ meson_txc_hdmi_get_edid_block, priv); ++ if (!drm_edid) { ++ drm_dbg(priv->bridge.dev, "Failed to get EDID\n"); ++ return NULL; ++ } ++ ++ return drm_edid; ++} ++ ++static const struct drm_bridge_funcs meson_txc_hdmi_bridge_funcs = { ++ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, ++ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, ++ .atomic_reset = drm_atomic_helper_bridge_reset, ++ .attach = meson_txc_hdmi_bridge_attach, ++ .atomic_get_output_bus_fmts = meson_txc_hdmi_bridge_atomic_get_output_bus_fmts, ++ .atomic_get_input_bus_fmts = meson_txc_hdmi_bridge_atomic_get_input_bus_fmts, ++ .atomic_enable = meson_txc_hdmi_bridge_atomic_enable, ++ .atomic_disable = meson_txc_hdmi_bridge_atomic_disable, ++ .mode_valid = meson_txc_hdmi_bridge_mode_valid, ++ .detect = meson_txc_hdmi_bridge_detect, ++ .edid_read = meson_txc_hdmi_bridge_edid_read, ++}; ++ ++static int meson_txc_hdmi_hw_init(struct meson_txc_hdmi *priv) ++{ ++ unsigned long ddc_i2c_bus_clk_hz = 500 * 1000; ++ unsigned long sys_clk_hz = 24 * 1000 * 1000; ++ int ret; ++ ++ ret = phy_init(priv->phy); ++ if (ret) { ++ dev_err(priv->dev, "Failed to initialize the PHY: %d\n", ret); ++ return ret; ++ } ++ ++ ret = clk_set_rate(priv->sys_clk, sys_clk_hz); ++ if (ret) { ++ dev_err(priv->dev, "Failed to set HDMI system clock to 24MHz\n"); ++ goto err_phy_exit; ++ } ++ ++ ret = clk_prepare_enable(priv->sys_clk); ++ if (ret) { ++ dev_err(priv->dev, "Failed to enable the sys clk\n"); ++ goto err_phy_exit; ++ } ++ ++ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, ++ HDMI_OTHER_CTRL1_POWER_ON, ++ HDMI_OTHER_CTRL1_POWER_ON); ++ ++ regmap_write(priv->regmap, TX_HDMI_PHY_CONFIG0, ++ TX_HDMI_PHY_CONFIG0_HDMI_COMMON_B7_B0); ++ ++ regmap_write(priv->regmap, TX_HDCP_MODE, 0x40); ++ ++ /* ++ * The vendor driver comments that this is a setting for "Band-gap and ++ * main-bias". 0x1d = power-up, 0x00 = power-down. ++ */ ++ regmap_write(priv->regmap, TX_SYS1_AFE_TEST, 0x1d); ++ ++ meson_txc_hdmi_config_serializer_clock(priv, HDMI_COLORIMETRY_NONE); ++ ++ /* ++ * The vendor driver has a comment with the following information for ++ * the magic value: ++ * bit[2:0]=011: CK channel output TMDS CLOCK ++ * bit[2:0]=101, ck channel output PHYCLCK ++ */ ++ regmap_write(priv->regmap, TX_SYS1_AFE_CONNECT, 0xfb); ++ ++ /* Termination resistor calib value */ ++ regmap_write(priv->regmap, TX_CORE_CALIB_VALUE, 0x0f); ++ ++ /* HPD glitch filter */ ++ regmap_write(priv->regmap, TX_HDCP_HPD_FILTER_L, 0xa0); ++ regmap_write(priv->regmap, TX_HDCP_HPD_FILTER_H, 0xa0); ++ ++ /* Disable MEM power-down */ ++ regmap_write(priv->regmap, TX_MEM_PD_REG0, 0x0); ++ ++ regmap_write(priv->regmap, TX_HDCP_CONFIG3, ++ FIELD_PREP(TX_HDCP_CONFIG3_DDC_I2C_BUS_CLOCK_TIME_DIVIDER, ++ (sys_clk_hz / ddc_i2c_bus_clk_hz) - 1)); ++ ++ /* Enable software controlled DDC transaction */ ++ regmap_write(priv->regmap, TX_HDCP_EDID_CONFIG, ++ TX_HDCP_EDID_CONFIG_FORCED_MEM_COPY_DONE | ++ TX_HDCP_EDID_CONFIG_MEM_COPY_DONE_CONFIG); ++ regmap_write(priv->regmap, TX_CORE_EDID_CONFIG_MORE, ++ TX_CORE_EDID_CONFIG_MORE_SYS_TRIGGER_CONFIG_SEMI_MANU); ++ ++ /* mask (= disable) all interrupts */ ++ regmap_write(priv->regmap, HDMI_OTHER_INTR_MASKN, 0x0); ++ ++ /* clear any pending interrupt */ ++ regmap_write(priv->regmap, HDMI_OTHER_INTR_STAT_CLR, ++ HDMI_OTHER_INTR_STAT_CLR_EDID_RISING | ++ HDMI_OTHER_INTR_STAT_CLR_HPD_FALLING | ++ HDMI_OTHER_INTR_STAT_CLR_HPD_RISING); ++ ++ return 0; ++ ++err_phy_exit: ++ phy_exit(priv->phy); ++ return 0; ++} ++ ++static void meson_txc_hdmi_hw_exit(struct meson_txc_hdmi *priv) ++{ ++ int ret; ++ ++ /* mask (= disable) all interrupts */ ++ regmap_write(priv->regmap, HDMI_OTHER_INTR_MASKN, ++ HDMI_OTHER_INTR_MASKN_TX_EDID_INT_RISE | ++ HDMI_OTHER_INTR_MASKN_TX_HPD_INT_FALL | ++ HDMI_OTHER_INTR_MASKN_TX_HPD_INT_RISE); ++ ++ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, ++ HDMI_OTHER_CTRL1_POWER_ON, 0); ++ ++ clk_disable_unprepare(priv->sys_clk); ++ ++ ret = phy_exit(priv->phy); ++ if (ret) ++ dev_err(priv->dev, "Failed to exit the PHY: %d\n", ret); ++} ++ ++static u32 meson_txc_hdmi_hdmi_codec_calc_audio_n(struct hdmi_codec_params *hparms) ++{ ++ u32 audio_n; ++ ++ if ((hparms->sample_rate % 44100) == 0) ++ audio_n = (128 * hparms->sample_rate) / 900; ++ else ++ audio_n = (128 * hparms->sample_rate) / 1000; ++ ++ if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_EAC3 || ++ hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_DTS_HD) ++ audio_n *= 4; ++ ++ return audio_n; ++} ++ ++static u8 meson_txc_hdmi_hdmi_codec_coding_type(struct hdmi_codec_params *hparms) ++{ ++ switch (hparms->cea.coding_type) { ++ case HDMI_AUDIO_CODING_TYPE_MLP: ++ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_HBR_AUDIO_PACKET; ++ case HDMI_AUDIO_CODING_TYPE_DSD: ++ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_ONE_BIT_AUDIO; ++ case HDMI_AUDIO_CODING_TYPE_DST: ++ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_DST_AUDIO_PACKET; ++ default: ++ return TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_AUDIO_SAMPLE_PACKET; ++ } ++} ++ ++static int meson_txc_hdmi_hdmi_codec_hw_params(struct device *dev, void *data, ++ struct hdmi_codec_daifmt *fmt, ++ struct hdmi_codec_params *hparms) ++{ ++ struct meson_txc_hdmi *priv = dev_get_drvdata(dev); ++ u8 buf[HDMI_INFOFRAME_SIZE(AUDIO)]; ++ u16 audio_tx_format; ++ u32 audio_n; ++ int len, i; ++ ++ if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_MLP) { ++ /* ++ * TODO: fixed CTS is not supported yet, it needs special ++ * TX_SYS1_ACR_N_* settings ++ */ ++ return -EINVAL; ++ } ++ ++ switch (hparms->sample_width) { ++ case 16: ++ audio_tx_format = FIELD_PREP(TX_AUDIO_FORMAT_BIT_WIDTH_MASK, ++ TX_AUDIO_FORMAT_BIT_WIDTH_16); ++ break; ++ ++ case 20: ++ audio_tx_format = FIELD_PREP(TX_AUDIO_FORMAT_BIT_WIDTH_MASK, ++ TX_AUDIO_FORMAT_BIT_WIDTH_20); ++ break; ++ ++ case 24: ++ audio_tx_format = FIELD_PREP(TX_AUDIO_FORMAT_BIT_WIDTH_MASK, ++ TX_AUDIO_FORMAT_BIT_WIDTH_24); ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ switch (fmt->fmt) { ++ case HDMI_I2S: ++ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, ++ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON, ++ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON); ++ ++ audio_tx_format |= TX_AUDIO_FORMAT_SPDIF_OR_I2S | ++ TX_AUDIO_FORMAT_I2S_ONE_BIT_OR_I2S | ++ FIELD_PREP(TX_AUDIO_FORMAT_I2S_FORMAT, 0x2); ++ ++ if (hparms->channels > 2) ++ audio_tx_format |= TX_AUDIO_FORMAT_I2S_2_OR_8_CH; ++ ++ regmap_write(priv->regmap, TX_AUDIO_FORMAT, audio_tx_format); ++ ++ regmap_write(priv->regmap, TX_AUDIO_I2S, TX_AUDIO_I2S_ENABLE); ++ regmap_write(priv->regmap, TX_AUDIO_SPDIF, 0x0); ++ break; ++ ++ case HDMI_SPDIF: ++ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, ++ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON, 0x0); ++ ++ if (hparms->cea.coding_type == HDMI_AUDIO_CODING_TYPE_STREAM) ++ audio_tx_format |= TX_AUDIO_FORMAT_SPDIF_CHANNEL_STATUS_FROM_DATA_OR_REG; ++ ++ regmap_write(priv->regmap, TX_AUDIO_FORMAT, audio_tx_format); ++ ++ regmap_write(priv->regmap, TX_AUDIO_I2S, 0x0); ++ regmap_write(priv->regmap, TX_AUDIO_SPDIF, TX_AUDIO_SPDIF_ENABLE); ++ break; ++ ++ default: ++ return -EINVAL; ++ } ++ ++ if (hparms->channels > 2) ++ regmap_write(priv->regmap, TX_AUDIO_HEADER, ++ TX_AUDIO_HEADER_AUDIO_SAMPLE_PACKET_HEADER_LAYOUT1); ++ else ++ regmap_write(priv->regmap, TX_AUDIO_HEADER, 0x0); ++ ++ regmap_write(priv->regmap, TX_AUDIO_SAMPLE, ++ FIELD_PREP(TX_AUDIO_SAMPLE_CHANNEL_VALID, ++ BIT(hparms->channels) - 1)); ++ ++ audio_n = meson_txc_hdmi_hdmi_codec_calc_audio_n(hparms); ++ ++ regmap_write(priv->regmap, TX_SYS1_ACR_N_0, ++ FIELD_PREP(TX_SYS1_ACR_N_0_N_BYTE0, ++ (audio_n >> 0) & 0xff)); ++ regmap_write(priv->regmap, TX_SYS1_ACR_N_1, ++ FIELD_PREP(TX_SYS1_ACR_N_1_N_BYTE1, ++ (audio_n >> 8) & 0xff)); ++ regmap_update_bits(priv->regmap, TX_SYS1_ACR_N_2, ++ TX_SYS1_ACR_N_2_N_UPPER_NIBBLE, ++ FIELD_PREP(TX_SYS1_ACR_N_2_N_UPPER_NIBBLE, ++ (audio_n >> 16) & 0xf)); ++ ++ regmap_write(priv->regmap, TX_SYS0_ACR_CTS_0, 0x0); ++ regmap_write(priv->regmap, TX_SYS0_ACR_CTS_1, 0x0); ++ regmap_write(priv->regmap, TX_SYS0_ACR_CTS_2, ++ TX_SYS0_ACR_CTS_2_FORCE_ARC_STABLE); ++ ++ regmap_write(priv->regmap, TX_AUDIO_CONTROL, ++ TX_AUDIO_CONTROL_AUTO_AUDIO_FIFO_CLEAR | ++ FIELD_PREP(TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_MASK, ++ meson_txc_hdmi_hdmi_codec_coding_type(hparms)) | ++ TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_FLAT); ++ ++ len = hdmi_audio_infoframe_pack(&hparms->cea, buf, sizeof(buf)); ++ if (len < 0) ++ return len; ++ ++ meson_txc_hdmi_write_infoframe(priv->regmap, ++ TX_PKT_REG_AUDIO_INFO_BASE_ADDR, ++ buf, len, true); ++ ++ for (i = 0; i < ARRAY_SIZE(hparms->iec.status); i++) { ++ unsigned char sub1, sub2; ++ ++ sub1 = sub2 = hparms->iec.status[i]; ++ ++ if (i == 2) { ++ sub1 |= FIELD_PREP(IEC958_AES2_CON_CHANNEL, 1); ++ sub2 |= FIELD_PREP(IEC958_AES2_CON_CHANNEL, 2); ++ } ++ ++ regmap_write(priv->regmap, TX_IEC60958_SUB1_OFFSET + i, sub1); ++ regmap_write(priv->regmap, TX_IEC60958_SUB2_OFFSET + i, sub2); ++ } ++ ++ return 0; ++} ++ ++static int meson_txc_hdmi_hdmi_codec_audio_startup(struct device *dev, ++ void *data) ++{ ++ struct meson_txc_hdmi *priv = dev_get_drvdata(dev); ++ ++ regmap_update_bits(priv->regmap, TX_PACKET_CONTROL_2, ++ TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE, 0x0); ++ ++ /* reset audio master and sample */ ++ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, ++ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN | ++ TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN); ++ regmap_write(priv->regmap, TX_SYS5_TX_SOFT_RESET_1, 0x0); ++ ++ regmap_write(priv->regmap, TX_AUDIO_CONTROL_MORE, ++ TX_AUDIO_CONTROL_MORE_ENABLE); ++ ++ regmap_write(priv->regmap, TX_AUDIO_FIFO, ++ FIELD_PREP(TX_AUDIO_FIFO_FIFO_DEPTH_MASK, ++ TX_AUDIO_FIFO_FIFO_DEPTH_512) | ++ FIELD_PREP(TX_AUDIO_FIFO_CRITICAL_THRESHOLD_MASK, ++ TX_AUDIO_FIFO_CRITICAL_THRESHOLD_DEPTH_DIV16) | ++ FIELD_PREP(TX_AUDIO_FIFO_NORMAL_THRESHOLD_MASK, ++ TX_AUDIO_FIFO_NORMAL_THRESHOLD_DEPTH_DIV8)); ++ ++ regmap_write(priv->regmap, TX_AUDIO_LIPSYNC, 0x0); ++ ++ regmap_write(priv->regmap, TX_SYS1_ACR_N_2, ++ FIELD_PREP(TX_SYS1_ACR_N_2_N_MEAS_TOLERANCE, 0x3)); ++ ++ return 0; ++} ++ ++static void meson_txc_hdmi_hdmi_codec_audio_shutdown(struct device *dev, ++ void *data) ++{ ++ struct meson_txc_hdmi *priv = dev_get_drvdata(dev); ++ ++ meson_txc_hdmi_disable_infoframe(priv, TX_PKT_REG_AUDIO_INFO_BASE_ADDR); ++ ++ regmap_write(priv->regmap, TX_AUDIO_CONTROL_MORE, 0x0); ++ regmap_update_bits(priv->regmap, HDMI_OTHER_CTRL1, ++ HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON, 0x0); ++ ++ regmap_update_bits(priv->regmap, TX_PACKET_CONTROL_2, ++ TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE, ++ TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE); ++} ++ ++static int meson_txc_hdmi_hdmi_codec_mute_stream(struct device *dev, ++ void *data, bool enable, ++ int direction) ++{ ++ struct meson_txc_hdmi *priv = dev_get_drvdata(dev); ++ ++ regmap_write(priv->regmap, TX_AUDIO_PACK, ++ enable ? 0 : TX_AUDIO_PACK_AUDIO_SAMPLE_PACKETS_ENABLE); ++ ++ return 0; ++} ++ ++static int meson_txc_hdmi_hdmi_codec_get_eld(struct device *dev, void *data, ++ uint8_t *buf, size_t len) ++{ ++ struct meson_txc_hdmi *priv = dev_get_drvdata(dev); ++ ++ if (priv->current_connector) ++ memcpy(buf, priv->current_connector->eld, ++ min_t(size_t, MAX_ELD_BYTES, len)); ++ else ++ memset(buf, 0, len); ++ ++ return 0; ++} ++ ++static int meson_txc_hdmi_hdmi_codec_get_dai_id(struct snd_soc_component *component, ++ struct device_node *endpoint) ++{ ++ struct of_endpoint of_ep; ++ int ret; ++ ++ ret = of_graph_parse_endpoint(endpoint, &of_ep); ++ if (ret < 0) ++ return ret; ++ ++ /* ++ * HDMI sound should be located as reg = <2> ++ * Then, it is sound port 0 ++ */ ++ if (of_ep.port == 2) ++ return 0; ++ ++ return -EINVAL; ++} ++ ++static int meson_txc_hdmi_hdmi_codec_hook_plugged_cb(struct device *dev, ++ void *data, ++ hdmi_codec_plugged_cb fn, ++ struct device *codec_dev) ++{ ++ struct meson_txc_hdmi *priv = dev_get_drvdata(dev); ++ ++ mutex_lock(&priv->codec_mutex); ++ priv->codec_plugged_cb = fn; ++ priv->codec_dev = codec_dev; ++ meson_txc_hdmi_handle_plugged_change(priv); ++ mutex_unlock(&priv->codec_mutex); ++ ++ return 0; ++} ++ ++static struct hdmi_codec_ops meson_txc_hdmi_hdmi_codec_ops = { ++ .hw_params = meson_txc_hdmi_hdmi_codec_hw_params, ++ .audio_startup = meson_txc_hdmi_hdmi_codec_audio_startup, ++ .audio_shutdown = meson_txc_hdmi_hdmi_codec_audio_shutdown, ++ .mute_stream = meson_txc_hdmi_hdmi_codec_mute_stream, ++ .get_eld = meson_txc_hdmi_hdmi_codec_get_eld, ++ .get_dai_id = meson_txc_hdmi_hdmi_codec_get_dai_id, ++ .hook_plugged_cb = meson_txc_hdmi_hdmi_codec_hook_plugged_cb, ++}; ++ ++static const struct hdmi_codec_pdata meson_txc_hdmi_codec_pdata = { ++ .ops = &meson_txc_hdmi_hdmi_codec_ops, ++ .i2s = 1, ++ .spdif = 1, ++ .max_i2s_channels = 8, ++}; ++ ++static int meson_txc_hdmi_codec_init(struct meson_txc_hdmi *priv) ++{ ++ priv->hdmi_codec_pdev = platform_device_register_data(priv->dev, ++ HDMI_CODEC_DRV_NAME, ++ PLATFORM_DEVID_AUTO, ++ &meson_txc_hdmi_codec_pdata, ++ sizeof(meson_txc_hdmi_codec_pdata)); ++ return PTR_ERR_OR_ZERO(priv->hdmi_codec_pdev); ++} ++ ++static int meson_txc_hdmi_probe(struct platform_device *pdev) ++{ ++ struct device_node *endpoint, *remote; ++ struct device *dev = &pdev->dev; ++ struct meson_txc_hdmi *priv; ++ void __iomem *base; ++ u32 regval; ++ int ret; ++ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ priv->dev = dev; ++ ++ mutex_init(&priv->codec_mutex); ++ ++ platform_set_drvdata(pdev, priv); ++ ++ base = devm_platform_ioremap_resource(pdev, 0); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ priv->regmap = devm_regmap_init(dev, NULL, base, ++ &meson_txc_hdmi_regmap_config); ++ if (IS_ERR(priv->regmap)) ++ return PTR_ERR(priv->regmap); ++ ++ priv->pclk = devm_clk_get(dev, "pclk"); ++ if (IS_ERR(priv->pclk)) ++ return dev_err_probe(dev, PTR_ERR(priv->pclk), ++ "Failed to get the pclk\n"); ++ ++ priv->sys_clk = devm_clk_get(dev, "sys"); ++ if (IS_ERR(priv->sys_clk)) ++ return dev_err_probe(dev, PTR_ERR(priv->sys_clk), ++ "Failed to get the sys clock\n"); ++ ++ priv->phy = devm_phy_get(dev, "hdmi"); ++ if (IS_ERR(priv->phy)) ++ return dev_err_probe(dev, PTR_ERR(priv->phy), ++ "Failed to get the HDMI PHY\n"); ++ ++ endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 1, -1); ++ if (!endpoint) ++ return dev_err_probe(dev, -ENODEV, ++ "Missing endpoint in port@1\n"); ++ ++ remote = of_graph_get_remote_port_parent(endpoint); ++ of_node_put(endpoint); ++ if (!remote) ++ return dev_err_probe(dev, -ENODEV, ++ "Endpoint in port@1 unconnected\n"); ++ ++ if (!of_device_is_available(remote)) { ++ of_node_put(remote); ++ return dev_err_probe(dev, -ENODEV, ++ "port@1 remote device is disabled\n"); ++ } ++ ++ priv->next_bridge = of_drm_find_bridge(remote); ++ of_node_put(remote); ++ if (!priv->next_bridge) ++ return -EPROBE_DEFER; ++ ++ ret = clk_prepare_enable(priv->pclk); ++ if (ret) ++ return dev_err_probe(dev, ret, "Failed to enable the pclk\n"); ++ ++ regval = readl(base + HDMI_CTRL_PORT); ++ regval |= HDMI_CTRL_PORT_APB3_ERR_EN; ++ writel(regval, base + HDMI_CTRL_PORT); ++ ++ ret = meson_txc_hdmi_hw_init(priv); ++ if (ret) ++ goto err_disable_clk; ++ ++ ret = meson_txc_hdmi_codec_init(priv); ++ if (ret) ++ goto err_hw_exit; ++ ++ priv->bridge.driver_private = priv; ++ priv->bridge.funcs = &meson_txc_hdmi_bridge_funcs; ++ priv->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID; ++ priv->bridge.of_node = dev->of_node; ++ priv->bridge.interlace_allowed = true; ++ ++ drm_bridge_add(&priv->bridge); ++ ++ return 0; ++ ++err_hw_exit: ++ meson_txc_hdmi_hw_exit(priv); ++err_disable_clk: ++ clk_disable_unprepare(priv->pclk); ++ return ret; ++} ++ ++static void meson_txc_hdmi_remove(struct platform_device *pdev) ++{ ++ struct meson_txc_hdmi *priv = platform_get_drvdata(pdev); ++ ++ platform_device_unregister(priv->hdmi_codec_pdev); ++ ++ drm_bridge_remove(&priv->bridge); ++ ++ meson_txc_hdmi_hw_exit(priv); ++ ++ clk_disable_unprepare(priv->pclk); ++} ++ ++static const struct of_device_id meson_txc_hdmi_of_table[] = { ++ { .compatible = "amlogic,meson8-hdmi-tx" }, ++ { .compatible = "amlogic,meson8b-hdmi-tx" }, ++ { /* sentinel */ } ++}; ++MODULE_DEVICE_TABLE(of, meson_txc_hdmi_of_table); ++ ++static struct platform_driver meson_txc_hdmi_platform_driver = { ++ .probe = meson_txc_hdmi_probe, ++ .remove_new = meson_txc_hdmi_remove, ++ .driver = { ++ .name = "meson-transwitch-hdmi", ++ .of_match_table = meson_txc_hdmi_of_table, ++ }, ++}; ++module_platform_driver(meson_txc_hdmi_platform_driver); ++ ++MODULE_AUTHOR("Martin Blumenstingl "); ++MODULE_DESCRIPTION("Amlogic Meson8 and Meson8b TranSwitch HDMI 1.4 TX driver"); ++MODULE_LICENSE("GPL v2"); +diff --git a/drivers/gpu/drm/meson/meson_transwitch_hdmi.h b/drivers/gpu/drm/meson/meson_transwitch_hdmi.h +new file mode 100644 +index 000000000..14929475c +--- /dev/null ++++ b/drivers/gpu/drm/meson/meson_transwitch_hdmi.h +@@ -0,0 +1,536 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2021 Martin Blumenstingl ++ * ++ * All registers and magic values are taken from Amlogic's GPL kernel sources: ++ * Copyright (C) 2010 Amlogic, Inc. ++ */ ++ ++#include ++#include ++ ++#ifndef __MESON_TRANSWITCH_HDMI_H__ ++#define __MESON_TRANSWITCH_HDMI_H__ ++ ++/* HDMI TX register */ ++ ++// System config 0 ++#define TX_SYS0_AFE_SIGNAL 0x0000 ++#define TX_SYS0_AFE_LOOP 0x0001 ++#define TX_SYS0_ACR_CTS_0 0x0002 ++ #define TX_SYS0_ACR_CTS_0_AUDIO_CTS_BYTE0 GENMASK(7, 0) ++#define TX_SYS0_ACR_CTS_1 0x0003 ++ #define TX_SYS0_ACR_CTS_1_AUDIO_CTS_BYTE1 GENMASK(7, 0) ++#define TX_SYS0_ACR_CTS_2 0x0004 ++ #define TX_SYS0_ACR_CTS_2_FORCE_ARC_STABLE BIT(5) ++#define TX_SYS0_BIST_CONTROL 0x0005 ++ #define TX_SYS0_BIST_CONTROL_AFE_BIST_ENABLE BIT(7) ++ #define TX_SYS0_BIST_CONTROL_TMDS_SHIFT_PATTERN_SELECT BIT(6) ++ #define TX_SYS0_BIST_CONTROL_TMDS_PRBS_PATTERN_SELECT GENMASK(5, 4) ++ #define TX_SYS0_BIST_CONTROL_TMDS_REPEAT_BIST_PATTERN GENMASK(2, 0) ++ ++#define TX_SYS0_BIST_DATA_0 0x0006 ++#define TX_SYS0_BIST_DATA_1 0x0007 ++#define TX_SYS0_BIST_DATA_2 0x0008 ++#define TX_SYS0_BIST_DATA_3 0x0009 ++#define TX_SYS0_BIST_DATA_4 0x000A ++#define TX_SYS0_BIST_DATA_5 0x000B ++#define TX_SYS0_BIST_DATA_6 0x000C ++#define TX_SYS0_BIST_DATA_7 0x000D ++#define TX_SYS0_BIST_DATA_8 0x000E ++#define TX_SYS0_BIST_DATA_9 0x000F ++ ++// system config 1 ++#define TX_HDMI_PHY_CONFIG0 0x0010 ++ #define TX_HDMI_PHY_CONFIG0_HDMI_COMMON_B7_B0 GENMASK(7, 0) ++#define TX_HDMI_PHY_CONFIG1 0x0010 ++ #define TX_HDMI_PHY_CONFIG1_HDMI_COMMON_B11_B8 GENMASK(3, 0) ++ #define TX_HDMI_PHY_CONFIG1_HDMI_CTL_REG_B3_B0 GENMASK(7, 4) ++#define TX_HDMI_PHY_CONFIG2 0x0012 ++ #define TX_HDMI_PHY_CONFIG_HDMI_CTL_REG_B11_B4 GENMASK(7, 0) ++#define TX_HDMI_PHY_CONFIG3 0x0013 ++ #define TX_HDMI_PHY_CONFIG3_HDMI_L2H_CTL GENMASK(3, 0) ++ #define TX_HDMI_PHY_CONFIG3_HDMI_MDR_PU GENMASK(7, 4) ++#define TX_HDMI_PHY_CONFIG4 0x0014 ++ #define TX_HDMI_PHY_CONFIG4_HDMI_LF_PD BIT(0) ++ #define TX_HDMI_PHY_CONFIG4_HDMI_PHY_CLK_EN BIT(1) ++ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE GENMASK(3, 2) ++ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_NORMAL 0x0 ++ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_CLK_CH3_EQUAL_CH0 0x1 ++ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_ALTERNATE_HIGH_LOW 0x2 ++ #define TX_HDMI_PHY_CONFIG4_HDMI_MODE_ALTERNATE_LOW_HIGH 0x3 ++ #define TX_HDMI_PHY_CONFIG4_HDMI_PREM_CTL GENMASK(7, 4) ++#define TX_HDMI_PHY_CONFIG5 0x0015 ++ #define TX_HDMI_PHY_CONFIG5_HDMI_VCM_CTL GENMASK(7, 5) ++ #define TX_HDMI_PHY_CONFIG5_HDMI_PREFCTL GENMASK(2, 0) ++#define TX_HDMI_PHY_CONFIG6 0x0016 ++ #define TX_HDMI_PHY_CONFIG6_HDMI_RTERM_CTL GENMASK(3, 0) ++ #define TX_HDMI_PHY_CONFIG6_HDMI_SWING_CTL GENMASK(7, 4) ++#define TX_SYS1_AFE_TEST 0x0017 ++#define TX_SYS1_PLL 0x0018 ++#define TX_SYS1_TUNE 0x0019 ++#define TX_SYS1_AFE_CONNECT 0x001A ++ ++#define TX_SYS1_ACR_N_0 0x001C ++ #define TX_SYS1_ACR_N_0_N_BYTE0 GENMASK(7, 0) ++#define TX_SYS1_ACR_N_1 0x001D ++ #define TX_SYS1_ACR_N_1_N_BYTE1 GENMASK(7, 0) ++#define TX_SYS1_ACR_N_2 0x001E ++ #define TX_SYS1_ACR_N_2_N_MEAS_TOLERANCE GENMASK(7, 4) ++ #define TX_SYS1_ACR_N_2_N_UPPER_NIBBLE GENMASK(3, 0) ++#define TX_SYS1_PRBS_DATA 0x001F ++ #define TX_SYS1_PRBS_DATA_PRBS_MODE GENMASK(1, 0) ++ #define TX_SYS1_PRBS_DATA_PRBS_MODE_11 0x0 ++ #define TX_SYS1_PRBS_DATA_PRBS_MODE_15 0x1 ++ #define TX_SYS1_PRBS_DATA_PRBS_MODE_7 0x2 ++ #define TX_SYS1_PRBS_DATA_PRBS_MODE_31 0x3 ++ ++// HDCP CONFIG ++#define TX_HDCP_ECC_CONFIG 0x0024 ++#define TX_HDCP_CRC_CONFIG 0x0025 ++#define TX_HDCP_EDID_CONFIG 0x0026 ++ #define TX_HDCP_EDID_CONFIG_FORCED_SYS_TRIGGER BIT(7) ++ #define TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG BIT(6) ++ #define TX_HDCP_EDID_CONFIG_MEM_ACC_SEQ_MODE BIT(5) ++ #define TX_HDCP_EDID_CONFIG_MEM_ACC_SEQ_START BIT(4) ++ #define TX_HDCP_EDID_CONFIG_FORCED_MEM_COPY_DONE BIT(3) ++ #define TX_HDCP_EDID_CONFIG_MEM_COPY_DONE_CONFIG BIT(2) ++ #define TX_HDCP_EDID_CONFIG_SYS_TRIGGER_CONFIG_SEMI_MANU BIT(1) ++ ++#define TX_HDCP_MEM_CONFIG 0x0027 ++ #define TX_HDCP_MEM_CONFIG_READ_DECRYPT BIT(3) ++ ++#define TX_HDCP_HPD_FILTER_L 0x0028 ++#define TX_HDCP_HPD_FILTER_H 0x0029 ++#define TX_HDCP_ENCRYPT_BYTE 0x002A ++#define TX_HDCP_CONFIG0 0x002B ++ #define TX_HDCP_CONFIG0_ROM_ENCRYPT_OFF GENMASK(4, 3) ++ ++#define TX_HDCP_CONFIG1 0x002C ++#define TX_HDCP_CONFIG2 0x002D ++#define TX_HDCP_CONFIG3 0x002E ++ #define TX_HDCP_CONFIG3_DDC_I2C_BUS_CLOCK_TIME_DIVIDER GENMASK(7, 0) ++ ++#define TX_HDCP_MODE 0x002F ++ #define TX_HDCP_MODE_CP_DESIRED BIT(7) ++ #define TX_HDCP_MODE_ESS_CONFIG BIT(6) ++ #define TX_HDCP_MODE_SET_AVMUTE BIT(5) ++ #define TX_HDCP_MODE_CLEAR_AVMUTE BIT(4) ++ #define TX_HDCP_MODE_HDCP_1_1 BIT(3) ++ #define TX_HDCP_MODE_VSYNC_HSYNC_FORCED_POLARITY_SELECT BIT(2) ++ #define TX_HDCP_MODE_FORCED_VSYNC_POLARITY BIT(1) ++ #define TX_HDCP_MODE_FORCED_HSYNC_POLARITY BIT(0) ++ ++// Video config, part 1 ++#define TX_VIDEO_ACTIVE_PIXELS_0 0x0030 ++#define TX_VIDEO_ACTIVE_PIXELS_1 0x0031 ++#define TX_VIDEO_FRONT_PIXELS 0x0032 ++#define TX_VIDEO_HSYNC_PIXELS 0x0033 ++#define TX_VIDEO_BACK_PIXELS 0x0034 ++#define TX_VIDEO_ACTIVE_LINES_0 0x0035 ++#define TX_VIDEO_ACTIVE_LINES_1 0x0036 ++#define TX_VIDEO_EOF_LINES 0x0037 ++#define TX_VIDEO_VSYNC_LINES 0x0038 ++#define TX_VIDEO_SOF_LINES 0x0039 ++#define TX_VIDEO_DTV_TIMING 0x003A ++ #define TX_VIDEO_DTV_TIMING_FORCE_DTV_TIMING_AUTO BIT(7) ++ #define TX_VIDEO_DTV_TIMING_FORCE_VIDEO_SCAN BIT(6) ++ #define TX_VIDEO_DTV_TIMING_FORCE_VIDEO_FIELD BIT(5) ++ #define TX_VIDEO_DTV_TIMING_DISABLE_VIC39_CORRECTION BIT(4) ++ ++#define TX_VIDEO_DTV_MODE 0x003B ++ #define TX_VIDEO_DTV_MODE_FORCED_DEFAULT_PHASE BIT(7) ++ #define TX_VIDEO_DTV_MODE_COLOR_DEPTH GENMASK(1, 0) ++ ++#define TX_VIDEO_DTV_FORMAT0 0x003C ++#define TX_VIDEO_DTV_FORMAT1 0x003D ++#define TX_VIDEO_PIXEL_PACK 0x003F ++// video config, part 2 ++#define TX_VIDEO_CSC_COEFF_B0 0x0040 ++#define TX_VIDEO_CSC_COEFF_B1 0x0041 ++#define TX_VIDEO_CSC_COEFF_R0 0x0042 ++#define TX_VIDEO_CSC_COEFF_R1 0x0043 ++#define TX_VIDEO_CSC_COEFF_CB0 0x0044 ++#define TX_VIDEO_CSC_COEFF_CB1 0x0045 ++#define TX_VIDEO_CSC_COEFF_CR0 0x0046 ++#define TX_VIDEO_CSC_COEFF_CR1 0x0047 ++#define TX_VIDEO_DTV_OPTION_L 0x0048 ++ #define TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_FORMAT GENMASK(7, 6) ++ #define TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_FORMAT GENMASK(5, 4) ++ #define TX_VIDEO_DTV_OPTION_L_OUTPUT_COLOR_DEPTH GENMASK(3, 2) ++ #define TX_VIDEO_DTV_OPTION_L_INPUT_COLOR_DEPTH GENMASK(1, 0) ++ ++#define TX_VIDEO_DTV_OPTION_H 0x0049 ++ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_235 0x0 ++ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_16_240 0x1 ++ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_1_254 0x2 ++ #define TX_VIDEO_DTV_OPTION_H_COLOR_RANGE_0_255 0x3 ++ #define TX_VIDEO_DTV_OPTION_H_OUTPUT_COLOR_RANGE GENMASK(3, 2) ++ #define TX_VIDEO_DTV_OPTION_H_INPUT_COLOR_RANGE GENMASK(1, 0) ++ ++#define TX_VIDEO_DTV_FILTER 0x004A ++#define TX_VIDEO_DTV_DITHER 0x004B ++#define TX_VIDEO_DTV_DEDITHER 0x004C ++#define TX_VIDEO_PROC_CONFIG0 0x004E ++#define TX_VIDEO_PROC_CONFIG1 0x004F ++ ++// Audio config ++#define TX_AUDIO_FORMAT 0x0058 ++ #define TX_AUDIO_FORMAT_SPDIF_OR_I2S BIT(7) ++ #define TX_AUDIO_FORMAT_I2S_2_OR_8_CH BIT(6) ++ #define TX_AUDIO_FORMAT_I2S_FORMAT GENMASK(5, 4) ++ #define TX_AUDIO_FORMAT_BIT_WIDTH_MASK GENMASK(3, 2) ++ #define TX_AUDIO_FORMAT_BIT_WIDTH_16 0x1 ++ #define TX_AUDIO_FORMAT_BIT_WIDTH_20 0x2 ++ #define TX_AUDIO_FORMAT_BIT_WIDTH_24 0x3 ++ #define TX_AUDIO_FORMAT_WS_POLARITY BIT(1) ++ #define TX_AUDIO_FORMAT_I2S_ONE_BIT_OR_I2S BIT(0) ++ #define TX_AUDIO_FORMAT_SPDIF_CHANNEL_STATUS_FROM_DATA_OR_REG BIT(0) ++ ++#define TX_AUDIO_SPDIF 0x0059 ++ #define TX_AUDIO_SPDIF_ENABLE BIT(0) ++#define TX_AUDIO_I2S 0x005A ++ #define TX_AUDIO_I2S_ENABLE BIT(0) ++#define TX_AUDIO_FIFO 0x005B ++ #define TX_AUDIO_FIFO_FIFO_DEPTH_MASK GENMASK(7, 4) ++ #define TX_AUDIO_FIFO_FIFO_DEPTH_512 0x4 ++ #define TX_AUDIO_FIFO_CRITICAL_THRESHOLD_MASK GENMASK(3, 2) ++ #define TX_AUDIO_FIFO_CRITICAL_THRESHOLD_DEPTH_DIV16 0x2 ++ #define TX_AUDIO_FIFO_NORMAL_THRESHOLD_MASK GENMASK(1, 0) ++ #define TX_AUDIO_FIFO_NORMAL_THRESHOLD_DEPTH_DIV8 0x1 ++#define TX_AUDIO_LIPSYNC 0x005C ++ #define TX_AUDIO_LIPSYNC_NORMALIZED_LIPSYNC_PARAM GENMASK(7, 0) ++#define TX_AUDIO_CONTROL 0x005D ++ #define TX_AUDIO_CONTROL_FORCED_AUDIO_FIFO_CLEAR BIT(7) ++ #define TX_AUDIO_CONTROL_AUTO_AUDIO_FIFO_CLEAR BIT(6) ++ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_MASK GENMASK(5, 4) ++ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_AUDIO_SAMPLE_PACKET 0x0 ++ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_ONE_BIT_AUDIO 0x1 ++ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_HBR_AUDIO_PACKET 0x2 ++ #define TX_AUDIO_CONTROL_AUDIO_PACKET_TYPE_DST_AUDIO_PACKET 0x3 ++ #define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_VALID BIT(2) ++ #define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_USER BIT(1) ++ #define TX_AUDIO_CONTROL_AUDIO_SAMPLE_PACKET_FLAT BIT(0) ++#define TX_AUDIO_HEADER 0x005E ++ #define TX_AUDIO_HEADER_AUDIO_SAMPLE_PACKET_HEADER_LAYOUT1 BIT(7) ++ #define TX_AUDIO_HEADER_SET_NORMAL_DOUBLE_IN_DST_PACKET_HEADER BIT(6) ++#define TX_AUDIO_SAMPLE 0x005F ++ #define TX_AUDIO_SAMPLE_CHANNEL_VALID GENMASK(7, 0) ++#define TX_AUDIO_VALID 0x0060 ++#define TX_AUDIO_USER 0x0061 ++#define TX_AUDIO_PACK 0x0062 ++ #define TX_AUDIO_PACK_AUDIO_SAMPLE_PACKETS_ENABLE BIT(0) ++#define TX_AUDIO_CONTROL_MORE 0x0064 ++ #define TX_AUDIO_CONTROL_MORE_ENABLE BIT(0) ++ ++// tmds config ++#define TX_TMDS_MODE 0x0068 ++ #define TX_TMDS_MODE_FORCED_HDMI BIT(7) ++ #define TX_TMDS_MODE_HDMI_CONFIG BIT(6) ++ #define TX_TMDS_MODE_BIT_SWAP BIT(3) ++ #define TX_TMDS_MODE_CHANNEL_SWAP GENMASK(2, 0) ++ ++#define TX_TMDS_CONFIG0 0x006C ++#define TX_TMDS_CONFIG1 0x006D ++ ++// packet config ++#define TX_PACKET_ALLOC_ACTIVE_1 0x0078 ++#define TX_PACKET_ALLOC_ACTIVE_2 0x0079 ++#define TX_PACKET_ALLOC_EOF_1 0x007A ++#define TX_PACKET_ALLOC_EOF_2 0x007B ++#define TX_PACKET_ALLOC_SOF_1 0x007C ++#define TX_PACKET_ALLOC_SOF_2 0x007D ++#define TX_PACKET_CONTROL_1 0x007E ++ #define TX_PACKET_CONTROL_1_FORCE_PACKET_TIMING BIT(7) ++ #define TX_PACKET_CONTROL_1_PACKET_ALLOC_MODE BIT(6) ++ #define TX_PACKET_CONTROL_1_PACKET_START_LATENCY GENMASK(5, 0) ++ ++#define TX_PACKET_CONTROL_2 0x007F ++ #define TX_PACKET_CONTROL_2_AUDIO_REQUEST_DISABLE BIT(3) ++ #define TX_PACKET_CONTROL_2_HORIZONTAL_GC_PACKET_TRANSPORT_EN BIT(1) ++ ++#define TX_CORE_EDID_CONFIG_MORE 0x0080 ++ #define TX_CORE_EDID_CONFIG_MORE_KEEP_EDID_ERROR BIT(1) ++ #define TX_CORE_EDID_CONFIG_MORE_SYS_TRIGGER_CONFIG_SEMI_MANU BIT(0) ++ ++#define TX_CORE_ALLOC_VSYNC_0 0x0081 ++#define TX_CORE_ALLOC_VSYNC_1 0x0082 ++#define TX_CORE_ALLOC_VSYNC_2 0x0083 ++#define TX_MEM_PD_REG0 0x0084 ++ ++// core config ++#define TX_CORE_DATA_CAPTURE_1 0x00F0 ++#define TX_CORE_DATA_CAPTURE_2 0x00F1 ++ #define TX_CORE_DATA_CAPTURE_2_AUDIO_SOURCE_SELECT GENMASK(7, 6) ++ #define TX_CORE_DATA_CAPTURE_2_EXTERNAL_PACKET_ENABLE BIT(5) ++ #define TX_CORE_DATA_CAPTURE_2_INTERNAL_PACKET_ENABLE BIT(4) ++ #define TX_CORE_DATA_CAPTURE_2_AFE_FIFO_SRC_LANE1 GENMASK(3, 2) ++ #define TX_CORE_DATA_CAPTURE_2_AFE_FIFO_SRC_LANE0 GENMASK(1, 0) ++ ++#define TX_CORE_DATA_MONITOR_1 0x00F2 ++ #define TX_CORE_DATA_MONITOR_1_LANE1 BIT(7) ++ #define TX_CORE_DATA_MONITOR_1_SELECT_LANE1 GENMASK(6, 4) ++ #define TX_CORE_DATA_MONITOR_1_LANE0 BIT(3) ++ #define TX_CORE_DATA_MONITOR_1_SELECT_LANE0 GENMASK(2, 0) ++ ++#define TX_CORE_DATA_MONITOR_2 0x00F3 ++ #define TX_CORE_DATA_MONITOR_2_MONITOR_SELECT GENMASK(2, 0) ++ ++#define TX_CORE_CALIB_MODE 0x00F4 ++#define TX_CORE_CALIB_SAMPLE_DELAY 0x00F5 ++#define TX_CORE_CALIB_VALUE_AUTO 0x00F6 ++#define TX_CORE_CALIB_VALUE 0x00F7 ++ ++// system config 4 ++#define TX_SYS4_TX_CKI_DDR 0x00A0 ++#define TX_SYS4_TX_CKO_DDR 0x00A1 ++#define TX_SYS4_RX_CKI_DDR 0x00A2 ++#define TX_SYS4_RX_CKO_DDR 0x00A3 ++#define TX_SYS4_CONNECT_SEL_0 0x00A4 ++#define TX_SYS4_CONNECT_SEL_1 0x00A5 ++ #define TX_SYS4_CONNECT_SEL_1_TX_CONNECT_SEL_UPPER_CHANNEL_DATA BIT(6) ++ ++#define TX_SYS4_CONNECT_SEL_2 0x00A6 ++#define TX_SYS4_CONNECT_SEL_3 0x00A7 ++#define TX_SYS4_CK_INV_VIDEO 0x00A8 ++ #define TX_SYS4_CK_INV_VIDEO_TMDS_CLK_PATTERN BIT(4) ++#define TX_SYS4_CK_INV_AUDIO 0x00A9 ++#define TX_SYS4_CK_INV_AFE 0x00AA ++#define TX_SYS4_CK_INV_CH01 0x00AB ++#define TX_SYS4_CK_INV_CH2 0x00AC ++#define TX_SYS4_CK_CEC 0x00AD ++#define TX_SYS4_CK_SOURCE_1 0x00AE ++#define TX_SYS4_CK_SOURCE_2 0x00AF ++ ++#define TX_IEC60958_SUB1_OFFSET 0x00B0 ++#define TX_IEC60958_SUB2_OFFSET 0x00C8 ++ ++// system config 5 ++#define TX_SYS5_TX_SOFT_RESET_1 0x00E0 ++ #define TX_SYS5_TX_SOFT_RESET_1_TX_PIXEL_RSTN BIT(7) ++ #define TX_SYS5_TX_SOFT_RESET_1_TX_TMDS_RSTN BIT(6) ++ #define TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_MASTER_RSTN BIT(5) ++ #define TX_SYS5_TX_SOFT_RESET_1_TX_AUDIO_RESAMPLE_RSTN BIT(4) ++ #define TX_SYS5_TX_SOFT_RESET_1_TX_I2S_RESET_RSTN BIT(3) ++ #define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH2 BIT(2) ++ #define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH1 BIT(1) ++ #define TX_SYS5_TX_SOFT_RESET_1_TX_DIG_RESET_N_CH0 BIT(0) ++ ++#define TX_SYS5_TX_SOFT_RESET_2 0x00E1 ++ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH3_RST_IN BIT(7) ++ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH2_RST_IN BIT(6) ++ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH1_RST_IN BIT(5) ++ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_CH0_RST_IN BIT(4) ++ #define TX_SYS5_TX_SOFT_RESET_2_HDMI_SR_RST BIT(3) ++ #define TX_SYS5_TX_SOFT_RESET_2_TX_DDC_HDCP_RSTN BIT(2) ++ #define TX_SYS5_TX_SOFT_RESET_2_TX_DDC_EDID_RSTN BIT(1) ++ #define TX_SYS5_TX_SOFT_RESET_2_TX_DIG_RESET_N_CH3 BIT(0) ++ ++#define TX_SYS5_RX_SOFT_RESET_1 0x00E2 ++#define TX_SYS5_RX_SOFT_RESET_2 0x00E3 ++#define TX_SYS5_RX_SOFT_RESET_3 0x00E4 ++#define TX_SYS5_SSTL_BIDIR_IN 0x00E5 ++#define TX_SYS5_SSTL_IN 0x00E6 ++#define TX_SYS5_SSTL_DIFF_IN 0x00E7 ++#define TX_SYS5_FIFO_CONFIG 0x00E8 ++ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_BYPASS BIT(6) ++ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_BYPASS BIT(5) ++ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_BYPASS BIT(4) ++ #define TX_SYS5_FIFO_CONFIG_CLK_CHANNEL3_OUTPUT_ENABLE BIT(3) ++ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL2_ENABLE BIT(2) ++ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL1_ENABLE BIT(1) ++ #define TX_SYS5_FIFO_CONFIG_AFE_FIFO_CHANNEL0_ENABLE BIT(0) ++ ++#define TX_SYS5_FIFO_SAMP01_CFG 0x00E9 ++#define TX_SYS5_FIFO_SAMP23_CFG 0x00EA ++#define TX_SYS5_CONNECT_FIFO_CFG 0x00EB ++#define TX_SYS5_IO_CALIB_CONTROL 0x00EC ++#define TX_SYS5_SSTL_BIDIR_OUT 0x00ED ++#define TX_SYS5_SSTL_OUT 0x00EE ++#define TX_SYS5_SSTL_DIFF_OUT 0x00EF ++ ++// HDCP shadow register ++#define TX_HDCP_SHW_BKSV_0 0x0100 ++#define TX_HDCP_SHW_BKSV_1 0x0101 ++#define TX_HDCP_SHW_BKSV_2 0x0102 ++#define TX_HDCP_SHW_BKSV_3 0x0103 ++#define TX_HDCP_SHW_BKSV_4 0x0104 ++#define TX_HDCP_SHW_RI1_0 0x0108 ++#define TX_HDCP_SHW_RI1_1 0x0109 ++#define TX_HDCP_SHW_PJ1 0x010A ++#define TX_HDCP_SHW_AKSV_0 0x0110 ++#define TX_HDCP_SHW_AKSV_1 0x0111 ++#define TX_HDCP_SHW_AKSV_2 0x0112 ++#define TX_HDCP_SHW_AKSV_3 0x0113 ++#define TX_HDCP_SHW_AKSV_4 0x0114 ++#define TX_HDCP_SHW_AINFO 0x0115 ++#define TX_HDCP_SHW_AN_0 0x0118 ++#define TX_HDCP_SHW_AN_1 0x0119 ++#define TX_HDCP_SHW_AN_2 0x011A ++#define TX_HDCP_SHW_AN_3 0x011B ++#define TX_HDCP_SHW_AN_4 0x011C ++#define TX_HDCP_SHW_AN_5 0x011D ++#define TX_HDCP_SHW_AN_6 0x011E ++#define TX_HDCP_SHW_AN_7 0x011F ++#define TX_HDCP_SHW_V1_H0_0 0x0120 ++#define TX_HDCP_SHW_V1_H0_1 0x0121 ++#define TX_HDCP_SHW_V1_H0_2 0x0122 ++#define TX_HDCP_SHW_V1_H0_3 0x0123 ++#define TX_HDCP_SHW_V1_H1_0 0x0124 ++#define TX_HDCP_SHW_V1_H1_1 0x0125 ++#define TX_HDCP_SHW_V1_H1_2 0x0126 ++#define TX_HDCP_SHW_V1_H1_3 0x0127 ++#define TX_HDCP_SHW_V1_H2_0 0x0128 ++#define TX_HDCP_SHW_V1_H2_1 0x0129 ++#define TX_HDCP_SHW_V1_H2_2 0x012A ++#define TX_HDCP_SHW_V1_H2_3 0x012B ++#define TX_HDCP_SHW_V1_H3_0 0x012C ++#define TX_HDCP_SHW_V1_H3_1 0x012D ++#define TX_HDCP_SHW_V1_H3_2 0x012E ++#define TX_HDCP_SHW_V1_H3_3 0x012F ++#define TX_HDCP_SHW_V1_H4_0 0x0130 ++#define TX_HDCP_SHW_V1_H4_1 0x0131 ++#define TX_HDCP_SHW_V1_H4_2 0x0132 ++#define TX_HDCP_SHW_V1_H4_3 0x0133 ++#define TX_HDCP_SHW_BCAPS 0x0140 ++#define TX_HDCP_SHW_BSTATUS_0 0x0141 ++#define TX_HDCP_SHW_BSTATUS_1 0x0142 ++#define TX_HDCP_SHW_KSV_FIFO 0x0143 ++ ++// system status 0 ++#define TX_SYSST0_CONNECT_FIFO 0x0180 ++#define TX_SYSST0_PLL_MONITOR 0x0181 ++#define TX_SYSST0_AFE_FIFO 0x0182 ++#define TX_SYSST0_ROM_STATUS 0x018F ++ ++// hdcp status ++#define TX_HDCP_ST_AUTHENTICATION 0x0190 ++#define TX_HDCP_ST_FRAME_COUNT 0x0191 ++#define TX_HDCP_ST_STATUS_0 0x0192 ++#define TX_HDCP_ST_STATUS_1 0x0193 ++#define TX_HDCP_ST_STATUS_2 0x0194 ++#define TX_HDCP_ST_STATUS_3 0x0195 ++#define TX_HDCP_ST_EDID_STATUS 0x0196 ++ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS GENMASK(7, 6) ++ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_NO_SINK_ATTACHED 0x0 ++ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_READING_EDID 0x1 ++ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_DVI_MODE 0x2 ++ #define TX_HDCP_ST_EDID_STATUS_SYSTEM_STATUS_HDMI_MODE 0x3 ++ #define TX_HDCP_ST_EDID_STATUS_EDID_DATA_READY BIT(4) ++ #define TX_HDCP_ST_EDID_STATUS_HPD_STATUS BIT(1) ++ ++#define TX_HDCP_ST_MEM_STATUS 0x0197 ++#define TX_HDCP_ST_ST_MODE 0x019F ++ ++// video status ++#define TX_VIDEO_ST_ACTIVE_PIXELS_1 0x01A0 ++#define TX_VIDEO_ST_ACTIVE_PIXELS_2 0x01A1 ++#define TX_VIDEO_ST_FRONT_PIXELS 0x01A2 ++#define TX_VIDEO_ST_HSYNC_PIXELS 0x01A3 ++#define TX_VIDEO_ST_BACK_PIXELS 0x01A4 ++#define TX_VIDEO_ST_ACTIVE_LINES_1 0x01A5 ++#define TX_VIDEO_ST_ACTIVE_LINES_2 0x01A6 ++#define TX_VIDEO_ST_EOF_LINES 0x01A7 ++#define TX_VIDEO_ST_VSYNC_LINES 0x01A8 ++#define TX_VIDEO_ST_SOF_LINES 0x01A9 ++#define TX_VIDEO_ST_DTV_TIMING 0x01AA ++#define TX_VIDEO_ST_DTV_MODE 0x01AB ++// audio status ++#define TX_VIDEO_ST_AUDIO_STATUS 0x01AC ++#define TX_AFE_STATUS_0 0x01AE ++#define TX_AFE_STATUS_1 0x01AF ++ ++#define TX_IEC60958_ST_SUB1_OFFSET 0x01B0 ++#define TX_IEC60958_ST_SUB2_OFFSET 0x01C8 ++ ++// system status 1 ++#define TX_SYSST1_CALIB_BIT_RESULT_0 0x01E0 ++#define TX_SYSST1_CALIB_BIT_RESULT_1 0x01E1 ++//HDMI_STATUS_OUT[7:0] ++#define TX_HDMI_PHY_READBACK_0 0x01E2 ++//HDMI_COMP_OUT[4] ++//HDMI_STATUS_OUT[11:8] ++#define TX_HDMI_PHY_READBACK_1 0x01E3 ++#define TX_SYSST1_CALIB_BIT_RESULT_4 0x01E4 ++#define TX_SYSST1_CALIB_BIT_RESULT_5 0x01E5 ++#define TX_SYSST1_CALIB_BIT_RESULT_6 0x01E6 ++#define TX_SYSST1_CALIB_BIT_RESULT_7 0x01E7 ++#define TX_SYSST1_CALIB_BUS_RESULT_0 0x01E8 ++#define TX_SYSST1_CALIB_BUS_RESULT_1 0x01E9 ++#define TX_SYSST1_CALIB_BUS_RESULT_2 0x01EA ++#define TX_SYSST1_CALIB_BUS_RESULT_3 0x01EB ++#define TX_SYSST1_CALIB_BUS_RESULT_4 0x01EC ++#define TX_SYSST1_CALIB_BUS_RESULT_5 0x01ED ++#define TX_SYSST1_CALIB_BUS_RESULT_6 0x01EE ++#define TX_SYSST1_CALIB_BUS_RESULT_7 0x01EF ++ ++// Packet status ++#define TX_PACKET_ST_REQUEST_STATUS_1 0x01F0 ++#define TX_PACKET_ST_REQUEST_STATUS_2 0x01F1 ++#define TX_PACKET_ST_REQUEST_MISSED_1 0x01F2 ++#define TX_PACKET_ST_REQUEST_MISSED_2 0x01F3 ++#define TX_PACKET_ST_ENCODE_STATUS_0 0x01F4 ++#define TX_PACKET_ST_ENCODE_STATUS_1 0x01F5 ++#define TX_PACKET_ST_ENCODE_STATUS_2 0x01F6 ++#define TX_PACKET_ST_TIMER_STATUS 0x01F7 ++ ++// tmds status ++#define TX_TMDS_ST_CLOCK_METER_1 0x01F8 ++#define TX_TMDS_ST_CLOCK_METER_2 0x01F9 ++#define TX_TMDS_ST_CLOCK_METER_3 0x01FA ++#define TX_TMDS_ST_TMDS_STATUS_1 0x01FC ++#define TX_TMDS_ST_TMDS_STATUS_2 0x01FD ++#define TX_TMDS_ST_TMDS_STATUS_3 0x01FE ++#define TX_TMDS_ST_TMDS_STATUS_4 0x01FF ++ ++// Packet register ++#define TX_PKT_REG_SPD_INFO_BASE_ADDR 0x0200 ++#define TX_PKT_REG_VEND_INFO_BASE_ADDR 0x0220 ++#define TX_PKT_REG_MPEG_INFO_BASE_ADDR 0x0240 ++#define TX_PKT_REG_AVI_INFO_BASE_ADDR 0x0260 ++#define TX_PKT_REG_AUDIO_INFO_BASE_ADDR 0x0280 ++#define TX_PKT_REG_ACP_INFO_BASE_ADDR 0x02A0 ++#define TX_PKT_REG_ISRC1_BASE_ADDR 0x02C0 ++#define TX_PKT_REG_ISRC2_BASE_ADDR 0x02E0 ++#define TX_PKT_REG_EXCEPT0_BASE_ADDR 0x0300 ++#define TX_PKT_REG_EXCEPT1_BASE_ADDR 0x0320 ++#define TX_PKT_REG_EXCEPT2_BASE_ADDR 0x0340 ++#define TX_PKT_REG_EXCEPT3_BASE_ADDR 0x0360 ++#define TX_PKT_REG_EXCEPT4_BASE_ADDR 0x0380 ++#define TX_PKT_REG_GAMUT_P0_BASE_ADDR 0x03A0 ++#define TX_PKT_REG_GAMUT_P1_1_BASE_ADDR 0x03C0 ++#define TX_PKT_REG_GAMUT_P1_2_BASE_ADDR 0x03E0 ++ ++#define TX_RX_EDID_OFFSET 0x0600 ++ ++/* HDMI OTHER registers */ ++ ++#define HDMI_OTHER_CTRL0 0x8000 ++#define HDMI_OTHER_CTRL1 0x8001 ++ #define HDMI_OTHER_CTRL1_POWER_ON BIT(15) ++ #define HDMI_OTHER_CTRL1_HDMI_AUDIO_CLOCK_ON BIT(13) ++ ++#define HDMI_OTHER_STATUS0 0x8002 ++#define HDMI_OTHER_CTRL2 0x8003 ++#define HDMI_OTHER_INTR_MASKN 0x8004 ++ #define HDMI_OTHER_INTR_MASKN_TX_EDID_INT_RISE BIT(2) ++ #define HDMI_OTHER_INTR_MASKN_TX_HPD_INT_FALL BIT(1) ++ #define HDMI_OTHER_INTR_MASKN_TX_HPD_INT_RISE BIT(0) ++ ++#define HDMI_OTHER_INTR_STAT 0x8005 ++ #define HDMI_OTHER_INTR_STAT_EDID_RISING BIT(2) ++ #define HDMI_OTHER_INTR_STAT_HPD_FALLING BIT(1) ++ #define HDMI_OTHER_INTR_STAT_HPD_RISING BIT(0) ++ ++#define HDMI_OTHER_INTR_STAT_CLR 0x8006 ++ #define HDMI_OTHER_INTR_STAT_CLR_EDID_RISING BIT(2) ++ #define HDMI_OTHER_INTR_STAT_CLR_HPD_FALLING BIT(1) ++ #define HDMI_OTHER_INTR_STAT_CLR_HPD_RISING BIT(0) ++ ++#define HDMI_OTHER_AVI_INTR_MASKN0 0x8008 ++#define HDMI_OTHER_AVI_INTR_MASKN1 0x8009 ++#define HDMI_OTHER_RX_AINFO_INTR_MASKN0 0x800a ++#define HDMI_OTHER_RX_AINFO_INTR_MASKN1 0x800b ++#define HDMI_OTHER_RX_PACKET_INTR_CLR 0x800c ++ ++#endif /* __MESON_TRANSWITCH_HDMI_H__ */ +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0057-drm-meson-Meson8-Meson8b-Meson8m2-VCLK-HACK.patch b/patch/kernel/archive/meson-6.9/0057-drm-meson-Meson8-Meson8b-Meson8m2-VCLK-HACK.patch new file mode 100644 index 000000000000..3203049fb263 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0057-drm-meson-Meson8-Meson8b-Meson8m2-VCLK-HACK.patch @@ -0,0 +1,485 @@ +From f105e98570211cb16a2ffdca32ac2869c92f9353 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 25 Apr 2020 22:13:51 +0200 +Subject: [PATCH 57/96] drm/meson: Meson8/Meson8b/Meson8m2 VCLK - HACK + +WiP + +Signed-off-by: Martin Blumenstingl +--- + drivers/gpu/drm/meson/meson_drv.c | 101 ++++++++++++++++++-- + drivers/gpu/drm/meson/meson_drv.h | 32 +++++++ + drivers/gpu/drm/meson/meson_vclk.c | 146 +++++++++++++++++++++++++++++ + drivers/gpu/drm/meson/meson_venc.c | 24 ++++- + 4 files changed, 293 insertions(+), 10 deletions(-) + +diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c +index 104b53861..2fb074e53 100644 +--- a/drivers/gpu/drm/meson/meson_drv.c ++++ b/drivers/gpu/drm/meson/meson_drv.c +@@ -170,6 +170,35 @@ static void meson_vpu_init(struct meson_drm *priv) + } + } + ++static int meson_video_clock_init(struct meson_drm *priv) ++{ ++ int ret; ++ ++ ret = clk_bulk_prepare(VPU_VID_CLK_NUM, priv->vid_clks); ++ if (ret) ++ return dev_err_probe(priv->dev, ret, ++ "Failed to prepare the video clocks\n"); ++ ++ ret = clk_bulk_prepare(priv->num_intr_clks, priv->intr_clks); ++ if (ret) ++ return dev_err_probe(priv->dev, ret, ++ "Failed to prepare the interrupt clocks\n"); ++ ++ return 0; ++} ++ ++static void meson_video_clock_exit(struct meson_drm *priv) ++{ ++ if (priv->clk_dac_enabled) ++ clk_disable(priv->clk_dac); ++ ++ if (priv->clk_venc_enabled) ++ clk_disable(priv->clk_venc); ++ ++ clk_bulk_unprepare(priv->num_intr_clks, priv->intr_clks); ++ clk_bulk_unprepare(VPU_VID_CLK_NUM, priv->vid_clks); ++} ++ + static void meson_fbdev_setup(struct meson_drm *priv) + { + unsigned int preferred_bpp; +@@ -263,10 +292,59 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) + priv->compat = match->compat; + priv->afbcd.ops = match->afbcd_ops; + ++ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { ++ priv->vid_pll_resets[VPU_RESET_VID_PLL_PRE].id = "vid_pll_pre"; ++ priv->vid_pll_resets[VPU_RESET_VID_PLL_POST].id = "vid_pll_post"; ++ priv->vid_pll_resets[VPU_RESET_VID_PLL_SOFT_PRE].id = "vid_pll_soft_pre"; ++ priv->vid_pll_resets[VPU_RESET_VID_PLL_SOFT_POST].id = "vid_pll_soft_post"; ++ ++ ret = devm_reset_control_bulk_get_exclusive(dev, ++ VPU_RESET_VID_PLL_NUM, ++ priv->vid_pll_resets); ++ if (ret) ++ goto free_drm; ++ ++ priv->intr_clks[0].id = "vpu_intr"; ++ priv->intr_clks[1].id = "hdmi_intr_sync"; ++ priv->intr_clks[2].id = "venci_int"; ++ priv->num_intr_clks = 3; ++ ++ ret = devm_clk_bulk_get(dev, priv->num_intr_clks, ++ priv->intr_clks); ++ if (ret) ++ goto free_drm; ++ ++ priv->vid_clks[VPU_VID_CLK_TMDS].id = "tmds"; ++ priv->vid_clks[VPU_VID_CLK_HDMI_TX_PIXEL].id = "hdmi_tx_pixel"; ++ priv->vid_clks[VPU_VID_CLK_CTS_ENCP].id = "cts_encp"; ++ priv->vid_clks[VPU_VID_CLK_CTS_ENCI].id = "cts_enci"; ++ priv->vid_clks[VPU_VID_CLK_CTS_ENCT].id = "cts_enct"; ++ priv->vid_clks[VPU_VID_CLK_CTS_ENCL].id = "cts_encl"; ++ priv->vid_clks[VPU_VID_CLK_CTS_VDAC0].id = "cts_vdac0"; ++ ++ ret = devm_clk_bulk_get(dev, VPU_VID_CLK_NUM, priv->vid_clks); ++ if (ret) ++ goto free_drm; ++ } else { ++ priv->intr_clks[0].id = "vpu_intr"; ++ priv->num_intr_clks = 1; ++ ++ ret = devm_clk_bulk_get_optional(dev, priv->num_intr_clks, ++ priv->intr_clks); ++ if (ret) ++ goto free_drm; ++ } ++ ++ ret = meson_video_clock_init(priv); ++ if (ret) ++ goto free_drm; ++ + regs = devm_platform_ioremap_resource_byname(pdev, "vpu"); + if (IS_ERR(regs)) { + ret = PTR_ERR(regs); +- goto free_drm; ++ goto video_clock_exit; + } + + priv->io_base = regs; +@@ -281,7 +359,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) + regs = devm_ioremap(dev, res->start, resource_size(res)); + if (!regs) { + ret = -EADDRNOTAVAIL; +- goto free_drm; ++ goto video_clock_exit; + } + + priv->hhi = devm_regmap_init_mmio(dev, regs, +@@ -290,36 +368,36 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) + dev_err(&pdev->dev, + "Couldn't create the HHI regmap\n"); + ret = PTR_ERR(priv->hhi); +- goto free_drm; ++ goto video_clock_exit; + } + } + + priv->canvas = meson_canvas_get(dev); + if (IS_ERR(priv->canvas)) { + ret = PTR_ERR(priv->canvas); +- goto free_drm; ++ goto video_clock_exit; + } + + ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1); + if (ret) +- goto free_drm; ++ goto video_clock_exit; + ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0); + if (ret) { + meson_canvas_free(priv->canvas, priv->canvas_id_osd1); +- goto free_drm; ++ goto video_clock_exit; + } + ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1); + if (ret) { + meson_canvas_free(priv->canvas, priv->canvas_id_osd1); + meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0); +- goto free_drm; ++ goto video_clock_exit; + } + ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2); + if (ret) { + meson_canvas_free(priv->canvas, priv->canvas_id_osd1); + meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0); + meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1); +- goto free_drm; ++ goto video_clock_exit; + } + + priv->vsync_irq = platform_get_irq(pdev, 0); +@@ -425,6 +503,8 @@ static int meson_drv_bind_master(struct device *dev, bool has_components) + exit_afbcd: + if (priv->afbcd.ops) + priv->afbcd.ops->exit(priv); ++video_clock_exit: ++ meson_video_clock_exit(priv); + free_drm: + drm_dev_put(drm); + +@@ -469,6 +549,8 @@ static void meson_drv_unbind(struct device *dev) + + if (priv->afbcd.ops) + priv->afbcd.ops->exit(priv); ++ ++ meson_video_clock_exit(priv); + } + + static const struct component_master_ops meson_drv_master_ops = { +@@ -483,6 +565,8 @@ static int __maybe_unused meson_drv_pm_suspend(struct device *dev) + if (!priv) + return 0; + ++ // TODO: video clock suspend ++ + return drm_mode_config_helper_suspend(priv->drm); + } + +@@ -493,6 +577,7 @@ static int __maybe_unused meson_drv_pm_resume(struct device *dev) + if (!priv) + return 0; + ++ meson_video_clock_init(priv); + meson_vpu_init(priv); + meson_venc_init(priv); + meson_vpp_init(priv); +diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h +index 8e1c01242..59f80fcc6 100644 +--- a/drivers/gpu/drm/meson/meson_drv.h ++++ b/drivers/gpu/drm/meson/meson_drv.h +@@ -7,9 +7,11 @@ + #ifndef __MESON_DRV_H + #define __MESON_DRV_H + ++#include + #include + #include + #include ++#include + + struct drm_crtc; + struct drm_device; +@@ -45,6 +47,25 @@ struct meson_drm_soc_limits { + unsigned int max_hdmi_phy_freq; + }; + ++enum vpu_bulk_clk_id { ++ VPU_VID_CLK_TMDS = 0, ++ VPU_VID_CLK_HDMI_TX_PIXEL, ++ VPU_VID_CLK_CTS_ENCP, ++ VPU_VID_CLK_CTS_ENCI, ++ VPU_VID_CLK_CTS_ENCT, ++ VPU_VID_CLK_CTS_ENCL, ++ VPU_VID_CLK_CTS_VDAC0, ++ VPU_VID_CLK_NUM ++}; ++ ++enum vpu_bulk_vid_pll_reset_id { ++ VPU_RESET_VID_PLL_PRE = 0, ++ VPU_RESET_VID_PLL_POST, ++ VPU_RESET_VID_PLL_SOFT_PRE, ++ VPU_RESET_VID_PLL_SOFT_POST, ++ VPU_RESET_VID_PLL_NUM ++}; ++ + struct meson_drm { + struct device *dev; + enum vpu_compatible compat; +@@ -70,6 +91,17 @@ struct meson_drm { + bool cvbs_dac_enabled; + struct platform_device *cvbs_dac_pdev; + ++ struct clk_bulk_data intr_clks[3]; ++ unsigned int num_intr_clks; ++ bool intr_clks_enabled; ++ struct clk_bulk_data vid_clks[VPU_VID_CLK_NUM]; ++ bool vid_clk_rate_exclusive[VPU_VID_CLK_NUM]; ++ struct clk *clk_venc; ++ bool clk_venc_enabled; ++ struct clk *clk_dac; ++ bool clk_dac_enabled; ++ struct reset_control_bulk_data vid_pll_resets[VPU_RESET_VID_PLL_NUM]; ++ + /* Components Data */ + struct { + bool osd1_enabled; +diff --git a/drivers/gpu/drm/meson/meson_vclk.c b/drivers/gpu/drm/meson/meson_vclk.c +index 2a82119eb..a2c1bf1ae 100644 +--- a/drivers/gpu/drm/meson/meson_vclk.c ++++ b/drivers/gpu/drm/meson/meson_vclk.c +@@ -732,6 +732,11 @@ meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq) + return MODE_CLOCK_HIGH; + } + ++ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) ++ return MODE_OK; ++ + if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od)) + return MODE_OK; + +@@ -784,6 +789,11 @@ meson_vclk_vic_supported_freq(struct meson_drm *priv, unsigned int phy_freq, + return MODE_CLOCK_HIGH; + } + ++ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) ++ return MODE_OK; ++ + for (i = 0 ; params[i].pixel_freq ; ++i) { + DRM_DEBUG_DRIVER("i = %d pixel_freq = %d alt = %d\n", + i, params[i].pixel_freq, +@@ -1024,6 +1034,128 @@ static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq, + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN); + } + ++static int meson_vclk_set_rate_exclusive(struct meson_drm *priv, ++ enum vpu_bulk_clk_id clk_id, ++ unsigned int rate_khz) ++{ ++ struct clk *clk = priv->vid_clks[clk_id].clk; ++ int ret; ++ ++ ret = clk_set_rate_exclusive(clk, rate_khz * 1000UL); ++ if (ret) ++ return ret; ++ ++ priv->vid_clk_rate_exclusive[clk_id] = true; ++ ++ return 0; ++} ++ ++static void meson_vclk_disable_ccf(struct meson_drm *priv) ++{ ++ unsigned int i; ++ ++ /* allow all clocks to be changed in _enable again */ ++ for (i = 0; i < VPU_VID_CLK_NUM; i++) { ++ if (!priv->vid_clk_rate_exclusive[i]) ++ continue; ++ ++ clk_rate_exclusive_put(priv->vid_clks[i].clk); ++ priv->vid_clk_rate_exclusive[i] = false; ++ } ++ ++ if (priv->clk_dac_enabled) { ++ clk_disable(priv->clk_dac); ++ priv->clk_dac_enabled = false; ++ } ++ ++ if (priv->clk_venc_enabled) { ++ clk_disable(priv->clk_venc); ++ priv->clk_venc_enabled = false; ++ } ++} ++ ++static int meson_vclk_enable_ccf(struct meson_drm *priv, unsigned int target, ++ bool hdmi_use_enci, unsigned int phy_freq, ++ unsigned int dac_freq, unsigned int venc_freq) ++{ ++ enum vpu_bulk_clk_id venc_clk_id, dac_clk_id; ++ int ret; ++ ++ if (target == MESON_VCLK_TARGET_CVBS || hdmi_use_enci) ++ venc_clk_id = VPU_VID_CLK_CTS_ENCI; ++ else ++ venc_clk_id = VPU_VID_CLK_CTS_ENCP; ++ ++ if (target == MESON_VCLK_TARGET_CVBS) ++ dac_clk_id = VPU_VID_CLK_CTS_VDAC0; ++ else ++ dac_clk_id = VPU_VID_CLK_HDMI_TX_PIXEL; ++ ++ /* ++ * The TMDS clock also updates the PLL. Protect the PLL rate so all ++ * following clocks are derived from the PLL setting which matches the ++ * TMDS clock. ++ */ ++ ret = meson_vclk_set_rate_exclusive(priv, VPU_VID_CLK_TMDS, phy_freq); ++ if (ret) { ++ dev_err(priv->dev, "Failed to set TMDS clock to %ukHz: %d\n", ++ phy_freq, ret); ++ goto out_enable_clocks; ++ } ++ ++ /* ++ * The DAC clock may be derived from a parent of the VENC clock so we ++ * must protect the VENC clock from changing it's rate. This works ++ * because the DAC freq can be divided by the VENC clock. ++ */ ++ ret = meson_vclk_set_rate_exclusive(priv, venc_clk_id, venc_freq); ++ if (ret) { ++ dev_warn(priv->dev, ++ "Failed to set VENC clock to %ukHz while TMDS clock is %ukHz: %d\n", ++ venc_freq, phy_freq, ret); ++ goto out_enable_clocks; ++ } ++ ++ priv->clk_venc = priv->vid_clks[venc_clk_id].clk; ++ ++ /* ++ * after changing any of the VID_PLL_* clocks (which can happen when ++ * update the VENC clock rate) we need to assert and then de-assert the ++ * VID_DIVIDER_CNTL_* reset lines. ++ */ ++ reset_control_bulk_assert(VPU_RESET_VID_PLL_NUM, priv->vid_pll_resets); ++ reset_control_bulk_deassert(VPU_RESET_VID_PLL_NUM, priv->vid_pll_resets); ++ ++ ret = meson_vclk_set_rate_exclusive(priv, dac_clk_id, dac_freq); ++ if (ret) { ++ dev_warn(priv->dev, ++ "Failed to set pixel clock to %ukHz while TMDS clock is %ukHz: %d\n", ++ dac_freq, phy_freq, ret); ++ goto out_enable_clocks; ++ } ++ ++ priv->clk_dac = priv->vid_clks[dac_clk_id].clk; ++ ++out_enable_clocks: ++ ret = clk_enable(priv->clk_venc); ++ if (ret) ++ dev_err(priv->dev, ++ "Failed to re-enable the VENC clock at %ukHz: %d\n", ++ venc_freq, ret); ++ else ++ priv->clk_venc_enabled = true; ++ ++ ret = clk_enable(priv->clk_dac); ++ if (ret) ++ dev_err(priv->dev, ++ "Failed to re-enable the pixel clock at %ukHz: %d\n", ++ dac_freq, ret); ++ else ++ priv->clk_dac_enabled = true; ++ ++ return ret; ++} ++ + void meson_vclk_setup(struct meson_drm *priv, unsigned int target, + unsigned int phy_freq, unsigned int vclk_freq, + unsigned int venc_freq, unsigned int dac_freq, +@@ -1034,6 +1166,20 @@ void meson_vclk_setup(struct meson_drm *priv, unsigned int target, + unsigned int hdmi_tx_div; + unsigned int venc_div; + ++ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8B) || ++ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_M8M2)) { ++ /* CVBS video clocks are generated off a 1296MHz base clock */ ++ if (target == MESON_VCLK_TARGET_CVBS) ++ phy_freq = 1296000; ++ ++ dev_err(priv->dev, "%s(target: %u, phy: %u, dac: %u, venc: %u, hdmi_use_enci: %u)\n", __func__, target, phy_freq, dac_freq, venc_freq, hdmi_use_enci); ++ meson_vclk_disable_ccf(priv); ++ meson_vclk_enable_ccf(priv, target, hdmi_use_enci, phy_freq, ++ dac_freq, venc_freq); ++ return; ++ } ++ + if (target == MESON_VCLK_TARGET_CVBS) { + meson_venci_cvbs_clock_config(priv); + return; +diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c +index 805751b9e..d834359c1 100644 +--- a/drivers/gpu/drm/meson/meson_venc.c ++++ b/drivers/gpu/drm/meson/meson_venc.c +@@ -1954,14 +1954,34 @@ void meson_venc_enable_vsync(struct meson_drm *priv) + priv->io_base + _REG(VENC_INTCTRL)); + } + +- if (priv->hhi) ++ if (priv->intr_clks[0].clk) { ++ if (!priv->intr_clks_enabled) { ++ int ret; ++ ++ ret = clk_bulk_enable(priv->num_intr_clks, ++ priv->intr_clks); ++ if (ret) ++ dev_err(priv->dev, ++ "Failed to enable the interrupt clocks\n"); ++ else ++ priv->intr_clks_enabled = true; ++ } ++ } else { + regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25)); ++ } + } + + void meson_venc_disable_vsync(struct meson_drm *priv) + { +- if (priv->hhi) ++ if (priv->intr_clks[0].clk) { ++ if (priv->intr_clks_enabled) { ++ clk_bulk_disable(priv->num_intr_clks, ++ priv->intr_clks); ++ priv->intr_clks_enabled = false; ++ } ++ } else { + regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), 0); ++ } + + writel_relaxed(0, priv->io_base + _REG(VENC_INTCTRL)); + } +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0058-drm-meson-Enable-support-for-Meson8-Meson8b-Meson8m2.patch b/patch/kernel/archive/meson-6.9/0058-drm-meson-Enable-support-for-Meson8-Meson8b-Meson8m2.patch new file mode 100644 index 000000000000..19a184237144 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0058-drm-meson-Enable-support-for-Meson8-Meson8b-Meson8m2.patch @@ -0,0 +1,52 @@ +From 8717397eb0cad729cc6244019665476aec47dbaf Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 25 Apr 2020 22:14:27 +0200 +Subject: [PATCH 58/96] drm/meson: Enable support for Meson8/Meson8b/Meson8m2 + +Add a compatible string for each of the three SoCs now that all hardware +specific quirks are added to the driver. + +Signed-off-by: Martin Blumenstingl +--- + drivers/gpu/drm/meson/meson_drv.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c +index 2fb074e53..3a853fa25 100644 +--- a/drivers/gpu/drm/meson/meson_drv.c ++++ b/drivers/gpu/drm/meson/meson_drv.c +@@ -660,6 +660,18 @@ static void meson_drv_remove(struct platform_device *pdev) + component_master_del(&pdev->dev, &meson_drv_master_ops); + } + ++static struct meson_drm_match_data meson_drm_m8_data = { ++ .compat = VPU_COMPATIBLE_M8, ++}; ++ ++static struct meson_drm_match_data meson_drm_m8b_data = { ++ .compat = VPU_COMPATIBLE_M8B, ++}; ++ ++static struct meson_drm_match_data meson_drm_m8m2_data = { ++ .compat = VPU_COMPATIBLE_M8M2, ++}; ++ + static struct meson_drm_match_data meson_drm_gxbb_data = { + .compat = VPU_COMPATIBLE_GXBB, + }; +@@ -679,6 +691,12 @@ static struct meson_drm_match_data meson_drm_g12a_data = { + }; + + static const struct of_device_id dt_match[] = { ++ { .compatible = "amlogic,meson8-vpu", ++ .data = (void *)&meson_drm_m8_data }, ++ { .compatible = "amlogic,meson8b-vpu", ++ .data = (void *)&meson_drm_m8b_data }, ++ { .compatible = "amlogic,meson8m2-vpu", ++ .data = (void *)&meson_drm_m8m2_data }, + { .compatible = "amlogic,meson-gxbb-vpu", + .data = (void *)&meson_drm_gxbb_data }, + { .compatible = "amlogic,meson-gxl-vpu", +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0059-ARM-dts-meson-add-the-VPU-WiP.patch b/patch/kernel/archive/meson-6.9/0059-ARM-dts-meson-add-the-VPU-WiP.patch new file mode 100644 index 000000000000..03c350ce62d2 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0059-ARM-dts-meson-add-the-VPU-WiP.patch @@ -0,0 +1,272 @@ +From 997c2fe858ecc56b1d0d2ccd56cce6c571b87d17 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sat, 8 Dec 2018 13:50:48 +0100 +Subject: [PATCH 59/96] ARM: dts: meson: add the VPU - WiP + +WiP + +Signed-off-by: Martin Blumenstingl +--- + arch/arm/boot/dts/amlogic/meson.dtsi | 10 +++ + arch/arm/boot/dts/amlogic/meson8.dtsi | 80 ++++++++++++++++++++++++ + arch/arm/boot/dts/amlogic/meson8b.dtsi | 81 +++++++++++++++++++++++++ + arch/arm/boot/dts/amlogic/meson8m2.dtsi | 4 ++ + 4 files changed, 175 insertions(+) + +diff --git a/arch/arm/boot/dts/amlogic/meson.dtsi b/arch/arm/boot/dts/amlogic/meson.dtsi +index d7f50fec8..d729a06da 100644 +--- a/arch/arm/boot/dts/amlogic/meson.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson.dtsi +@@ -38,6 +38,16 @@ hhi: system-controller@4000 { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x4000 0x400>; ++ ++ ++ cvbs_dac: video-dac@2f4 { ++ compatible = "amlogic,meson-cvbs-dac"; ++ reg = <0x2f4 0x8>; ++ ++ #phy-cells = <0>; ++ ++ status = "disabled"; ++ }; + }; + + aiu: audio-controller@5400 { +diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi +index 454c35530..519443e19 100644 +--- a/arch/arm/boot/dts/amlogic/meson8.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson8.dtsi +@@ -314,6 +314,71 @@ mali: gpu@c0000 { + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; ++ ++ vpu: vpu@100000 { ++ compatible = "amlogic,meson8-vpu"; ++ ++ reg = <0x100000 0x10000>; ++ reg-names = "vpu"; ++ ++ interrupts = ; ++ ++ amlogic,canvas = <&canvas>; ++ ++ /* ++ * The VCLK{,2}_IN path always needs to derived from ++ * the CLKID_VID_PLL_FINAL_DIV so other clocks like ++ * MPLL1 are not used (MPLL1 is reserved for audio ++ * purposes). ++ */ ++ assigned-clocks = <&clkc CLKID_VCLK_IN_SEL>, ++ <&clkc CLKID_VCLK2_IN_SEL>; ++ assigned-clock-parents = <&clkc CLKID_VID_PLL_FINAL_DIV>, ++ <&clkc CLKID_VID_PLL_FINAL_DIV>; ++ ++ clocks = <&clkc CLKID_VPU_INTR>, ++ <&clkc CLKID_HDMI_INTR_SYNC>, ++ <&clkc CLKID_GCLK_VENCI_INT>, ++ <&clkc CLKID_HDMI_PLL_HDMI_OUT>, ++ <&clkc CLKID_HDMI_TX_PIXEL>, ++ <&clkc CLKID_CTS_ENCP>, ++ <&clkc CLKID_CTS_ENCI>, ++ <&clkc CLKID_CTS_ENCT>, ++ <&clkc CLKID_CTS_ENCL>, ++ <&clkc CLKID_CTS_VDAC0>; ++ clock-names = "vpu_intr", ++ "hdmi_intr_sync", ++ "venci_int", ++ "tmds", ++ "hdmi_tx_pixel", ++ "cts_encp", ++ "cts_enci", ++ "cts_enct", ++ "cts_encl", ++ "cts_vdac0"; ++ ++ resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>, ++ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>, ++ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>, ++ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>; ++ reset-names = "vid_pll_pre", ++ "vid_pll_post", ++ "vid_pll_soft_pre", ++ "vid_pll_soft_post"; ++ ++ phys = <&cvbs_dac>; ++ phy-names = "cvbs-dac"; ++ ++ power-domains = <&pwrc PWRC_MESON8_VPU_ID>; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* CVBS VDAC output port */ ++ cvbs_vdac_port: port@0 { ++ reg = <0>; ++ }; ++ }; + }; + }; /* end of / */ + +@@ -617,6 +682,17 @@ smp-sram@1ff80 { + }; + }; + ++&cvbs_dac { ++ compatible = "amlogic,meson8-cvbs-dac", "amlogic,meson-cvbs-dac"; ++ ++ clocks = <&clkc CLKID_CTS_VDAC0>; ++ ++ nvmem-cells = <&cvbs_trimming>; ++ nvmem-cell-names = "cvbs_trimming"; ++ ++ status = "okay"; ++}; ++ + &efuse { + compatible = "amlogic,meson8-efuse"; + clocks = <&clkc CLKID_EFUSE>; +@@ -626,6 +702,10 @@ temperature_calib: calib@1f4 { + /* only the upper two bytes are relevant */ + reg = <0x1f4 0x4>; + }; ++ ++ cvbs_trimming: calib@1f8 { ++ reg = <0x1f8 0x2>; ++ }; + }; + + ðmac { +diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi +index 5ffedca99..87aa74675 100644 +--- a/arch/arm/boot/dts/amlogic/meson8b.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi +@@ -276,6 +276,71 @@ mali: gpu@c0000 { + operating-points-v2 = <&gpu_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; ++ ++ vpu: vpu@100000 { ++ compatible = "amlogic,meson8b-vpu"; ++ ++ reg = <0x100000 0x10000>; ++ reg-names = "vpu"; ++ ++ interrupts = ; ++ ++ amlogic,canvas = <&canvas>; ++ ++ /* ++ * The VCLK{,2}_IN path always needs to derived from ++ * the CLKID_VID_PLL_FINAL_DIV so other clocks like ++ * MPLL1 are not used (MPLL1 is reserved for audio ++ * purposes). ++ */ ++ assigned-clocks = <&clkc CLKID_VCLK_IN_SEL>, ++ <&clkc CLKID_VCLK2_IN_SEL>; ++ assigned-clock-parents = <&clkc CLKID_VID_PLL_FINAL_DIV>, ++ <&clkc CLKID_VID_PLL_FINAL_DIV>; ++ ++ clocks = <&clkc CLKID_VPU_INTR>, ++ <&clkc CLKID_HDMI_INTR_SYNC>, ++ <&clkc CLKID_GCLK_VENCI_INT>, ++ <&clkc CLKID_HDMI_PLL_HDMI_OUT>, ++ <&clkc CLKID_HDMI_TX_PIXEL>, ++ <&clkc CLKID_CTS_ENCP>, ++ <&clkc CLKID_CTS_ENCI>, ++ <&clkc CLKID_CTS_ENCT>, ++ <&clkc CLKID_CTS_ENCL>, ++ <&clkc CLKID_CTS_VDAC0>; ++ clock-names = "vpu_intr", ++ "hdmi_intr_sync", ++ "venci_int", ++ "tmds", ++ "hdmi_tx_pixel", ++ "cts_encp", ++ "cts_enci", ++ "cts_enct", ++ "cts_encl", ++ "cts_vdac0"; ++ ++ resets = <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE>, ++ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST>, ++ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE>, ++ <&clkc CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST>; ++ reset-names = "vid_pll_pre", ++ "vid_pll_post", ++ "vid_pll_soft_pre", ++ "vid_pll_soft_post"; ++ ++ phys = <&cvbs_dac>; ++ phy-names = "cvbs-dac"; ++ ++ power-domains = <&pwrc PWRC_MESON8_VPU_ID>; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* CVBS VDAC output port */ ++ cvbs_vdac_port: port@0 { ++ reg = <0>; ++ }; ++ }; + }; + }; /* end of / */ + +@@ -389,6 +454,8 @@ &ao_arc_rproc { + sram = <&ao_arc_sram>; + resets = <&reset RESET_MEDIA_CPU>; + clocks = <&clkc CLKID_AO_MEDIA_CPU>; ++ status = "okay"; ++ firmware-name = "zephyr.elf"; + }; + + &cbus { +@@ -547,6 +614,16 @@ smp-sram@1ff80 { + }; + }; + ++&cvbs_dac { ++ compatible = "amlogic,meson8b-cvbs-dac", "amlogic,meson-cvbs-dac"; ++ ++ clocks = <&clkc CLKID_CTS_VDAC0>; ++ ++ nvmem-cells = <&cvbs_trimming>; ++ nvmem-cell-names = "cvbs_trimming"; ++ ++ status = "okay"; ++}; + + &efuse { + compatible = "amlogic,meson8b-efuse"; +@@ -557,6 +634,10 @@ temperature_calib: calib@1f4 { + /* only the upper two bytes are relevant */ + reg = <0x1f4 0x4>; + }; ++ ++ cvbs_trimming: calib@1f8 { ++ reg = <0x1f8 0x2>; ++ }; + }; + + ðmac { +diff --git a/arch/arm/boot/dts/amlogic/meson8m2.dtsi b/arch/arm/boot/dts/amlogic/meson8m2.dtsi +index 6725dd9fd..fcb2ad976 100644 +--- a/arch/arm/boot/dts/amlogic/meson8m2.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson8m2.dtsi +@@ -96,6 +96,10 @@ &usb1_phy { + compatible = "amlogic,meson8m2-usb2-phy", "amlogic,meson-mx-usb2-phy"; + }; + ++&vpu { ++ compatible = "amlogic,meson8m2-vpu"; ++}; ++ + &wdt { + compatible = "amlogic,meson8m2-wdt", "amlogic,meson8b-wdt"; + }; +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0060-ARM-dts-meson8-add-the-HDMI-controller-WiP.patch b/patch/kernel/archive/meson-6.9/0060-ARM-dts-meson8-add-the-HDMI-controller-WiP.patch new file mode 100644 index 000000000000..be898c6dfe0f --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0060-ARM-dts-meson8-add-the-HDMI-controller-WiP.patch @@ -0,0 +1,125 @@ +From d724d428a4f5d92bf2b5f169f948e698549b4386 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sun, 5 May 2019 02:30:11 +0200 +Subject: [PATCH 60/96] ARM: dts: meson8: add the HDMI controller - WiP + +WiP + +Signed-off-by: Martin Blumenstingl +--- + arch/arm/boot/dts/amlogic/meson8.dtsi | 67 ++++++++++++++++++++++++++- + 1 file changed, 65 insertions(+), 2 deletions(-) + +diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi +index 519443e19..f63ac1404 100644 +--- a/arch/arm/boot/dts/amlogic/meson8.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson8.dtsi +@@ -315,6 +315,39 @@ mali: gpu@c0000 { + #cooling-cells = <2>; /* min followed by max */ + }; + ++ hdmi_tx: hdmi-tx@42000 { ++ compatible = "amlogic,meson8-hdmi-tx"; ++ reg = <0x42000 0xc>; ++ interrupts = ; ++ phys = <&hdmi_tx_phy>; ++ phy-names = "hdmi"; ++ clocks = <&clkc CLKID_HDMI_PCLK>, ++ <&clkc CLKID_HDMI_SYS>; ++ clock-names = "pclk", "sys"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ #sound-dai-cells = <1>; ++ sound-name-prefix = "HDMITX"; ++ ++ status = "disabled"; ++ ++ /* VPU VENC Input */ ++ hdmi_tx_venc_port: port@0 { ++ reg = <0>; ++ ++ hdmi_tx_in: endpoint { ++ remote-endpoint = <&hdmi_tx_out>; ++ }; ++ }; ++ ++ /* TMDS Output */ ++ hdmi_tx_tmds_port: port@1 { ++ reg = <1>; ++ }; ++ }; ++ + vpu: vpu@100000 { + compatible = "amlogic,meson8-vpu"; + +@@ -378,6 +411,15 @@ vpu: vpu@100000 { + cvbs_vdac_port: port@0 { + reg = <0>; + }; ++ ++ /* HDMI-TX output port */ ++ hdmi_tx_port: port@1 { ++ reg = <1>; ++ ++ hdmi_tx_out: endpoint { ++ remote-endpoint = <&hdmi_tx_in>; ++ }; ++ }; + }; + }; + }; /* end of / */ +@@ -544,11 +586,26 @@ gpio: banks@80b0 { + gpio-ranges = <&pinctrl_cbus 0 0 120>; + }; + ++ hdmi_hpd_pins: hdmi-hpd { ++ mux { ++ groups = "hdmi_hpd"; ++ function = "hdmi"; ++ bias-disable; ++ }; ++ }; ++ ++ hdmi_i2c_pins: hdmi-i2c { ++ mux { ++ groups = "hdmi_sda", "hdmi_scl"; ++ function = "hdmi"; ++ bias-disable; ++ }; ++ }; ++ + pwm_c_dv9_pins: pwm-c-dv9 { + mux { + groups = "pwm_c_dv9"; + function = "pwm_c"; +- bias-disable; + }; + }; + +@@ -556,7 +613,6 @@ pwm_d_pins: pwm-d { + mux { + groups = "pwm_d"; + function = "pwm_d"; +- bias-disable; + }; + }; + +@@ -740,6 +796,13 @@ pwrc: power-controller@100 { + assigned-clocks = <&clkc CLKID_VPU>; + assigned-clock-rates = <364285714>; + }; ++ ++ hdmi_tx_phy: hdmi-phy@3a0 { ++ compatible = "amlogic,meson8-hdmi-tx-phy"; ++ clocks = <&clkc CLKID_HDMI_PLL_HDMI_OUT>; ++ reg = <0x3a0 0xc>; ++ #phy-cells = <0>; ++ }; + }; + + &hwrng { +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0061-ARM-dts-meson8-Add-the-shared-CMA-dma-memory-pool.patch b/patch/kernel/archive/meson-6.9/0061-ARM-dts-meson8-Add-the-shared-CMA-dma-memory-pool.patch new file mode 100644 index 000000000000..44252b702e9e --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0061-ARM-dts-meson8-Add-the-shared-CMA-dma-memory-pool.patch @@ -0,0 +1,36 @@ +From 1b8ef484e7a3af4367b771e74c8f72e8326f897f Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Fri, 4 Jun 2021 21:50:06 +0200 +Subject: [PATCH 61/96] ARM: dts: meson8: Add the shared CMA dma memory pool + +The 4K HDMI modes needs more CMA memory (than the default 64MiB) to be +reserved at boot-time. Add a shared-dma-pool with increased size so the +4K HDMI modes can be used. + +Signed-off-by: Martin Blumenstingl +--- + arch/arm/boot/dts/amlogic/meson8.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi +index f63ac1404..de9845433 100644 +--- a/arch/arm/boot/dts/amlogic/meson8.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson8.dtsi +@@ -193,6 +193,14 @@ power-firmware@4f00000 { + reg = <0x4f00000 0x100000>; + no-map; + }; ++ ++ linux,cma { ++ compatible = "shared-dma-pool"; ++ reusable; ++ size = <0x10000000>; ++ alignment = <0x400000>; ++ linux,cma-default; ++ }; + }; + + thermal-zones { +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0062-ARM-dts-meson8-add-the-AO-CEC-controller-WiP.patch b/patch/kernel/archive/meson-6.9/0062-ARM-dts-meson8-add-the-AO-CEC-controller-WiP.patch new file mode 100644 index 000000000000..47fc63fa7d95 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0062-ARM-dts-meson8-add-the-AO-CEC-controller-WiP.patch @@ -0,0 +1,50 @@ +From 4d4c55a553ee723670f756737589633fc95894f2 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sun, 5 May 2019 11:44:08 +0200 +Subject: [PATCH 62/96] ARM: dts: meson8: add the AO CEC controller - WiP + +WiP + +Signed-off-by: Martin Blumenstingl +--- + arch/arm/boot/dts/amlogic/meson8.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/arm/boot/dts/amlogic/meson8.dtsi b/arch/arm/boot/dts/amlogic/meson8.dtsi +index de9845433..ae1047eca 100644 +--- a/arch/arm/boot/dts/amlogic/meson8.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson8.dtsi +@@ -478,6 +478,14 @@ gpio_ao: ao-bank@14 { + gpio-ranges = <&pinctrl_aobus 0 0 16>; + }; + ++ hdmi_cec_ao_pins: hdmi-cec-ao { ++ mux { ++ groups = "hdmi_cec_ao"; ++ function = "hdmi_cec_ao"; ++ bias-pull-up; ++ }; ++ }; ++ + i2s_am_clk_pins: i2s-am-clk-out { + mux { + groups = "i2s_am_clk_out_ao"; +@@ -542,6 +550,15 @@ mux { + }; + }; + }; ++ ++ cec_AO: cec@100 { ++ compatible = "amlogic,meson-gx-ao-cec"; // FIXME ++ reg = <0x100 0x14>; ++ interrupts = ; ++ // TODO: 32768HZ clock ++ hdmi-phandle = <&hdmi_tx>; ++ status = "disabled"; ++ }; + }; + + &ao_arc_rproc { +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0063-ARM-dts-meson8b-add-the-HDMI-controller-WiP.patch b/patch/kernel/archive/meson-6.9/0063-ARM-dts-meson8b-add-the-HDMI-controller-WiP.patch new file mode 100644 index 000000000000..c30bc6b01de6 --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0063-ARM-dts-meson8b-add-the-HDMI-controller-WiP.patch @@ -0,0 +1,120 @@ +From 15091212cb8b362780e0c54ae0e430bfeca46525 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sun, 5 May 2019 02:30:29 +0200 +Subject: [PATCH 63/96] ARM: dts: meson8b: add the HDMI controller - WiP + +WiP + +Signed-off-by: Martin Blumenstingl +--- + arch/arm/boot/dts/amlogic/meson8b.dtsi | 69 ++++++++++++++++++++++++++ + 1 file changed, 69 insertions(+) + +diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi +index 87aa74675..176b2dc71 100644 +--- a/arch/arm/boot/dts/amlogic/meson8b.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi +@@ -277,6 +277,39 @@ mali: gpu@c0000 { + #cooling-cells = <2>; /* min followed by max */ + }; + ++ hdmi_tx: hdmi-tx@42000 { ++ compatible = "amlogic,meson8b-hdmi-tx"; ++ reg = <0x42000 0xc>; ++ interrupts = ; ++ phys = <&hdmi_tx_phy>; ++ phy-names = "hdmi"; ++ clocks = <&clkc CLKID_HDMI_PCLK>, ++ <&clkc CLKID_HDMI_SYS>; ++ clock-names = "pclk", "sys"; ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ #sound-dai-cells = <1>; ++ sound-name-prefix = "HDMITX"; ++ ++ status = "disabled"; ++ ++ /* VPU VENC Input */ ++ hdmi_tx_venc_port: port@0 { ++ reg = <0>; ++ ++ hdmi_tx_in: endpoint { ++ remote-endpoint = <&hdmi_tx_out>; ++ }; ++ }; ++ ++ /* TMDS Output */ ++ hdmi_tx_tmds_port: port@1 { ++ reg = <1>; ++ }; ++ }; ++ + vpu: vpu@100000 { + compatible = "amlogic,meson8b-vpu"; + +@@ -336,10 +369,22 @@ vpu: vpu@100000 { + #address-cells = <1>; + #size-cells = <0>; + ++ #sound-dai-cells = <0>; ++ sound-name-prefix = "HDMITX"; ++ + /* CVBS VDAC output port */ + cvbs_vdac_port: port@0 { + reg = <0>; + }; ++ ++ /* HDMI-TX output port */ ++ hdmi_tx_port: port@1 { ++ reg = <1>; ++ ++ hdmi_tx_out: endpoint { ++ remote-endpoint = <&hdmi_tx_in>; ++ }; ++ }; + }; + }; + }; /* end of / */ +@@ -538,6 +583,22 @@ mux { + }; + }; + ++ hdmi_hpd_pins: hdmi-hpd { ++ mux { ++ groups = "hdmi_hpd"; ++ function = "hdmi"; ++ bias-disable; ++ }; ++ }; ++ ++ hdmi_i2c_pins: hdmi-i2c { ++ mux { ++ groups = "hdmi_sda", "hdmi_scl"; ++ function = "hdmi"; ++ bias-disable; ++ }; ++ }; ++ + i2c_a_pins: i2c-a { + mux { + groups = "i2c_sda_a", "i2c_sck_a"; +@@ -700,6 +761,14 @@ pwrc: power-controller@100 { + assigned-clocks = <&clkc CLKID_VPU>; + assigned-clock-rates = <182142857>; + }; ++ ++ hdmi_tx_phy: hdmi-phy@3a0 { ++ compatible = "amlogic,meson8b-hdmi-tx-phy", ++ "amlogic,meson8-hdmi-tx-phy"; ++ clocks = <&clkc CLKID_HDMI_PLL_HDMI_OUT>; ++ reg = <0x3a0 0xc>; ++ #phy-cells = <0>; ++ }; + }; + + &hwrng { +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.9/0064-ARM-dts-meson8b-add-the-AO-CEC-controller-WiP.patch b/patch/kernel/archive/meson-6.9/0064-ARM-dts-meson8b-add-the-AO-CEC-controller-WiP.patch new file mode 100644 index 000000000000..5419a017463e --- /dev/null +++ b/patch/kernel/archive/meson-6.9/0064-ARM-dts-meson8b-add-the-AO-CEC-controller-WiP.patch @@ -0,0 +1,50 @@ +From 6b21e706b95e5e0c8c5b9f691f2fc64befdf8d08 Mon Sep 17 00:00:00 2001 +From: Martin Blumenstingl +Date: Sun, 5 May 2019 11:44:20 +0200 +Subject: [PATCH 64/96] ARM: dts: meson8b: add the AO CEC controller - WiP + +WiP + +Signed-off-by: Martin Blumenstingl +--- + arch/arm/boot/dts/amlogic/meson8b.dtsi | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +diff --git a/arch/arm/boot/dts/amlogic/meson8b.dtsi b/arch/arm/boot/dts/amlogic/meson8b.dtsi +index 176b2dc71..3e5d97e0c 100644 +--- a/arch/arm/boot/dts/amlogic/meson8b.dtsi ++++ b/arch/arm/boot/dts/amlogic/meson8b.dtsi +@@ -435,6 +435,14 @@ gpio_ao: ao-bank@14 { + gpio-ranges = <&pinctrl_aobus 0 0 16>; + }; + ++ hdmi_cec_ao_pins: hdmi-cec-ao { ++ mux { ++ groups = "hdmi_cec_1"; ++ function = "hdmi_cec"; ++ bias-pull-up; ++ }; ++ }; ++ + i2s_am_clk_pins: i2s-am-clk-out { + mux { + groups = "i2s_am_clk_out"; +@@ -491,6 +499,15 @@ mux { + }; + }; + }; ++ ++ cec_AO: cec@100 { ++ compatible = "amlogic,meson-gx-ao-cec"; // FIXME ++ reg = <0x100 0x14>; ++ interrupts = ; ++ // TODO: 32768HZ clock ++ hdmi-phandle = <&hdmi_tx>; ++ status = "disabled"; ++ }; + }; + + &ao_arc_rproc { +-- +2.45.1 + diff --git a/patch/kernel/archive/meson-6.8/odroidc1-dts-Enable-HDMI.patch b/patch/kernel/archive/meson-6.9/0066-ARM-dts-meson8b-odroid-c1-enable-HDMI-for-the-Odroid.patch similarity index 84% rename from patch/kernel/archive/meson-6.8/odroidc1-dts-Enable-HDMI.patch rename to patch/kernel/archive/meson-6.9/0066-ARM-dts-meson8b-odroid-c1-enable-HDMI-for-the-Odroid.patch index 4edaefe9ac98..6244851104fe 100644 --- a/patch/kernel/archive/meson-6.8/odroidc1-dts-Enable-HDMI.patch +++ b/patch/kernel/archive/meson-6.9/0066-ARM-dts-meson8b-odroid-c1-enable-HDMI-for-the-Odroid.patch @@ -1,7 +1,7 @@ -From e9d0d7bb75ff8234d717fb640c020ffe303a8d11 Mon Sep 17 00:00:00 2001 +From 9d61f99a90171d451718e0afb254d5733c4b4852 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Fri, 20 Mar 2020 15:17:51 +0100 -Subject: [PATCH] ARM: dts: meson8b: odroid-c1: enable HDMI for the +Subject: [PATCH 66/96] ARM: dts: meson8b: odroid-c1: enable HDMI for the Odroid-C1 - WiP WiP @@ -12,7 +12,7 @@ Signed-off-by: Martin Blumenstingl 1 file changed, 59 insertions(+) diff --git a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts -index 94168284..7e43212e 100644 +index eaf89638c..b03273d90 100644 --- a/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/amlogic/meson8b-odroidc1.dts @@ -32,6 +32,17 @@ emmc_pwrseq: emmc-pwrseq { @@ -69,10 +69,10 @@ index 94168284..7e43212e 100644 + }; + }; + - vcc_1v8: regulator-vcc-1v8 { - /* - * RICHTEK RT9179 configured for a fixed output voltage of -@@ -187,6 +230,10 @@ vdd_rtc: regulator-vdd-rtc { + usb0_vbus: regulator-usb0-vbus { + /* Richtek RT9715EGB */ + compatible = "regulator-fixed"; +@@ -201,6 +244,10 @@ vdd_rtc: regulator-vdd-rtc { }; }; @@ -83,7 +83,7 @@ index 94168284..7e43212e 100644 &cpu0 { cpu-supply = <&vcck>; }; -@@ -283,6 +330,18 @@ &gpio_ao { +@@ -297,6 +344,18 @@ &gpio_ao { "SYS_LED", "", ""; }; @@ -103,5 +103,5 @@ index 94168284..7e43212e 100644 status = "okay"; pinctrl-0 = <&ir_recv_pins>; -- -2.34.1 +2.45.1 diff --git a/patch/kernel/archive/meson-6.8/generic-Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch b/patch/kernel/archive/meson-6.9/generic-Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch similarity index 100% rename from patch/kernel/archive/meson-6.8/generic-Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch rename to patch/kernel/archive/meson-6.9/generic-Revert-mmc-core-Set-HS-clock-speed-before-sending-HS-CMD13.patch diff --git a/patch/kernel/archive/meson-6.8/generic-Revert-pwm-meson-modify-and-simplify-calculation-in-.patch b/patch/kernel/archive/meson-6.9/generic-Revert-pwm-meson-modify-and-simplify-calculation-in-.patch similarity index 100% rename from patch/kernel/archive/meson-6.8/generic-Revert-pwm-meson-modify-and-simplify-calculation-in-.patch rename to patch/kernel/archive/meson-6.9/generic-Revert-pwm-meson-modify-and-simplify-calculation-in-.patch diff --git a/patch/kernel/archive/meson-6.8/onecloud-0001-add-dts.patch b/patch/kernel/archive/meson-6.9/onecloud-0001-add-dts.patch similarity index 100% rename from patch/kernel/archive/meson-6.8/onecloud-0001-add-dts.patch rename to patch/kernel/archive/meson-6.9/onecloud-0001-add-dts.patch diff --git a/patch/kernel/archive/meson-6.8/onecloud-0002-dts-Support-HDMI.patch b/patch/kernel/archive/meson-6.9/onecloud-0002-dts-Support-HDMI.patch similarity index 100% rename from patch/kernel/archive/meson-6.8/onecloud-0002-dts-Support-HDMI.patch rename to patch/kernel/archive/meson-6.9/onecloud-0002-dts-Support-HDMI.patch diff --git a/patch/kernel/archive/meson64-6.8/general-add-overlay-compilation-support.patch b/patch/kernel/archive/meson64-6.8/general-add-overlay-compilation-support.patch deleted file mode 100644 index dcd7f487c379..000000000000 --- a/patch/kernel/archive/meson64-6.8/general-add-overlay-compilation-support.patch +++ /dev/null @@ -1,97 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Martin Ayotte -Date: Sat, 11 Feb 2017 18:32:53 +0100 -Subject: add overlay-compilation-support to meson64-dev - -- 871bed1a24e21952f7aeb1981c26ad5fc573be9d: Martin Ayotte : 'add overlay-compilation-support to meson64-dev' ---- - arch/arm/boot/.gitignore | 2 + - scripts/Makefile.dtbinst | 14 ++++++- - scripts/Makefile.lib | 20 ++++++++++ - 3 files changed, 35 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore -index 8c759326baf4..e6ce8f6ad4b1 100644 ---- a/arch/arm/boot/.gitignore -+++ b/arch/arm/boot/.gitignore -@@ -4,3 +4,5 @@ zImage - xipImage - bootpImage - uImage -+*.dtb* -+*.scr -diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst -index 4405d5b67578..04df2e7c8453 100644 ---- a/scripts/Makefile.dtbinst -+++ b/scripts/Makefile.dtbinst -@@ -18,9 +18,12 @@ include $(srctree)/scripts/Kbuild.include - include $(kbuild-file) - - dtbs := $(addprefix $(dst)/, $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-))) -+dtbos := $(addprefix $(dst)/, $(dtbo-y)) -+scrs := $(addprefix $(dst)/, $(scr-y)) -+readmes := $(addprefix $(dst)/, $(dtbotxt-y)) - subdirs := $(addprefix $(obj)/, $(subdir-y) $(subdir-m)) - --__dtbs_install: $(dtbs) $(subdirs) -+__dtbs_install: $(dtbs) $(dtbos) $(scrs) $(readmes) $(subdirs) - @: - - quiet_cmd_dtb_install = INSTALL $@ -@@ -32,6 +35,15 @@ $(dst)/%.dtb: $(obj)/%.dtb - $(dst)/%.dtbo: $(obj)/%.dtbo - $(call cmd,dtb_install) - -+$(dst)/%.dtbo: $(obj)/%.dtbo -+ $(call cmd,dtb_install) -+ -+$(dst)/%.scr: $(obj)/%.scr -+ $(call cmd,dtb_install) -+ -+$(dst)/README.meson-overlays: $(src)/README.meson-overlays -+ $(call cmd,dtb_install) -+ - PHONY += $(subdirs) - $(subdirs): - $(Q)$(MAKE) $(dtbinst)=$@ dst=$(if $(CONFIG_ARCH_WANT_FLAT_DTB_INSTALL),$(dst),$(patsubst $(obj)/%,$(dst)/%,$@)) -diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib -index cd5b181060f1..75008c9921f6 100644 ---- a/scripts/Makefile.lib -+++ b/scripts/Makefile.lib -@@ -343,6 +343,9 @@ DTC ?= $(objtree)/scripts/dtc/dtc - DTC_FLAGS += -Wno-interrupt_provider \ - -Wno-unique_unit_address - -+# Overlay support -+DTC_FLAGS += -@ -Wno-unit_address_format -Wno-simple_bus_reg -+ - # Disable noisy checks by default - ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),) - DTC_FLAGS += -Wno-unit_address_vs_reg \ -@@ -421,6 +424,23 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE - $(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE - $(call if_changed_dep,dtc) - -+quiet_cmd_dtco = DTCO $@ -+cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \ -+ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ -+ $(DTC) -O dtb -o $@ -b 0 \ -+ -i $(dir $<) $(DTC_FLAGS) \ -+ -d $(depfile).dtc.tmp $(dtc-tmp) ; \ -+ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) -+ -+$(obj)/%.dtbo: $(src)/%.dts FORCE -+ $(call if_changed_dep,dtco) -+ -+quiet_cmd_scr = MKIMAGE $@ -+cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ -+ -+$(obj)/%.scr: $(src)/%.scr-cmd FORCE -+ $(call if_changed,scr) -+ - dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) - - # Bzip2 --- -Armbian - diff --git a/patch/kernel/archive/meson64-6.8/general-socinfo-sm-3-soc-amlogic-meson-gx-socinfo-add-new-definition-for-.patch b/patch/kernel/archive/meson64-6.8/general-socinfo-sm-3-soc-amlogic-meson-gx-socinfo-add-new-definition-for-.patch deleted file mode 100644 index 044a6f496b3e..000000000000 --- a/patch/kernel/archive/meson64-6.8/general-socinfo-sm-3-soc-amlogic-meson-gx-socinfo-add-new-definition-for-.patch +++ /dev/null @@ -1,28 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Viacheslav Bocharov -Date: Wed, 21 Feb 2024 15:30:32 +0300 -Subject: soc: amlogic: meson-gx-socinfo: add new definition for Amlogic A113X - package - -Add new definition for Amlogix A113X soc found in JetHub D1/D1+ devices. - -Signed-off-by: Viacheslav Bocharov ---- - drivers/soc/amlogic/meson-gx-socinfo-internal.h | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/drivers/soc/amlogic/meson-gx-socinfo-internal.h b/drivers/soc/amlogic/meson-gx-socinfo-internal.h -index 3ebb80972fc7..2028101bb9b2 100644 ---- a/drivers/soc/amlogic/meson-gx-socinfo-internal.h -+++ b/drivers/soc/amlogic/meson-gx-socinfo-internal.h -@@ -78,6 +78,7 @@ static const struct meson_gx_package_id { - { "962X", 0x24, 0x10, 0xf0 }, - { "962E", 0x24, 0x20, 0xf0 }, - { "A113X", 0x25, 0x37, 0xff }, -+ { "A113X", 0x25, 0x43, 0xff }, - { "A113D", 0x25, 0x22, 0xff }, - { "S905D2", 0x28, 0x10, 0xf0 }, - { "S905Y2", 0x28, 0x30, 0xf0 }, --- -Armbian - diff --git a/patch/kernel/archive/meson64-6.8/0000.patching_config.yaml b/patch/kernel/archive/meson64-6.9/0000.patching_config.yaml similarity index 100% rename from patch/kernel/archive/meson64-6.8/0000.patching_config.yaml rename to patch/kernel/archive/meson64-6.9/0000.patching_config.yaml diff --git a/patch/kernel/archive/meson64-6.8/board-bananapi-cm4-cm4io.patch b/patch/kernel/archive/meson64-6.9/board-bananapi-cm4-cm4io.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-bananapi-cm4-cm4io.patch rename to patch/kernel/archive/meson64-6.9/board-bananapi-cm4-cm4io.patch diff --git a/patch/kernel/archive/meson64-6.8/board-bananapi-m2s.patch b/patch/kernel/archive/meson64-6.9/board-bananapi-m2s.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-bananapi-m2s.patch rename to patch/kernel/archive/meson64-6.9/board-bananapi-m2s.patch diff --git a/patch/kernel/archive/meson64-6.8/board-bananapim5-001-sd-use-270-mmc-clock-phase-via-dt.patch b/patch/kernel/archive/meson64-6.9/board-bananapim5-001-sd-use-270-mmc-clock-phase-via-dt.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-bananapim5-001-sd-use-270-mmc-clock-phase-via-dt.patch rename to patch/kernel/archive/meson64-6.9/board-bananapim5-001-sd-use-270-mmc-clock-phase-via-dt.patch diff --git a/patch/kernel/archive/meson64-6.8/board-bananapim5-002-add-wifi-bt-support.patch b/patch/kernel/archive/meson64-6.9/board-bananapim5-002-add-wifi-bt-support.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-bananapim5-002-add-wifi-bt-support.patch rename to patch/kernel/archive/meson64-6.9/board-bananapim5-002-add-wifi-bt-support.patch diff --git a/patch/kernel/archive/meson64-6.8/board-bananapism1-add-uart_A-and-AO_B.patch b/patch/kernel/archive/meson64-6.9/board-bananapism1-add-uart_A-and-AO_B.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-bananapism1-add-uart_A-and-AO_B.patch rename to patch/kernel/archive/meson64-6.9/board-bananapism1-add-uart_A-and-AO_B.patch diff --git a/patch/kernel/archive/meson64-6.8/board-khadas-vim3-fix-missing-i2c3-nod.patch b/patch/kernel/archive/meson64-6.9/board-khadas-vim3-fix-missing-i2c3-nod.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-khadas-vim3-fix-missing-i2c3-nod.patch rename to patch/kernel/archive/meson64-6.9/board-khadas-vim3-fix-missing-i2c3-nod.patch diff --git a/patch/kernel/archive/meson64-6.8/board-khadas-vims-add-rtc-vrtc-aliases.patch b/patch/kernel/archive/meson64-6.9/board-khadas-vims-add-rtc-vrtc-aliases.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-khadas-vims-add-rtc-vrtc-aliases.patch rename to patch/kernel/archive/meson64-6.9/board-khadas-vims-add-rtc-vrtc-aliases.patch diff --git a/patch/kernel/archive/meson64-6.8/board-nanopi-k2-add-uartC-alias.patch b/patch/kernel/archive/meson64-6.9/board-nanopi-k2-add-uartC-alias.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-nanopi-k2-add-uartC-alias.patch rename to patch/kernel/archive/meson64-6.9/board-nanopi-k2-add-uartC-alias.patch diff --git a/patch/kernel/archive/meson64-6.8/board-nanopi-k2-enable-emmc.patch b/patch/kernel/archive/meson64-6.9/board-nanopi-k2-enable-emmc.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-nanopi-k2-enable-emmc.patch rename to patch/kernel/archive/meson64-6.9/board-nanopi-k2-enable-emmc.patch diff --git a/patch/kernel/archive/meson64-6.8/board-odroidc2-add-uartA-uartC.patch b/patch/kernel/archive/meson64-6.9/board-odroidc2-add-uartA-uartC.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-odroidc2-add-uartA-uartC.patch rename to patch/kernel/archive/meson64-6.9/board-odroidc2-add-uartA-uartC.patch diff --git a/patch/kernel/archive/meson64-6.8/board-odroidc2-enable-SPI.patch b/patch/kernel/archive/meson64-6.9/board-odroidc2-enable-SPI.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-odroidc2-enable-SPI.patch rename to patch/kernel/archive/meson64-6.9/board-odroidc2-enable-SPI.patch diff --git a/patch/kernel/archive/meson64-6.8/board-odroidc2-enable-scpi-dvfs.patch b/patch/kernel/archive/meson64-6.9/board-odroidc2-enable-scpi-dvfs.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-odroidc2-enable-scpi-dvfs.patch rename to patch/kernel/archive/meson64-6.9/board-odroidc2-enable-scpi-dvfs.patch diff --git a/patch/kernel/archive/meson64-6.8/board-odroidc2-usb-hub-disable-autosuspend-for-Genesys-Logic-.patch b/patch/kernel/archive/meson64-6.9/board-odroidc2-usb-hub-disable-autosuspend-for-Genesys-Logic-.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-odroidc2-usb-hub-disable-autosuspend-for-Genesys-Logic-.patch rename to patch/kernel/archive/meson64-6.9/board-odroidc2-usb-hub-disable-autosuspend-for-Genesys-Logic-.patch diff --git a/patch/kernel/archive/meson64-6.8/board-odroidc4-reset.patch b/patch/kernel/archive/meson64-6.9/board-odroidc4-reset.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-odroidc4-reset.patch rename to patch/kernel/archive/meson64-6.9/board-odroidc4-reset.patch diff --git a/patch/kernel/archive/meson64-6.8/board-odroidhc4-enable-fan1_input.patch b/patch/kernel/archive/meson64-6.9/board-odroidhc4-enable-fan1_input.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-odroidhc4-enable-fan1_input.patch rename to patch/kernel/archive/meson64-6.9/board-odroidhc4-enable-fan1_input.patch diff --git a/patch/kernel/archive/meson64-6.8/board-odroidn2plus-Add-missing-CPU-opp.patch b/patch/kernel/archive/meson64-6.9/board-odroidn2plus-Add-missing-CPU-opp.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-odroidn2plus-Add-missing-CPU-opp.patch rename to patch/kernel/archive/meson64-6.9/board-odroidn2plus-Add-missing-CPU-opp.patch diff --git a/patch/kernel/archive/meson64-6.8/board-radxa-zero-dts-add-aliases-for-serial-i2c-and-spi.patch b/patch/kernel/archive/meson64-6.9/board-radxa-zero-dts-add-aliases-for-serial-i2c-and-spi.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-radxa-zero-dts-add-aliases-for-serial-i2c-and-spi.patch rename to patch/kernel/archive/meson64-6.9/board-radxa-zero-dts-add-aliases-for-serial-i2c-and-spi.patch diff --git a/patch/kernel/archive/meson64-6.8/board-radxa-zero-dts-add-support-for-the-usb-c-controller.patch b/patch/kernel/archive/meson64-6.9/board-radxa-zero-dts-add-support-for-the-usb-c-controller.patch similarity index 98% rename from patch/kernel/archive/meson64-6.8/board-radxa-zero-dts-add-support-for-the-usb-c-controller.patch rename to patch/kernel/archive/meson64-6.9/board-radxa-zero-dts-add-support-for-the-usb-c-controller.patch index 2f9afba7c054..7238245834ab 100644 --- a/patch/kernel/archive/meson64-6.8/board-radxa-zero-dts-add-support-for-the-usb-c-controller.patch +++ b/patch/kernel/archive/meson64-6.9/board-radxa-zero-dts-add-support-for-the-usb-c-controller.patch @@ -38,7 +38,7 @@ index 2e4646e255ad..9dd5e6c2583d 100644 + vin-supply = <&ao_5v>; + }; + - ao_5v: regulator-ao_5v { + ao_5v: regulator-ao-5v { compatible = "regulator-fixed"; regulator-name = "AO_5V"; @@ -202,6 +210,18 @@ wifi32k: wifi32k { diff --git a/patch/kernel/archive/meson64-6.8/board-radxa-zero-dts-slow-down-sdio-for-working-wifi.patch b/patch/kernel/archive/meson64-6.9/board-radxa-zero-dts-slow-down-sdio-for-working-wifi.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-radxa-zero-dts-slow-down-sdio-for-working-wifi.patch rename to patch/kernel/archive/meson64-6.9/board-radxa-zero-dts-slow-down-sdio-for-working-wifi.patch diff --git a/patch/kernel/archive/meson64-6.8/board-t95z-add-rc-remote-keymap.patch b/patch/kernel/archive/meson64-6.9/board-t95z-add-rc-remote-keymap.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/board-t95z-add-rc-remote-keymap.patch rename to patch/kernel/archive/meson64-6.9/board-t95z-add-rc-remote-keymap.patch diff --git a/patch/kernel/archive/meson64-6.8/driver-power-meson64-reset.patch b/patch/kernel/archive/meson64-6.9/driver-power-meson64-reset.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/driver-power-meson64-reset.patch rename to patch/kernel/archive/meson64-6.9/driver-power-meson64-reset.patch diff --git a/patch/kernel/archive/meson64-6.8/drv-spi-spidev-remove-warnings.patch b/patch/kernel/archive/meson64-6.9/drv-spi-spidev-remove-warnings.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/drv-spi-spidev-remove-warnings.patch rename to patch/kernel/archive/meson64-6.9/drv-spi-spidev-remove-warnings.patch diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-g12-enable-spinor.dtsi b/patch/kernel/archive/meson64-6.9/dt/meson-g12-enable-spinor.dtsi similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-g12-enable-spinor.dtsi rename to patch/kernel/archive/meson64-6.9/dt/meson-g12-enable-spinor.dtsi diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-g12a-radxa-zero-spidev.dts b/patch/kernel/archive/meson64-6.9/dt/meson-g12a-radxa-zero-spidev.dts similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-g12a-radxa-zero-spidev.dts rename to patch/kernel/archive/meson64-6.9/dt/meson-g12a-radxa-zero-spidev.dts diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-g12b-a311d-khadas-vim3-spidev.dts b/patch/kernel/archive/meson64-6.9/dt/meson-g12b-a311d-khadas-vim3-spidev.dts similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-g12b-a311d-khadas-vim3-spidev.dts rename to patch/kernel/archive/meson64-6.9/dt/meson-g12b-a311d-khadas-vim3-spidev.dts diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-g12b-a311d-khadas-vim3-spinor.dts b/patch/kernel/archive/meson64-6.9/dt/meson-g12b-a311d-khadas-vim3-spinor.dts similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-g12b-a311d-khadas-vim3-spinor.dts rename to patch/kernel/archive/meson64-6.9/dt/meson-g12b-a311d-khadas-vim3-spinor.dts diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-g12b-odroid-n2-plus-spidev.dts b/patch/kernel/archive/meson64-6.9/dt/meson-g12b-odroid-n2-plus-spidev.dts similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-g12b-odroid-n2-plus-spidev.dts rename to patch/kernel/archive/meson64-6.9/dt/meson-g12b-odroid-n2-plus-spidev.dts diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-g12b-odroid-n2-plus-spinor.dts b/patch/kernel/archive/meson64-6.9/dt/meson-g12b-odroid-n2-plus-spinor.dts similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-g12b-odroid-n2-plus-spinor.dts rename to patch/kernel/archive/meson64-6.9/dt/meson-g12b-odroid-n2-plus-spinor.dts diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-g12b-odroid-n2-spinor.dts b/patch/kernel/archive/meson64-6.9/dt/meson-g12b-odroid-n2-spinor.dts similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-g12b-odroid-n2-spinor.dts rename to patch/kernel/archive/meson64-6.9/dt/meson-g12b-odroid-n2-spinor.dts diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-g12b-radxa-zero2-spidev.dts b/patch/kernel/archive/meson64-6.9/dt/meson-g12b-radxa-zero2-spidev.dts similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-g12b-radxa-zero2-spidev.dts rename to patch/kernel/archive/meson64-6.9/dt/meson-g12b-radxa-zero2-spidev.dts diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-g12b-waveshare-cm4-io-base-b.dts b/patch/kernel/archive/meson64-6.9/dt/meson-g12b-waveshare-cm4-io-base-b.dts similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-g12b-waveshare-cm4-io-base-b.dts rename to patch/kernel/archive/meson64-6.9/dt/meson-g12b-waveshare-cm4-io-base-b.dts diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-gxm-mini-m8s-pro.dts b/patch/kernel/archive/meson64-6.9/dt/meson-gxm-mini-m8s-pro.dts similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-gxm-mini-m8s-pro.dts rename to patch/kernel/archive/meson64-6.9/dt/meson-gxm-mini-m8s-pro.dts diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-gxm-t95z-plus.dts b/patch/kernel/archive/meson64-6.9/dt/meson-gxm-t95z-plus.dts similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-gxm-t95z-plus.dts rename to patch/kernel/archive/meson64-6.9/dt/meson-gxm-t95z-plus.dts diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-sm1-khadas-vim3l-spidev.dts b/patch/kernel/archive/meson64-6.9/dt/meson-sm1-khadas-vim3l-spidev.dts similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-sm1-khadas-vim3l-spidev.dts rename to patch/kernel/archive/meson64-6.9/dt/meson-sm1-khadas-vim3l-spidev.dts diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-sm1-khadas-vim3l-spinor.dts b/patch/kernel/archive/meson64-6.9/dt/meson-sm1-khadas-vim3l-spinor.dts similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-sm1-khadas-vim3l-spinor.dts rename to patch/kernel/archive/meson64-6.9/dt/meson-sm1-khadas-vim3l-spinor.dts diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-sm1-odroid-c4-spidev.dts b/patch/kernel/archive/meson64-6.9/dt/meson-sm1-odroid-c4-spidev.dts similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-sm1-odroid-c4-spidev.dts rename to patch/kernel/archive/meson64-6.9/dt/meson-sm1-odroid-c4-spidev.dts diff --git a/patch/kernel/archive/meson64-6.8/dt/meson-sm1-ugoos-x3.dts b/patch/kernel/archive/meson64-6.9/dt/meson-sm1-ugoos-x3.dts similarity index 100% rename from patch/kernel/archive/meson64-6.8/dt/meson-sm1-ugoos-x3.dts rename to patch/kernel/archive/meson64-6.9/dt/meson-sm1-ugoos-x3.dts diff --git a/patch/kernel/archive/meson64-6.8/general-add-Amlogic-Meson-GX-PM-Suspend.patch b/patch/kernel/archive/meson64-6.9/general-add-Amlogic-Meson-GX-PM-Suspend.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-add-Amlogic-Meson-GX-PM-Suspend.patch rename to patch/kernel/archive/meson64-6.9/general-add-Amlogic-Meson-GX-PM-Suspend.patch diff --git a/patch/kernel/archive/meson64-6.9/general-add-overlay-compilation-support.patch b/patch/kernel/archive/meson64-6.9/general-add-overlay-compilation-support.patch new file mode 100644 index 000000000000..b2e233f4dda4 --- /dev/null +++ b/patch/kernel/archive/meson64-6.9/general-add-overlay-compilation-support.patch @@ -0,0 +1,69 @@ +From 088e1cd9b9dd113f0a5e9e19a7f31c37532e002a Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Sun, 2 Jun 2024 21:53:01 +0200 +Subject: [PATCH] compile .scr and install overlays in right path + +--- + scripts/Makefile.dtbinst | 2 +- + scripts/Makefile.lib | 8 +++++++- + 2 files changed, 8 insertions(+), 2 deletions(-) + +diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst +index 67956f6496a5..151687728a60 100644 +--- a/scripts/Makefile.dtbinst ++++ b/scripts/Makefile.dtbinst +@@ -33,7 +33,18 @@ endef + + $(foreach d, $(sort $(dir $(dtbs))), $(eval $(call gen_install_rules,$(d)))) + +-dtbs := $(notdir $(dtbs)) ++# Very convoluted way to flatten all the device tree ++# directories, but keep the "/overlay/" directory ++ ++# topmost directory (ie: from rockchip/overlay/rk322x-emmc.dtbo extracts rockchip) ++topmost_dir = $(firstword $(subst /, ,$(dtbs))) ++# collect dtbs entries which starts with "$topmost_dir/overlay/", then remove "$topmost_dir" ++dtbs_overlays = $(subst $(topmost_dir)/,,$(filter $(topmost_dir)/overlay/%, $(dtbs))) ++# collect the non-overlay dtbs ++dtbs_regular = $(filter-out $(topmost_dir)/overlay/%, $(dtbs)) ++# compose the dtbs variable flattening all the non-overlays entries ++# and appending the overlays entries ++dtbs := $(notdir $(dtbs_regular)) $(dtbs_overlays) + + endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL + +diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib +index 3179747cbd2c..59925208734a 100644 +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -398,7 +398,7 @@ $(obj)/%.dtbo.S: $(obj)/%.dtbo FORCE + + quiet_cmd_dtc = DTC $@ + cmd_dtc = $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ +- $(DTC) -o $@ -b 0 \ ++ $(DTC) -@ -o $@ -b 0 \ + $(addprefix -i,$(dir $<) $(DTC_INCLUDE)) $(DTC_FLAGS) \ + -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) +@@ -423,12 +423,18 @@ quiet_cmd_dtb = $(quiet_cmd_dtc) + cmd_dtb = $(cmd_dtc) + endif + ++quiet_cmd_scr = MKIMAGE $@ ++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ ++ + $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE + $(call if_changed_dep,dtb) + + $(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE + $(call if_changed_dep,dtc) + ++$(obj)/%.scr: $(src)/%.scr-cmd FORCE ++ $(call if_changed,scr) ++ + dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + + # Bzip2 +-- +2.34.1 + diff --git a/patch/kernel/archive/meson64-6.8/general-driver-tm1628-auxdisplay-add-support-for-Titanmec-TM16.patch b/patch/kernel/archive/meson64-6.9/general-driver-tm1628-auxdisplay-add-support-for-Titanmec-TM16.patch similarity index 99% rename from patch/kernel/archive/meson64-6.8/general-driver-tm1628-auxdisplay-add-support-for-Titanmec-TM16.patch rename to patch/kernel/archive/meson64-6.9/general-driver-tm1628-auxdisplay-add-support-for-Titanmec-TM16.patch index 3e524f0e0040..e19c081f38af 100644 --- a/patch/kernel/archive/meson64-6.8/general-driver-tm1628-auxdisplay-add-support-for-Titanmec-TM16.patch +++ b/patch/kernel/archive/meson64-6.9/general-driver-tm1628-auxdisplay-add-support-for-Titanmec-TM16.patch @@ -194,9 +194,9 @@ index 6968ed4d3f0a..7728e17e1c5a 100644 --- a/drivers/auxdisplay/Makefile +++ b/drivers/auxdisplay/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_HT16K33) += ht16k33.o + obj-$(CONFIG_MAX6959) += max6959.o obj-$(CONFIG_PARPORT_PANEL) += panel.o - obj-$(CONFIG_LCD2S) += lcd2s.o - obj-$(CONFIG_LINEDISP) += line-display.o + obj-$(CONFIG_SEG_LED_GPIO) += seg-led-gpio.o +obj-$(CONFIG_TM1628) += tm1628.o diff --git a/drivers/auxdisplay/tm1628.c b/drivers/auxdisplay/tm1628.c new file mode 100644 diff --git a/patch/kernel/archive/meson64-6.8/general-drm-dw-hdmi-call-hdmi_set_cts_n-after-clock.patch b/patch/kernel/archive/meson64-6.9/general-drm-dw-hdmi-call-hdmi_set_cts_n-after-clock.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-drm-dw-hdmi-call-hdmi_set_cts_n-after-clock.patch rename to patch/kernel/archive/meson64-6.9/general-drm-dw-hdmi-call-hdmi_set_cts_n-after-clock.patch diff --git a/patch/kernel/archive/meson64-6.8/general-drm-panfrost-fix-reference-leak.patch b/patch/kernel/archive/meson64-6.9/general-drm-panfrost-fix-reference-leak.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-drm-panfrost-fix-reference-leak.patch rename to patch/kernel/archive/meson64-6.9/general-drm-panfrost-fix-reference-leak.patch diff --git a/patch/kernel/archive/meson64-6.8/general-fix-Kodi-sysinfo-CPU-information.patch b/patch/kernel/archive/meson64-6.9/general-fix-Kodi-sysinfo-CPU-information.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-fix-Kodi-sysinfo-CPU-information.patch rename to patch/kernel/archive/meson64-6.9/general-fix-Kodi-sysinfo-CPU-information.patch diff --git a/patch/kernel/archive/meson64-6.8/general-gpu-drm-add-new-display-resolution-2560x1440.patch b/patch/kernel/archive/meson64-6.9/general-gpu-drm-add-new-display-resolution-2560x1440.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-gpu-drm-add-new-display-resolution-2560x1440.patch rename to patch/kernel/archive/meson64-6.9/general-gpu-drm-add-new-display-resolution-2560x1440.patch diff --git a/patch/kernel/archive/meson64-6.8/general-hdmi-codec-reorder-channel-allocation-list.patch b/patch/kernel/archive/meson64-6.9/general-hdmi-codec-reorder-channel-allocation-list.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-hdmi-codec-reorder-channel-allocation-list.patch rename to patch/kernel/archive/meson64-6.9/general-hdmi-codec-reorder-channel-allocation-list.patch diff --git a/patch/kernel/archive/meson64-6.8/general-input-touchscreen-Add-D-WAV-Multitouch.patch b/patch/kernel/archive/meson64-6.9/general-input-touchscreen-Add-D-WAV-Multitouch.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-input-touchscreen-Add-D-WAV-Multitouch.patch rename to patch/kernel/archive/meson64-6.9/general-input-touchscreen-Add-D-WAV-Multitouch.patch diff --git a/patch/kernel/archive/meson64-6.8/general-media-cec-silence-CEC-timeout-message-HACK.patch b/patch/kernel/archive/meson64-6.9/general-media-cec-silence-CEC-timeout-message-HACK.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-media-cec-silence-CEC-timeout-message-HACK.patch rename to patch/kernel/archive/meson64-6.9/general-media-cec-silence-CEC-timeout-message-HACK.patch diff --git a/patch/kernel/archive/meson64-6.8/general-memory-marked-nomap.patch b/patch/kernel/archive/meson64-6.9/general-memory-marked-nomap.patch similarity index 72% rename from patch/kernel/archive/meson64-6.8/general-memory-marked-nomap.patch rename to patch/kernel/archive/meson64-6.9/general-memory-marked-nomap.patch index 09b2642d0b45..a57432be8e0f 100644 --- a/patch/kernel/archive/meson64-6.8/general-memory-marked-nomap.patch +++ b/patch/kernel/archive/meson64-6.9/general-memory-marked-nomap.patch @@ -10,14 +10,16 @@ since Linux 5.10; which are also causing crashes in some distros: Signed-off-by: Christian Hewitt --- - drivers/of/fdt.c | 9 --------- + drivers/of/of_reserved_mem.c | 9 --------- 1 file changed, 9 deletions(-) -diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c -index bf502ba8da95..0789f61be489 100644 ---- a/drivers/of/fdt.c -+++ b/drivers/of/fdt.c -@@ -480,15 +480,6 @@ static int __init early_init_dt_reserve_memory(phys_addr_t base, +diff --git a/drivers/of/of_reserved_mem.c b/drivers/of/of_reserved_mem.c +index 8236ecae2953..82e5cee9dc5c 100644 +--- a/drivers/of/of_reserved_mem.c ++++ b/drivers/of/of_reserved_mem.c +@@ -80,19 +80,10 @@ static void __init fdt_reserved_mem_save_node(unsigned long node, const char *un + + static int __init early_init_dt_reserve_memory(phys_addr_t base, phys_addr_t size, bool nomap) { if (nomap) { @@ -33,6 +35,8 @@ index bf502ba8da95..0789f61be489 100644 return memblock_mark_nomap(base, size); } return memblock_reserve(base, size); --- + } + +-- Armbian diff --git a/patch/kernel/archive/meson64-6.8/general-meson-aiu-Fix-HDMI-codec-control-selection.patch b/patch/kernel/archive/meson64-6.9/general-meson-aiu-Fix-HDMI-codec-control-selection.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-meson-aiu-Fix-HDMI-codec-control-selection.patch rename to patch/kernel/archive/meson64-6.9/general-meson-aiu-Fix-HDMI-codec-control-selection.patch diff --git a/patch/kernel/archive/meson64-6.8/general-meson-mmc-1-arm64-amlogic-mmc-meson-gx-Add-core-tx-rx-eMMC-SD-SD.patch b/patch/kernel/archive/meson64-6.9/general-meson-mmc-1-arm64-amlogic-mmc-meson-gx-Add-core-tx-rx-eMMC-SD-SD.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-meson-mmc-1-arm64-amlogic-mmc-meson-gx-Add-core-tx-rx-eMMC-SD-SD.patch rename to patch/kernel/archive/meson64-6.9/general-meson-mmc-1-arm64-amlogic-mmc-meson-gx-Add-core-tx-rx-eMMC-SD-SD.patch diff --git a/patch/kernel/archive/meson64-6.8/general-meson-mmc-2-arm64-amlogic-dts-meson-update-meson-axg-device-tree.patch b/patch/kernel/archive/meson64-6.9/general-meson-mmc-2-arm64-amlogic-dts-meson-update-meson-axg-device-tree.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-meson-mmc-2-arm64-amlogic-dts-meson-update-meson-axg-device-tree.patch rename to patch/kernel/archive/meson64-6.9/general-meson-mmc-2-arm64-amlogic-dts-meson-update-meson-axg-device-tree.patch diff --git a/patch/kernel/archive/meson64-6.8/general-meson-mmc-3-arm64-dts-docs-Update-mmc-meson-gx-documentation-for.patch b/patch/kernel/archive/meson64-6.9/general-meson-mmc-3-arm64-dts-docs-Update-mmc-meson-gx-documentation-for.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-meson-mmc-3-arm64-dts-docs-Update-mmc-meson-gx-documentation-for.patch rename to patch/kernel/archive/meson64-6.9/general-meson-mmc-3-arm64-dts-docs-Update-mmc-meson-gx-documentation-for.patch diff --git a/patch/kernel/archive/meson64-6.8/general-meson-vdec-add-HEVC-decode-codec.patch b/patch/kernel/archive/meson64-6.9/general-meson-vdec-add-HEVC-decode-codec.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-meson-vdec-add-HEVC-decode-codec.patch rename to patch/kernel/archive/meson64-6.9/general-meson-vdec-add-HEVC-decode-codec.patch diff --git a/patch/kernel/archive/meson64-6.8/general-meson-vdec-add-handling-to-HEVC-decoder-.patch b/patch/kernel/archive/meson64-6.9/general-meson-vdec-add-handling-to-HEVC-decoder-.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-meson-vdec-add-handling-to-HEVC-decoder-.patch rename to patch/kernel/archive/meson64-6.9/general-meson-vdec-add-handling-to-HEVC-decoder-.patch diff --git a/patch/kernel/archive/meson64-6.8/general-meson-vdec-check-if-parser-has-really-parser.patch b/patch/kernel/archive/meson64-6.9/general-meson-vdec-check-if-parser-has-really-parser.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-meson-vdec-check-if-parser-has-really-parser.patch rename to patch/kernel/archive/meson64-6.9/general-meson-vdec-check-if-parser-has-really-parser.patch diff --git a/patch/kernel/archive/meson64-6.8/general-meson-vdec-improve-mmu-and-fbc-handling-.patch b/patch/kernel/archive/meson64-6.9/general-meson-vdec-improve-mmu-and-fbc-handling-.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-meson-vdec-improve-mmu-and-fbc-handling-.patch rename to patch/kernel/archive/meson64-6.9/general-meson-vdec-improve-mmu-and-fbc-handling-.patch diff --git a/patch/kernel/archive/meson64-6.8/general-meson64-overlays.patch b/patch/kernel/archive/meson64-6.9/general-meson64-overlays.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-meson64-overlays.patch rename to patch/kernel/archive/meson64-6.9/general-meson64-overlays.patch diff --git a/patch/kernel/archive/meson64-6.8/general-si2168-fix-cmd-timeout.patch b/patch/kernel/archive/meson64-6.9/general-si2168-fix-cmd-timeout.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-si2168-fix-cmd-timeout.patch rename to patch/kernel/archive/meson64-6.9/general-si2168-fix-cmd-timeout.patch diff --git a/patch/kernel/archive/meson64-6.9/general-socinfo-sm-1-soc-amlogic-meson-gx-socinfo-Add-S905L-ID.patch b/patch/kernel/archive/meson64-6.9/general-socinfo-sm-1-soc-amlogic-meson-gx-socinfo-Add-S905L-ID.patch new file mode 100644 index 000000000000..e804e22b80d6 --- /dev/null +++ b/patch/kernel/archive/meson64-6.9/general-socinfo-sm-1-soc-amlogic-meson-gx-socinfo-Add-S905L-ID.patch @@ -0,0 +1,30 @@ +From 0120fd45f5c58571ab609497e6f968f7251d8d45 Mon Sep 17 00:00:00 2001 +From: Christian Hewitt +Date: Tue, 4 Jun 2024 05:07:52 +0000 +Subject: [PATCH 1/6] soc: amlogic: meson-gx-socinfo: Add S905L ID + +Add the S905L SoC ID observed in several P271 boards: + +kernel: soc soc0: Amlogic Meson GXLX (S905L) Revision 26:a (c1:2) Detected + +Signed-off-by: Christian Hewitt +Reviewed-by: Neil Armstrong +--- + drivers/soc/amlogic/meson-gx-socinfo.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c +index 6abb730344ab..7e255acf5430 100644 +--- a/drivers/soc/amlogic/meson-gx-socinfo.c ++++ b/drivers/soc/amlogic/meson-gx-socinfo.c +@@ -64,6 +64,7 @@ static const struct meson_gx_package_id { + { "962E", 0x24, 0x20, 0xf0 }, + { "A113X", 0x25, 0x37, 0xff }, + { "A113D", 0x25, 0x22, 0xff }, ++ { "S905L", 0x26, 0, 0x0 }, + { "S905D2", 0x28, 0x10, 0xf0 }, + { "S905Y2", 0x28, 0x30, 0xf0 }, + { "S905X2", 0x28, 0x40, 0xf0 }, +-- +2.45.2 + diff --git a/patch/kernel/archive/meson64-6.9/general-socinfo-sm-2-soc-amlogic-meson-gx-socinfo-add-new-A113X-SoC-id.patch b/patch/kernel/archive/meson64-6.9/general-socinfo-sm-2-soc-amlogic-meson-gx-socinfo-add-new-A113X-SoC-id.patch new file mode 100644 index 000000000000..224dac3e3e8d --- /dev/null +++ b/patch/kernel/archive/meson64-6.9/general-socinfo-sm-2-soc-amlogic-meson-gx-socinfo-add-new-A113X-SoC-id.patch @@ -0,0 +1,29 @@ +From 90b6ee09d8c950ec5ec1062ccafe7815bb033199 Mon Sep 17 00:00:00 2001 +From: Viacheslav Bocharov +Date: Tue, 4 Jun 2024 17:04:51 +0300 +Subject: [PATCH 2/6] soc: amlogic: meson-gx-socinfo: add new A113X SoC id + +Add new definition for Amlogix A113X SoC found in JetHub D1/D1+ devices: + +soc soc0: Amlogic Meson AXG (A113X) Revision 25:b (43:2) Detected + +Signed-off-by: Viacheslav Bocharov +--- + drivers/soc/amlogic/meson-gx-socinfo.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c +index 7e255acf5430..8809a948201a 100644 +--- a/drivers/soc/amlogic/meson-gx-socinfo.c ++++ b/drivers/soc/amlogic/meson-gx-socinfo.c +@@ -63,6 +63,7 @@ static const struct meson_gx_package_id { + { "962X", 0x24, 0x10, 0xf0 }, + { "962E", 0x24, 0x20, 0xf0 }, + { "A113X", 0x25, 0x37, 0xff }, ++ { "A113X", 0x25, 0x43, 0xff }, + { "A113D", 0x25, 0x22, 0xff }, + { "S905L", 0x26, 0, 0x0 }, + { "S905D2", 0x28, 0x10, 0xf0 }, +-- +2.45.2 + diff --git a/patch/kernel/archive/meson64-6.8/general-socinfo-sm-1-soc-amlogic-meson-gx-socinfo-move-common-code-to-hea.patch b/patch/kernel/archive/meson64-6.9/general-socinfo-sm-3-soc-amlogic-meson-gx-socinfo-move-common-code-to-hea.patch similarity index 87% rename from patch/kernel/archive/meson64-6.8/general-socinfo-sm-1-soc-amlogic-meson-gx-socinfo-move-common-code-to-hea.patch rename to patch/kernel/archive/meson64-6.9/general-socinfo-sm-3-soc-amlogic-meson-gx-socinfo-move-common-code-to-hea.patch index 05e0cfc14264..90ad1e305fcc 100644 --- a/patch/kernel/archive/meson64-6.8/general-socinfo-sm-1-soc-amlogic-meson-gx-socinfo-move-common-code-to-hea.patch +++ b/patch/kernel/archive/meson64-6.9/general-socinfo-sm-3-soc-amlogic-meson-gx-socinfo-move-common-code-to-hea.patch @@ -1,23 +1,25 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From c4d792a1bc40b7265b2cbf23b5f5605e42e21928 Mon Sep 17 00:00:00 2001 From: Viacheslav Bocharov -Date: Wed, 21 Feb 2024 16:35:01 +0300 -Subject: soc: amlogic: meson-gx-socinfo: move common code to header file +Date: Tue, 4 Jun 2024 17:18:08 +0300 +Subject: [PATCH 3/6] soc: amlogic: meson-gx-socinfo: move common code to + header file Move common constants and inline functions from meson-gx-socinfo driver to header file. Create new structures for store meson64 cpu_id and chip_id. Signed-off-by: Viacheslav Bocharov --- - drivers/soc/amlogic/meson-gx-socinfo-internal.h | 120 ++++++++ - drivers/soc/amlogic/meson-gx-socinfo.c | 136 +--------- - 2 files changed, 134 insertions(+), 122 deletions(-) + .../soc/amlogic/meson-gx-socinfo-internal.h | 122 +++++++++++++++ + drivers/soc/amlogic/meson-gx-socinfo.c | 140 ++---------------- + 2 files changed, 137 insertions(+), 125 deletions(-) + create mode 100644 drivers/soc/amlogic/meson-gx-socinfo-internal.h diff --git a/drivers/soc/amlogic/meson-gx-socinfo-internal.h b/drivers/soc/amlogic/meson-gx-socinfo-internal.h new file mode 100644 -index 000000000000..3ebb80972fc7 +index 000000000000..42cd57e67390 --- /dev/null +++ b/drivers/soc/amlogic/meson-gx-socinfo-internal.h -@@ -0,0 +1,120 @@ +@@ -0,0 +1,122 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2017 BayLibre, SAS @@ -98,7 +100,9 @@ index 000000000000..3ebb80972fc7 + { "962X", 0x24, 0x10, 0xf0 }, + { "962E", 0x24, 0x20, 0xf0 }, + { "A113X", 0x25, 0x37, 0xff }, ++ { "A113X", 0x25, 0x43, 0xff }, + { "A113D", 0x25, 0x22, 0xff }, ++ { "S905L", 0x26, 0, 0x0 }, + { "S905D2", 0x28, 0x10, 0xf0 }, + { "S905Y2", 0x28, 0x30, 0xf0 }, + { "S905X2", 0x28, 0x40, 0xf0 }, @@ -139,10 +143,20 @@ index 000000000000..3ebb80972fc7 + +#endif /* _MESON_GX_SOCINFO_INTERNAL_H_ */ diff --git a/drivers/soc/amlogic/meson-gx-socinfo.c b/drivers/soc/amlogic/meson-gx-socinfo.c -index 6abb730344ab..006f3b09940d 100644 +index 8809a948201a..ca7b82c07083 100644 --- a/drivers/soc/amlogic/meson-gx-socinfo.c +++ b/drivers/soc/amlogic/meson-gx-socinfo.c -@@ -12,118 +12,10 @@ +@@ -1,8 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0+ + /* + * Copyright (c) 2017 BayLibre, SAS + * Author: Neil Armstrong + * +- * SPDX-License-Identifier: GPL-2.0+ + */ + + #include +@@ -12,120 +12,10 @@ #include #include #include @@ -197,7 +211,9 @@ index 6abb730344ab..006f3b09940d 100644 - { "962X", 0x24, 0x10, 0xf0 }, - { "962E", 0x24, 0x20, 0xf0 }, - { "A113X", 0x25, 0x37, 0xff }, +- { "A113X", 0x25, 0x43, 0xff }, - { "A113D", 0x25, 0x22, 0xff }, +- { "S905L", 0x26, 0, 0x0 }, - { "S905D2", 0x28, 0x10, 0xf0 }, - { "S905Y2", 0x28, 0x30, 0xf0 }, - { "S905X2", 0x28, 0x40, 0xf0 }, @@ -262,7 +278,7 @@ index 6abb730344ab..006f3b09940d 100644 static int __init meson_gx_socinfo_init(void) { -@@ -131,7 +23,7 @@ static int __init meson_gx_socinfo_init(void) +@@ -133,7 +23,7 @@ static int __init meson_gx_socinfo_init(void) struct soc_device *soc_dev; struct device_node *np; struct regmap *regmap; @@ -271,7 +287,7 @@ index 6abb730344ab..006f3b09940d 100644 struct device *dev; int ret; -@@ -160,11 +52,11 @@ static int __init meson_gx_socinfo_init(void) +@@ -162,11 +52,11 @@ static int __init meson_gx_socinfo_init(void) return -ENODEV; } @@ -285,7 +301,7 @@ index 6abb730344ab..006f3b09940d 100644 pr_err("%s: invalid chipid value\n", __func__); return -EINVAL; } -@@ -175,13 +67,13 @@ static int __init meson_gx_socinfo_init(void) +@@ -177,13 +67,13 @@ static int __init meson_gx_socinfo_init(void) soc_dev_attr->family = "Amlogic Meson"; soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%x:%x - %x:%x", @@ -305,7 +321,7 @@ index 6abb730344ab..006f3b09940d 100644 soc_dev = soc_device_register(soc_dev_attr); if (IS_ERR(soc_dev)) { -@@ -194,10 +86,10 @@ static int __init meson_gx_socinfo_init(void) +@@ -196,10 +86,10 @@ static int __init meson_gx_socinfo_init(void) dev_info(dev, "Amlogic Meson %s Revision %x:%x (%x:%x) Detected\n", soc_dev_attr->soc_id, @@ -321,5 +337,5 @@ index 6abb730344ab..006f3b09940d 100644 return 0; } -- -Armbian +2.45.2 diff --git a/patch/kernel/archive/meson64-6.8/general-socinfo-sm-2-soc-amlogic-meson-gx-socinfo-sm-Add-Amlogic-secure-m.patch b/patch/kernel/archive/meson64-6.9/general-socinfo-sm-4-soc-amlogic-meson-gx-socinfo-sm-Add-Amlogic-secure-m.patch similarity index 69% rename from patch/kernel/archive/meson64-6.8/general-socinfo-sm-2-soc-amlogic-meson-gx-socinfo-sm-Add-Amlogic-secure-m.patch rename to patch/kernel/archive/meson64-6.9/general-socinfo-sm-4-soc-amlogic-meson-gx-socinfo-sm-Add-Amlogic-secure-m.patch index 1660e9cfff47..c0e382f9d655 100644 --- a/patch/kernel/archive/meson64-6.8/general-socinfo-sm-2-soc-amlogic-meson-gx-socinfo-sm-Add-Amlogic-secure-m.patch +++ b/patch/kernel/archive/meson64-6.9/general-socinfo-sm-4-soc-amlogic-meson-gx-socinfo-sm-Add-Amlogic-secure-m.patch @@ -1,8 +1,8 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From 4fc80646e728133378fb44abe1bffa72655104c6 Mon Sep 17 00:00:00 2001 From: Viacheslav Bocharov Date: Wed, 21 Feb 2024 16:41:30 +0300 -Subject: soc: amlogic: meson-gx-socinfo-sm: Add Amlogic secure-monitor SoC - Information driver +Subject: [PATCH 4/6] soc: amlogic: meson-gx-socinfo-sm: Add Amlogic + secure-monitor SoC Information driver Amlogic SoCs have a SoC information secure-monitor call for SoC type, package type, revision information and chipid. @@ -12,10 +12,12 @@ Information driver. Signed-off-by: Viacheslav Bocharov --- - drivers/soc/amlogic/Kconfig | 10 + - drivers/soc/amlogic/Makefile | 1 + - drivers/soc/amlogic/meson-gx-socinfo-sm.c | 192 ++++++++++ - 3 files changed, 203 insertions(+) + drivers/soc/amlogic/Kconfig | 10 + + drivers/soc/amlogic/Makefile | 1 + + .../soc/amlogic/meson-gx-socinfo-internal.h | 14 +- + drivers/soc/amlogic/meson-gx-socinfo-sm.c | 190 ++++++++++++++++++ + 4 files changed, 211 insertions(+), 4 deletions(-) + create mode 100644 drivers/soc/amlogic/meson-gx-socinfo-sm.c diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig index d08e398bdad4..82fc77ca3b4b 100644 @@ -48,12 +50,37 @@ index c25f835e6a26..45d9d6f5904c 100644 obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o +obj-$(CONFIG_MESON_GX_SOCINFO_SM) += meson-gx-socinfo-sm.o obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o +diff --git a/drivers/soc/amlogic/meson-gx-socinfo-internal.h b/drivers/soc/amlogic/meson-gx-socinfo-internal.h +index 42cd57e67390..f032f4c9cc83 100644 +--- a/drivers/soc/amlogic/meson-gx-socinfo-internal.h ++++ b/drivers/soc/amlogic/meson-gx-socinfo-internal.h +@@ -33,10 +33,16 @@ union meson_cpu_id { + u32 raw; + }; + +-struct meson_sm_chip_id { +- u32 version; +- union meson_cpu_id cpu_id; +- u8 serial[12]; ++union meson_sm_chip_id { ++ struct { // cpu_id v2 ++ u32 version; ++ union meson_cpu_id cpu_id; ++ u8 serial[12]; ++ } v2; ++ struct { // raw ++ u32 version; ++ u8 buf[12+sizeof(union meson_cpu_id)]; ++ } raw; + }; + + static const struct meson_gx_soc_id { diff --git a/drivers/soc/amlogic/meson-gx-socinfo-sm.c b/drivers/soc/amlogic/meson-gx-socinfo-sm.c new file mode 100644 -index 000000000000..e30e1d2feb61 +index 000000000000..e12f45cd8de2 --- /dev/null +++ b/drivers/soc/amlogic/meson-gx-socinfo-sm.c -@@ -0,0 +1,192 @@ +@@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2017 BayLibre, SAS @@ -81,51 +108,52 @@ index 000000000000..e30e1d2feb61 + union meson_cpu_id *socinfo) +{ + char *buf; -+ struct meson_sm_chip_id *id_buf; ++ union meson_sm_chip_id *id_buf; + int ret; + -+ id_buf = devm_kzalloc(dev, sizeof(struct meson_sm_chip_id)+1, GFP_KERNEL); ++ id_buf = kzalloc(sizeof(union meson_sm_chip_id)+1, GFP_KERNEL); + if (!id_buf) + return NULL; + -+ ret = meson_sm_call_read(fw, id_buf, sizeof(struct meson_sm_chip_id), SM_GET_CHIP_ID, ++ ret = meson_sm_call_read(fw, id_buf, sizeof(union meson_sm_chip_id), SM_GET_CHIP_ID, + 2, 0, 0, 0, 0); + if (ret < 0) { + kfree(id_buf); + return NULL; + } -+ dev_info(dev, "got sm version call %i\n", id_buf->version); ++ dev_info(dev, "got sm version call %i\n", id_buf->raw.version); + -+ if (id_buf->version != 2) { ++ if (id_buf->raw.version != 2) { + + u8 tmp; + /** + * Legacy 12-byte chip ID read out, transform data + * to expected order format + */ -+ memmove((void *)&id_buf->serial, (void *)&id_buf->cpu_id, 12); ++ memmove((void *)&id_buf->v2.serial, (void *)&id_buf->raw.buf, 12); + for (int i = 0; i < 6; i++) { -+ tmp = id_buf->serial[i]; -+ id_buf->serial[i] = id_buf->serial[11 - i]; -+ id_buf->serial[11 - i] = tmp; ++ tmp = id_buf->v2.serial[i]; ++ id_buf->v2.serial[i] = id_buf->v2.serial[11 - i]; ++ id_buf->v2.serial[11 - i] = tmp; + } -+ id_buf->cpu_id.v2.major_id = socinfo->v1.major_id; -+ id_buf->cpu_id.v2.pack_id = socinfo->v1.pack_id; -+ id_buf->cpu_id.v2.chip_rev = socinfo->v1.chip_rev; -+ id_buf->cpu_id.v2.reserved = socinfo->v1.reserved; -+ id_buf->cpu_id.v2.layout_ver = socinfo->v1.layout_ver; ++ id_buf->v2.cpu_id.v2.major_id = socinfo->v1.major_id; ++ id_buf->v2.cpu_id.v2.pack_id = socinfo->v1.pack_id; ++ id_buf->v2.cpu_id.v2.chip_rev = socinfo->v1.chip_rev; ++ id_buf->v2.cpu_id.v2.reserved = socinfo->v1.reserved; ++ id_buf->v2.cpu_id.v2.layout_ver = socinfo->v1.layout_ver; + } else { + /** + * rewrite socinfo from regmap with value from secure monitor call + */ -+ socinfo->v1.major_id = id_buf->cpu_id.v2.major_id; -+ socinfo->v1.pack_id = id_buf->cpu_id.v2.pack_id; -+ socinfo->v1.chip_rev = id_buf->cpu_id.v2.chip_rev; -+ socinfo->v1.reserved = id_buf->cpu_id.v2.reserved; -+ socinfo->v1.layout_ver = id_buf->cpu_id.v2.layout_ver; ++ socinfo->v1.major_id = id_buf->v2.cpu_id.v2.major_id; ++ socinfo->v1.pack_id = id_buf->v2.cpu_id.v2.pack_id; ++ socinfo->v1.chip_rev = id_buf->v2.cpu_id.v2.chip_rev; ++ socinfo->v1.reserved = id_buf->v2.cpu_id.v2.reserved; ++ socinfo->v1.layout_ver = id_buf->v2.cpu_id.v2.layout_ver; + } + -+ buf = kasprintf(GFP_KERNEL, "%4phN%12phN", &(id_buf->cpu_id), &(id_buf->serial)); ++ buf = devm_kasprintf(dev, GFP_KERNEL, "%4phN%12phN", &(id_buf->v2.cpu_id), ++ &(id_buf->v2.serial)); + + kfree(id_buf); + @@ -149,21 +177,19 @@ index 000000000000..e30e1d2feb61 + + /* node should be a syscon */ + regmap = syscon_node_to_regmap(pdev->dev.of_node); -+ if (IS_ERR(regmap)) { -+ dev_err(&pdev->dev, "failed to get regmap\n"); -+ return -ENODEV; -+ } ++ if (IS_ERR(regmap)) ++ return dev_err_probe(&pdev->dev, PTR_ERR(regmap), "failed to get regmap\n"); + + sm_np = of_parse_phandle(pdev->dev.of_node, "secure-monitor", 0); + if (!sm_np) { + dev_err(&pdev->dev, "no secure-monitor node found\n"); -+ return -ENODEV; ++ return -EINVAL; + } + + fw = meson_sm_get(sm_np); + of_node_put(sm_np); + if (!fw) { -+ dev_info(&pdev->dev, "secure-monitor device not ready, probe later\n"); ++ dev_dbg(&pdev->dev, "secure-monitor device not ready, probe later\n"); + return -EPROBE_DEFER; + } + @@ -199,7 +225,6 @@ index 000000000000..e30e1d2feb61 + if (IS_ERR(soc_dev)) { + kfree(soc_dev_attr->revision); + kfree_const(soc_dev_attr->soc_id); -+ kfree(soc_dev_attr); + return PTR_ERR(soc_dev); + } + @@ -247,5 +272,5 @@ index 000000000000..e30e1d2feb61 +MODULE_DESCRIPTION("Amlogic Meson GX SOC SM driver"); +MODULE_LICENSE("GPL"); -- -Armbian +2.45.2 diff --git a/patch/kernel/archive/meson64-6.8/general-socinfo-sm-4-arm64-dts-meson-add-dts-links-to-secure-monitor-for-.patch b/patch/kernel/archive/meson64-6.9/general-socinfo-sm-5-arm64-dts-meson-add-dts-links-to-secure-monitor-for-.patch similarity index 84% rename from patch/kernel/archive/meson64-6.8/general-socinfo-sm-4-arm64-dts-meson-add-dts-links-to-secure-monitor-for-.patch rename to patch/kernel/archive/meson64-6.9/general-socinfo-sm-5-arm64-dts-meson-add-dts-links-to-secure-monitor-for-.patch index d5c1580520f8..f91d89f3653f 100644 --- a/patch/kernel/archive/meson64-6.8/general-socinfo-sm-4-arm64-dts-meson-add-dts-links-to-secure-monitor-for-.patch +++ b/patch/kernel/archive/meson64-6.9/general-socinfo-sm-5-arm64-dts-meson-add-dts-links-to-secure-monitor-for-.patch @@ -1,8 +1,8 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From ee45df40ba6acbecf5ea4b976ec72688fbb1dd19 Mon Sep 17 00:00:00 2001 From: Viacheslav Bocharov -Date: Thu, 22 Feb 2024 12:00:32 +0300 -Subject: arm64: dts: meson: add dts links to secure-monitor for soc driver in - a1, axg, gx, g12 +Date: Thu, 14 Mar 2024 09:59:54 +0300 +Subject: [PATCH 5/6] arm64: dts: meson: add dts links to secure-monitor for + soc driver in a1, axg, gx, g12 Add links to secure-monitor in soc driver section for A1, AXG, GX, G12 Amlogic family for use with meson-socinfo-sm driver. @@ -16,7 +16,7 @@ Signed-off-by: Viacheslav Bocharov 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi -index 648e7f49424f..449b328d62b1 100644 +index c03e207ea6c5..d47f056117fc 100644 --- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi @@ -407,6 +407,7 @@ hwrng: rng@5118 { @@ -28,10 +28,10 @@ index 648e7f49424f..449b328d62b1 100644 }; diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi -index 1d5e10a6f617..97c9b2770a74 100644 +index 6d12b760b90f..45791ec6694a 100644 --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi -@@ -1682,6 +1682,7 @@ mux { +@@ -1689,6 +1689,7 @@ mux { sec_AO: ao-secure@140 { compatible = "amlogic,meson-gx-ao-secure", "syscon"; reg = <0x0 0x140 0x0 0x140>; @@ -40,10 +40,10 @@ index 1d5e10a6f617..97c9b2770a74 100644 }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi -index abc0483ff3b4..a33deaee557e 100644 +index 9d5eab6595d0..a8c1c72543b7 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi -@@ -2035,6 +2035,7 @@ cec_AO: cec@100 { +@@ -2026,6 +2026,7 @@ cec_AO: cec@100 { sec_AO: ao-secure@140 { compatible = "amlogic,meson-gx-ao-secure", "syscon"; reg = <0x0 0x140 0x0 0x140>; @@ -64,5 +64,5 @@ index 2673f0dbafe7..656e08b3d872 100644 }; -- -Armbian +2.45.2 diff --git a/patch/kernel/archive/meson64-6.9/general-socinfo-sm-6-dt-bindings-arm-amlogic-amlogic-meson-gx-ao-secure-a.patch b/patch/kernel/archive/meson64-6.9/general-socinfo-sm-6-dt-bindings-arm-amlogic-amlogic-meson-gx-ao-secure-a.patch new file mode 100644 index 000000000000..5ae5c82bb1c0 --- /dev/null +++ b/patch/kernel/archive/meson64-6.9/general-socinfo-sm-6-dt-bindings-arm-amlogic-amlogic-meson-gx-ao-secure-a.patch @@ -0,0 +1,31 @@ +From 562c95035406acfee1f6c941dc4017a4e5b305f6 Mon Sep 17 00:00:00 2001 +From: Viacheslav Bocharov +Date: Tue, 4 Jun 2024 17:54:53 +0300 +Subject: [PATCH 6/6] dt-bindings: arm: amlogic: amlogic,meson-gx-ao-secure: + add secure-monitor property + +Add secure-monitor property to schema for meson-gx-socinfo-sm driver. + +Signed-off-by: Viacheslav Bocharov +--- + .../bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml | 4 ++++ + 1 file changed, 4 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml +index 7dff32f373cb..1128a794ec89 100644 +--- a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml ++++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml +@@ -32,6 +32,10 @@ properties: + reg: + maxItems: 1 + ++ secure-monitor: ++ description: phandle to the secure-monitor node ++ $ref: /schemas/types.yaml#/definitions/phandle ++ + amlogic,has-chip-id: + description: | + A firmware register encodes the SoC type, package and revision +-- +2.45.2 + diff --git a/patch/kernel/archive/meson64-6.8/general-sound-soc-remove-mono-channel-as-it-curren.patch b/patch/kernel/archive/meson64-6.9/general-sound-soc-remove-mono-channel-as-it-curren.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-sound-soc-remove-mono-channel-as-it-curren.patch rename to patch/kernel/archive/meson64-6.9/general-sound-soc-remove-mono-channel-as-it-curren.patch diff --git a/patch/kernel/archive/meson64-6.8/general-spi-nor-add-support-for-XT25F128B.patch b/patch/kernel/archive/meson64-6.9/general-spi-nor-add-support-for-XT25F128B.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-spi-nor-add-support-for-XT25F128B.patch rename to patch/kernel/archive/meson64-6.9/general-spi-nor-add-support-for-XT25F128B.patch diff --git a/patch/kernel/archive/meson64-6.8/general-usb-core-improve-handling-of-hubs-with-no-ports.patch b/patch/kernel/archive/meson64-6.9/general-usb-core-improve-handling-of-hubs-with-no-ports.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/general-usb-core-improve-handling-of-hubs-with-no-ports.patch rename to patch/kernel/archive/meson64-6.9/general-usb-core-improve-handling-of-hubs-with-no-ports.patch diff --git a/patch/kernel/archive/meson64-6.8/hwmon-emc2305-fixups-for-driver.patch b/patch/kernel/archive/meson64-6.9/hwmon-emc2305-fixups-for-driver.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/hwmon-emc2305-fixups-for-driver.patch rename to patch/kernel/archive/meson64-6.9/hwmon-emc2305-fixups-for-driver.patch diff --git a/patch/kernel/archive/meson64-6.8/jethome-0001-Fix-meson64-add-gpio-irq-patch-from-https-lkml.org-l.patch b/patch/kernel/archive/meson64-6.9/jethome-0001-Fix-meson64-add-gpio-irq-patch-from-https-lkml.org-l.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/jethome-0001-Fix-meson64-add-gpio-irq-patch-from-https-lkml.org-l.patch rename to patch/kernel/archive/meson64-6.9/jethome-0001-Fix-meson64-add-gpio-irq-patch-from-https-lkml.org-l.patch diff --git a/patch/kernel/archive/meson64-6.8/jethome-0002-arm64-dts-jethub-j1xx-add-eeprom-node.patch b/patch/kernel/archive/meson64-6.9/jethome-0002-arm64-dts-jethub-j1xx-add-eeprom-node.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/jethome-0002-arm64-dts-jethub-j1xx-add-eeprom-node.patch rename to patch/kernel/archive/meson64-6.9/jethome-0002-arm64-dts-jethub-j1xx-add-eeprom-node.patch diff --git a/patch/kernel/archive/meson64-6.8/jethome-0003-arm64-dts-meson-add-dts-links-to-secure-monitor-for-jethub.patch.disabled b/patch/kernel/archive/meson64-6.9/jethome-0003-arm64-dts-meson-add-dts-links-to-secure-monitor-for-jethub.patch.disabled similarity index 100% rename from patch/kernel/archive/meson64-6.8/jethome-0003-arm64-dts-meson-add-dts-links-to-secure-monitor-for-jethub.patch.disabled rename to patch/kernel/archive/meson64-6.9/jethome-0003-arm64-dts-meson-add-dts-links-to-secure-monitor-for-jethub.patch.disabled diff --git a/patch/kernel/archive/meson64-6.8/kernel-6.8-tools-cgroup-makefile.patch b/patch/kernel/archive/meson64-6.9/kernel-6.8-tools-cgroup-makefile.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/kernel-6.8-tools-cgroup-makefile.patch rename to patch/kernel/archive/meson64-6.9/kernel-6.8-tools-cgroup-makefile.patch diff --git a/patch/kernel/archive/meson64-6.8/meson-g12a-pinctrl-add-missing-ir-options.patch b/patch/kernel/archive/meson64-6.9/meson-g12a-pinctrl-add-missing-ir-options.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/meson-g12a-pinctrl-add-missing-ir-options.patch rename to patch/kernel/archive/meson64-6.9/meson-g12a-pinctrl-add-missing-ir-options.patch diff --git a/patch/kernel/archive/meson64-6.8/meson-g12b-pinctrl-Add-missing-pinmux-for-pwm.patch b/patch/kernel/archive/meson64-6.9/meson-g12b-pinctrl-Add-missing-pinmux-for-pwm.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/meson-g12b-pinctrl-Add-missing-pinmux-for-pwm.patch rename to patch/kernel/archive/meson64-6.9/meson-g12b-pinctrl-Add-missing-pinmux-for-pwm.patch diff --git a/patch/kernel/archive/meson64-6.8/meson-gx-dts-add-support-for-GX-PM-and-VRTC.patch b/patch/kernel/archive/meson64-6.9/meson-gx-dts-add-support-for-GX-PM-and-VRTC.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/meson-gx-dts-add-support-for-GX-PM-and-VRTC.patch rename to patch/kernel/archive/meson64-6.9/meson-gx-dts-add-support-for-GX-PM-and-VRTC.patch diff --git a/patch/kernel/archive/meson64-6.8/meson-gxbb-dts-i2cX-missing-pins.patch b/patch/kernel/archive/meson64-6.9/meson-gxbb-dts-i2cX-missing-pins.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/meson-gxbb-dts-i2cX-missing-pins.patch rename to patch/kernel/archive/meson64-6.9/meson-gxbb-dts-i2cX-missing-pins.patch diff --git a/patch/kernel/archive/meson64-6.8/meson-gxbb-vdec-add-HEVC-support-to-GXBB.patch b/patch/kernel/archive/meson64-6.9/meson-gxbb-vdec-add-HEVC-support-to-GXBB.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/meson-gxbb-vdec-add-HEVC-support-to-GXBB.patch rename to patch/kernel/archive/meson64-6.9/meson-gxbb-vdec-add-HEVC-support-to-GXBB.patch diff --git a/patch/kernel/archive/meson64-6.8/meson-gxl-gxm-arm64-dts-meson-set-p212-p23x-q20x-SDIO-to-100MH.patch b/patch/kernel/archive/meson64-6.9/meson-gxl-gxm-arm64-dts-meson-set-p212-p23x-q20x-SDIO-to-100MH.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/meson-gxl-gxm-arm64-dts-meson-set-p212-p23x-q20x-SDIO-to-100MH.patch rename to patch/kernel/archive/meson64-6.9/meson-gxl-gxm-arm64-dts-meson-set-p212-p23x-q20x-SDIO-to-100MH.patch diff --git a/patch/kernel/archive/meson64-6.8/meson-gxm-vdec-add-VP9-support-to-GXM.patch b/patch/kernel/archive/meson64-6.9/meson-gxm-vdec-add-VP9-support-to-GXM.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/meson-gxm-vdec-add-VP9-support-to-GXM.patch rename to patch/kernel/archive/meson64-6.9/meson-gxm-vdec-add-VP9-support-to-GXM.patch diff --git a/patch/kernel/archive/meson64-6.8/meson-sm1-dts-add-higher-clocks.patch b/patch/kernel/archive/meson64-6.9/meson-sm1-dts-add-higher-clocks.patch similarity index 100% rename from patch/kernel/archive/meson64-6.8/meson-sm1-dts-add-higher-clocks.patch rename to patch/kernel/archive/meson64-6.9/meson-sm1-dts-add-higher-clocks.patch diff --git a/patch/kernel/archive/meson64-6.8/overlay/Makefile b/patch/kernel/archive/meson64-6.9/overlay/Makefile similarity index 93% rename from patch/kernel/archive/meson64-6.8/overlay/Makefile rename to patch/kernel/archive/meson64-6.9/overlay/Makefile index a15a46f73ffe..a725d266fcd0 100644 --- a/patch/kernel/archive/meson64-6.8/overlay/Makefile +++ b/patch/kernel/archive/meson64-6.9/overlay/Makefile @@ -36,7 +36,6 @@ scr-$(CONFIG_ARCH_MESON) += \ dtbotxt-$(CONFIG_ARCH_MESON) += \ README.meson-overlays -targets += $(dtbo-y) $(scr-y) $(dtbotxt-y) +dtb-y += $(dtbo-y) $(scr-y) $(dtbotxt-y) -always := $(dtbo-y) $(scr-y) $(dtbotxt-y) clean-files := *.dtbo *.scr diff --git a/patch/kernel/archive/meson64-6.8/overlay/README.meson-overlays b/patch/kernel/archive/meson64-6.9/overlay/README.meson-overlays similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/README.meson-overlays rename to patch/kernel/archive/meson64-6.9/overlay/README.meson-overlays diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-fixup.scr-cmd b/patch/kernel/archive/meson64-6.9/overlay/meson-fixup.scr-cmd similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-fixup.scr-cmd rename to patch/kernel/archive/meson64-6.9/overlay/meson-fixup.scr-cmd diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12-gxl-cma-pool-896MB.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12-gxl-cma-pool-896MB.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12-gxl-cma-pool-896MB.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12-gxl-cma-pool-896MB.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12-pwm-gpiox-5-fan.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12-pwm-gpiox-5-fan.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12-pwm-gpiox-5-fan.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12-pwm-gpiox-5-fan.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-gpio-10-led.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-gpio-10-led.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-gpio-10-led.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-gpio-10-led.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-gpio-8-led.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-gpio-8-led.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-gpio-8-led.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-gpio-8-led.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-i2c-ao-m0-gpioao-2-gpioao-3.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-i2c-ao-m0-gpioao-2-gpioao-3.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-i2c-ao-m0-gpioao-2-gpioao-3.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-i2c-ao-m0-gpioao-2-gpioao-3.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-i2c-ee-m1-gpioh-6-gpioh-7.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-i2c-ee-m1-gpioh-6-gpioh-7.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-i2c-ee-m1-gpioh-6-gpioh-7.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-i2c-ee-m1-gpioh-6-gpioh-7.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-i2c-ee-m1-gpiox-10-gpiox-11.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-i2c-ee-m1-gpiox-10-gpiox-11.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-i2c-ee-m1-gpiox-10-gpiox-11.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-i2c-ee-m1-gpiox-10-gpiox-11.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-i2c-ee-m3-gpioa-14-gpioa-15.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-i2c-ee-m3-gpioa-14-gpioa-15.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-i2c-ee-m3-gpioa-14-gpioa-15.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-i2c-ee-m3-gpioa-14-gpioa-15.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-pwm-c-on-gpiox-8.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-pwm-c-on-gpiox-8.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-pwm-c-on-gpiox-8.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-pwm-c-on-gpiox-8.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-pwmao-a-on-gpioao-11.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-pwmao-a-on-gpioao-11.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-pwmao-a-on-gpioao-11.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-pwmao-a-on-gpioao-11.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-spi-spidev.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-spi-spidev.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-spi-spidev.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-spi-spidev.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-uart-ao-a-on-gpioao-0-gpioao-1.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-uart-ao-a-on-gpioao-0-gpioao-1.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-uart-ao-a-on-gpioao-0-gpioao-1.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-uart-ao-a-on-gpioao-0-gpioao-1.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-uart-ao-b-on-gpioao-2-gpioao-3.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-uart-ao-b-on-gpioao-2-gpioao-3.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-uart-ao-b-on-gpioao-2-gpioao-3.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-uart-ao-b-on-gpioao-2-gpioao-3.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-uart-ao-b-on-gpioao-8-gpioao-9.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-uart-ao-b-on-gpioao-8-gpioao-9.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-uart-ao-b-on-gpioao-8-gpioao-9.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-uart-ao-b-on-gpioao-8-gpioao-9.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-uart-ee-c.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-uart-ee-c.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12a-radxa-zero-uart-ee-c.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12a-radxa-zero-uart-ee-c.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12b-bananapi-cm4-pwm-gpioh-5-fan.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12b-bananapi-cm4-pwm-gpioh-5-fan.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12b-bananapi-cm4-pwm-gpioh-5-fan.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12b-bananapi-cm4-pwm-gpioh-5-fan.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12b-bananapi-m2s-rtl8822cs.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12b-bananapi-m2s-rtl8822cs.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12b-bananapi-m2s-rtl8822cs.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12b-bananapi-m2s-rtl8822cs.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12b-odroid-n2-spi.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12b-odroid-n2-spi.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12b-odroid-n2-spi.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12b-odroid-n2-spi.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-g12b-waveshare-cm4-io-base-usb.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-g12b-waveshare-cm4-io-base-usb.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-g12b-waveshare-cm4-io-base-usb.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-g12b-waveshare-cm4-io-base-usb.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-i2cA.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-i2cA.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-i2cA.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-i2cA.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-i2cB.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-i2cB.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-i2cB.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-i2cB.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-sm1-bananapi-m5-rtl8822cs.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-sm1-bananapi-m5-rtl8822cs.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-sm1-bananapi-m5-rtl8822cs.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-sm1-bananapi-m5-rtl8822cs.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-sm1-bananapi-uartA.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-sm1-bananapi-uartA.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-sm1-bananapi-uartA.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-sm1-bananapi-uartA.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-sm1-bananapi-uartAO_B.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-sm1-bananapi-uartAO_B.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-sm1-bananapi-uartAO_B.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-sm1-bananapi-uartAO_B.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-sm1-bananapi-uartA_cts_rts.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-sm1-bananapi-uartA_cts_rts.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-sm1-bananapi-uartA_cts_rts.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-sm1-bananapi-uartA_cts_rts.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-uartA.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-uartA.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-uartA.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-uartA.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-uartC.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-uartC.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-uartC.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-uartC.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-w1-gpio.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-w1-gpio.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-w1-gpio.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-w1-gpio.dtso diff --git a/patch/kernel/archive/meson64-6.8/overlay/meson-w1AB-gpio.dts b/patch/kernel/archive/meson64-6.9/overlay/meson-w1AB-gpio.dtso similarity index 100% rename from patch/kernel/archive/meson64-6.8/overlay/meson-w1AB-gpio.dts rename to patch/kernel/archive/meson64-6.9/overlay/meson-w1AB-gpio.dtso diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/general-add-overlay-compilation-support.patch b/patch/kernel/archive/rockchip-6.8/patches.armbian/general-add-overlay-compilation-support.patch deleted file mode 100644 index f21b1540cb04..000000000000 --- a/patch/kernel/archive/rockchip-6.8/patches.armbian/general-add-overlay-compilation-support.patch +++ /dev/null @@ -1,99 +0,0 @@ -diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore -index 3c79f859..4e5c1d59 100644 ---- a/arch/arm/boot/.gitignore -+++ b/arch/arm/boot/.gitignore -@@ -3,3 +3,5 @@ zImage - xipImage - bootpImage - uImage -+*.dtb* -+*.scr -diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst -index 50d580d77..94bd15617 100644 ---- a/scripts/Makefile.dtbinst -+++ b/scripts/Makefile.dtbinst -@@ -18,9 +18,12 @@ include scripts/Kbuild.include - include $(src)/Makefile - - dtbs := $(addprefix $(dst)/, $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-))) -+dtbos := $(addprefix $(dst)/overlay/, $(dtbo-y)) -+scrs := $(addprefix $(dst)/overlay/, $(scr-y)) -+readmes := $(addprefix $(dst)/overlay/, $(dtbotxt-y)) - subdirs := $(addprefix $(obj)/, $(subdir-y) $(subdir-m)) - --__dtbs_install: $(dtbs) $(subdirs) -+__dtbs_install: $(dtbs) $(dtbos) $(scrs) $(readmes) $(subdirs) - @: - - quiet_cmd_dtb_install = INSTALL $@ -@@ -29,6 +32,18 @@ quiet_cmd_dtb_install = INSTALL $@ - $(dst)/%.dtb: $(obj)/%.dtb - $(call cmd,dtb_install) - -+$(dst)/overlay/%.dtbo: $(obj)/%.dtbo -+ $(call cmd,dtb_install) -+ -+$(dst)/overlay/%.scr: $(obj)/%.scr -+ $(call cmd,dtb_install) -+ -+$(dst)/overlay/README.rockchip-overlays: $(src)/README.rockchip-overlays -+ $(call cmd,dtb_install) -+ -+$(dst)/overlay/README.rk322x-overlays: $(src)/README.rk322x-overlays -+ $(call cmd,dtb_install) -+ - PHONY += $(subdirs) - $(subdirs): - $(Q)$(MAKE) $(dtbinst)=$@ dst=$(patsubst $(obj)/%,$(dst)/%,$@) -diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib -index 58c05e5d..2b95dda9 100644 ---- a/scripts/Makefile.lib -+++ b/scripts/Makefile.lib -@@ -278,6 +278,9 @@ cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -n -f -9 > $@) || \ - # --------------------------------------------------------------------------- - DTC ?= $(objtree)/scripts/dtc/dtc - -+# Overlay support -+DTC_FLAGS += -@ -Wno-unit_address_format -Wno-simple_bus_reg -+ - # Disable noisy checks by default - ifeq ($(KBUILD_ENABLE_EXTRA_GCC_CHECKS),) - DTC_FLAGS += -Wno-unit_address_vs_reg \ -@@ -324,6 +327,23 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ - $(obj)/%.dtb: $(src)/%.dts FORCE - $(call if_changed_dep,dtc) - -+quiet_cmd_dtco = DTCO $@ -+cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \ -+ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ -+ $(DTC) -O dtb -o $@ -b 0 \ -+ -i $(dir $<) $(DTC_FLAGS) \ -+ -d $(depfile).dtc.tmp $(dtc-tmp) ; \ -+ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) -+ -+$(obj)/%.dtbo: $(src)/%.dts FORCE -+ $(call if_changed_dep,dtco) -+ -+quiet_cmd_scr = MKIMAGE $@ -+cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ -+ -+$(obj)/%.scr: $(src)/%.scr-cmd FORCE -+ $(call if_changed,scr) -+ - dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) - - # Bzip2 -diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib -index 41c50f9461e5..387659d5b252 100644 ---- a/scripts/Makefile.lib -+++ b/scripts/Makefile.lib -@@ -79,6 +79,9 @@ header-test-y += $(filter-out $(header-test-), \ - - extra-$(CONFIG_HEADER_TEST) += $(addsuffix .s, $(header-test-y) $(header-test-m)) - -+# Overlay targets -+extra-y += $(dtbo-y) $(scr-y) $(dtbotxt-y) -+ - # Add subdir path - - extra-y := $(addprefix $(obj)/,$(extra-y)) diff --git a/patch/kernel/archive/rockchip-6.8/0000.patching_config.yaml b/patch/kernel/archive/rockchip-6.9/0000.patching_config.yaml similarity index 95% rename from patch/kernel/archive/rockchip-6.8/0000.patching_config.yaml rename to patch/kernel/archive/rockchip-6.9/0000.patching_config.yaml index 30e0c1d6a04a..e7deb39f09ca 100644 --- a/patch/kernel/archive/rockchip-6.8/0000.patching_config.yaml +++ b/patch/kernel/archive/rockchip-6.9/0000.patching_config.yaml @@ -1,10 +1,10 @@ config: # Just some info stuff; not used by the patching scripts - name: rockchip-6.7 + name: rockchip-6.9 kind: kernel type: mainline # or: vendor - branch: linux-6.7.y - last-known-good-tag: v6.7.0 + branch: linux-6.9.y + last-known-good-tag: v6.9.3 maintainers: - { github: paolo.sabatino, name: Paolo Sabatino, email: paolo.sabatino@gmail.com, armbian-forum: jock } diff --git a/patch/kernel/archive/rockchip-6.8/armbian.series b/patch/kernel/archive/rockchip-6.9/armbian.series similarity index 100% rename from patch/kernel/archive/rockchip-6.8/armbian.series rename to patch/kernel/archive/rockchip-6.9/armbian.series diff --git a/patch/kernel/archive/rockchip-6.8/dt/rk322x-box.dts b/patch/kernel/archive/rockchip-6.9/dt/rk322x-box.dts similarity index 100% rename from patch/kernel/archive/rockchip-6.8/dt/rk322x-box.dts rename to patch/kernel/archive/rockchip-6.9/dt/rk322x-box.dts diff --git a/patch/kernel/archive/rockchip-6.8/dt/rk3288-xt-q8l-v10.dts b/patch/kernel/archive/rockchip-6.9/dt/rk3288-xt-q8l-v10.dts similarity index 100% rename from patch/kernel/archive/rockchip-6.8/dt/rk3288-xt-q8l-v10.dts rename to patch/kernel/archive/rockchip-6.9/dt/rk3288-xt-q8l-v10.dts diff --git a/patch/kernel/archive/rockchip-6.8/kernel-6.8-tools-cgroup-makefile.patch b/patch/kernel/archive/rockchip-6.9/kernel-6.8-tools-cgroup-makefile.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/kernel-6.8-tools-cgroup-makefile.patch rename to patch/kernel/archive/rockchip-6.9/kernel-6.8-tools-cgroup-makefile.patch diff --git a/patch/kernel/archive/rockchip-6.8/libreelec.series b/patch/kernel/archive/rockchip-6.9/libreelec.series similarity index 100% rename from patch/kernel/archive/rockchip-6.8/libreelec.series rename to patch/kernel/archive/rockchip-6.9/libreelec.series diff --git a/patch/kernel/archive/rockchip-6.8/overlay/Makefile b/patch/kernel/archive/rockchip-6.9/overlay/Makefile similarity index 93% rename from patch/kernel/archive/rockchip-6.8/overlay/Makefile rename to patch/kernel/archive/rockchip-6.9/overlay/Makefile index b486eef2ec89..9aa0bda64de5 100644 --- a/patch/kernel/archive/rockchip-6.8/overlay/Makefile +++ b/patch/kernel/archive/rockchip-6.9/overlay/Makefile @@ -48,8 +48,7 @@ dtbotxt-$(CONFIG_ARCH_ROCKCHIP) += \ README.rk322x-overlays \ README.rockchip-overlays -targets += $(dtbo-y) $(scr-y) $(dtbotxt-y) +dtb-y += $(dtbo-y) $(scr-y) $(dtbotxt-y) -always := $(dtbo-y) $(scr-y) $(dtbotxt-y) clean-files := *.dtbo *.scr diff --git a/patch/kernel/archive/rockchip-6.8/overlay/README.rk322x-overlays b/patch/kernel/archive/rockchip-6.9/overlay/README.rk322x-overlays similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/README.rk322x-overlays rename to patch/kernel/archive/rockchip-6.9/overlay/README.rk322x-overlays diff --git a/patch/kernel/archive/rockchip-6.8/overlay/README.rockchip-overlays b/patch/kernel/archive/rockchip-6.9/overlay/README.rockchip-overlays similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/README.rockchip-overlays rename to patch/kernel/archive/rockchip-6.9/overlay/README.rockchip-overlays diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-bt-8723cs.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-bt-8723cs.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-bt-8723cs.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-bt-8723cs.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-cpu-hs-lv.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-cpu-hs-lv.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-cpu-hs-lv.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-cpu-hs-lv.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-cpu-hs.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-cpu-hs.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-cpu-hs.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-cpu-hs.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-cpu-stability.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-cpu-stability.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-cpu-stability.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-cpu-stability.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-ddr3-330.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-ddr3-330.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-ddr3-330.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-ddr3-330.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-ddr3-528.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-ddr3-528.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-ddr3-528.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-ddr3-528.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-ddr3-660.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-ddr3-660.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-ddr3-660.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-ddr3-660.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-ddr3-800.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-ddr3-800.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-ddr3-800.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-ddr3-800.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-emmc-ddr-ph180.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-emmc-ddr-ph180.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-emmc-ddr-ph180.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-emmc-ddr-ph180.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-emmc-ddr-ph45.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-emmc-ddr-ph45.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-emmc-ddr-ph45.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-emmc-ddr-ph45.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-emmc-hs200.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-emmc-hs200.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-emmc-hs200.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-emmc-hs200.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-emmc-pins.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-emmc-pins.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-emmc-pins.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-emmc-pins.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-emmc.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-emmc.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-emmc.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-emmc.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-fixup.scr-cmd b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-fixup.scr-cmd similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-fixup.scr-cmd rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-fixup.scr-cmd diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-ir-wakeup.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-ir-wakeup.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-ir-wakeup.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-ir-wakeup.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf-default.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf-default.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf-default.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf-default.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf1.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf1.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf1.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf1.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf2.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf2.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf2.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf2.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf3.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf3.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf3.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf3.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf4.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf4.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf4.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf4.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf5.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf5.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf5.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf5.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf6.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf6.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf6.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf6.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf7.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf7.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf7.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf7.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf8.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf8.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-led-conf8.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-led-conf8.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-nand.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-nand.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-nand.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-nand.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-usb-otg-peripheral.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-usb-otg-peripheral.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-usb-otg-peripheral.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-usb-otg-peripheral.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rk322x-wlan-alt-wiring.dts b/patch/kernel/archive/rockchip-6.9/overlay/rk322x-wlan-alt-wiring.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rk322x-wlan-alt-wiring.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rk322x-wlan-alt-wiring.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-ds1307.dtbo b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-ds1307.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-ds1307.dtbo rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-ds1307.dtbo diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-ds1307.dts b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-ds1307.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-ds1307.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-ds1307.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-fixup.scr-cmd b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-fixup.scr-cmd similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-fixup.scr-cmd rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-fixup.scr-cmd diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-i2c1.dtbo b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-i2c1.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-i2c1.dtbo rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-i2c1.dtbo diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-i2c1.dts b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-i2c1.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-i2c1.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-i2c1.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-i2c4.dtbo b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-i2c4.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-i2c4.dtbo rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-i2c4.dtbo diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-i2c4.dts b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-i2c4.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-i2c4.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-i2c4.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-spi0.dtbo b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-spi0.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-spi0.dtbo rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-spi0.dtbo diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-spi0.dts b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-spi0.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-spi0.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-spi0.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-spi2.dtbo b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-spi2.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-spi2.dtbo rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-spi2.dtbo diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-spi2.dts b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-spi2.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-spi2.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-spi2.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-spidev0.dtbo b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-spidev0.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-spidev0.dtbo rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-spidev0.dtbo diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-spidev0.dts b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-spidev0.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-spidev0.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-spidev0.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-spidev2.dtbo b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-spidev2.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-spidev2.dtbo rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-spidev2.dtbo diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-spidev2.dts b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-spidev2.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-spidev2.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-spidev2.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart1.dtbo b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart1.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart1.dtbo rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart1.dtbo diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart1.dts b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart1.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart1.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart1.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart2.dtbo b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart2.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart2.dtbo rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart2.dtbo diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart2.dts b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart2.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart2.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart2.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart3.dtbo b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart3.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart3.dtbo rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart3.dtbo diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart3.dts b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart3.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart3.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart3.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart4.dtbo b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart4.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart4.dtbo rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart4.dtbo diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart4.dts b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart4.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-uart4.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-uart4.dtso diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-w1-gpio.dtbo b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-w1-gpio.dtbo similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-w1-gpio.dtbo rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-w1-gpio.dtbo diff --git a/patch/kernel/archive/rockchip-6.8/overlay/rockchip-w1-gpio.dts b/patch/kernel/archive/rockchip-6.9/overlay/rockchip-w1-gpio.dtso similarity index 100% rename from patch/kernel/archive/rockchip-6.8/overlay/rockchip-w1-gpio.dts rename to patch/kernel/archive/rockchip-6.9/overlay/rockchip-w1-gpio.dtso diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/bt-broadcom-serdev-workaround.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/bt-broadcom-serdev-workaround.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/bt-broadcom-serdev-workaround.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/bt-broadcom-serdev-workaround.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/clk-rk322x-composite-mmc-clk.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/clk-rk322x-composite-mmc-clk.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/clk-rk322x-composite-mmc-clk.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/clk-rk322x-composite-mmc-clk.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/clk-rockchip-max-frac-divider.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/clk-rockchip-max-frac-divider.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/clk-rockchip-max-frac-divider.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/clk-rockchip-max-frac-divider.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/driver-rk322x-audio-codec.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/driver-rk322x-audio-codec.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/driver-rk322x-audio-codec.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/driver-rk322x-audio-codec.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/driver-rk3288-gpiomem.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/driver-rk3288-gpiomem.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/driver-rk3288-gpiomem.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/driver-rk3288-gpiomem.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/driver-tinkerboard-alc4040-codec.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/driver-tinkerboard-alc4040-codec.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/driver-tinkerboard-alc4040-codec.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/driver-tinkerboard-alc4040-codec.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/drm-rk322x-plane-overlay.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/drm-rk322x-plane-overlay.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/drm-rk322x-plane-overlay.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/drm-rk322x-plane-overlay.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/drm-rk322x-yuv-10bit-modes.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/drm-rk322x-yuv-10bit-modes.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/drm-rk322x-yuv-10bit-modes.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/drm-rk322x-yuv-10bit-modes.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/drm-rockchip-hardware-cursor.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/drm-rockchip-hardware-cursor.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/drm-rockchip-hardware-cursor.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/drm-rockchip-hardware-cursor.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-miqi-fan.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-miqi-fan.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-miqi-fan.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-miqi-fan.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-miqi-hevc-rga.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-miqi-hevc-rga.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-miqi-hevc-rga.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-miqi-hevc-rga.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-miqi-mali-gpu.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-miqi-mali-gpu.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-miqi-mali-gpu.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-miqi-mali-gpu.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-miqi-regulator-fix.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-miqi-regulator-fix.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-miqi-regulator-fix.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-miqi-regulator-fix.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-rk322x-iep-node.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-rk322x-iep-node.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-rk322x-iep-node.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-rk322x-iep-node.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-rk322x-pinctrl-nand.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-rk322x-pinctrl-nand.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-rk322x-pinctrl-nand.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-rk322x-pinctrl-nand.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-rk3288-disable-serial-dma.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-rk3288-disable-serial-dma.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-rk3288-disable-serial-dma.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-rk3288-disable-serial-dma.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-rk3288-fix-mmc-aliases.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-rk3288-fix-mmc-aliases.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-rk3288-fix-mmc-aliases.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-rk3288-fix-mmc-aliases.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-rk3288-gpu-500mhz-opp.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-rk3288-gpu-500mhz-opp.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-rk3288-gpu-500mhz-opp.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-rk3288-gpu-500mhz-opp.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-rk3288-pinctrl-spi2.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-rk3288-pinctrl-spi2.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-rk3288-pinctrl-spi2.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-rk3288-pinctrl-spi2.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-rk3288-thermal-rearrange-zones.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-rk3288-thermal-rearrange-zones.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-rk3288-thermal-rearrange-zones.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-rk3288-thermal-rearrange-zones.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-tinkerboard-bt-rtl8723bs.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-tinkerboard-bt-uart-pins.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-tinkerboard-bt-uart-pins.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-tinkerboard-bt-uart-pins.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-tinkerboard-bt-uart-pins.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-tinkerboard-hevc-rga.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-tinkerboard-hevc-rga.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-tinkerboard-hevc-rga.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-tinkerboard-hevc-rga.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-tinkerboard-sdio-wifi.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-tinkerboard-sdio-wifi.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-tinkerboard-sdio-wifi.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-tinkerboard-sdio-wifi.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-tinkerboard-sdmmc-properties.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-tinkerboard-sdmmc-properties.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-tinkerboard-sdmmc-properties.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-tinkerboard-sdmmc-properties.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-tinkerboard-spi-interface.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-tinkerboard-spi-interface.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-tinkerboard-spi-interface.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-tinkerboard-spi-interface.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/dts-veyron-flag-cache-flush.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/dts-veyron-flag-cache-flush.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/dts-veyron-flag-cache-flush.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/dts-veyron-flag-cache-flush.patch diff --git a/patch/kernel/archive/rockchip-6.9/patches.armbian/general-add-overlay-compilation-support.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/general-add-overlay-compilation-support.patch new file mode 100644 index 000000000000..b2e233f4dda4 --- /dev/null +++ b/patch/kernel/archive/rockchip-6.9/patches.armbian/general-add-overlay-compilation-support.patch @@ -0,0 +1,69 @@ +From 088e1cd9b9dd113f0a5e9e19a7f31c37532e002a Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Sun, 2 Jun 2024 21:53:01 +0200 +Subject: [PATCH] compile .scr and install overlays in right path + +--- + scripts/Makefile.dtbinst | 2 +- + scripts/Makefile.lib | 8 +++++++- + 2 files changed, 8 insertions(+), 2 deletions(-) + +diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst +index 67956f6496a5..151687728a60 100644 +--- a/scripts/Makefile.dtbinst ++++ b/scripts/Makefile.dtbinst +@@ -33,7 +33,18 @@ endef + + $(foreach d, $(sort $(dir $(dtbs))), $(eval $(call gen_install_rules,$(d)))) + +-dtbs := $(notdir $(dtbs)) ++# Very convoluted way to flatten all the device tree ++# directories, but keep the "/overlay/" directory ++ ++# topmost directory (ie: from rockchip/overlay/rk322x-emmc.dtbo extracts rockchip) ++topmost_dir = $(firstword $(subst /, ,$(dtbs))) ++# collect dtbs entries which starts with "$topmost_dir/overlay/", then remove "$topmost_dir" ++dtbs_overlays = $(subst $(topmost_dir)/,,$(filter $(topmost_dir)/overlay/%, $(dtbs))) ++# collect the non-overlay dtbs ++dtbs_regular = $(filter-out $(topmost_dir)/overlay/%, $(dtbs)) ++# compose the dtbs variable flattening all the non-overlays entries ++# and appending the overlays entries ++dtbs := $(notdir $(dtbs_regular)) $(dtbs_overlays) + + endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL + +diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib +index 3179747cbd2c..59925208734a 100644 +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -398,7 +398,7 @@ $(obj)/%.dtbo.S: $(obj)/%.dtbo FORCE + + quiet_cmd_dtc = DTC $@ + cmd_dtc = $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ +- $(DTC) -o $@ -b 0 \ ++ $(DTC) -@ -o $@ -b 0 \ + $(addprefix -i,$(dir $<) $(DTC_INCLUDE)) $(DTC_FLAGS) \ + -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) +@@ -423,12 +423,18 @@ quiet_cmd_dtb = $(quiet_cmd_dtc) + cmd_dtb = $(cmd_dtc) + endif + ++quiet_cmd_scr = MKIMAGE $@ ++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ ++ + $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE + $(call if_changed_dep,dtb) + + $(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE + $(call if_changed_dep,dtc) + ++$(obj)/%.scr: $(src)/%.scr-cmd FORCE ++ $(call if_changed,scr) ++ + dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + + # Bzip2 +-- +2.34.1 + diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/general-add-overlay-configfs.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/general-add-overlay-configfs.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/general-add-overlay-configfs.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/general-add-overlay-configfs.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/general-add-restart-handler-for-act8846.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/general-add-restart-handler-for-act8846.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/general-add-restart-handler-for-act8846.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/general-add-restart-handler-for-act8846.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/general-dwc2-fix-wait-peripheral.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/general-dwc2-fix-wait-peripheral.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/general-dwc2-fix-wait-peripheral.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/general-dwc2-fix-wait-peripheral.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/general-dwc2-fix-wait-time.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/general-dwc2-fix-wait-time.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/general-dwc2-fix-wait-time.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/general-dwc2-fix-wait-time.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/general-dwc2-nak-gadget.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/general-dwc2-nak-gadget.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/general-dwc2-nak-gadget.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/general-dwc2-nak-gadget.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/general-fix-reboot-from-kwiboo.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/general-fix-reboot-from-kwiboo.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/general-fix-reboot-from-kwiboo.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/general-fix-reboot-from-kwiboo.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/general-linux-export-mm-trace-rss-stats.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/general-linux-export-mm-trace-rss-stats.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/general-linux-export-mm-trace-rss-stats.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/general-linux-export-mm-trace-rss-stats.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/general-rk322x-gpio-ir-driver.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/general-rk322x-gpio-ir-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/general-rk322x-gpio-ir-driver.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/general-rk322x-gpio-ir-driver.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/general-rockchip-various-fixes.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/general-rockchip-various-fixes.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/general-rockchip-various-fixes.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/general-rockchip-various-fixes.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/ir-keymap-rk322x-box.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/ir-keymap-rk322x-box.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/ir-keymap-rk322x-box.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/ir-keymap-rk322x-box.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/ir-keymap-xt-q8l-v10.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/ir-keymap-xt-q8l-v10.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/ir-keymap-xt-q8l-v10.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/ir-keymap-xt-q8l-v10.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/misc-tinkerboard-spi-interface.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/misc-tinkerboard-spi-interface.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/misc-tinkerboard-spi-interface.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/misc-tinkerboard-spi-interface.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/mmc-tinkerboard-sdmmc-reboot-fix.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/rk322x-dmc-driver-01-sipv2-calls.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/rk322x-dmc-driver-02-sip-constants.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/rk322x-dmc-driver-02-sip-constants.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/rk322x-dmc-driver-02-sip-constants.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/rk322x-dmc-driver-02-sip-constants.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/rk322x-dmc-driver-03-dfi-driver.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/rk322x-dmc-driver-04-driver.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/rk322x-dmc-driver-04-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/rk322x-dmc-driver-04-driver.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/rk322x-dmc-driver-04-driver.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/rk322x-dwc2-no-clock-gating.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/rk322x-dwc2-no-clock-gating.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/rk322x-dwc2-no-clock-gating.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/rk322x-dwc2-no-clock-gating.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/rk322x-usb-reset-props.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/rk322x-usb-reset-props.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/rk322x-usb-reset-props.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/rk322x-usb-reset-props.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/wifi-ath9k-no-bulk-EP3-EP4.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/wifi-brcmfmac-add-bcm43342.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/wifi-brcmfmac-add-bcm43342.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/wifi-brcmfmac-add-bcm43342.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/wifi-brcmfmac-add-bcm43342.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/wifi-brcmfmac-ap6330-firmware.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/wifi-brcmfmac-ap6330-firmware.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/wifi-brcmfmac-ap6330-firmware.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/wifi-brcmfmac-ap6330-firmware.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/wifi-driver-esp8089.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/wifi-driver-esp8089.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/wifi-driver-esp8089.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/wifi-driver-esp8089.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.armbian/wifi-driver-ssv6051.patch b/patch/kernel/archive/rockchip-6.9/patches.armbian/wifi-driver-ssv6051.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.armbian/wifi-driver-ssv6051.patch rename to patch/kernel/archive/rockchip-6.9/patches.armbian/wifi-driver-ssv6051.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.libreelec/linux-0002-rockchip-from-list.patch b/patch/kernel/archive/rockchip-6.9/patches.libreelec/linux-0002-rockchip-from-list.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.libreelec/linux-0002-rockchip-from-list.patch rename to patch/kernel/archive/rockchip-6.9/patches.libreelec/linux-0002-rockchip-from-list.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.libreelec/linux-0011-v4l2-from-list.patch b/patch/kernel/archive/rockchip-6.9/patches.libreelec/linux-0011-v4l2-from-list.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.libreelec/linux-0011-v4l2-from-list.patch rename to patch/kernel/archive/rockchip-6.9/patches.libreelec/linux-0011-v4l2-from-list.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.libreelec/linux-1000-drm-rockchip.patch b/patch/kernel/archive/rockchip-6.9/patches.libreelec/linux-1000-drm-rockchip.patch similarity index 100% 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a/patch/kernel/archive/rockchip-6.8/patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch b/patch/kernel/archive/rockchip-6.9/patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch rename to patch/kernel/archive/rockchip-6.9/patches.libreelec/linux-1003-temp-dw_hdmi-rockchip.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch b/patch/kernel/archive/rockchip-6.9/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch rename to patch/kernel/archive/rockchip-6.9/patches.libreelec/linux-2000-v4l2-wip-rkvdec-hevc.patch diff --git a/patch/kernel/archive/rockchip-6.8/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch b/patch/kernel/archive/rockchip-6.9/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip-6.8/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch rename to patch/kernel/archive/rockchip-6.9/patches.libreelec/linux-2001-v4l2-wip-iep-driver.patch diff --git a/patch/kernel/archive/rockchip-6.8/series.conf b/patch/kernel/archive/rockchip-6.9/series.conf similarity index 100% rename from patch/kernel/archive/rockchip-6.8/series.conf rename to patch/kernel/archive/rockchip-6.9/series.conf diff --git a/patch/kernel/archive/rockchip64-6.8/general-add-overlay-compilation-support.patch b/patch/kernel/archive/rockchip64-6.8/general-add-overlay-compilation-support.patch deleted file mode 100644 index 7357d074e42c..000000000000 --- a/patch/kernel/archive/rockchip64-6.8/general-add-overlay-compilation-support.patch +++ /dev/null @@ -1,413 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: zador-blood-stained -Date: Sat, 11 Feb 2017 20:32:53 +0300 -Subject: [ARCHEOLOGY] Rename, split and improve H3 DT overlays - -> X-Git-Archeology: > recovered message: > Fix OPi Zero DT -> X-Git-Archeology: > recovered message: > Improve DT loading reliability -> X-Git-Archeology: - Revision bacf56710491e3307e0fb2bc1c828dad828c9f23: https://github.com/armbian/build/commit/bacf56710491e3307e0fb2bc1c828dad828c9f23 -> X-Git-Archeology: Date: Sat, 11 Feb 2017 20:32:53 +0300 -> X-Git-Archeology: From: zador-blood-stained -> X-Git-Archeology: Subject: Rename, split and improve H3 DT overlays -> X-Git-Archeology: -> X-Git-Archeology: - Revision c7bbc3257e8dcbf75398301602150fe9f1666c86: https://github.com/armbian/build/commit/c7bbc3257e8dcbf75398301602150fe9f1666c86 -> X-Git-Archeology: Date: Sun, 26 Feb 2017 19:46:15 +0300 -> X-Git-Archeology: From: zador-blood-stained -> X-Git-Archeology: Subject: Initial A20 overlays support for sunxi-next kernel -> X-Git-Archeology: -> X-Git-Archeology: - Revision caf4b1b037e7510cae7edd1b5f75482eed41b547: https://github.com/armbian/build/commit/caf4b1b037e7510cae7edd1b5f75482eed41b547 -> X-Git-Archeology: Date: Mon, 13 Mar 2017 20:32:37 +0300 -> X-Git-Archeology: From: zador-blood-stained -> X-Git-Archeology: Subject: Add new A20 overlays -> X-Git-Archeology: -> X-Git-Archeology: - Revision b30fcea3f95804175199bc1865a7e39cdf07cf73: https://github.com/armbian/build/commit/b30fcea3f95804175199bc1865a7e39cdf07cf73 -> X-Git-Archeology: Date: Sun, 14 May 2017 17:59:35 +0300 -> X-Git-Archeology: From: zador-blood-stained -> X-Git-Archeology: Subject: Update sunxi-next branch to 4.11 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 20240e9669055030076e69452cf6a1ccb368cc2e: https://github.com/armbian/build/commit/20240e9669055030076e69452cf6a1ccb368cc2e -> X-Git-Archeology: Date: Tue, 30 May 2017 21:30:38 -0400 -> X-Git-Archeology: From: Martin Ayotte -> X-Git-Archeology: Subject: add overlays to sunxi-dev -> X-Git-Archeology: -> X-Git-Archeology: - Revision b0fcb64aaca589359338a500e7bc07eb7ca1cb71: https://github.com/armbian/build/commit/b0fcb64aaca589359338a500e7bc07eb7ca1cb71 -> X-Git-Archeology: Date: Thu, 07 Dec 2017 07:09:10 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Temporally disabling broken patches on sunxi DEV branch -> X-Git-Archeology: -> X-Git-Archeology: - Revision 2123e539ed288e3355ef3d3adc79788a187f62df: https://github.com/armbian/build/commit/2123e539ed288e3355ef3d3adc79788a187f62df -> X-Git-Archeology: Date: Thu, 15 Feb 2018 11:21:51 +0200 -> X-Git-Archeology: From: Stefan Mavrodiev -> X-Git-Archeology: Subject: Add overlays support for upstream kernel -> X-Git-Archeology: -> X-Git-Archeology: - Revision 2c08ec8f5a210de35f9482f482ac01ea15381792: https://github.com/armbian/build/commit/2c08ec8f5a210de35f9482f482ac01ea15381792 -> X-Git-Archeology: Date: Thu, 24 May 2018 13:32:29 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Merge sunxi family into stable -> X-Git-Archeology: -> X-Git-Archeology: - Revision 1a12994e79b6ef173dc58efe4df8919cb6cc7781: https://github.com/armbian/build/commit/1a12994e79b6ef173dc58efe4df8919cb6cc7781 -> X-Git-Archeology: Date: Tue, 17 Jul 2018 15:53:30 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Moving sunxi-next to 4.17.y (#1049) -> X-Git-Archeology: -> X-Git-Archeology: - Revision a57ce78b37f8dd2eb94a3836f4a7f6969f2ffd72: https://github.com/armbian/build/commit/a57ce78b37f8dd2eb94a3836f4a7f6969f2ffd72 -> X-Git-Archeology: Date: Tue, 21 Aug 2018 10:41:10 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Reverting sunxi/sunxi64 NEXT to 4.14. (#1087) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 871bed1a24e21952f7aeb1981c26ad5fc573be9d: https://github.com/armbian/build/commit/871bed1a24e21952f7aeb1981c26ad5fc573be9d -> X-Git-Archeology: Date: Tue, 04 Dec 2018 16:25:53 -0500 -> X-Git-Archeology: From: Martin Ayotte -> X-Git-Archeology: Subject: add overlay-compilation-support to meson64-dev -> X-Git-Archeology: -> X-Git-Archeology: - Revision 7c5fb27d79d1c737fc2ca92a1069226e9aae2154: https://github.com/armbian/build/commit/7c5fb27d79d1c737fc2ca92a1069226e9aae2154 -> X-Git-Archeology: Date: Wed, 09 Jan 2019 23:33:47 -0500 -> X-Git-Archeology: From: Thomas McKahan -> X-Git-Archeology: Subject: [ meson64-next ] Shift Next to 4.19 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 2fa7c680c29a144214706dda35c2a6afdd708858: https://github.com/armbian/build/commit/2fa7c680c29a144214706dda35c2a6afdd708858 -> X-Git-Archeology: Date: Thu, 21 Mar 2019 14:57:07 -0400 -> X-Git-Archeology: From: Martin Ayotte -> X-Git-Archeology: Subject: fix overlay patch -> X-Git-Archeology: -> X-Git-Archeology: - Revision a040785d4299e10255d87fdfcfa70b56e0b6779f: https://github.com/armbian/build/commit/a040785d4299e10255d87fdfcfa70b56e0b6779f -> X-Git-Archeology: Date: Sun, 04 Aug 2019 18:05:50 -0400 -> X-Git-Archeology: From: chwe17 -> X-Git-Archeology: Subject: Tinkerboard camera support (#1482) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 150ac0c2afa147d9e3b036c8ecd8238fe5648cf3: https://github.com/armbian/build/commit/150ac0c2afa147d9e3b036c8ecd8238fe5648cf3 -> X-Git-Archeology: Date: Tue, 19 Nov 2019 23:25:39 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Remove K<4, change branches, new features (#1586) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 23604e8a0dcdf81ec6c28ccd4b2a64b90816d8e7: https://github.com/armbian/build/commit/23604e8a0dcdf81ec6c28ccd4b2a64b90816d8e7 -> X-Git-Archeology: Date: Fri, 19 Jun 2020 17:27:27 +0200 -> X-Git-Archeology: From: Paolo -> X-Git-Archeology: Subject: Introducing Rockchip RK322X SoC support (#2032) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 99afbdfe7e08334bb5dde05c4f3dab536e87224e: https://github.com/armbian/build/commit/99afbdfe7e08334bb5dde05c4f3dab536e87224e -> X-Git-Archeology: Date: Fri, 26 Jun 2020 15:53:20 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump meson64 current to 5.7.y (#2069) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 812245def37a695bce9e7ece148b2920d82c8b37: https://github.com/armbian/build/commit/812245def37a695bce9e7ece148b2920d82c8b37 -> X-Git-Archeology: Date: Sat, 18 Jul 2020 23:07:01 +0200 -> X-Git-Archeology: From: Werner -> X-Git-Archeology: Subject: Move rockchip/64 current to 5.7.y (#2099) -> X-Git-Archeology: -> X-Git-Archeology: - Revision caa47bad650f82cb8045d19c384595b1760bd9e1: https://github.com/armbian/build/commit/caa47bad650f82cb8045d19c384595b1760bd9e1 -> X-Git-Archeology: Date: Sat, 18 Jul 2020 23:08:52 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Move sunxi/64 current to 5.7, legacy to 5.4 (#2098) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 804a6b60d4c2724ada9eb975e3caf2d9753beba9: https://github.com/armbian/build/commit/804a6b60d4c2724ada9eb975e3caf2d9753beba9 -> X-Git-Archeology: Date: Fri, 28 Aug 2020 18:48:55 +0200 -> X-Git-Archeology: From: Paolo -> X-Git-Archeology: Subject: Moved rk322x-dev to rk322x-current (current now is 5.7.y) (#2153) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 661371868def63655e46e8c513d8ba0f42cf4066: https://github.com/armbian/build/commit/661371868def63655e46e8c513d8ba0f42cf4066 -> X-Git-Archeology: Date: Fri, 28 Aug 2020 19:26:08 +0200 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Enable overlays for rk3399-legacy (#2144) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 4cdf3c3d0e31fb9fa05d9b818915d54c465dffa0: https://github.com/armbian/build/commit/4cdf3c3d0e31fb9fa05d9b818915d54c465dffa0 -> X-Git-Archeology: Date: Sun, 18 Oct 2020 14:43:30 -0400 -> X-Git-Archeology: From: tonymac32 -> X-Git-Archeology: Subject: [ rockchip ] add overlay compilation support -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0cdffb29b07305209efb12cf3b5ac6032d3a1153: https://github.com/armbian/build/commit/0cdffb29b07305209efb12cf3b5ac6032d3a1153 -> X-Git-Archeology: Date: Wed, 24 Mar 2021 19:01:53 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Renaming DEV branch to EDGE (#2704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 3b3d85e25c2ecde30df7b5274fc6f1b9c0299ea2: https://github.com/armbian/build/commit/3b3d85e25c2ecde30df7b5274fc6f1b9c0299ea2 -> X-Git-Archeology: Date: Sat, 22 May 2021 17:08:44 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Upgrade EDGE to 5.12.y (#2825) -> X-Git-Archeology: -> X-Git-Archeology: - Revision e21e82b546d3817e69ec062bb1e56c63c33e9c21: https://github.com/armbian/build/commit/e21e82b546d3817e69ec062bb1e56c63c33e9c21 -> X-Git-Archeology: Date: Wed, 21 Jul 2021 00:46:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Upgrading sunxi, sunxi64, imx6, jetson-nano, mvebu and mvebu64 EDGE to 5.13 (#3042) -> X-Git-Archeology: -> X-Git-Archeology: - Revision e7377248b3cae186e24e2be781cd3365b43246f0: https://github.com/armbian/build/commit/e7377248b3cae186e24e2be781cd3365b43246f0 -> X-Git-Archeology: Date: Thu, 22 Jul 2021 00:15:54 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Second part of EDGE bumping to 5.13.y (#3045) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 744ea89a589d62cb6f409baab60fc6664520bc39: https://github.com/armbian/build/commit/744ea89a589d62cb6f409baab60fc6664520bc39 -> X-Git-Archeology: Date: Wed, 08 Sep 2021 17:51:34 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bumping EDGE kernel to 5.14.y (#3125) -> X-Git-Archeology: -> X-Git-Archeology: - Revision f15bc37276f8a06c024628b41905a7255934e93b: https://github.com/armbian/build/commit/f15bc37276f8a06c024628b41905a7255934e93b -> X-Git-Archeology: Date: Sat, 11 Sep 2021 12:51:28 +0000 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rk322x: add back edge kernel patches lost in the process, hardware cursor dedicated plane -> X-Git-Archeology: -> X-Git-Archeology: - Revision dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e: https://github.com/armbian/build/commit/dd51f9f2afcbc83a3e10b32eb6a5061d91d1558e -> X-Git-Archeology: Date: Tue, 09 Nov 2021 18:06:34 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump imx6, xu4, rockchip64 and jetson-nano to 5.15 (#3238) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 4c3dcbf4fcd3616999cb91a1dddfa74668eb6de9: https://github.com/armbian/build/commit/4c3dcbf4fcd3616999cb91a1dddfa74668eb6de9 -> X-Git-Archeology: Date: Tue, 09 Nov 2021 21:58:35 +0100 -> X-Git-Archeology: From: Paolo -> X-Git-Archeology: Subject: Rockchip 5.15 (#3242) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6b490e16944b30ff69bf9c13678905187df0d9d4: https://github.com/armbian/build/commit/6b490e16944b30ff69bf9c13678905187df0d9d4 -> X-Git-Archeology: Date: Tue, 11 Jan 2022 15:26:11 +0100 -> X-Git-Archeology: From: Oleg -> X-Git-Archeology: Subject: move kernel edge to 5.16 (#3387) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 1e37959e5381a0a1d1eaf0629cdc19658f30df9a: https://github.com/armbian/build/commit/1e37959e5381a0a1d1eaf0629cdc19658f30df9a -> X-Git-Archeology: Date: Thu, 10 Feb 2022 20:32:58 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bumping sunxi/64, xu4, rockchip and mvebu64 to 5.16.y (#3453) -> X-Git-Archeology: -> X-Git-Archeology: - Revision ac8fc4385594d59257ee9dffd9efa85e3497fa7d: https://github.com/armbian/build/commit/ac8fc4385594d59257ee9dffd9efa85e3497fa7d -> X-Git-Archeology: Date: Sat, 26 Feb 2022 07:46:44 +0100 -> X-Git-Archeology: From: Piotr Szczepanik -> X-Git-Archeology: Subject: Switch rockchip64 current to linux 5.15.y (#3489) -> X-Git-Archeology: -> X-Git-Archeology: - Revision f52a4193d02ef88333ba117c68d49486dfd7ff41: https://github.com/armbian/build/commit/f52a4193d02ef88333ba117c68d49486dfd7ff41 -> X-Git-Archeology: Date: Sun, 20 Mar 2022 22:58:21 +0100 -> X-Git-Archeology: From: Oleg -> X-Git-Archeology: Subject: Adding Pine64 Quartz64a as WIP target (#3539) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 2fe1ddfe451d3a3dba01e4ba1204d2b9fe7eb44e: https://github.com/armbian/build/commit/2fe1ddfe451d3a3dba01e4ba1204d2b9fe7eb44e -> X-Git-Archeology: Date: Sat, 26 Mar 2022 17:59:23 +0000 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rockchip: add tinkerboard overlays for current 5.15 kernel -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0777be9e754c8bd24cff0297226b5158564bbc96: https://github.com/armbian/build/commit/0777be9e754c8bd24cff0297226b5158564bbc96 -> X-Git-Archeology: Date: Sun, 10 Apr 2022 16:45:06 +0200 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rk322x: move edge flavour to kernel 5.17, adapt patches were necessary -> X-Git-Archeology: -> X-Git-Archeology: - Revision 49b2aba89124b15a0f6b81ccf44b3792b6b35497: https://github.com/armbian/build/commit/49b2aba89124b15a0f6b81ccf44b3792b6b35497 -> X-Git-Archeology: Date: Mon, 11 Apr 2022 22:05:28 +0200 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rockchip: copy patch archive from 5.16 to 5.17 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0afe24c95729044910e0b3f84dc5500bcdc6524c: https://github.com/armbian/build/commit/0afe24c95729044910e0b3f84dc5500bcdc6524c -> X-Git-Archeology: Date: Sun, 24 Apr 2022 22:33:47 +0200 -> X-Git-Archeology: From: Oleg -> X-Git-Archeology: Subject: move kernel media edge to 5.17 (#3704) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 897674aa74bce0326ed7fe06f5336bf4709a8a1f: https://github.com/armbian/build/commit/897674aa74bce0326ed7fe06f5336bf4709a8a1f -> X-Git-Archeology: Date: Tue, 03 May 2022 08:27:32 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump and freeze kernel at last known working versions (#3736) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 597d2dac11f00d9070a4e49d6bad1b2244e36cb3: https://github.com/armbian/build/commit/597d2dac11f00d9070a4e49d6bad1b2244e36cb3 -> X-Git-Archeology: Date: Sat, 28 May 2022 07:56:22 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64-edge to 5.18 (#3814) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 3c4189e311ca60427d47dae796620a9fc98dc1f3: https://github.com/armbian/build/commit/3c4189e311ca60427d47dae796620a9fc98dc1f3 -> X-Git-Archeology: Date: Sun, 29 May 2022 17:15:36 +0200 -> X-Git-Archeology: From: Paolo -> X-Git-Archeology: Subject: rockchip: upgrade edge kernel to v5.18 (#3842) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 809ce98a75163e3d37cffae811e1d19fd0758ef4: https://github.com/armbian/build/commit/809ce98a75163e3d37cffae811e1d19fd0758ef4 -> X-Git-Archeology: Date: Sun, 29 May 2022 17:26:16 +0200 -> X-Git-Archeology: From: Paolo -> X-Git-Archeology: Subject: rk322x: move edge kernel to v5.18 (#3844) -> X-Git-Archeology: -> X-Git-Archeology: - Revision d064b2dce2a58299bff98e8ccb275fec861777e9: https://github.com/armbian/build/commit/d064b2dce2a58299bff98e8ccb275fec861777e9 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 19:10:25 +0200 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rk322x: advance edge kernel to 5.19 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 8c6641e7b79f0d50acdc306d140e586a4e923cf0: https://github.com/armbian/build/commit/8c6641e7b79f0d50acdc306d140e586a4e923cf0 -> X-Git-Archeology: Date: Wed, 03 Aug 2022 22:22:55 +0200 -> X-Git-Archeology: From: Jianfeng Liu -> X-Git-Archeology: Subject: update rockchip64 edge to 5.19 (#4039) -> X-Git-Archeology: -> X-Git-Archeology: - Revision c87542aba26b01703746d3db94ac0820575b23b2: https://github.com/armbian/build/commit/c87542aba26b01703746d3db94ac0820575b23b2 -> X-Git-Archeology: Date: Thu, 04 Aug 2022 11:20:06 +0200 -> X-Git-Archeology: From: Paolo -> X-Git-Archeology: Subject: rockchip: switch edge kernel to v5.19 (#4045) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 73691a9e24440e0a8104b2c25d168ba8947a10ad: https://github.com/armbian/build/commit/73691a9e24440e0a8104b2c25d168ba8947a10ad -> X-Git-Archeology: Date: Thu, 04 Aug 2022 21:50:40 +0200 -> X-Git-Archeology: From: Ricardo Pardini -> X-Git-Archeology: Subject: meson64: edge: rework to kernel 5.19 (#3941) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 6765f734cc4a22aeaa9f99a3ad28c8c322de26f6: https://github.com/armbian/build/commit/6765f734cc4a22aeaa9f99a3ad28c8c322de26f6 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 11:26:51 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump rockchip64 edge to 6.0.y (#4337) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 1b12209ded2c356df514e3dd99bd945c0afd7a32: https://github.com/armbian/build/commit/1b12209ded2c356df514e3dd99bd945c0afd7a32 -> X-Git-Archeology: Date: Tue, 25 Oct 2022 20:38:31 +0200 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump meson64 edge to 6.0.y (#4341) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 35db7a3995d0d6e92638a0ed173e7252a927e339: https://github.com/armbian/build/commit/35db7a3995d0d6e92638a0ed173e7252a927e339 -> X-Git-Archeology: Date: Tue, 15 Nov 2022 20:19:17 +0100 -> X-Git-Archeology: From: Paolo -> X-Git-Archeology: Subject: rk322x: bump kernel to 6.0 (#4443) -> X-Git-Archeology: -> X-Git-Archeology: - Revision ed2c6d3c6764e9da4f54cb3b210e5106864dfa0f: https://github.com/armbian/build/commit/ed2c6d3c6764e9da4f54cb3b210e5106864dfa0f -> X-Git-Archeology: Date: Tue, 15 Nov 2022 20:22:47 +0100 -> X-Git-Archeology: From: Paolo -> X-Git-Archeology: Subject: rockchip: advance edge kernel to v6.0 (#4445) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 5b46bd7273909a2a9688efe85c4d45d00d407865: https://github.com/armbian/build/commit/5b46bd7273909a2a9688efe85c4d45d00d407865 -> X-Git-Archeology: Date: Mon, 12 Dec 2022 08:02:25 +0100 -> X-Git-Archeology: From: Ricardo Pardini -> X-Git-Archeology: Subject: `meson64-6.0` kernel patches: mbox formatting, archeology to find lost authors/descriptions; rebase against 6.0.12; no actual changes (#4546) -> X-Git-Archeology: -> X-Git-Archeology: - Revision eb7d4a0bd20e56118f9c8c9089c063154c58a239: https://github.com/armbian/build/commit/eb7d4a0bd20e56118f9c8c9089c063154c58a239 -> X-Git-Archeology: Date: Mon, 12 Dec 2022 08:02:49 +0100 -> X-Git-Archeology: From: Ricardo Pardini -> X-Git-Archeology: Subject: `meson64`: bump `edge` to `6.1-rc8` (#4554) -> X-Git-Archeology: -> X-Git-Archeology: - Revision c0001d566b3770dae722c47180dcb942bed7006a: https://github.com/armbian/build/commit/c0001d566b3770dae722c47180dcb942bed7006a -> X-Git-Archeology: Date: Wed, 14 Dec 2022 01:43:31 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Bump bcm, imx, mvebu64 and xu4 EDGE to 6.1.y (#4560) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 92f1a22d76b987afa7ba555d5b509adc51d689e7: https://github.com/armbian/build/commit/92f1a22d76b987afa7ba555d5b509adc51d689e7 -> X-Git-Archeology: Date: Fri, 16 Dec 2022 13:38:13 +0100 -> X-Git-Archeology: From: Igor Pecovnik -> X-Git-Archeology: Subject: Re-add rockchip64 6.0 patches (#4575) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 80dffbc7611bd76d675fcf74d352e1c55ce51f29: https://github.com/armbian/build/commit/80dffbc7611bd76d675fcf74d352e1c55ce51f29 -> X-Git-Archeology: Date: Tue, 10 Jan 2023 00:31:35 +0100 -> X-Git-Archeology: From: Ricardo Pardini -> X-Git-Archeology: Subject: `meson64`: `edge`: bump to `6.2` - copy patches as-is from 6.1 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 0ea5a3547b393059da92da9925a76bccef93631a: https://github.com/armbian/build/commit/0ea5a3547b393059da92da9925a76bccef93631a -> X-Git-Archeology: Date: Tue, 10 Jan 2023 00:31:41 +0100 -> X-Git-Archeology: From: Ricardo Pardini -> X-Git-Archeology: Subject: `meson64`: `edge`: bump to `6.2` - rebased patches against tag `v6.2-rc3` -> X-Git-Archeology: -> X-Git-Archeology: - Revision 8652bf3d37c9d9f7d87588dc1f97e82626dac489: https://github.com/armbian/build/commit/8652bf3d37c9d9f7d87588dc1f97e82626dac489 -> X-Git-Archeology: Date: Sun, 12 Feb 2023 21:20:35 +0100 -> X-Git-Archeology: From: Joao Assuncao -> X-Git-Archeology: Subject: Adds SPI, I2C, and PWM DTS overlays for odroid-m1 (#4825) -> X-Git-Archeology: -> X-Git-Archeology: - Revision 3f704692a7933a67b5e8cc6ff690d92ef3a5e735: https://github.com/armbian/build/commit/3f704692a7933a67b5e8cc6ff690d92ef3a5e735 -> X-Git-Archeology: Date: Fri, 24 Mar 2023 23:12:56 +0100 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rockchip: bump edge kernel to 6.2 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 5930e5e536d6b2f1a1446b8910648d7b0183919e: https://github.com/armbian/build/commit/5930e5e536d6b2f1a1446b8910648d7b0183919e -> X-Git-Archeology: Date: Fri, 24 Mar 2023 23:14:09 +0100 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rk322x: move edge kernel to 6.2 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 98b6aec55439c5aa8cee13898451e0969f7df9ce: https://github.com/armbian/build/commit/98b6aec55439c5aa8cee13898451e0969f7df9ce -> X-Git-Archeology: Date: Thu, 27 Apr 2023 21:30:02 +0200 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rk322x: bump edge kernel to 6.3 -> X-Git-Archeology: -> X-Git-Archeology: - Revision da0ab48b7939235608c8fc042c61ae997681e865: https://github.com/armbian/build/commit/da0ab48b7939235608c8fc042c61ae997681e865 -> X-Git-Archeology: Date: Thu, 27 Apr 2023 21:31:27 +0200 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rockchip: bump edge kernel to 6.3 -> X-Git-Archeology: -> X-Git-Archeology: - Revision 7a5cd0b246d3f0ae5949b6afa5a59081bd2376e9: https://github.com/armbian/build/commit/7a5cd0b246d3f0ae5949b6afa5a59081bd2376e9 -> X-Git-Archeology: Date: Sat, 29 Apr 2023 07:46:18 +0200 -> X-Git-Archeology: From: Paolo Sabatino -> X-Git-Archeology: Subject: rockchip: fix dtbs_install step for overlays -> X-Git-Archeology: -> X-Git-Archeology: - Revision 34ae84fac5d0b66a1ab2d1e51534b7beb13ef245: https://github.com/armbian/build/commit/34ae84fac5d0b66a1ab2d1e51534b7beb13ef245 -> X-Git-Archeology: Date: Fri, 05 May 2023 14:22:00 +0200 -> X-Git-Archeology: From: amazingfate -> X-Git-Archeology: Subject: bump rockchip64 edge to v6.3 -> X-Git-Archeology: ---- - arch/arm/boot/.gitignore | 2 + - scripts/Makefile.dtbinst | 14 ++++++- - scripts/Makefile.lib | 20 ++++++++++ - 3 files changed, 35 insertions(+), 1 deletion(-) - -diff --git a/arch/arm/boot/.gitignore b/arch/arm/boot/.gitignore -index 8c759326baf4..e6ce8f6ad4b1 100644 ---- a/arch/arm/boot/.gitignore -+++ b/arch/arm/boot/.gitignore -@@ -4,3 +4,5 @@ zImage - xipImage - bootpImage - uImage -+*.dtb* -+*.scr -diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst -index 4405d5b67578..4adbe6644d0c 100644 ---- a/scripts/Makefile.dtbinst -+++ b/scripts/Makefile.dtbinst -@@ -18,9 +18,12 @@ include $(srctree)/scripts/Kbuild.include - include $(kbuild-file) - - dtbs := $(addprefix $(dst)/, $(dtb-y) $(if $(CONFIG_OF_ALL_DTBS),$(dtb-))) -+dtbos := $(addprefix $(dst)/, $(dtbo-y)) -+scrs := $(addprefix $(dst)/, $(scr-y)) -+readmes := $(addprefix $(dst)/, $(dtbotxt-y)) - subdirs := $(addprefix $(obj)/, $(subdir-y) $(subdir-m)) - --__dtbs_install: $(dtbs) $(subdirs) -+__dtbs_install: $(dtbs) $(dtbos) $(scrs) $(readmes) $(subdirs) - @: - - quiet_cmd_dtb_install = INSTALL $@ -@@ -32,6 +35,15 @@ $(dst)/%.dtb: $(obj)/%.dtb - $(dst)/%.dtbo: $(obj)/%.dtbo - $(call cmd,dtb_install) - -+$(dst)/%.dtbo: $(obj)/%.dtbo -+ $(call cmd,dtb_install) -+ -+$(dst)/%.scr: $(obj)/%.scr -+ $(call cmd,dtb_install) -+ -+$(dst)/README.rockchip-overlays: $(src)/README.rockchip-overlays -+ $(call cmd,dtb_install) -+ - PHONY += $(subdirs) - $(subdirs): - $(Q)$(MAKE) $(dtbinst)=$@ dst=$(if $(CONFIG_ARCH_WANT_FLAT_DTB_INSTALL),$(dst),$(patsubst $(obj)/%,$(dst)/%,$@)) -diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib -index 68d0134bdbf9..9ea801a22569 100644 ---- a/scripts/Makefile.lib -+++ b/scripts/Makefile.lib -@@ -343,6 +343,9 @@ DTC ?= $(objtree)/scripts/dtc/dtc - DTC_FLAGS += -Wno-interrupt_provider \ - -Wno-unique_unit_address - -+# Overlay support -+DTC_FLAGS += -@ -Wno-unit_address_format -Wno-simple_bus_reg -+ - # Disable noisy checks by default - ifeq ($(findstring 1,$(KBUILD_EXTRA_WARN)),) - DTC_FLAGS += -Wno-unit_address_vs_reg \ -@@ -421,6 +424,23 @@ $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE - $(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE - $(call if_changed_dep,dtc) - -+quiet_cmd_dtco = DTCO $@ -+cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \ -+ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ -+ $(DTC) -O dtb -o $@ -b 0 \ -+ -i $(dir $<) $(DTC_FLAGS) \ -+ -d $(depfile).dtc.tmp $(dtc-tmp) ; \ -+ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) -+ -+$(obj)/%.dtbo: $(src)/%.dts FORCE -+ $(call if_changed_dep,dtco) -+ -+quiet_cmd_scr = MKIMAGE $@ -+cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ -+ -+$(obj)/%.scr: $(src)/%.scr-cmd FORCE -+ $(call if_changed,scr) -+ - dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) - - # Bzip2 --- -Armbian - diff --git a/patch/kernel/archive/rockchip64-6.8/0000.patching_config.yaml b/patch/kernel/archive/rockchip64-6.9/0000.patching_config.yaml similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/0000.patching_config.yaml rename to patch/kernel/archive/rockchip64-6.9/0000.patching_config.yaml diff --git a/patch/kernel/archive/rockchip64-6.8/add-board-helios64.patch b/patch/kernel/archive/rockchip64-6.9/add-board-helios64.patch.disabled similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/add-board-helios64.patch rename to patch/kernel/archive/rockchip64-6.9/add-board-helios64.patch.disabled diff --git a/patch/kernel/archive/rockchip64-6.8/board-firefly-rk3399-dts.patch b/patch/kernel/archive/rockchip64-6.9/board-firefly-rk3399-dts.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-firefly-rk3399-dts.patch rename to patch/kernel/archive/rockchip64-6.9/board-firefly-rk3399-dts.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-helios64-dts-fix-stability-issues.patch b/patch/kernel/archive/rockchip64-6.9/board-helios64-dts-fix-stability-issues.patch.disabled similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-helios64-dts-fix-stability-issues.patch rename to patch/kernel/archive/rockchip64-6.9/board-helios64-dts-fix-stability-issues.patch.disabled diff --git a/patch/kernel/archive/rockchip64-6.8/board-helios64-remove-overclock.patch b/patch/kernel/archive/rockchip64-6.9/board-helios64-remove-overclock.patch.disabled similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-helios64-remove-overclock.patch rename to patch/kernel/archive/rockchip64-6.9/board-helios64-remove-overclock.patch.disabled diff --git a/patch/kernel/archive/rockchip64-6.8/board-helios64-remove-pcie-ep-gpios.patch b/patch/kernel/archive/rockchip64-6.9/board-helios64-remove-pcie-ep-gpios.patch.disabled similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-helios64-remove-pcie-ep-gpios.patch rename to patch/kernel/archive/rockchip64-6.9/board-helios64-remove-pcie-ep-gpios.patch.disabled diff --git a/patch/kernel/archive/rockchip64-6.8/board-nanopc-t4-add-typec-dp.patch b/patch/kernel/archive/rockchip64-6.9/board-nanopc-t4-add-typec-dp.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-nanopc-t4-add-typec-dp.patch rename to patch/kernel/archive/rockchip64-6.9/board-nanopc-t4-add-typec-dp.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-nanopi-m4v2-dts-add-sound-card.patch b/patch/kernel/archive/rockchip64-6.9/board-nanopi-m4v2-dts-add-sound-card.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-nanopi-m4v2-dts-add-sound-card.patch rename to patch/kernel/archive/rockchip64-6.9/board-nanopi-m4v2-dts-add-sound-card.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-nanopi-r2c-plus.patch b/patch/kernel/archive/rockchip64-6.9/board-nanopi-r2c-plus.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-nanopi-r2c-plus.patch rename to patch/kernel/archive/rockchip64-6.9/board-nanopi-r2c-plus.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-nanopi-r2s.patch b/patch/kernel/archive/rockchip64-6.9/board-nanopi-r2s.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-nanopi-r2s.patch rename to patch/kernel/archive/rockchip64-6.9/board-nanopi-r2s.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-nanopi-r4s-pwmfan.patch b/patch/kernel/archive/rockchip64-6.9/board-nanopi-r4s-pwmfan.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-nanopi-r4s-pwmfan.patch rename to patch/kernel/archive/rockchip64-6.9/board-nanopi-r4s-pwmfan.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-orangepi-r1-plus.patch b/patch/kernel/archive/rockchip64-6.9/board-orangepi-r1-plus.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-orangepi-r1-plus.patch rename to patch/kernel/archive/rockchip64-6.9/board-orangepi-r1-plus.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-orangepi-rk3399-pcie.patch b/patch/kernel/archive/rockchip64-6.9/board-orangepi-rk3399-pcie.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-orangepi-rk3399-pcie.patch rename to patch/kernel/archive/rockchip64-6.9/board-orangepi-rk3399-pcie.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-pbp-add-dp-alt-mode.patch b/patch/kernel/archive/rockchip64-6.9/board-pbp-add-dp-alt-mode.patch similarity index 94% rename from patch/kernel/archive/rockchip64-6.8/board-pbp-add-dp-alt-mode.patch rename to patch/kernel/archive/rockchip64-6.9/board-pbp-add-dp-alt-mode.patch index 2b576b0a03d7..6e29666c547e 100644 --- a/patch/kernel/archive/rockchip64-6.8/board-pbp-add-dp-alt-mode.patch +++ b/patch/kernel/archive/rockchip64-6.9/board-pbp-add-dp-alt-mode.patch @@ -186,10 +186,10 @@ index d962f67c95ae..5ac809870867 100644 #include #include #include -@@ -492,6 +493,12 @@ struct tcpm_port { - * transitions. +@@ -552,6 +552,12 @@ struct tcpm_port { */ - bool potential_contaminant; + unsigned int message_id_prime; + unsigned int rx_msgid_prime; + +#ifdef CONFIG_EXTCON + struct extcon_dev *extcon; @@ -262,18 +262,20 @@ index d962f67c95ae..5ac809870867 100644 } port->partner_altmode[i] = altmode; } -@@ -1717,9 +1757,11 @@ static int tcpm_pd_svdm(struct tcpm_port *port, struct typec_altmode *adev, - modep->svid_index++; - if (modep->svid_index < modep->nsvids) { - u16 svid = modep->svids[modep->svid_index]; -+ tcpm_log(port, "More modes available, sending discover"); - response[0] = VDO(svid, 1, svdm_version, CMD_DISCOVER_MODES); - rlen = 1; - } else { -+ tcpm_log(port, "Got all patner modes, registering"); - tcpm_register_partner_altmodes(port); - } - break; +@@ -2167,11 +2173,13 @@ static int tcpm_pd_svdm(struct tcpm_port *port, struct typec_altmode *adev, + modep->svid_index++; + if (modep->svid_index < modep->nsvids) { + u16 svid = modep->svids[modep->svid_index]; ++ tcpm_log(port, "More modes available, sending discover"); + *response_tx_sop_type = TCPC_TX_SOP; + response[0] = VDO(svid, 1, svdm_version, + CMD_DISCOVER_MODES); + rlen = 1; + } else if (tcpm_cable_vdm_supported(port)) { ++ tcpm_log(port, "Got all patner modes, registering"); + *response_tx_sop_type = TCPC_TX_SOP_PRIME; + response[0] = VDO(USB_SID_PD, 1, + typec_get_cable_svdm_version(typec), @@ -3650,8 +3692,9 @@ static int tcpm_src_attach(struct tcpm_port *port) static void tcpm_typec_disconnect(struct tcpm_port *port) { @@ -416,3 +418,4 @@ index d962f67c95ae..5ac809870867 100644 -- Armbian + diff --git a/patch/kernel/archive/rockchip64-6.8/board-radxa-e25-sdmmc0-fix.patch b/patch/kernel/archive/rockchip64-6.9/board-radxa-e25-sdmmc0-fix.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-radxa-e25-sdmmc0-fix.patch rename to patch/kernel/archive/rockchip64-6.9/board-radxa-e25-sdmmc0-fix.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-radxa-e25-usb3-and-emmc-fix.patch b/patch/kernel/archive/rockchip64-6.9/board-radxa-e25-usb3-and-emmc-fix.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-radxa-e25-usb3-and-emmc-fix.patch rename to patch/kernel/archive/rockchip64-6.9/board-radxa-e25-usb3-and-emmc-fix.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rk3328-roc-cc-dts-enable-dmc.patch b/patch/kernel/archive/rockchip64-6.9/board-rk3328-roc-cc-dts-enable-dmc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rk3328-roc-cc-dts-enable-dmc.patch rename to patch/kernel/archive/rockchip64-6.9/board-rk3328-roc-cc-dts-enable-dmc.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rk3328-roc-cc-dts-ram-profile.patch b/patch/kernel/archive/rockchip64-6.9/board-rk3328-roc-cc-dts-ram-profile.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rk3328-roc-cc-dts-ram-profile.patch rename to patch/kernel/archive/rockchip64-6.9/board-rk3328-roc-cc-dts-ram-profile.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rk3328-roc-pc-dts-ram-profile.patch b/patch/kernel/archive/rockchip64-6.9/board-rk3328-roc-pc-dts-ram-profile.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rk3328-roc-pc-dts-ram-profile.patch rename to patch/kernel/archive/rockchip64-6.9/board-rk3328-roc-pc-dts-ram-profile.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rk3328-roc-pc.patch b/patch/kernel/archive/rockchip64-6.9/board-rk3328-roc-pc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rk3328-roc-pc.patch rename to patch/kernel/archive/rockchip64-6.9/board-rk3328-roc-pc.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rock3a-emmc-sfc.patch b/patch/kernel/archive/rockchip64-6.9/board-rock3a-emmc-sfc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rock3a-emmc-sfc.patch rename to patch/kernel/archive/rockchip64-6.9/board-rock3a-emmc-sfc.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rock3a-usb3.patch b/patch/kernel/archive/rockchip64-6.9/board-rock3a-usb3.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rock3a-usb3.patch rename to patch/kernel/archive/rockchip64-6.9/board-rock3a-usb3.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rock64-mail-supply.patch b/patch/kernel/archive/rockchip64-6.9/board-rock64-mail-supply.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rock64-mail-supply.patch rename to patch/kernel/archive/rockchip64-6.9/board-rock64-mail-supply.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpi3-enable-dmc.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpi3-enable-dmc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpi3-enable-dmc.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpi3-enable-dmc.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpi4-0003-arm64-dts-pcie.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpi4-0003-arm64-dts-pcie.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpi4-0003-arm64-dts-pcie.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpi4-0003-arm64-dts-pcie.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpis-0001-arm64-dts.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpis-0001-arm64-dts.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpis-0001-arm64-dts.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpis-0001-arm64-dts.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpis-0005-arm64-dts-rk3308-Add-gmac-node-at-dtsi-level.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpis-0005-arm64-dts-rk3308-Add-gmac-node-at-dtsi-level.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpis-0005-arm64-dts-rk3308-Add-gmac-node-at-dtsi-level.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpis-0005-arm64-dts-rk3308-Add-gmac-node-at-dtsi-level.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpis-0007-arm64-dts-rockchip-add-cpu-s-thermal-config-for-rk33.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpis-0007-arm64-dts-rockchip-add-cpu-s-thermal-config-for-rk33.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpis-0007-arm64-dts-rockchip-add-cpu-s-thermal-config-for-rk33.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpis-0007-arm64-dts-rockchip-add-cpu-s-thermal-config-for-rk33.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpis-0008-thermal-rockchip-add-tsadc-support-for-rk3308.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpis-0008-thermal-rockchip-add-tsadc-support-for-rk3308.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpis-0008-thermal-rockchip-add-tsadc-support-for-rk3308.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpis-0008-thermal-rockchip-add-tsadc-support-for-rk3308.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpis-0010-arm64-dts-rockchip-add-i2s_8ch-for-rk3308.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpis-0010-arm64-dts-rockchip-add-i2s_8ch-for-rk3308.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpis-0010-arm64-dts-rockchip-add-i2s_8ch-for-rk3308.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpis-0010-arm64-dts-rockchip-add-i2s_8ch-for-rk3308.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpis-0012-arm64-dts-rk3308-Add-rk-timer-rtc.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpis-0012-arm64-dts-rk3308-Add-rk-timer-rtc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpis-0012-arm64-dts-rk3308-Add-rk-timer-rtc.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpis-0012-arm64-dts-rk3308-Add-rk-timer-rtc.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpis-0018-ASoC-codecs-Add-RK3308-internal-codec-driver.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpis-0018-ASoC-codecs-Add-RK3308-internal-codec-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpis-0018-ASoC-codecs-Add-RK3308-internal-codec-driver.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpis-0018-ASoC-codecs-Add-RK3308-internal-codec-driver.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpis-0019-Sync-rk3308_codec-to-BSP-tree.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpis-0019-Sync-rk3308_codec-to-BSP-tree.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpis-0019-Sync-rk3308_codec-to-BSP-tree.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpis-0019-Sync-rk3308_codec-to-BSP-tree.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpis-0020-arm64-dts-rockchip-Add-acodec-node-for-rk3308.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpis-0020-arm64-dts-rockchip-Add-acodec-node-for-rk3308.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpis-0020-arm64-dts-rockchip-Add-acodec-node-for-rk3308.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpis-0020-arm64-dts-rockchip-Add-acodec-node-for-rk3308.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpis-0022-ASoC-rk3308_codec-replace-codec-to-component.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpis-0022-ASoC-rk3308_codec-replace-codec-to-component.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpis-0022-ASoC-rk3308_codec-replace-codec-to-component.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpis-0022-ASoC-rk3308_codec-replace-codec-to-component.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpis-0027-arm64-dts-rk3308-add-otp-cpuinfo.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpis-0027-arm64-dts-rk3308-add-otp-cpuinfo.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpis-0027-arm64-dts-rk3308-add-otp-cpuinfo.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpis-0027-arm64-dts-rk3308-add-otp-cpuinfo.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpis-0029-arm64-dts-rk3308-add-reserved-memory-ramoops.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpis-0029-arm64-dts-rk3308-add-reserved-memory-ramoops.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpis-0029-arm64-dts-rk3308-add-reserved-memory-ramoops.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpis-0029-arm64-dts-rk3308-add-reserved-memory-ramoops.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpro64-0001-Add-pcie-bus-scan-delay.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpro64-change-rx_delay-for-gmac.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpro64-change-rx_delay-for-gmac.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpro64-change-rx_delay-for-gmac.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpro64-change-rx_delay-for-gmac.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpro64-fix-emmc.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpro64-fix-emmc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpro64-fix-emmc.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpro64-fix-emmc.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpro64-fix-spi1-flash-speed.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpro64-fix-spi1-flash-speed.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpro64-fix-spi1-flash-speed.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpro64-fix-spi1-flash-speed.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rockpro64-work-led-heartbeat.patch b/patch/kernel/archive/rockchip64-6.9/board-rockpro64-work-led-heartbeat.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rockpro64-work-led-heartbeat.patch rename to patch/kernel/archive/rockchip64-6.9/board-rockpro64-work-led-heartbeat.patch diff --git a/patch/kernel/archive/rockchip64-6.8/board-rocks0-0001-deviceTree.patch b/patch/kernel/archive/rockchip64-6.9/board-rocks0-0001-deviceTree.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/board-rocks0-0001-deviceTree.patch rename to patch/kernel/archive/rockchip64-6.9/board-rocks0-0001-deviceTree.patch diff --git a/patch/kernel/archive/rockchip64-6.8/drv-spi-spidev-remove-warnings.patch b/patch/kernel/archive/rockchip64-6.9/drv-spi-spidev-remove-warnings.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/drv-spi-spidev-remove-warnings.patch rename to patch/kernel/archive/rockchip64-6.9/drv-spi-spidev-remove-warnings.patch diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3308-sakurapi-rk3308b.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3308-sakurapi-rk3308b.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3308-sakurapi-rk3308b.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3308-sakurapi-rk3308b.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3318-box.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3318-box.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3318-box.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3318-box.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3328-nanopi-neo3-rev02.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3328-nanopi-neo3-rev02.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3328-nanopi-neo3-rev02.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3328-nanopi-neo3-rev02.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3328-nanopi-r2-rev00.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3328-nanopi-r2-rev00.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3328-nanopi-r2-rev00.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3328-nanopi-r2-rev00.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3328-nanopi-r2-rev06.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3328-nanopi-r2-rev06.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3328-nanopi-r2-rev06.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3328-nanopi-r2-rev06.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3328-nanopi-r2-rev20.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3328-nanopi-r2-rev20.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3328-nanopi-r2-rev20.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3328-nanopi-r2-rev20.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3328-orangepi-r1-plus-lts.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3328-orangepi-r1-plus-lts.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3328-orangepi-r1-plus-lts.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3328-orangepi-r1-plus-lts.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3328-z28pro.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3328-z28pro.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3328-z28pro.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3328-z28pro.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3399-nanopi-m4v2.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3399-nanopi-m4v2.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3399-nanopi-m4v2.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3399-nanopi-m4v2.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3399-nanopi-r4se.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3399-nanopi-r4se.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3399-nanopi-r4se.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3399-nanopi-r4se.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3399-orangepi-4-lts.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3399-orangepi-4-lts.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3399-orangepi-4-lts.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3399-orangepi-4-lts.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3399-orangepi-4.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3399-orangepi-4.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3399-orangepi-4.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3399-orangepi-4.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3399-rock-pi-4.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3399-rock-pi-4.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3399-rock-pi-4.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3399-rock-pi-4.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3399-rock-pi-4c.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3399-rock-pi-4c.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3399-rock-pi-4c.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3399-rock-pi-4c.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3399-tinker-2.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3399-tinker-2.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3399-tinker-2.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3399-tinker-2.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3399pro-tinker-edge-r.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3399pro-tinker-edge-r.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3399pro-tinker-edge-r.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3399pro-tinker-edge-r.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3566-firefly-roc-pc.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3566-firefly-roc-pc.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3566-firefly-roc-pc.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3566-firefly-roc-pc.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3566-jp-tvbox.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3566-jp-tvbox.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3566-jp-tvbox.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3566-jp-tvbox.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3566-orangepi-3b-sata.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3566-orangepi-3b-sata.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3566-orangepi-3b-sata.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3566-orangepi-3b-sata.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3566-orangepi-3b.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3566-orangepi-3b.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3566-orangepi-3b.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3566-orangepi-3b.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3566-panther-x2.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3566-panther-x2.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3566-panther-x2.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3566-panther-x2.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3566-rock-3c.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3566-rock-3c.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3566-rock-3c.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3566-rock-3c.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3568-hinlink-h66k.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3568-hinlink-h66k.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3568-hinlink-h66k.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3568-hinlink-h66k.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3568-hinlink-h68k.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3568-hinlink-h68k.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3568-hinlink-h68k.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3568-hinlink-h68k.dts diff --git a/patch/kernel/archive/rockchip64-6.8/dt/rk3568-odroid-m1.dts b/patch/kernel/archive/rockchip64-6.9/dt/rk3568-odroid-m1.dts similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/dt/rk3568-odroid-m1.dts rename to patch/kernel/archive/rockchip64-6.9/dt/rk3568-odroid-m1.dts diff --git a/patch/kernel/archive/rockchip64-6.8/general-add-miniDP-dt-doc.patch b/patch/kernel/archive/rockchip64-6.9/general-add-miniDP-dt-doc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-add-miniDP-dt-doc.patch rename to patch/kernel/archive/rockchip64-6.9/general-add-miniDP-dt-doc.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-add-miniDP-virtual-extcon.patch b/patch/kernel/archive/rockchip64-6.9/general-add-miniDP-virtual-extcon.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-add-miniDP-virtual-extcon.patch rename to patch/kernel/archive/rockchip64-6.9/general-add-miniDP-virtual-extcon.patch diff --git a/patch/kernel/archive/rockchip64-6.9/general-add-overlay-compilation-support.patch b/patch/kernel/archive/rockchip64-6.9/general-add-overlay-compilation-support.patch new file mode 100644 index 000000000000..b2e233f4dda4 --- /dev/null +++ b/patch/kernel/archive/rockchip64-6.9/general-add-overlay-compilation-support.patch @@ -0,0 +1,69 @@ +From 088e1cd9b9dd113f0a5e9e19a7f31c37532e002a Mon Sep 17 00:00:00 2001 +From: Paolo Sabatino +Date: Sun, 2 Jun 2024 21:53:01 +0200 +Subject: [PATCH] compile .scr and install overlays in right path + +--- + scripts/Makefile.dtbinst | 2 +- + scripts/Makefile.lib | 8 +++++++- + 2 files changed, 8 insertions(+), 2 deletions(-) + +diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst +index 67956f6496a5..151687728a60 100644 +--- a/scripts/Makefile.dtbinst ++++ b/scripts/Makefile.dtbinst +@@ -33,7 +33,18 @@ endef + + $(foreach d, $(sort $(dir $(dtbs))), $(eval $(call gen_install_rules,$(d)))) + +-dtbs := $(notdir $(dtbs)) ++# Very convoluted way to flatten all the device tree ++# directories, but keep the "/overlay/" directory ++ ++# topmost directory (ie: from rockchip/overlay/rk322x-emmc.dtbo extracts rockchip) ++topmost_dir = $(firstword $(subst /, ,$(dtbs))) ++# collect dtbs entries which starts with "$topmost_dir/overlay/", then remove "$topmost_dir" ++dtbs_overlays = $(subst $(topmost_dir)/,,$(filter $(topmost_dir)/overlay/%, $(dtbs))) ++# collect the non-overlay dtbs ++dtbs_regular = $(filter-out $(topmost_dir)/overlay/%, $(dtbs)) ++# compose the dtbs variable flattening all the non-overlays entries ++# and appending the overlays entries ++dtbs := $(notdir $(dtbs_regular)) $(dtbs_overlays) + + endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL + +diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib +index 3179747cbd2c..59925208734a 100644 +--- a/scripts/Makefile.lib ++++ b/scripts/Makefile.lib +@@ -398,7 +398,7 @@ $(obj)/%.dtbo.S: $(obj)/%.dtbo FORCE + + quiet_cmd_dtc = DTC $@ + cmd_dtc = $(HOSTCC) -E $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ +- $(DTC) -o $@ -b 0 \ ++ $(DTC) -@ -o $@ -b 0 \ + $(addprefix -i,$(dir $<) $(DTC_INCLUDE)) $(DTC_FLAGS) \ + -d $(depfile).dtc.tmp $(dtc-tmp) ; \ + cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) +@@ -423,12 +423,18 @@ quiet_cmd_dtb = $(quiet_cmd_dtc) + cmd_dtb = $(cmd_dtc) + endif + ++quiet_cmd_scr = MKIMAGE $@ ++cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@ ++ + $(obj)/%.dtb: $(src)/%.dts $(DTC) $(DT_TMP_SCHEMA) FORCE + $(call if_changed_dep,dtb) + + $(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE + $(call if_changed_dep,dtc) + ++$(obj)/%.scr: $(src)/%.scr-cmd FORCE ++ $(call if_changed,scr) ++ + dtc-tmp = $(subst $(comma),_,$(dot-target).dts.tmp) + + # Bzip2 +-- +2.34.1 + diff --git a/patch/kernel/archive/rockchip64-6.8/general-add-overlay-configfs.patch b/patch/kernel/archive/rockchip64-6.9/general-add-overlay-configfs.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-add-overlay-configfs.patch rename to patch/kernel/archive/rockchip64-6.9/general-add-overlay-configfs.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-add-panel-simple-dsi.patch b/patch/kernel/archive/rockchip64-6.9/general-add-panel-simple-dsi.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-add-panel-simple-dsi.patch rename to patch/kernel/archive/rockchip64-6.9/general-add-panel-simple-dsi.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-add-pll-hdmi-timings.patch b/patch/kernel/archive/rockchip64-6.9/general-add-pll-hdmi-timings.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-add-pll-hdmi-timings.patch rename to patch/kernel/archive/rockchip64-6.9/general-add-pll-hdmi-timings.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-add-xtx-spi-nor-chips.patch b/patch/kernel/archive/rockchip64-6.9/general-add-xtx-spi-nor-chips.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-add-xtx-spi-nor-chips.patch rename to patch/kernel/archive/rockchip64-6.9/general-add-xtx-spi-nor-chips.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-cryptov1-trng.patch b/patch/kernel/archive/rockchip64-6.9/general-cryptov1-trng.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-cryptov1-trng.patch rename to patch/kernel/archive/rockchip64-6.9/general-cryptov1-trng.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-disable-mtu-validation.patch b/patch/kernel/archive/rockchip64-6.9/general-disable-mtu-validation.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-disable-mtu-validation.patch rename to patch/kernel/archive/rockchip64-6.9/general-disable-mtu-validation.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-fix-es8316-kernel-panic.patch b/patch/kernel/archive/rockchip64-6.9/general-fix-es8316-kernel-panic.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-fix-es8316-kernel-panic.patch rename to patch/kernel/archive/rockchip64-6.9/general-fix-es8316-kernel-panic.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-fix-inno-usb2-phy-init.patch b/patch/kernel/archive/rockchip64-6.9/general-fix-inno-usb2-phy-init.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-fix-inno-usb2-phy-init.patch rename to patch/kernel/archive/rockchip64-6.9/general-fix-inno-usb2-phy-init.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-fix-mmc-signal-voltage-before-reboot.patch b/patch/kernel/archive/rockchip64-6.9/general-fix-mmc-signal-voltage-before-reboot.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-fix-mmc-signal-voltage-before-reboot.patch rename to patch/kernel/archive/rockchip64-6.9/general-fix-mmc-signal-voltage-before-reboot.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-hdmi-clock-fixes.patch b/patch/kernel/archive/rockchip64-6.9/general-hdmi-clock-fixes.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-hdmi-clock-fixes.patch rename to patch/kernel/archive/rockchip64-6.9/general-hdmi-clock-fixes.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-increasing_DMA_block_memory_allocation_to_2048.patch b/patch/kernel/archive/rockchip64-6.9/general-increasing_DMA_block_memory_allocation_to_2048.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-increasing_DMA_block_memory_allocation_to_2048.patch rename to patch/kernel/archive/rockchip64-6.9/general-increasing_DMA_block_memory_allocation_to_2048.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-legacy-rockchip-hwrng.patch b/patch/kernel/archive/rockchip64-6.9/general-legacy-rockchip-hwrng.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-legacy-rockchip-hwrng.patch rename to patch/kernel/archive/rockchip64-6.9/general-legacy-rockchip-hwrng.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-legacy-rockchip-hwrng_5.10.patch b/patch/kernel/archive/rockchip64-6.9/general-legacy-rockchip-hwrng_5.10.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-legacy-rockchip-hwrng_5.10.patch rename to patch/kernel/archive/rockchip64-6.9/general-legacy-rockchip-hwrng_5.10.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-possibility-of-disabling-rk808-rtc.patch b/patch/kernel/archive/rockchip64-6.9/general-possibility-of-disabling-rk808-rtc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-possibility-of-disabling-rk808-rtc.patch rename to patch/kernel/archive/rockchip64-6.9/general-possibility-of-disabling-rk808-rtc.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-rk3328-dtsi-trb-ent-quirk.patch b/patch/kernel/archive/rockchip64-6.9/general-rk3328-dtsi-trb-ent-quirk.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-rk3328-dtsi-trb-ent-quirk.patch rename to patch/kernel/archive/rockchip64-6.9/general-rk3328-dtsi-trb-ent-quirk.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-rk808-configurable-switch-voltage-steps.patch b/patch/kernel/archive/rockchip64-6.9/general-rk808-configurable-switch-voltage-steps.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-rk808-configurable-switch-voltage-steps.patch rename to patch/kernel/archive/rockchip64-6.9/general-rk808-configurable-switch-voltage-steps.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-rockchip-overlays.patch b/patch/kernel/archive/rockchip64-6.9/general-rockchip-overlays.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-rockchip-overlays.patch rename to patch/kernel/archive/rockchip64-6.9/general-rockchip-overlays.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-rt5651-add-mclk.patch b/patch/kernel/archive/rockchip64-6.9/general-rt5651-add-mclk.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-rt5651-add-mclk.patch rename to patch/kernel/archive/rockchip64-6.9/general-rt5651-add-mclk.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-v4l2-iep-driver.patch b/patch/kernel/archive/rockchip64-6.9/general-v4l2-iep-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-v4l2-iep-driver.patch rename to patch/kernel/archive/rockchip64-6.9/general-v4l2-iep-driver.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-v4l2-rkvdec-00-fixes.patch b/patch/kernel/archive/rockchip64-6.9/general-v4l2-rkvdec-00-fixes.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-v4l2-rkvdec-00-fixes.patch rename to patch/kernel/archive/rockchip64-6.9/general-v4l2-rkvdec-00-fixes.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-v4l2-rkvdec-01-vp9.patch b/patch/kernel/archive/rockchip64-6.9/general-v4l2-rkvdec-01-vp9.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-v4l2-rkvdec-01-vp9.patch rename to patch/kernel/archive/rockchip64-6.9/general-v4l2-rkvdec-01-vp9.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-v4l2-rkvdec-02-hevc.patch b/patch/kernel/archive/rockchip64-6.9/general-v4l2-rkvdec-02-hevc.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-v4l2-rkvdec-02-hevc.patch rename to patch/kernel/archive/rockchip64-6.9/general-v4l2-rkvdec-02-hevc.patch diff --git a/patch/kernel/archive/rockchip64-6.8/general-workaround-broadcom-bt-serdev.patch b/patch/kernel/archive/rockchip64-6.9/general-workaround-broadcom-bt-serdev.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/general-workaround-broadcom-bt-serdev.patch rename to patch/kernel/archive/rockchip64-6.9/general-workaround-broadcom-bt-serdev.patch diff --git a/patch/kernel/archive/rockchip64-6.8/kernel-6.8-tools-cgroup-makefile.patch b/patch/kernel/archive/rockchip64-6.9/kernel-6.8-tools-cgroup-makefile.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/kernel-6.8-tools-cgroup-makefile.patch rename to patch/kernel/archive/rockchip64-6.9/kernel-6.8-tools-cgroup-makefile.patch diff --git a/patch/kernel/archive/rockchip64-6.8/media-0001-dma-mapping-let-dma_alloc_noncontiguous-allow-DMA_AT.patch b/patch/kernel/archive/rockchip64-6.9/media-0001-dma-mapping-let-dma_alloc_noncontiguous-allow-DMA_AT.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/media-0001-dma-mapping-let-dma_alloc_noncontiguous-allow-DMA_AT.patch rename to patch/kernel/archive/rockchip64-6.9/media-0001-dma-mapping-let-dma_alloc_noncontiguous-allow-DMA_AT.patch diff --git a/patch/kernel/archive/rockchip64-6.8/media-0002-Enable-non-coherent-dst-bufs-for-Hantro-V4L2-driver.patch b/patch/kernel/archive/rockchip64-6.9/media-0002-Enable-non-coherent-dst-bufs-for-Hantro-V4L2-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/media-0002-Enable-non-coherent-dst-bufs-for-Hantro-V4L2-driver.patch rename to patch/kernel/archive/rockchip64-6.9/media-0002-Enable-non-coherent-dst-bufs-for-Hantro-V4L2-driver.patch diff --git a/patch/kernel/archive/rockchip64-6.8/media-0003-Enable-non-coherent-dst-bufs-for-Rkvdec-V4L2-driver.patch b/patch/kernel/archive/rockchip64-6.9/media-0003-Enable-non-coherent-dst-bufs-for-Rkvdec-V4L2-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/media-0003-Enable-non-coherent-dst-bufs-for-Rkvdec-V4L2-driver.patch rename to patch/kernel/archive/rockchip64-6.9/media-0003-Enable-non-coherent-dst-bufs-for-Rkvdec-V4L2-driver.patch diff --git a/patch/kernel/archive/rockchip64-6.8/net-usb-r8152-add-LED-configuration-from-OF.patch b/patch/kernel/archive/rockchip64-6.9/net-usb-r8152-add-LED-configuration-from-OF.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/net-usb-r8152-add-LED-configuration-from-OF.patch rename to patch/kernel/archive/rockchip64-6.9/net-usb-r8152-add-LED-configuration-from-OF.patch diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/Makefile b/patch/kernel/archive/rockchip64-6.9/overlay/Makefile similarity index 94% rename from patch/kernel/archive/rockchip64-6.8/overlay/Makefile rename to patch/kernel/archive/rockchip64-6.9/overlay/Makefile index c6bfcdb71501..0d2893349f50 100644 --- a/patch/kernel/archive/rockchip64-6.8/overlay/Makefile +++ b/patch/kernel/archive/rockchip64-6.9/overlay/Makefile @@ -50,8 +50,7 @@ scr-$(CONFIG_ARCH_ROCKCHIP) += \ dtbotxt-$(CONFIG_ARCH_ROCKCHIP) += \ README.rockchip-overlays -targets += $(dtbo-y) $(scr-y) $(dtbotxt-y) +dtb-y += $(dtbo-y) $(scr-y) $(dtbotxt-y) -always := $(dtbo-y) $(scr-y) $(dtbotxt-y) clean-files := *.dtbo *.scr diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/README.rockchip-overlays b/patch/kernel/archive/rockchip64-6.9/overlay/README.rockchip-overlays similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/README.rockchip-overlays rename to patch/kernel/archive/rockchip64-6.9/overlay/README.rockchip-overlays diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rk3308-b@1.3ghz.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rk3308-b@1.3ghz.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rk3308-b@1.3ghz.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rk3308-b@1.3ghz.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rk3308-bs.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rk3308-bs.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rk3308-bs.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rk3308-bs.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rk3308-bs@1.3ghz.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rk3308-bs@1.3ghz.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rk3308-bs@1.3ghz.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rk3308-bs@1.3ghz.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rk3308-emmc.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rk3308-emmc.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rk3308-emmc.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rk3308-emmc.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rk3308-s0-ext-antenna.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rk3308-s0-ext-antenna.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rk3308-s0-ext-antenna.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rk3308-s0-ext-antenna.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rk3308-sdio@10mhz.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rk3308-sdio@10mhz.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rk3308-sdio@10mhz.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rk3308-sdio@10mhz.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rk3308-sdio@4mhz.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rk3308-sdio@4mhz.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rk3308-sdio@4mhz.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rk3308-sdio@4mhz.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-fixup.scr-cmd b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-fixup.scr-cmd similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-fixup.scr-cmd rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-fixup.scr-cmd diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-cpu-hs.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-cpu-hs.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-cpu-hs.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-cpu-hs.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-emmc-ddr.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-emmc-ddr.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-emmc-ddr.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-emmc-ddr.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-emmc-hs200.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-emmc-hs200.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-emmc-hs200.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-emmc-hs200.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-led-conf1.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-led-conf1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-led-conf1.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-led-conf1.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-led-conf2.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-led-conf2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-led-conf2.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-led-conf2.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-led-conf3.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-led-conf3.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-led-conf3.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-led-conf3.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-led-conf4.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-led-conf4.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-led-conf4.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-led-conf4.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-wlan-ap6330.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-wlan-ap6330.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-wlan-ap6330.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-wlan-ap6330.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-wlan-ap6334.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-wlan-ap6334.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-wlan-ap6334.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-wlan-ap6334.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-wlan-ext.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-wlan-ext.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3318-box-wlan-ext.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3318-box-wlan-ext.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3328-i2c0.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3328-i2c0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3328-i2c0.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3328-i2c0.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3328-i2s1-pcm5102.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3328-i2s1-pcm5102.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3328-i2s1-pcm5102.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3328-i2s1-pcm5102.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3328-opp-1.4ghz.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3328-opp-1.4ghz.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3328-opp-1.4ghz.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3328-opp-1.4ghz.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3328-opp-1.5ghz.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3328-opp-1.5ghz.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3328-opp-1.5ghz.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3328-opp-1.5ghz.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3328-uart1.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3328-uart1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3328-uart1.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3328-uart1.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-dwc3-0-host.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-dwc3-0-host.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-dwc3-0-host.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-dwc3-0-host.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-i2c7.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-i2c7.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-i2c7.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-i2c7.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-i2c8.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-i2c8.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-i2c8.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-i2c8.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-opp-2ghz.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-opp-2ghz.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-opp-2ghz.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-opp-2ghz.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-pcie-gen2.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-pcie-gen2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-pcie-gen2.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-pcie-gen2.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-spi-jedec-nor.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-spi-jedec-nor.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-spi-jedec-nor.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-spi-jedec-nor.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-spi-spidev.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-spi-spidev.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-spi-spidev.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-spi-spidev.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-uart4.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-uart4.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-uart4.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-uart4.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-w1-gpio.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-w1-gpio.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3399-w1-gpio.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3399-w1-gpio.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3566-sata2.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3566-sata2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3566-sata2.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3566-sata2.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-i2c0.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-i2c0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-i2c0.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-i2c0.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-i2c1.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-i2c1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-i2c1.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-i2c1.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-pwm1.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-pwm1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-pwm1.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-pwm1.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-pwm2.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-pwm2.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-pwm2.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-pwm2.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-pwm9.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-pwm9.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-pwm9.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-pwm9.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-spi-spidev.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-spi-spidev.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-spi-spidev.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-spi-spidev.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-uart0-rts_cts.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-uart0-rts_cts.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-uart0-rts_cts.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-uart0-rts_cts.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-uart0.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-uart0.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-uart0.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-uart0.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-uart1.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-uart1.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-hk-uart1.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-hk-uart1.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-nanopi-r5c-leds.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-nanopi-r5c-leds.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-nanopi-r5c-leds.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-nanopi-r5c-leds.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-nanopi-r5s-leds.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-nanopi-r5s-leds.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rk3568-nanopi-r5s-leds.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rk3568-nanopi-r5s-leds.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rockpi4cplus-usb-host.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rockpi4cplus-usb-host.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rockpi4cplus-usb-host.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rockpi4cplus-usb-host.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rockpro64-lcd.dts b/patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rockpro64-lcd.dtso similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/overlay/rockchip-rockpro64-lcd.dts rename to patch/kernel/archive/rockchip64-6.9/overlay/rockchip-rockpro64-lcd.dtso diff --git a/patch/kernel/archive/rockchip64-6.8/regulator-add-fan53200-driver.patch b/patch/kernel/archive/rockchip64-6.9/regulator-add-fan53200-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/regulator-add-fan53200-driver.patch rename to patch/kernel/archive/rockchip64-6.9/regulator-add-fan53200-driver.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3308-0001-pinctrl-slew-mux.patch b/patch/kernel/archive/rockchip64-6.9/rk3308-0001-pinctrl-slew-mux.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3308-0001-pinctrl-slew-mux.patch rename to patch/kernel/archive/rockchip64-6.9/rk3308-0001-pinctrl-slew-mux.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3308-0002-iodomains.patch b/patch/kernel/archive/rockchip64-6.9/rk3308-0002-iodomains.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3308-0002-iodomains.patch rename to patch/kernel/archive/rockchip64-6.9/rk3308-0002-iodomains.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3308-0003-pinctrl-io-voltage-domains.patch b/patch/kernel/archive/rockchip64-6.9/rk3308-0003-pinctrl-io-voltage-domains.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3308-0003-pinctrl-io-voltage-domains.patch rename to patch/kernel/archive/rockchip64-6.9/rk3308-0003-pinctrl-io-voltage-domains.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3328-add-dmc-driver.patch b/patch/kernel/archive/rockchip64-6.9/rk3328-add-dmc-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3328-add-dmc-driver.patch rename to patch/kernel/archive/rockchip64-6.9/rk3328-add-dmc-driver.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3328-add-rga-node.patch b/patch/kernel/archive/rockchip64-6.9/rk3328-add-rga-node.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3328-add-rga-node.patch rename to patch/kernel/archive/rockchip64-6.9/rk3328-add-rga-node.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3328-dtsi-mali-opp-table.patch b/patch/kernel/archive/rockchip64-6.9/rk3328-dtsi-mali-opp-table.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3328-dtsi-mali-opp-table.patch rename to patch/kernel/archive/rockchip64-6.9/rk3328-dtsi-mali-opp-table.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3328-dtsi-mmc-reset-properties.patch b/patch/kernel/archive/rockchip64-6.9/rk3328-dtsi-mmc-reset-properties.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3328-dtsi-mmc-reset-properties.patch rename to patch/kernel/archive/rockchip64-6.9/rk3328-dtsi-mmc-reset-properties.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3328-dtsi-sdmmc-ext-node.patch b/patch/kernel/archive/rockchip64-6.9/rk3328-dtsi-sdmmc-ext-node.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3328-dtsi-sdmmc-ext-node.patch rename to patch/kernel/archive/rockchip64-6.9/rk3328-dtsi-sdmmc-ext-node.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3328-dtsi-spdif.patch b/patch/kernel/archive/rockchip64-6.9/rk3328-dtsi-spdif.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3328-dtsi-spdif.patch rename to patch/kernel/archive/rockchip64-6.9/rk3328-dtsi-spdif.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3328-dtsi-usb3-reset-properties.patch b/patch/kernel/archive/rockchip64-6.9/rk3328-dtsi-usb3-reset-properties.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3328-dtsi-usb3-reset-properties.patch rename to patch/kernel/archive/rockchip64-6.9/rk3328-dtsi-usb3-reset-properties.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3328-gpu-cooling-target.patch b/patch/kernel/archive/rockchip64-6.9/rk3328-gpu-cooling-target.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3328-gpu-cooling-target.patch rename to patch/kernel/archive/rockchip64-6.9/rk3328-gpu-cooling-target.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3328-roc-cc-add-missing-nodes.patch b/patch/kernel/archive/rockchip64-6.9/rk3328-roc-cc-add-missing-nodes.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3328-roc-cc-add-missing-nodes.patch rename to patch/kernel/archive/rockchip64-6.9/rk3328-roc-cc-add-missing-nodes.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3399-add-sclk-i2sout-src-clock.patch b/patch/kernel/archive/rockchip64-6.9/rk3399-add-sclk-i2sout-src-clock.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3399-add-sclk-i2sout-src-clock.patch rename to patch/kernel/archive/rockchip64-6.9/rk3399-add-sclk-i2sout-src-clock.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3399-dmc-polling-rate.patch b/patch/kernel/archive/rockchip64-6.9/rk3399-dmc-polling-rate.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3399-dmc-polling-rate.patch rename to patch/kernel/archive/rockchip64-6.9/rk3399-dmc-polling-rate.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch b/patch/kernel/archive/rockchip64-6.9/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch rename to patch/kernel/archive/rockchip64-6.9/rk3399-enable-dwc3-xhci-usb-trb-quirk.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3399-fix-pci-phy.patch b/patch/kernel/archive/rockchip64-6.9/rk3399-fix-pci-phy.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3399-fix-pci-phy.patch rename to patch/kernel/archive/rockchip64-6.9/rk3399-fix-pci-phy.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3399-fix-usb-phy.patch b/patch/kernel/archive/rockchip64-6.9/rk3399-fix-usb-phy.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3399-fix-usb-phy.patch rename to patch/kernel/archive/rockchip64-6.9/rk3399-fix-usb-phy.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch b/patch/kernel/archive/rockchip64-6.9/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch rename to patch/kernel/archive/rockchip64-6.9/rk3399-rp64-pcie-Reimplement-rockchip-PCIe-bus-scan-delay.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3399-sd-drive-level-8ma.patch b/patch/kernel/archive/rockchip64-6.9/rk3399-sd-drive-level-8ma.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3399-sd-drive-level-8ma.patch rename to patch/kernel/archive/rockchip64-6.9/rk3399-sd-drive-level-8ma.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3399-sd-pwr-pinctrl.patch b/patch/kernel/archive/rockchip64-6.9/rk3399-sd-pwr-pinctrl.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3399-sd-pwr-pinctrl.patch rename to patch/kernel/archive/rockchip64-6.9/rk3399-sd-pwr-pinctrl.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk3399-unlock-temperature.patch b/patch/kernel/archive/rockchip64-6.9/rk3399-unlock-temperature.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk3399-unlock-temperature.patch rename to patch/kernel/archive/rockchip64-6.9/rk3399-unlock-temperature.patch diff --git a/patch/kernel/archive/rockchip64-6.8/rk35xx-montjoie-crypto-v2-rk35xx.patch b/patch/kernel/archive/rockchip64-6.9/rk35xx-montjoie-crypto-v2-rk35xx.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/rk35xx-montjoie-crypto-v2-rk35xx.patch rename to patch/kernel/archive/rockchip64-6.9/rk35xx-montjoie-crypto-v2-rk35xx.patch diff --git a/patch/kernel/archive/rockchip64-6.8/wifi-4003-add-bcm43342-chip.patch b/patch/kernel/archive/rockchip64-6.9/wifi-4003-add-bcm43342-chip.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/wifi-4003-add-bcm43342-chip.patch rename to patch/kernel/archive/rockchip64-6.9/wifi-4003-add-bcm43342-chip.patch diff --git a/patch/kernel/archive/rockchip64-6.8/wifi-4003-ssv-6051-driver.patch b/patch/kernel/archive/rockchip64-6.9/wifi-4003-ssv-6051-driver.patch similarity index 100% rename from patch/kernel/archive/rockchip64-6.8/wifi-4003-ssv-6051-driver.patch rename to patch/kernel/archive/rockchip64-6.9/wifi-4003-ssv-6051-driver.patch diff --git a/patch/kernel/archive/sunxi-6.6/patches.armbian/sound-soc-sunxi-h616-h618.patch b/patch/kernel/archive/sunxi-6.6/patches.armbian/sound-soc-sunxi-h616-h618.patch new file mode 100644 index 000000000000..16dcbdf3d6fa --- /dev/null +++ b/patch/kernel/archive/sunxi-6.6/patches.armbian/sound-soc-sunxi-h616-h618.patch @@ -0,0 +1,5504 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Stephen Graf +Date: Thu, 9 May 2024 20:59:34 -0700 +Subject: Sound for H616, H618 Allwinner SOCs + arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi + arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi + drivers/clk/sunxi-ng/ccu-sun50i-h616.c include/sound/soc-dai.h + sound/soc/Kconfig sound/soc/Makefile sound/soc/soc-core.c + sound/soc/sunxi/Kconfig sound/soc/sunxi/Makefile + sound/soc/sunxi/sun50iw9-codec.c sound/soc/sunxi_v2/Kconfig + sound/soc/sunxi_v2/Makefile sound/soc/sunxi_v2/drv_hdmi.h + sound/soc/sunxi_v2/snd_sunxi_ahub.c sound/soc/sunxi_v2/snd_sunxi_ahub.h + sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c + sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h sound/soc/sunxi_v2/snd_sunxi_common.c + sound/soc/sunxi_v2/snd_sunxi_common.h sound/soc/sunxi_v2/snd_sunxi_log.h + sound/soc/sunxi_v2/snd_sunxi_mach.c sound/soc/sunxi_v2/snd_sunxi_mach.h + sound/soc/sunxi_v2/snd_sunxi_mach_utils.c + sound/soc/sunxi_v2/snd_sunxi_mach_utils.h + +Signed-off-by: Stephen Graf +--- + arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 18 + + arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 83 + + drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 33 +- + include/sound/soc-dai.h | 13 + + sound/soc/Kconfig | 1 + + sound/soc/Makefile | 1 + + sound/soc/soc-core.c | 25 + + sound/soc/sunxi/Kconfig | 8 + + sound/soc/sunxi/Makefile | 1 + + sound/soc/sunxi/sun50iw9-codec.c | 1093 +++++++ + sound/soc/sunxi_v2/Kconfig | 48 + + sound/soc/sunxi_v2/Makefile | 11 + + sound/soc/sunxi_v2/drv_hdmi.h | 63 + + sound/soc/sunxi_v2/snd_sunxi_ahub.c | 1477 ++++++++++ + sound/soc/sunxi_v2/snd_sunxi_ahub.h | 67 + + sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c | 534 ++++ + sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h | 291 ++ + sound/soc/sunxi_v2/snd_sunxi_common.c | 267 ++ + sound/soc/sunxi_v2/snd_sunxi_common.h | 67 + + sound/soc/sunxi_v2/snd_sunxi_log.h | 29 + + sound/soc/sunxi_v2/snd_sunxi_mach.c | 479 +++ + sound/soc/sunxi_v2/snd_sunxi_mach.h | 17 + + sound/soc/sunxi_v2/snd_sunxi_mach_utils.c | 422 +++ + sound/soc/sunxi_v2/snd_sunxi_mach_utils.h | 116 + + 24 files changed, 5147 insertions(+), 17 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi +index ce3dc6d9c..23553f224 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi +@@ -103,10 +103,28 @@ wifi_pwrseq: wifi-pwrseq { + + &de { + status = "okay"; + }; + ++&codec { ++ allwinner,audio-routing = ++ "Line Out", "LINEOUT"; ++ status = "okay"; ++}; ++ ++&ahub_dam_plat { ++ status = "okay"; ++}; ++ ++&ahub1_plat { ++ status = "okay"; ++}; ++ ++&ahub1_mach { ++ status = "okay"; ++}; ++ + &ehci1 { + status = "okay"; + }; + + /* USB 2 & 3 are on headers only. */ +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +index 36c75d783..1b004503b 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -180,10 +180,82 @@ dma: dma-controller@3002000 { + dma-requests = <49>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + ++ codec: codec@05096000 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun50i-h616-codec"; ++ reg = <0x05096000 0x31c>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_AUDIO_CODEC>, ++ <&ccu CLK_AUDIO_CODEC_1X>, ++ <&ccu CLK_AUDIO_CODEC_4X>; ++ clock-names = "apb", "audio-codec-1x", "audio-codec-4x"; ++ resets = <&ccu RST_BUS_AUDIO_CODEC>; ++ dmas = <&dma 6>; ++ dma-names = "tx"; ++ status = "disabled"; ++ }; ++ ++ ahub_dam_plat:ahub_dam_plat@5097000 { ++ #sound-dai-cells = <0>; ++ /* sound card without pcm for hardware mix setting */ ++ compatible = "allwinner,sunxi-snd-plat-ahub_dam"; ++ reg = <0x05097000 0x1000>; ++ resets = <&ccu RST_BUS_AUDIO_HUB>; ++ clocks = <&ccu CLK_AUDIO_CODEC_1X>, ++ <&ccu CLK_AUDIO_CODEC_4X>, ++ <&ccu CLK_AUDIO_HUB>, ++ <&ccu CLK_BUS_AUDIO_HUB>; ++ clock-names = "clk_pll_audio", ++ "clk_pll_audio_4x", ++ "clk_audio_hub", ++ "clk_bus_audio_hub"; ++ status = "disabled"; ++ }; ++ ++ ahub1_plat:ahub1_plat { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sunxi-snd-plat-ahub"; ++ apb_num = <1>; /* for dma port 4 */ ++ dmas = <&dma 4>, <&dma 4>; ++ dma-names = "tx", "rx"; ++ playback_cma = <128>; ++ capture_cma = <128>; ++ tx_fifo_size = <128>; ++ rx_fifo_size = <128>; ++ ++ tdm_num = <1>; ++ tx_pin = <0>; ++ rx_pin = <0>; ++ status = "disabled"; ++ }; ++ ++ ahub1_mach:ahub1_mach { ++ compatible = "allwinner,sunxi-snd-mach"; ++ soundcard-mach,name = "HDMI"; ++ ++ soundcard-mach,format = "i2s"; ++ soundcard-mach,frame-master = <&ahub1_cpu>; ++ soundcard-mach,bitclock-master = <&ahub1_cpu>; ++ /* soundcard-mach,frame-inversion; */ ++ /* soundcard-mach,bitclock-inversion; */ ++ soundcard-mach,slot-num = <2>; ++ soundcard-mach,slot-width = <32>; ++ status = "disabled"; ++ ahub1_cpu: soundcard-mach,cpu { ++ sound-dai = <&ahub1_plat>; ++ soundcard-mach,pll-fs = <4>; ++ soundcard-mach,mclk-fs = <0>; ++ }; ++ ++ ahub1_codec: soundcard-mach,codec { ++ sound-dai = <&hdmi>; ++ }; ++ }; ++ + gpu: gpu@1800000 { + compatible = "allwinner,sun50i-h616-mali", + "arm,mali-bifrost"; + reg = <0x1800000 0x40000>; + interrupts = , +@@ -455,10 +527,21 @@ gic: interrupt-controller@3021000 { + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + ++ iommu: iommu@30f0000 { ++ compatible = "allwinner,sun50i-h616-iommu", ++ "allwinner,sun50i-h6-iommu"; ++ reg = <0x030f0000 0x10000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_IOMMU>; ++ resets = <&ccu RST_BUS_IOMMU>; ++ #iommu-cells = <1>; ++ status = "okay"; ++ }; ++ + mmc0: mmc@4020000 { + compatible = "allwinner,sun50i-h616-mmc", + "allwinner,sun50i-a100-mmc"; + reg = <0x04020000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c +index 21e918582..ab2628596 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c +@@ -213,24 +213,26 @@ static struct ccu_nkmp pll_de_clk = { + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, + }; + +-/* +- * TODO: Determine SDM settings for the audio PLL. The manual suggests +- * PLL_FACTOR_N=16, PLL_POST_DIV_P=2, OUTPUT_DIV=2, pattern=0xe000c49b +- * for 24.576 MHz, and PLL_FACTOR_N=22, PLL_POST_DIV_P=3, OUTPUT_DIV=2, +- * pattern=0xe001288c for 22.5792 MHz. +- * This clashes with our fixed PLL_POST_DIV_P. +- */ + #define SUN50I_H616_PLL_AUDIO_REG 0x078 ++ ++static struct ccu_sdm_setting pll_audio_sdm_table[] = { ++ { .rate = 90316800, .pattern = 0xc001288d, .m = 3, .n = 22 }, ++ { .rate = 98304000, .pattern = 0xc001eb85, .m = 5, .n = 40 }, ++}; ++ + static struct ccu_nm pll_audio_hs_clk = { + .enable = BIT(31), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), +- .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ ++ .m = _SUNXI_CCU_DIV(16, 6), ++ .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, ++ BIT(24), 0x178, BIT(31)), + .common = { ++ .features = CCU_FEATURE_SIGMA_DELTA_MOD, + .reg = 0x078, + .hw.init = CLK_HW_INIT("pll-audio-hs", "osc24M", + &ccu_nm_ops, + CLK_SET_RATE_UNGATE), + }, +@@ -686,17 +688,17 @@ static const struct clk_hw *clk_parent_pll_audio[] = { + * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200 + * rates can be set exactly in conjunction with sigma-delta modulation. + */ + static CLK_FIXED_FACTOR_HWS(pll_audio_1x_clk, "pll-audio-1x", + clk_parent_pll_audio, +- 96, 1, CLK_SET_RATE_PARENT); ++ 4, 1, CLK_SET_RATE_PARENT); + static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", + clk_parent_pll_audio, +- 48, 1, CLK_SET_RATE_PARENT); ++ 2, 1, CLK_SET_RATE_PARENT); + static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x", + clk_parent_pll_audio, +- 24, 1, CLK_SET_RATE_PARENT); ++ 1, 1, CLK_SET_RATE_PARENT); + + static const struct clk_hw *pll_periph0_parents[] = { + &pll_periph0_clk.common.hw + }; + +@@ -1128,17 +1130,14 @@ static int sun50i_h616_ccu_probe(struct platform_device *pdev) + val = readl(reg + usb2_clk_regs[i]); + val &= ~GENMASK(25, 24); + writel(val, reg + usb2_clk_regs[i]); + } + +- /* +- * Force the post-divider of pll-audio to 12 and the output divider +- * of it to 2, so 24576000 and 22579200 rates can be set exactly. +- */ + val = readl(reg + SUN50I_H616_PLL_AUDIO_REG); +- val &= ~(GENMASK(21, 16) | BIT(0)); +- writel(val | (11 << 16) | BIT(0), reg + SUN50I_H616_PLL_AUDIO_REG); ++ val &= ~BIT(1); ++ val |= BIT(0); ++ writel(val, reg + SUN50I_H616_PLL_AUDIO_REG); + + /* + * First clock parent (osc32K) is unusable for CEC. But since there + * is no good way to force parent switch (both run with same frequency), + * just set second clock parent here. +diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h +index adcd8719d..778751096 100644 +--- a/include/sound/soc-dai.h ++++ b/include/sound/soc-dai.h +@@ -413,20 +413,33 @@ struct snd_soc_dai_driver { + unsigned int id; + unsigned int base; + struct snd_soc_dobj dobj; + struct of_phandle_args *dai_args; + ++ /* DAI driver callbacks */ ++ int (*probe)(struct snd_soc_dai *dai); ++ int (*remove)(struct snd_soc_dai *dai); ++ /* compress dai */ ++ int (*compress_new)(struct snd_soc_pcm_runtime *rtd, int num); ++ /* Optional Callback used at pcm creation*/ ++ int (*pcm_new)(struct snd_soc_pcm_runtime *rtd, ++ struct snd_soc_dai *dai); ++ + /* ops */ + const struct snd_soc_dai_ops *ops; + const struct snd_soc_cdai_ops *cops; + + /* DAI capabilities */ + struct snd_soc_pcm_stream capture; + struct snd_soc_pcm_stream playback; + unsigned int symmetric_rate:1; + unsigned int symmetric_channels:1; + unsigned int symmetric_sample_bits:1; ++ ++ /* probe ordering - for components with runtime dependencies */ ++ int probe_order; ++ int remove_order; + }; + + /* for Playback/Capture */ + struct snd_soc_dai_stream { + struct snd_soc_dapm_widget *widget; +diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig +index 439fa631c..7dc3967cc 100644 +--- a/sound/soc/Kconfig ++++ b/sound/soc/Kconfig +@@ -106,10 +106,11 @@ source "sound/soc/spear/Kconfig" + source "sound/soc/sprd/Kconfig" + source "sound/soc/starfive/Kconfig" + source "sound/soc/sti/Kconfig" + source "sound/soc/stm/Kconfig" + source "sound/soc/sunxi/Kconfig" ++source "sound/soc/sunxi_v2/Kconfig" + source "sound/soc/tegra/Kconfig" + source "sound/soc/ti/Kconfig" + source "sound/soc/uniphier/Kconfig" + source "sound/soc/ux500/Kconfig" + source "sound/soc/xilinx/Kconfig" +diff --git a/sound/soc/Makefile b/sound/soc/Makefile +index 8376fdb21..79b48e8b3 100644 +--- a/sound/soc/Makefile ++++ b/sound/soc/Makefile +@@ -63,10 +63,11 @@ obj-$(CONFIG_SND_SOC) += spear/ + obj-$(CONFIG_SND_SOC) += sprd/ + obj-$(CONFIG_SND_SOC) += starfive/ + obj-$(CONFIG_SND_SOC) += sti/ + obj-$(CONFIG_SND_SOC) += stm/ + obj-$(CONFIG_SND_SOC) += sunxi/ ++obj-$(CONFIG_SND_SOC) += sunxi_v2/ + obj-$(CONFIG_SND_SOC) += tegra/ + obj-$(CONFIG_SND_SOC) += ti/ + obj-$(CONFIG_SND_SOC) += uniphier/ + obj-$(CONFIG_SND_SOC) += ux500/ + obj-$(CONFIG_SND_SOC) += xilinx/ +diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c +index b2bd45e87..723c19fb4 100644 +--- a/sound/soc/soc-core.c ++++ b/sound/soc/soc-core.c +@@ -2518,10 +2518,11 @@ struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component, + struct snd_soc_dai_driver *dai_drv, + bool legacy_dai_naming) + { + struct device *dev = component->dev; + struct snd_soc_dai *dai; ++ struct snd_soc_dai_ops *ops; /* REMOVE ME */ + + lockdep_assert_held(&client_mutex); + + dai = devm_kzalloc(dev, sizeof(*dai), GFP_KERNEL); + if (dai == NULL) +@@ -2546,10 +2547,34 @@ struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component, + dai->id = component->num_dai; + } + if (!dai->name) + return NULL; + ++ /* REMOVE ME */ ++ if (dai_drv->probe || ++ dai_drv->remove || ++ dai_drv->compress_new || ++ dai_drv->pcm_new || ++ dai_drv->probe_order || ++ dai_drv->remove_order) { ++ ++ ops = devm_kzalloc(dev, sizeof(struct snd_soc_dai_ops), GFP_KERNEL); ++ if (!ops) ++ return NULL; ++ if (dai_drv->ops) ++ memcpy(ops, dai_drv->ops, sizeof(struct snd_soc_dai_ops)); ++ ++ ops->probe = dai_drv->probe; ++ ops->remove = dai_drv->remove; ++ ops->compress_new = dai_drv->compress_new; ++ ops->pcm_new = dai_drv->pcm_new; ++ ops->probe_order = dai_drv->probe_order; ++ ops->remove_order = dai_drv->remove_order; ++ ++ dai_drv->ops = ops; ++ } ++ + dai->component = component; + dai->dev = dev; + dai->driver = dai_drv; + + /* see for_each_component_dais */ +diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig +index 753c38c5d..0f6579ea7 100644 +--- a/sound/soc/sunxi/Kconfig ++++ b/sound/soc/sunxi/Kconfig +@@ -8,10 +8,18 @@ config SND_SUN4I_CODEC + select REGMAP_MMIO + help + Select Y or M to add support for the Codec embedded in the Allwinner + A10 and affiliated SoCs. + ++config SND_SUN50IW9_CODEC ++ tristate "Allwinner H616 Codec Support" ++ select SND_SOC_GENERIC_DMAENGINE_PCM ++ select REGMAP_MMIO ++ help ++ Select Y or M to add support for the Codec embedded in the Allwinner ++ H616 and affiliated SoCs. ++ + config SND_SUN8I_CODEC + tristate "Allwinner SUN8I audio codec" + depends on OF + depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST + depends on COMMON_CLK +diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile +index b0b976a3d..f72d94f30 100644 +--- a/sound/soc/sunxi/Makefile ++++ b/sound/soc/sunxi/Makefile +@@ -1,8 +1,9 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o + obj-$(CONFIG_SND_SUN4I_CODEC) += sun4i-codec.o ++obj-$(CONFIG_SND_SUN50IW9_CODEC) += sun50iw9-codec.o + obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o + obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o + obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o + obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o + obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o +diff --git a/sound/soc/sunxi/sun50iw9-codec.c b/sound/soc/sunxi/sun50iw9-codec.c +new file mode 100644 +index 000000000..38b1d3824 +--- /dev/null ++++ b/sound/soc/sunxi/sun50iw9-codec.c +@@ -0,0 +1,1093 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Copyright 2014 Emilio López ++ * Copyright 2014 Jon Smirl ++ * Copyright 2015 Maxime Ripard ++ * Copyright 2015 Adam Sampson ++ * Copyright 2016 Chen-Yu Tsai ++ * Copyright 2021 gryzun ++ * ++ * Based on the Allwinner SDK driver, released under the GPL. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SUNXI_DAC_DPC (0x00) ++#define SUNXI_DAC_DPC_EN_DA (31) ++#define SUNXI_DAC_DPC_DVOL (12) ++#define SUNXI_DAC_DPC_HPF_EN (18) ++ ++#define SUNXI_DAC_FIFOC (0x10) ++#define SUNXI_DAC_FIFOC_DAC_FS (29) ++#define SUNXI_DAC_FIFOC_TX_FIFO_MODE (24) ++#define SUNXI_DAC_FIFOC_DRQ_CLR_CNT (21) ++#define SUNXI_DAC_FIFOC_MONO_EN (6) ++#define SUNXI_DAC_FIFOC_TX_SAMPLE_BITS (5) ++#define SUNXI_DAC_FIFOC_DAC_DRQ_EN (4) ++#define SUNXI_DAC_FIFOC_FIFO_FLUSH (0) ++ ++#define SUNXI_DAC_FIFO_STA (0x14) ++#define SUNXI_DAC_TXE_INT (3) ++#define SUNXI_DAC_TXU_INT (2) ++#define SUNXI_DAC_TXO_INT (1) ++#define SUNXI_DAC_TXDATA (0x20) ++#define SUNXI_DAC_CNT (0x24) ++#define SUNXI_DAC_DG_REG (0x28) ++#define SUNXI_DAC_DAP_CTL (0xf0) ++ ++#define SUNXI_DAC_AC_DAC_REG (0x310) ++#define SUNXI_DAC_LEN (15) ++#define SUNXI_DAC_REN (14) ++#define SUNXI_LINEOUTL_EN (13) ++#define SUNXI_LMUTE (12) ++#define SUNXI_LINEOUTR_EN (11) ++#define SUNXI_RMUTE (10) ++#define SUNXI_RSWITCH (9) ++#define SUNXI_RAMPEN (8) ++#define SUNXI_LINEOUTL_SEL (6) ++#define SUNXI_LINEOUTR_SEL (5) ++#define SUNXI_LINEOUT_VOL (0) ++ ++#define SUNXI_DAC_AC_MIXER_REG (0x314) ++#define SUNXI_LMIX_LDAC (21) ++#define SUNXI_LMIX_RDAC (20) ++#define SUNXI_RMIX_RDAC (17) ++#define SUNXI_RMIX_LDAC (16) ++#define SUNXI_LMIXEN (11) ++#define SUNXI_RMIXEN (10) ++ ++#define SUNXI_DAC_AC_RAMP_REG (0x31c) ++#define SUNXI_RAMP_STEP (4) ++#define SUNXI_RDEN (0) ++ ++#define LABEL(constant) \ ++ { \ ++#constant, constant, 0 \ ++ } ++#define LABEL_END \ ++ { \ ++ NULL, 0, -1 \ ++ } ++ ++struct audiocodec_reg_label ++{ ++ const char *name; ++ const unsigned int address; ++ int value; ++}; ++ ++static struct audiocodec_reg_label reg_labels[] = { ++ LABEL(SUNXI_DAC_DPC), ++ LABEL(SUNXI_DAC_FIFOC), ++ LABEL(SUNXI_DAC_FIFO_STA), ++ LABEL(SUNXI_DAC_CNT), ++ LABEL(SUNXI_DAC_DG_REG), ++ LABEL(SUNXI_DAC_DAP_CTL), ++ LABEL(SUNXI_DAC_AC_DAC_REG), ++ LABEL(SUNXI_DAC_AC_MIXER_REG), ++ LABEL(SUNXI_DAC_AC_RAMP_REG), ++ LABEL_END, ++}; ++ ++struct regmap *codec_regmap_debug = NULL; ++ ++struct sun50i_h616_codec ++{ ++ unsigned char *name; ++ struct device *dev; ++ struct regmap *regmap; ++ struct clk *clk_apb; ++ struct clk *clk_module; ++ struct reset_control *rst; ++ struct gpio_desc *gpio_pa; ++ ++ /* ADC_FIFOC register is at different offset on different SoCs */ ++ struct regmap_field *reg_adc_fifoc; ++ ++ struct snd_dmaengine_dai_dma_data playback_dma_data; ++}; ++ ++static void sun50i_h616_codec_start_playback(struct sun50i_h616_codec *scodec) ++{ ++ /* Flush TX FIFO */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_FIFO_FLUSH), ++ BIT(SUNXI_DAC_FIFOC_FIFO_FLUSH)); ++ ++ /* Enable DAC DRQ */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_DAC_DRQ_EN), ++ BIT(SUNXI_DAC_FIFOC_DAC_DRQ_EN)); ++} ++ ++static void sun50i_h616_codec_stop_playback(struct sun50i_h616_codec *scodec) ++{ ++ /* Disable DAC DRQ */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_DAC_DRQ_EN), ++ 0); ++} ++ ++static int sun50i_h616_codec_trigger(struct snd_pcm_substream *substream, int cmd, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card); ++ ++ switch (cmd) ++ { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN), ++ (0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN)); ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN), ++ (0x0 << SUNXI_DAC_FIFOC_DAC_DRQ_EN)); ++ break; ++ default: ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static int sun50i_h616_codec_prepare(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ (0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH), ++ (0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH)); ++ regmap_write(scodec->regmap, SUNXI_DAC_FIFO_STA, ++ (0x1 << SUNXI_DAC_TXE_INT | 1 << SUNXI_DAC_TXU_INT | 0x1 << SUNXI_DAC_TXO_INT)); ++ regmap_write(scodec->regmap, SUNXI_DAC_CNT, 0); ++ ++ return 0; ++} ++ ++static unsigned long sun50i_h616_codec_get_mod_freq(struct snd_pcm_hw_params *params) ++{ ++ unsigned int rate = params_rate(params); ++ ++ switch (rate) ++ { ++ case 176400: ++ case 88200: ++ case 44100: ++ case 33075: ++ case 22050: ++ case 14700: ++ case 11025: ++ case 7350: ++ return 22579200; ++ ++ case 192000: ++ case 96000: ++ case 48000: ++ case 32000: ++ case 24000: ++ case 16000: ++ case 12000: ++ case 8000: ++ return 24576000; ++ ++ default: ++ return 0; ++ } ++} ++ ++static int sun50i_h616_codec_get_hw_rate(struct snd_pcm_hw_params *params) ++{ ++ unsigned int rate = params_rate(params); ++ ++ switch (rate) ++ { ++ case 192000: ++ case 176400: ++ return 6; ++ ++ case 96000: ++ case 88200: ++ return 7; ++ ++ case 48000: ++ case 44100: ++ return 0; ++ ++ case 32000: ++ case 33075: ++ return 1; ++ ++ case 24000: ++ case 22050: ++ return 2; ++ ++ case 16000: ++ case 14700: ++ return 3; ++ ++ case 12000: ++ case 11025: ++ return 4; ++ ++ case 8000: ++ case 7350: ++ return 5; ++ ++ default: ++ return -EINVAL; ++ } ++} ++ ++static int sun50i_h616_codec_hw_params_playback(struct sun50i_h616_codec *scodec, ++ struct snd_pcm_hw_params *params, ++ unsigned int hwrate) ++{ ++ u32 val; ++ ++ /* Set DAC sample rate */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ 7 << SUNXI_DAC_FIFOC_DAC_FS, ++ hwrate << SUNXI_DAC_FIFOC_DAC_FS); ++ ++ /* Set the number of channels we want to use */ ++ if (params_channels(params) == 1) ++ val = BIT(SUNXI_DAC_FIFOC_MONO_EN); ++ else ++ val = 0; ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_MONO_EN), ++ val); ++ ++ /* Set the number of sample bits to either 16 or 24 bits */ ++ if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) ++ { ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_TX_SAMPLE_BITS), ++ BIT(SUNXI_DAC_FIFOC_TX_SAMPLE_BITS)); ++ ++ /* Set TX FIFO mode to padding the LSBs with 0 */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_TX_FIFO_MODE), ++ 0); ++ ++ scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ } ++ else ++ { ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_TX_SAMPLE_BITS), ++ 0); ++ ++ /* Set TX FIFO mode to repeat the MSB */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_TX_FIFO_MODE), ++ BIT(SUNXI_DAC_FIFOC_TX_FIFO_MODE)); ++ ++ scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ } ++ ++ return 0; ++} ++ ++struct sample_rate ++{ ++ unsigned int samplerate; ++ unsigned int rate_bit; ++}; ++ ++static const struct sample_rate sample_rate_conv[] = { ++ {44100, 0}, ++ {48000, 0}, ++ {8000, 5}, ++ {32000, 1}, ++ {22050, 2}, ++ {24000, 2}, ++ {16000, 3}, ++ {11025, 4}, ++ {12000, 4}, ++ {192000, 6}, ++ {96000, 7}, ++}; ++ ++static int sun50i_h616_codec_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card); ++ unsigned long clk_freq; ++ int ret, hwrate; ++ int i; ++ ++ clk_freq = sun50i_h616_codec_get_mod_freq(params); ++ if (!clk_freq) ++ return -EINVAL; ++ ++ ret = clk_set_rate(scodec->clk_module, clk_freq * 2); ++ if (ret) ++ return ret; ++ ++ hwrate = sun50i_h616_codec_get_hw_rate(params); ++ if (hwrate < 0) ++ return hwrate; ++ ++ switch (params_format(params)) ++ { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ { ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x3 << SUNXI_DAC_FIFOC_TX_FIFO_MODE), ++ (0x3 << SUNXI_DAC_FIFOC_TX_FIFO_MODE)); ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x1 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS), ++ (0x0 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS)); ++ } ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ { ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x3 << SUNXI_DAC_FIFOC_TX_FIFO_MODE), ++ (0x0 << SUNXI_DAC_FIFOC_TX_FIFO_MODE)); ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x1 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS), ++ (0x1 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS)); ++ } ++ break; ++ default: ++ break; ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(sample_rate_conv); i++) ++ { ++ if (sample_rate_conv[i].samplerate == params_rate(params)) ++ { ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ { ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x7 << SUNXI_DAC_FIFOC_DAC_FS), ++ (sample_rate_conv[i].rate_bit << SUNXI_DAC_FIFOC_DAC_FS)); ++ } ++ } ++ } ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ { ++ switch (params_channels(params)) ++ { ++ case 1: ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x1 << SUNXI_DAC_FIFOC_MONO_EN), ++ (0x1 << SUNXI_DAC_FIFOC_MONO_EN)); ++ break; ++ case 2: ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x1 << SUNXI_DAC_FIFOC_MONO_EN), ++ (0x0 << SUNXI_DAC_FIFOC_MONO_EN)); ++ break; ++ default: ++ pr_err("[%s] Playback cannot support %d channels.\n", ++ __func__, params_channels(params)); ++ return -EINVAL; ++ } ++ } ++ ++ return 0; ++} ++ ++static unsigned int sun50i_h616_codec_src_rates[] = { ++ 8000, 11025, 12000, 16000, 22050, 24000, 32000, ++ 44100, 48000, 96000, 192000}; ++ ++static struct snd_pcm_hw_constraint_list sun50i_h616_codec_constraints = { ++ .count = ARRAY_SIZE(sun50i_h616_codec_src_rates), ++ .list = sun50i_h616_codec_src_rates, ++}; ++ ++static int sun50i_h616_codec_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card); ++ ++ snd_pcm_hw_constraint_list(substream->runtime, 0, ++ SNDRV_PCM_HW_PARAM_RATE, &sun50i_h616_codec_constraints); ++ ++ /* ++ * Stop issuing DRQ when we have room for less than 16 samples ++ * in our TX FIFO ++ */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ 3 << SUNXI_DAC_FIFOC_DRQ_CLR_CNT, ++ 3 << SUNXI_DAC_FIFOC_DRQ_CLR_CNT); ++ ++ return clk_prepare_enable(scodec->clk_module); ++} ++ ++static void sun50i_h616_codec_shutdown(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card); ++ ++ clk_disable_unprepare(scodec->clk_module); ++} ++ ++static const struct snd_soc_dai_ops sun50i_h616_codec_dai_ops = { ++ .startup = sun50i_h616_codec_startup, ++ .shutdown = sun50i_h616_codec_shutdown, ++ .trigger = sun50i_h616_codec_trigger, ++ .hw_params = sun50i_h616_codec_hw_params, ++ .prepare = sun50i_h616_codec_prepare, ++}; ++ ++static struct snd_soc_dai_driver sun50i_h616_codec_dai = { ++ .name = "Codec", ++ .ops = &sun50i_h616_codec_dai_ops, ++ .playback = { ++ .stream_name = "Codec Playback", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rate_min = 8000, ++ .rate_max = 192000, ++ .rates = SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S24_LE, ++ .sig_bits = 24, ++ }, ++}; ++ ++static int sunxi_lineout_event(struct snd_soc_dapm_widget *w, ++ struct snd_kcontrol *k, int event) ++{ ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card); ++ ++ switch (event) ++ { ++ case SND_SOC_DAPM_POST_PMU: ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG, ++ (0x1 << SUNXI_RDEN), (0x1 << SUNXI_RDEN)); ++ msleep(25); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_LINEOUTL_EN) | (0x1 << SUNXI_LINEOUTR_EN), ++ (0x1 << SUNXI_LINEOUTL_EN) | (0x1 << SUNXI_LINEOUTR_EN)); ++ break; ++ case SND_SOC_DAPM_PRE_PMD: ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG, ++ (0x1 << SUNXI_RDEN), (0x0 << SUNXI_RDEN)); ++ msleep(25); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_LINEOUTL_EN) | (0x1 << SUNXI_LINEOUTR_EN), ++ (0x0 << SUNXI_LINEOUTL_EN) | (0x0 << SUNXI_LINEOUTR_EN)); ++ ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static const DECLARE_TLV_DB_SCALE(digital_tlv, 0, -116, -7424); ++static const DECLARE_TLV_DB_SCALE(linein_to_l_r_mix_vol_tlv, -450, 150, 0); ++static const DECLARE_TLV_DB_SCALE(fmin_to_l_r_mix_vol_tlv, -450, 150, 0); ++ ++static const unsigned int lineout_tlv[] = { ++ TLV_DB_RANGE_HEAD(2), ++ 0, ++ 0, ++ TLV_DB_SCALE_ITEM(0, 0, 1), ++ 1, ++ 31, ++ TLV_DB_SCALE_ITEM(-4350, 150, 1), ++}; ++ ++/*lineoutL mux select */ ++const char *const left_lineoutl_text[] = { ++ "LOMixer", ++ "LROMixer", ++}; ++ ++static const struct soc_enum left_lineout_enum = ++ SOC_ENUM_SINGLE(SUNXI_DAC_AC_DAC_REG, SUNXI_LINEOUTL_SEL, ++ ARRAY_SIZE(left_lineoutl_text), left_lineoutl_text); ++ ++static const struct snd_kcontrol_new left_lineout_mux = ++ SOC_DAPM_ENUM("Left LINEOUT Mux", left_lineout_enum); ++ ++/*lineoutR mux select */ ++const char *const right_lineoutr_text[] = { ++ "ROMixer", ++ "LROMixer", ++}; ++ ++static const struct soc_enum right_lineout_enum = ++ SOC_ENUM_SINGLE(SUNXI_DAC_AC_DAC_REG, SUNXI_LINEOUTR_SEL, ++ ARRAY_SIZE(right_lineoutr_text), right_lineoutr_text); ++ ++static const struct snd_kcontrol_new right_lineout_mux = ++ SOC_DAPM_ENUM("Right LINEOUT Mux", right_lineout_enum); ++ ++static const struct snd_kcontrol_new sun50i_h616_codec_codec_controls[] = { ++ ++ SOC_SINGLE_TLV("digital volume", SUNXI_DAC_DPC, ++ SUNXI_DAC_DPC_DVOL, 0x3F, 0, digital_tlv), ++ ++ SOC_SINGLE_TLV("LINEOUT volume", SUNXI_DAC_AC_DAC_REG, ++ SUNXI_LINEOUT_VOL, 0x1F, 0, lineout_tlv), ++}; ++ ++static const struct snd_kcontrol_new left_output_mixer[] = { ++ SOC_DAPM_SINGLE("DACL Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_LMIX_LDAC, 1, 0), ++ SOC_DAPM_SINGLE("DACR Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_LMIX_RDAC, 1, 0), ++}; ++ ++static const struct snd_kcontrol_new right_output_mixer[] = { ++ SOC_DAPM_SINGLE("DACL Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_RMIX_LDAC, 1, 0), ++ SOC_DAPM_SINGLE("DACR Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_RMIX_RDAC, 1, 0), ++}; ++ ++static const struct snd_soc_dapm_widget sun50i_h616_codec_codec_widgets[] = { ++ ++ /* Digital parts of the DACs */ ++ SND_SOC_DAPM_SUPPLY("DAC Enable", SUNXI_DAC_DPC, ++ SUNXI_DAC_DPC_EN_DA, 0, NULL, 0), ++ ++ SND_SOC_DAPM_AIF_IN_E("DACL", "Codec Playback", 0, SUNXI_DAC_AC_DAC_REG, SUNXI_DAC_LEN, 0, ++ NULL, 0), ++ SND_SOC_DAPM_AIF_IN_E("DACR", "Codec Playback", 0, SUNXI_DAC_AC_DAC_REG, SUNXI_DAC_REN, 0, ++ NULL, 0), ++ ++ SND_SOC_DAPM_MIXER("Left Output Mixer", SUNXI_DAC_AC_MIXER_REG, SUNXI_LMIXEN, 0, ++ left_output_mixer, ARRAY_SIZE(left_output_mixer)), ++ SND_SOC_DAPM_MIXER("Right Output Mixer", SUNXI_DAC_AC_MIXER_REG, SUNXI_RMIXEN, 0, ++ right_output_mixer, ARRAY_SIZE(right_output_mixer)), ++ ++ SND_SOC_DAPM_MUX("Left LINEOUT Mux", SND_SOC_NOPM, ++ 0, 0, &left_lineout_mux), ++ SND_SOC_DAPM_MUX("Right LINEOUT Mux", SND_SOC_NOPM, ++ 0, 0, &right_lineout_mux), ++ ++ SND_SOC_DAPM_OUTPUT("LINEOUTL"), ++ SND_SOC_DAPM_OUTPUT("LINEOUTR"), ++ ++ SND_SOC_DAPM_LINE("LINEOUT", sunxi_lineout_event), ++}; ++ ++static const struct snd_soc_component_driver sun50i_h616_codec_codec = { ++ .controls = sun50i_h616_codec_codec_controls, ++ .num_controls = ARRAY_SIZE(sun50i_h616_codec_codec_controls), ++ .dapm_widgets = sun50i_h616_codec_codec_widgets, ++ .num_dapm_widgets = ARRAY_SIZE(sun50i_h616_codec_codec_widgets), ++ .idle_bias_on = 1, ++ .use_pmdown_time = 1, ++ .endianness = 1, ++}; ++ ++static const struct snd_soc_component_driver sun50i_h616_codec_component = { ++ .name = "sun50i_h616-codec", ++ .legacy_dai_naming = 1, ++#ifdef CONFIG_DEBUG_FS ++ .debugfs_prefix = "cpu", ++#endif ++}; ++ ++#define SUN50IW9_CODEC_RATES (SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT) ++#define SUN50IW9_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) ++ ++static int sun50i_h616_codec_dai_probe(struct snd_soc_dai *dai) ++{ ++ struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(card); ++ ++ snd_soc_dai_init_dma_data(dai, &scodec->playback_dma_data, ++ NULL); ++ ++ return 0; ++} ++ ++static struct snd_soc_dai_driver dummy_cpu_dai = { ++ .name = "sun50i_h616-codec-cpu-dai", ++ .probe = sun50i_h616_codec_dai_probe, ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = SUN50IW9_CODEC_RATES, ++ .formats = SUN50IW9_CODEC_FORMATS, ++ .sig_bits = 24, ++ }, ++}; ++ ++static struct snd_soc_dai_link *sun50i_h616_codec_create_link(struct device *dev, ++ int *num_links) ++{ ++ struct snd_soc_dai_link *link = devm_kzalloc(dev, sizeof(*link), ++ GFP_KERNEL); ++ struct snd_soc_dai_link_component *dlc = devm_kzalloc(dev, ++ 3 * sizeof(*dlc), GFP_KERNEL); ++ if (!link || !dlc) ++ return NULL; ++ ++ link->cpus = &dlc[0]; ++ link->codecs = &dlc[1]; ++ link->platforms = &dlc[2]; ++ ++ link->num_cpus = 1; ++ link->num_codecs = 1; ++ link->num_platforms = 1; ++ ++ link->name = "cdc"; ++ link->stream_name = "CDC PCM"; ++ link->codecs->dai_name = "Codec"; ++ link->cpus->dai_name = dev_name(dev); ++ link->codecs->name = dev_name(dev); ++ link->platforms->name = dev_name(dev); ++ link->dai_fmt = SND_SOC_DAIFMT_I2S; ++ link->playback_only = true; ++ link->capture_only = false; ++ ++ *num_links = 1; ++ ++ return link; ++}; ++ ++static int sun50i_h616_codec_spk_event(struct snd_soc_dapm_widget *w, ++ struct snd_kcontrol *k, int event) ++{ ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card); ++ ++ gpiod_set_value_cansleep(scodec->gpio_pa, ++ !!SND_SOC_DAPM_EVENT_ON(event)); ++ ++ if (SND_SOC_DAPM_EVENT_ON(event)) ++ { ++ /* ++ * Need a delay to wait for DAC to push the data. 700ms seems ++ * to be the best compromise not to feel this delay while ++ * playing a sound. ++ */ ++ msleep(700); ++ } ++ ++ return 0; ++} ++ ++static const struct snd_soc_dapm_widget sun6i_codec_card_dapm_widgets[] = { ++ SND_SOC_DAPM_LINE("Line Out", NULL), ++ SND_SOC_DAPM_SPK("Speaker", sun50i_h616_codec_spk_event), ++}; ++ ++/* Connect digital side enables to analog side widgets */ ++static const struct snd_soc_dapm_route sun8i_codec_card_routes[] = { ++ /* DAC Routes */ ++ {"DACR", NULL, "DAC Enable"}, ++ {"DACL", NULL, "DAC Enable"}, ++ ++ {"Left Output Mixer", "DACR Switch", "DACR"}, ++ {"Left Output Mixer", "DACL Switch", "DACL"}, ++ ++ {"Right Output Mixer", "DACL Switch", "DACL"}, ++ {"Right Output Mixer", "DACR Switch", "DACR"}, ++ ++ {"Left LINEOUT Mux", "LOMixer", "Left Output Mixer"}, ++ {"Left LINEOUT Mux", "LROMixer", "Right Output Mixer"}, ++ {"Right LINEOUT Mux", "ROMixer", "Right Output Mixer"}, ++ {"Right LINEOUT Mux", "LROMixer", "Left Output Mixer"}, ++ ++ {"LINEOUTL", NULL, "Left LINEOUT Mux"}, ++ {"LINEOUTR", NULL, "Right LINEOUT Mux"}, ++ ++ {"LINEOUT", NULL, "LINEOUTL"}, ++ {"LINEOUT", NULL, "LINEOUTR"}, ++ ++ {"Speaker", NULL, "LINEOUTL"}, ++ {"Speaker", NULL, "LINEOUTR"}, ++}; ++ ++static const struct snd_kcontrol_new sunxi_card_controls[] = { ++ SOC_DAPM_PIN_SWITCH("LINEOUT"), ++}; ++ ++static struct snd_soc_card *sun50i_h616_codec_create_card(struct device *dev) ++{ ++ struct snd_soc_card *card; ++ int ret; ++ ++ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); ++ if (!card) ++ return ERR_PTR(-ENOMEM); ++ ++ card->dai_link = sun50i_h616_codec_create_link(dev, &card->num_links); ++ if (!card->dai_link) ++ return ERR_PTR(-ENOMEM); ++ ++ card->dev = dev; ++ card->owner = THIS_MODULE; ++ card->name = "audiocodec"; ++ card->controls = sunxi_card_controls; ++ card->num_controls = ARRAY_SIZE(sunxi_card_controls), ++ card->dapm_widgets = sun6i_codec_card_dapm_widgets; ++ card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets); ++ card->dapm_routes = sun8i_codec_card_routes; ++ card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes); ++ card->fully_routed = true; ++ ++ ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing"); ++ if (ret) ++ dev_warn(dev, "failed to parse audio-routing: %d\n", ret); ++ ++ return card; ++}; ++ ++static const struct regmap_config sun50i_h616_codec_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = SUNXI_DAC_AC_RAMP_REG, ++ .cache_type = REGCACHE_NONE, ++}; ++ ++struct sun50i_h616_codec_quirks ++{ ++ const struct regmap_config *regmap_config; ++ const struct snd_soc_component_driver *codec; ++ struct snd_soc_card *(*create_card)(struct device *dev); ++ struct reg_field reg_adc_fifoc; /* used for regmap_field */ ++ unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */ ++ unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */ ++ bool has_reset; ++}; ++ ++static const struct sun50i_h616_codec_quirks sun50i_h616_codec_quirks = { ++ .regmap_config = &sun50i_h616_codec_regmap_config, ++ .codec = &sun50i_h616_codec_codec, ++ .create_card = sun50i_h616_codec_create_card, ++ .reg_dac_txdata = SUNXI_DAC_TXDATA, ++ .has_reset = true, ++}; ++ ++static const struct of_device_id sun50i_h616_codec_of_match[] = { ++ { ++ .compatible = "allwinner,sun50i-h616-codec", ++ .data = &sun50i_h616_codec_quirks, ++ }, ++ {}}; ++MODULE_DEVICE_TABLE(of, sun50i_h616_codec_of_match); ++ ++static ssize_t show_audio_reg(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ int count = 0, i = 0; ++ unsigned int reg_val; ++ unsigned int size = ARRAY_SIZE(reg_labels); ++ ++ count += sprintf(buf, "dump audiocodec reg:\n"); ++ ++ while ((i < size) && (reg_labels[i].name != NULL)) ++ { ++ regmap_read(codec_regmap_debug, ++ reg_labels[i].address, ®_val); ++ count += sprintf(buf + count, "%-20s [0x%03x]: 0x%-10x save_val:0x%x\n", ++ reg_labels[i].name, (reg_labels[i].address), ++ reg_val, reg_labels[i].value); ++ i++; ++ } ++ ++ return count; ++} ++ ++static DEVICE_ATTR(audio_reg, 0644, show_audio_reg, NULL); ++ ++static struct attribute *audio_debug_attrs[] = { ++ &dev_attr_audio_reg.attr, ++ NULL, ++}; ++ ++static struct attribute_group audio_debug_attr_group = { ++ .name = "audio_reg_debug", ++ .attrs = audio_debug_attrs, ++}; ++ ++static void sunxi_codec_init(struct sun50i_h616_codec *scodec) ++{ ++ /* Disable DRC function for playback */ ++ regmap_write(scodec->regmap, SUNXI_DAC_DAP_CTL, 0); ++ ++ /* Enable HPF(high passed filter) */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_DPC, ++ (0x1 << SUNXI_DAC_DPC_HPF_EN), (0x1 << SUNXI_DAC_DPC_HPF_EN)); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1f << SUNXI_LINEOUT_VOL), ++ (0x1a << SUNXI_LINEOUT_VOL)); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_DPC, ++ (0x3f << SUNXI_DAC_DPC_DVOL), (0 << SUNXI_DAC_DPC_DVOL)); ++ ++ /* Mixer to channel LINEOUT MUTE control init */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_LMUTE), (0x1 << SUNXI_LMUTE)); ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_RMUTE), (0x1 << SUNXI_RMUTE)); ++ ++ /* ramp func about */ ++ if (0) ++ { ++ /* Not used the ramp func cause there is the MUTE to avoid pop noise */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_RSWITCH), (0x1 << SUNXI_RSWITCH)); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_RAMPEN), (0x0 << SUNXI_RAMPEN)); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG, ++ (0x7 << SUNXI_RAMP_STEP), (0x0 << SUNXI_RAMP_STEP)); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG, ++ (0x1 << SUNXI_RDEN), (0x0 << SUNXI_RDEN)); ++ } ++ else ++ { ++ /* If no MUTE to avoid pop, just use the ramp func to avoid it */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_RSWITCH), (0x0 << SUNXI_RSWITCH)); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_RAMPEN), (0x1 << SUNXI_RAMPEN)); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG, ++ (0x7 << SUNXI_RAMP_STEP), (0x1 << SUNXI_RAMP_STEP)); ++ } ++} ++ ++static int sun50i_h616_codec_probe(struct platform_device *pdev) ++{ ++ struct snd_soc_card *card; ++ struct sun50i_h616_codec *scodec; ++ const struct sun50i_h616_codec_quirks *quirks; ++ struct resource *res; ++ void __iomem *base; ++ int ret; ++ ++ scodec = devm_kzalloc(&pdev->dev, sizeof(struct sun50i_h616_codec), GFP_KERNEL); ++ if (!scodec) ++ return -ENOMEM; ++ ++ scodec->dev = &pdev->dev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ quirks = of_device_get_match_data(&pdev->dev); ++ if (quirks == NULL) ++ { ++ dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); ++ return -ENODEV; ++ } ++ ++ scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base, ++ quirks->regmap_config); ++ if (IS_ERR(scodec->regmap)) ++ { ++ dev_err(&pdev->dev, "Failed to create our regmap\n"); ++ return PTR_ERR(scodec->regmap); ++ } ++ ++ /* Get the clocks from the DT */ ++ scodec->clk_apb = devm_clk_get(&pdev->dev, "apb"); ++ if (IS_ERR(scodec->clk_apb)) ++ { ++ dev_err(&pdev->dev, "Failed to get the APB clock\n"); ++ return PTR_ERR(scodec->clk_apb); ++ } ++ ++ scodec->clk_module = devm_clk_get(&pdev->dev, "audio-codec-1x"); ++ if (IS_ERR(scodec->clk_module)) ++ { ++ dev_err(&pdev->dev, "Failed to get the codec module clock\n"); ++ return PTR_ERR(scodec->clk_module); ++ } ++ ++ if (quirks->has_reset) ++ { ++ scodec->rst = devm_reset_control_get_exclusive(&pdev->dev, ++ NULL); ++ if (IS_ERR(scodec->rst)) ++ { ++ dev_err(&pdev->dev, "Failed to get reset control\n"); ++ return PTR_ERR(scodec->rst); ++ } ++ } ++ ++ scodec->gpio_pa = devm_gpiod_get_optional(&pdev->dev, "allwinner,pa", ++ GPIOD_OUT_LOW); ++ if (IS_ERR(scodec->gpio_pa)) ++ { ++ ret = PTR_ERR(scodec->gpio_pa); ++ if (ret != -EPROBE_DEFER) ++ dev_err(&pdev->dev, "Failed to get pa gpio: %d\n", ret); ++ return ret; ++ } ++ ++ /* Enable the bus clock */ ++ if (clk_prepare_enable(scodec->clk_apb)) ++ { ++ dev_err(&pdev->dev, "Failed to enable the APB clock\n"); ++ return -EINVAL; ++ } ++ ++ /* Deassert the reset control */ ++ if (scodec->rst) ++ { ++ ret = reset_control_deassert(scodec->rst); ++ if (ret) ++ { ++ dev_err(&pdev->dev, ++ "Failed to deassert the reset control\n"); ++ goto err_clk_disable; ++ } ++ } ++ ++ /* DMA configuration for TX FIFO */ ++ scodec->playback_dma_data.addr = res->start + quirks->reg_dac_txdata; ++ scodec->playback_dma_data.maxburst = 8; ++ scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ ++ ret = devm_snd_soc_register_component(&pdev->dev, quirks->codec, ++ &sun50i_h616_codec_dai, 1); ++ if (ret) ++ { ++ dev_err(&pdev->dev, "Failed to register our codec\n"); ++ goto err_assert_reset; ++ } ++ ++ ret = devm_snd_soc_register_component(&pdev->dev, ++ &sun50i_h616_codec_component, ++ &dummy_cpu_dai, 1); ++ if (ret) ++ { ++ dev_err(&pdev->dev, "Failed to register our DAI\n"); ++ goto err_assert_reset; ++ } ++ ++ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); ++ if (ret) ++ { ++ dev_err(&pdev->dev, "Failed to register against DMAEngine\n"); ++ goto err_assert_reset; ++ } ++ ++ card = quirks->create_card(&pdev->dev); ++ if (IS_ERR(card)) ++ { ++ ret = PTR_ERR(card); ++ dev_err(&pdev->dev, "Failed to create our card\n"); ++ goto err_assert_reset; ++ } ++ ++ snd_soc_card_set_drvdata(card, scodec); ++ ++ codec_regmap_debug = scodec->regmap; ++ ++ ret = snd_soc_register_card(card); ++ if (ret) ++ { ++ dev_err(&pdev->dev, "Failed to register our card\n"); ++ goto err_assert_reset; ++ } ++ ++ ret = sysfs_create_group(&pdev->dev.kobj, &audio_debug_attr_group); ++ if (ret) ++ dev_warn(&pdev->dev, "failed to create attr group\n"); ++ ++ sunxi_codec_init(scodec); ++ ++ return 0; ++ ++err_assert_reset: ++ if (scodec->rst) ++ reset_control_assert(scodec->rst); ++err_clk_disable: ++ clk_disable_unprepare(scodec->clk_apb); ++ return ret; ++} ++ ++static int sun50i_h616_codec_remove(struct platform_device *pdev) ++{ ++ struct snd_soc_card *card = platform_get_drvdata(pdev); ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(card); ++ ++ snd_soc_unregister_card(card); ++ if (scodec->rst) ++ reset_control_assert(scodec->rst); ++ clk_disable_unprepare(scodec->clk_apb); ++ ++ return 0; ++} ++ ++static struct platform_driver sun50i_h616_codec_driver = { ++ .driver = { ++ .name = "sun50i-h616-codec", ++ .of_match_table = sun50i_h616_codec_of_match, ++ }, ++ .probe = sun50i_h616_codec_probe, ++ .remove = sun50i_h616_codec_remove, ++}; ++module_platform_driver(sun50i_h616_codec_driver); ++ ++MODULE_DESCRIPTION("Allwinner H616 codec driver"); ++MODULE_AUTHOR("Emilio López "); ++MODULE_AUTHOR("Jon Smirl "); ++MODULE_AUTHOR("Maxime Ripard "); ++MODULE_AUTHOR("Chen-Yu Tsai "); ++MODULE_AUTHOR("Leeboby "); ++MODULE_LICENSE("GPL"); +diff --git a/sound/soc/sunxi_v2/Kconfig b/sound/soc/sunxi_v2/Kconfig +new file mode 100644 +index 000000000..37fc579ba +--- /dev/null ++++ b/sound/soc/sunxi_v2/Kconfig +@@ -0,0 +1,48 @@ ++# common ++config SND_SOC_SUNXI_MACH ++ tristate ++ ++# ahub dam ++config SND_SOC_SUNXI_AHUB_DAM ++ tristate ++ ++config SND_SOC_SUNXI_INTERNALCODEC ++ tristate ++ ++config SND_SOC_SUNXI_SUN50IW9_CODEC ++ tristate ++ ++# menu select ++menu "Allwinner SoC Audio support V2" ++ depends on ARCH_SUNXI ++ ++# aaudio ++config SND_SOC_SUNXI_AAUDIO ++ tristate "Allwinner AAUDIO support" ++ select REGMAP_MMIO ++ select SND_SOC_GENERIC_DMAENGINE_PCM ++ select SND_SOC_SUNXI_MACH ++ select SND_SOC_SUNXI_INTERNALCODEC ++ select SND_SOC_SUNXI_SUN50IW9_CODEC ++ depends on ARCH_SUNXI ++ help ++ Select Y or M to support analog-audio Module in the Allwinner SoCs. ++ ++# ahub ++config SND_SOC_SUNXI_AHUB ++ tristate "Allwinner AHUB Support" ++ select REGMAP_MMIO ++ select SND_SOC_GENERIC_DMAENGINE_PCM ++ select SND_SOC_SUNXI_MACH ++ select SND_SOC_SUNXI_AHUB_DAM ++ depends on ARCH_SUNXI ++ help ++ Select Y or M to support audio-hub Module in Allwinner SoCs. ++ ++config SND_SOC_SUNXI_DEBUG ++ tristate "Components Debug" ++ depends on SND_SOC_SUNXI_COMPONENTS ++ help ++ Select Y or M to support debug components. ++ ++endmenu +diff --git a/sound/soc/sunxi_v2/Makefile b/sound/soc/sunxi_v2/Makefile +new file mode 100644 +index 000000000..c7c2ef8f9 +--- /dev/null ++++ b/sound/soc/sunxi_v2/Makefile +@@ -0,0 +1,11 @@ ++# platform -> ahub ++snd_soc_sunxi_ahub_dam-objs += snd_sunxi_ahub_dam.o ++obj-$(CONFIG_SND_SOC_SUNXI_AHUB_DAM) += snd_soc_sunxi_ahub_dam.o ++ ++snd_soc_sunxi_ahub-objs += snd_sunxi_ahub.o ++obj-$(CONFIG_SND_SOC_SUNXI_AHUB) += snd_soc_sunxi_ahub.o ++ ++# common -> machine (note: Finally compile, save system startup time) ++snd_soc_sunxi_machine-objs += snd_sunxi_mach.o ++snd_soc_sunxi_machine-objs += snd_sunxi_mach_utils.o ++obj-$(CONFIG_SND_SOC_SUNXI_MACH) += snd_soc_sunxi_machine.o +diff --git a/sound/soc/sunxi_v2/drv_hdmi.h b/sound/soc/sunxi_v2/drv_hdmi.h +new file mode 100644 +index 000000000..2e05489b0 +--- /dev/null ++++ b/sound/soc/sunxi_v2/drv_hdmi.h +@@ -0,0 +1,63 @@ ++/* ++ * Allwinner SoCs hdmi driver. ++ * ++ * Copyright (C) 2016 Allwinner. ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++#ifndef __DRV_HDMI_H__ ++#define __DRV_HDMI_H__ ++ ++typedef struct { ++ __u8 hw_intf; /* 0:iis 1:spdif 2:pcm */ ++ __u16 fs_between; /* fs */ ++ __u32 sample_rate; /*sample rate*/ ++ __u8 clk_edge; /* 0:*/ ++ __u8 ch0_en; /* 1 */ ++ __u8 ch1_en; /* 0 */ ++ __u8 ch2_en; /* 0 */ ++ __u8 ch3_en; /* 0 */ ++ __u8 word_length; /* 32 */ ++ __u8 shift_ctl; /* 0 */ ++ __u8 dir_ctl; /* 0 */ ++ __u8 ws_pol; ++ __u8 just_pol; ++ __u8 channel_num; ++ __u8 data_raw; ++ __u8 sample_bit; ++ __u8 ca; /* channel allocation */ ++} hdmi_audio_t; ++ ++typedef struct { ++ __s32 (*hdmi_audio_enable)(__u8 mode, __u8 channel); ++ __s32 (*hdmi_set_audio_para)(hdmi_audio_t *audio_para); ++ __s32 (*hdmi_is_playback)(void); ++} __audio_hdmi_func; ++ ++enum hdmi_hpd_status { ++ STATUE_CLOSE = 0, ++ STATUE_OPEN = 1, ++}; ++ ++void audio_set_hdmi_func(__audio_hdmi_func *hdmi_func); ++#if defined(CONFIG_SND_SUNXI_SOC_AUDIOHUB_INTERFACE) ++void audio_set_muti_hdmi_func(__audio_hdmi_func *hdmi_func); ++#endif ++ ++/******************** SND_HDMI for sunxi_v2 begain ***************************/ ++#if IS_ENABLED(CONFIG_HDMI2_DISP2_SUNXI) ++extern int snd_hdmi_get_func(__audio_hdmi_func *hdmi_func); ++#else ++static inline int snd_hdmi_get_func(__audio_hdmi_func *hdmi_func) ++{ ++ pr_err("HDMI Audio API is disable\n"); ++ ++ return -1; ++} ++#endif ++/******************** SND_HDMI for sunxi_v2 end ******************************/ ++ ++#endif +diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub.c b/sound/soc/sunxi_v2/snd_sunxi_ahub.c +new file mode 100644 +index 000000000..8a1065e91 +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub.c +@@ -0,0 +1,1477 @@ ++/* ++ * sound\soc\sunxi\snd_sunxi_ahub.c ++ * (C) Copyright 2021-2025 ++ * AllWinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "snd_sunxi_log.h" ++#include "snd_sunxi_ahub.h" ++ ++#define HLOG "AHUB" ++#define DRV_NAME "sunxi-snd-plat-ahub" ++ ++static int sunxi_ahub_dai_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int apb_num, tdm_num; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ regmap = ahub_info->mem_info.regmap; ++ apb_num = ahub_info->dts_info.apb_num; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ snd_soc_dai_set_dma_data(dai, substream, ++ &ahub_info->playback_dma_param); ++ } else { ++ snd_soc_dai_set_dma_data(dai, substream, ++ &ahub_info->capture_dma_param); ++ } ++ ++ /* APBIF & I2S of RST and GAT */ ++ if (tdm_num > 3 || apb_num > 2) { ++ SND_LOG_ERR(HLOG, "unspport tdm num or apbif num\n"); ++ return -EINVAL; ++ } ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ regmap_update_bits(regmap, SUNXI_AHUB_RST, ++ 0x1 << (APBIF_TXDIF0_RST - apb_num), ++ 0x1 << (APBIF_TXDIF0_RST - apb_num)); ++ regmap_update_bits(regmap, SUNXI_AHUB_GAT, ++ 0x1 << (APBIF_TXDIF0_GAT - apb_num), ++ 0x1 << (APBIF_TXDIF0_GAT - apb_num)); ++ } else { ++ regmap_update_bits(regmap, SUNXI_AHUB_RST, ++ 0x1 << (APBIF_RXDIF0_RST - apb_num), ++ 0x1 << (APBIF_RXDIF0_RST - apb_num)); ++ regmap_update_bits(regmap, SUNXI_AHUB_GAT, ++ 0x1 << (APBIF_RXDIF0_GAT - apb_num), ++ 0x1 << (APBIF_RXDIF0_GAT - apb_num)); ++ } ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_set_pll(struct snd_soc_dai *dai, ++ int pll_id, int source, ++ unsigned int freq_in, unsigned int freq_out) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct sunxi_ahub_clk_info *clk_info = NULL; ++ ++ SND_LOG_DEBUG(HLOG, "stream -> %s, freq_in ->%u, freq_out ->%u\n", ++ pll_id ? "IN" : "OUT", freq_in, freq_out); ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null.\n"); ++ return -ENOMEM; ++ } ++ clk_info = &ahub_info->clk_info; ++ ++ if (freq_in > 24576000) { ++ //if (clk_set_parent(clk_info->clk_module, clk_info->clk_pllx4)) { ++ // SND_LOG_ERR(HLOG, "set parent of clk_module to pllx4 failed\n"); ++ // return -EINVAL; ++ //} ++ ++ if (clk_set_rate(clk_info->clk_pll, freq_in)) { ++ SND_LOG_ERR(HLOG, "freq : %u pllx4 clk unsupport\n", freq_in); ++ return -EINVAL; ++ } ++ } else { ++ //if (clk_set_parent(clk_info->clk_module, clk_info->clk_pll)) { ++ // SND_LOG_ERR(HLOG, "set parent of clk_module to pll failed\n"); ++ // return -EINVAL; ++ //} ++ if (clk_set_rate(clk_info->clk_pll, freq_in)) { ++ SND_LOG_ERR(HLOG, "freq : %u pll clk unsupport\n", freq_in); ++ return -EINVAL; ++ } ++ } ++ if (clk_set_rate(clk_info->clk_module, freq_out / 2)) { ++ SND_LOG_ERR(HLOG, "freq : %u module clk unsupport\n", freq_out); ++ return -EINVAL; ++ } ++ ++ ahub_info->pllclk_freq = freq_in; ++ ahub_info->mclk_freq = freq_out; ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id, ++ unsigned int freq, int dir) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int tdm_num; ++ unsigned int mclk_ratio, mclk_ratio_map; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null.\n"); ++ return -ENOMEM; ++ } ++ regmap = ahub_info->mem_info.regmap; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ ++ if (freq == 0) { ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num), ++ 0x1 << I2S_CLKD_MCLK, 0x0 << I2S_CLKD_MCLK); ++ SND_LOG_DEBUG(HLOG, "mclk freq: 0\n"); ++ return 0; ++ } ++ if (ahub_info->pllclk_freq == 0) { ++ SND_LOG_ERR(HLOG, "pllclk freq is invalid\n"); ++ return -ENOMEM; ++ } ++ mclk_ratio = ahub_info->pllclk_freq / freq; ++ ++ switch (mclk_ratio) { ++ case 1: ++ mclk_ratio_map = 1; ++ break; ++ case 2: ++ mclk_ratio_map = 2; ++ break; ++ case 4: ++ mclk_ratio_map = 3; ++ break; ++ case 6: ++ mclk_ratio_map = 4; ++ break; ++ case 8: ++ mclk_ratio_map = 5; ++ break; ++ case 12: ++ mclk_ratio_map = 6; ++ break; ++ case 16: ++ mclk_ratio_map = 7; ++ break; ++ case 24: ++ mclk_ratio_map = 8; ++ break; ++ case 32: ++ mclk_ratio_map = 9; ++ break; ++ case 48: ++ mclk_ratio_map = 10; ++ break; ++ case 64: ++ mclk_ratio_map = 11; ++ break; ++ case 96: ++ mclk_ratio_map = 12; ++ break; ++ case 128: ++ mclk_ratio_map = 13; ++ break; ++ case 176: ++ mclk_ratio_map = 14; ++ break; ++ case 192: ++ mclk_ratio_map = 15; ++ break; ++ default: ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num), ++ 0x1 << I2S_CLKD_MCLK, 0x0 << I2S_CLKD_MCLK); ++ SND_LOG_ERR(HLOG, "mclk freq div unsupport\n"); ++ return -EINVAL; ++ } ++ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num), ++ 0xf << I2S_CLKD_MCLKDIV, ++ mclk_ratio_map << I2S_CLKD_MCLKDIV); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num), ++ 0x1 << I2S_CLKD_MCLK, 0x1 << I2S_CLKD_MCLK); ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int tdm_num; ++ unsigned int bclk_ratio; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null.\n"); ++ return -ENOMEM; ++ } ++ regmap = ahub_info->mem_info.regmap; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ ++ /* ratio -> cpudai pllclk / pcm rate */ ++ switch (ratio) { ++ case 1: ++ bclk_ratio = 1; ++ break; ++ case 2: ++ bclk_ratio = 2; ++ break; ++ case 4: ++ bclk_ratio = 3; ++ break; ++ case 6: ++ bclk_ratio = 4; ++ break; ++ case 8: ++ bclk_ratio = 5; ++ break; ++ case 12: ++ bclk_ratio = 6; ++ break; ++ case 16: ++ bclk_ratio = 7; ++ break; ++ case 24: ++ bclk_ratio = 8; ++ break; ++ case 32: ++ bclk_ratio = 9; ++ break; ++ case 48: ++ bclk_ratio = 10; ++ break; ++ case 64: ++ bclk_ratio = 11; ++ break; ++ case 96: ++ bclk_ratio = 12; ++ break; ++ case 128: ++ bclk_ratio = 13; ++ break; ++ case 176: ++ bclk_ratio = 14; ++ break; ++ case 192: ++ bclk_ratio = 15; ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "bclk freq div unsupport\n"); ++ return -EINVAL; ++ } ++ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num), ++ 0xf << I2S_CLKD_BCLKDIV, ++ (bclk_ratio - 2) << I2S_CLKD_BCLKDIV); ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int tdm_num, tx_pin, rx_pin; ++ unsigned int mode, offset; ++ unsigned int lrck_polarity, brck_polarity; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ ahub_info->fmt = fmt; ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null.\n"); ++ return -ENOMEM; ++ } ++ regmap = ahub_info->mem_info.regmap; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ tx_pin = ahub_info->dts_info.tx_pin; ++ rx_pin = ahub_info->dts_info.rx_pin; ++ ++ /* set TDM format */ ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ mode = 1; ++ offset = 1; ++ break; ++ case SND_SOC_DAIFMT_RIGHT_J: ++ mode = 2; ++ offset = 0; ++ break; ++ case SND_SOC_DAIFMT_LEFT_J: ++ mode = 1; ++ offset = 0; ++ break; ++ case SND_SOC_DAIFMT_DSP_A: ++ mode = 0; ++ offset = 1; ++ /* L data MSB after FRM LRC (short frame) */ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x1 << I2S_FMT0_LRCK_WIDTH, ++ 0x0 << I2S_FMT0_LRCK_WIDTH); ++ break; ++ case SND_SOC_DAIFMT_DSP_B: ++ mode = 0; ++ offset = 0; ++ /* L data MSB during FRM LRC (long frame) */ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x1 << I2S_FMT0_LRCK_WIDTH, ++ 0x1 << I2S_FMT0_LRCK_WIDTH); ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "format setting failed\n"); ++ return -EINVAL; ++ } ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x3 << I2S_CTL_MODE, mode << I2S_CTL_MODE); ++ /* regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin), ++ * 0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET); ++ */ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 0), ++ 0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 1), ++ 0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 2), ++ 0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 3), ++ 0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_IN_SLOT(tdm_num), ++ 0x3 << I2S_IN_OFFSET, offset << I2S_IN_OFFSET); ++ ++ /* set lrck & bclk polarity */ ++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { ++ case SND_SOC_DAIFMT_NB_NF: ++ lrck_polarity = 0; ++ brck_polarity = 0; ++ break; ++ case SND_SOC_DAIFMT_NB_IF: ++ lrck_polarity = 1; ++ brck_polarity = 0; ++ break; ++ case SND_SOC_DAIFMT_IB_NF: ++ lrck_polarity = 0; ++ brck_polarity = 1; ++ break; ++ case SND_SOC_DAIFMT_IB_IF: ++ lrck_polarity = 1; ++ brck_polarity = 1; ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "invert clk setting failed\n"); ++ return -EINVAL; ++ } ++ if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_A) || ++ ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_B)) ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x1 << I2S_FMT0_LRCK_POLARITY, ++ (lrck_polarity^1) << I2S_FMT0_LRCK_POLARITY); ++ else ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x1 << I2S_FMT0_LRCK_POLARITY, ++ lrck_polarity << I2S_FMT0_LRCK_POLARITY); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x1 << I2S_FMT0_BCLK_POLARITY, ++ brck_polarity << I2S_FMT0_BCLK_POLARITY); ++ ++ /* set master/slave */ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBM_CFM: ++ /* lrck & bclk dir output */ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_CLK_OUT, 0x0 << I2S_CTL_CLK_OUT); ++ break; ++ case SND_SOC_DAIFMT_CBS_CFS: ++ /* lrck & bclk dir input */ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_CLK_OUT, 0x1 << I2S_CTL_CLK_OUT); ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "unknown master/slave format\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_set_tdm_slot(struct snd_soc_dai *dai, ++ unsigned int tx_mask, unsigned int rx_mask, ++ int slots, int slot_width) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int tdm_num, tx_pin, rx_pin; ++ unsigned int slot_width_map, lrck_width_map; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null\n"); ++ return -ENOMEM; ++ } ++ regmap = ahub_info->mem_info.regmap; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ tx_pin = ahub_info->dts_info.tx_pin; ++ rx_pin = ahub_info->dts_info.rx_pin; ++ ++ switch (slot_width) { ++ case 8: ++ slot_width_map = 1; ++ break; ++ case 12: ++ slot_width_map = 2; ++ break; ++ case 16: ++ slot_width_map = 3; ++ break; ++ case 20: ++ slot_width_map = 4; ++ break; ++ case 24: ++ slot_width_map = 5; ++ break; ++ case 28: ++ slot_width_map = 6; ++ break; ++ case 32: ++ slot_width_map = 7; ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "unknown slot width\n"); ++ return -EINVAL; ++ } ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x7 << I2S_FMT0_SW, slot_width_map << I2S_FMT0_SW); ++ ++ /* bclk num of per channel ++ * I2S/RIGHT_J/LEFT_J -> lrck long total is lrck_width_map * 2 ++ * DSP_A/DAP_B -> lrck long total is lrck_width_map * 1 ++ */ ++ switch (ahub_info->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ case SND_SOC_DAIFMT_RIGHT_J: ++ case SND_SOC_DAIFMT_LEFT_J: ++ slots /= 2; ++ break; ++ case SND_SOC_DAIFMT_DSP_A: ++ case SND_SOC_DAIFMT_DSP_B: ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "unsupoort format\n"); ++ return -EINVAL; ++ } ++ lrck_width_map = slots * slot_width - 1; ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x3ff << I2S_FMT0_LRCK_PERIOD, ++ lrck_width_map << I2S_FMT0_LRCK_PERIOD); ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int apb_num, tdm_num, tx_pin, rx_pin; ++ unsigned int channels; ++ unsigned int channels_en[16] = { ++ 0x0001, 0x0003, 0x0007, 0x000f, 0x001f, 0x003f, 0x007f, 0x00ff, ++ 0x01ff, 0x03ff, 0x07ff, 0x0fff, 0x1fff, 0x3fff, 0x7fff, 0xffff ++ }; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null.\n"); ++ return -ENOMEM; ++ } ++ regmap = ahub_info->mem_info.regmap; ++ apb_num = ahub_info->dts_info.apb_num; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ tx_pin = ahub_info->dts_info.tx_pin; ++ rx_pin = ahub_info->dts_info.rx_pin; ++ ++ /* configure DMA */ ++ switch (params_physical_width(params)) { ++ case 16: ++ ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ break; ++ case 24: ++ case 32: ++ ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ break; ++ default: ++ dev_err(dai->dev, "Unsupported physical sample width: %d\n", ++ params_physical_width(params)); ++ return -EINVAL; ++ } ++ ++ /* set bits */ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ /* apbifn bits */ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ regmap_update_bits(regmap, ++ SUNXI_AHUB_APBIF_TX_CTL(apb_num), ++ 0x7 << APBIF_TX_WS, ++ 0x3 << APBIF_TX_WS); ++ regmap_update_bits(regmap, ++ SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num), ++ 0x1 << APBIF_TX_TXIM, ++ 0x1 << APBIF_TX_TXIM); ++ } else { ++ regmap_update_bits(regmap, ++ SUNXI_AHUB_APBIF_RX_CTL(apb_num), ++ 0x7 << APBIF_RX_WS, ++ 0x3 << APBIF_RX_WS); ++ regmap_update_bits(regmap, ++ SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num), ++ 0x3 << APBIF_RX_RXOM, ++ 0x1 << APBIF_RX_RXOM); ++ } ++ ++ regmap_update_bits(regmap, ++ SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x7 << I2S_FMT0_SR, ++ 0x3 << I2S_FMT0_SR); ++ break; ++ case SNDRV_PCM_FORMAT_S20_3LE: ++ case SNDRV_PCM_FORMAT_S24_LE: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num), ++ 0x7 << APBIF_TX_WS, 0x5 << APBIF_TX_WS); ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num), ++ 0x1 << APBIF_TX_TXIM, 0x1 << APBIF_TX_TXIM); ++ } else { ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num), ++ 0x7 << APBIF_RX_WS, 0x5 << APBIF_RX_WS); ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num), ++ 0x3 << APBIF_RX_RXOM, 0x1 << APBIF_RX_RXOM); ++ } ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x7 << I2S_FMT0_SR, 0x5 << I2S_FMT0_SR); ++ break; ++ case SNDRV_PCM_FORMAT_S32_LE: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num), ++ 0x7 << APBIF_TX_WS, 0x7 << APBIF_TX_WS); ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num), ++ 0x1 << APBIF_TX_TXIM, 0x1 << APBIF_TX_TXIM); ++ } else { ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num), ++ 0x7 << APBIF_RX_WS, 0x7 << APBIF_RX_WS); ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num), ++ 0x3 << APBIF_RX_RXOM, 0x1 << APBIF_RX_RXOM); ++ } ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x7 << I2S_FMT0_SR, 0x7 << I2S_FMT0_SR); ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "unrecognized format bits\n"); ++ return -EINVAL; ++ } ++ ++ /* set channels */ ++ channels = params_channels(params); ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ /* apbifn channels */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num), ++ 0xf << APBIF_TX_CHAN_NUM, ++ (channels - 1) << APBIF_TX_CHAN_NUM); ++ /* tdmn channels */ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CHCFG(tdm_num), ++ 0xf << I2S_CHCFG_TX_CHANNUM, ++ (channels - 1) << I2S_CHCFG_TX_CHANNUM); ++ ++ regmap_update_bits(regmap, ++ SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin), ++ 0xf << I2S_OUT_SLOT_NUM, ++ (channels - 1) << I2S_OUT_SLOT_NUM); ++ regmap_update_bits(regmap, ++ SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin), ++ 0xffff << I2S_OUT_SLOT_EN, ++ channels_en[channels - 1] << I2S_OUT_SLOT_EN); ++ } else { ++ /* apbifn channels */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num), ++ 0xf << APBIF_RX_CHAN_NUM, ++ (channels - 1) << APBIF_RX_CHAN_NUM); ++ /* tdmn channels */ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CHCFG(tdm_num), ++ 0xf << I2S_CHCFG_RX_CHANNUM, ++ (channels - 1) << I2S_CHCFG_RX_CHANNUM); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_IN_SLOT(tdm_num), ++ 0xf << I2S_IN_SLOT_NUM, ++ (channels - 1) << I2S_IN_SLOT_NUM); ++ } ++ ++ return 0; ++} ++ ++static void sunxi_ahub_dai_tx_route(struct sunxi_ahub_info *ahub_info, ++ bool enable) ++{ ++ struct regmap *regmap = NULL; ++ unsigned int tdm_num, tx_pin; ++ unsigned int apb_num; ++ ++ SND_LOG_DEBUG(HLOG, "%s\n", enable ? "on" : "off"); ++ ++ regmap = ahub_info->mem_info.regmap; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ tx_pin = ahub_info->dts_info.tx_pin; ++ apb_num = ahub_info->dts_info.apb_num; ++ ++ if (enable) ++ goto tx_route_enable; ++ else ++ goto tx_route_disable; ++ ++tx_route_enable: ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << (I2S_CTL_SDO0_EN + tx_pin), ++ 0x1 << (I2S_CTL_SDO0_EN + tx_pin)); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_TXEN, 0x1 << I2S_CTL_TXEN); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_OUT_MUTE, 0x0 << I2S_CTL_OUT_MUTE); ++ /* start apbif tx */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num), ++ 0x1 << APBIF_TX_START, 0x1 << APBIF_TX_START); ++ /* enable tx drq */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_IRQ_CTL(apb_num), ++ 0x1 << APBIF_TX_DRQ, 0x1 << APBIF_TX_DRQ); ++ return; ++ ++tx_route_disable: ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_OUT_MUTE, 0x1 << I2S_CTL_OUT_MUTE); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_TXEN, 0x0 << I2S_CTL_TXEN); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << (I2S_CTL_SDO0_EN + tx_pin), ++ 0x0 << (I2S_CTL_SDO0_EN + tx_pin)); ++ /* stop apbif tx */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num), ++ 0x1 << APBIF_TX_START, 0x0 << APBIF_TX_START); ++ /* disable tx drq */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_IRQ_CTL(apb_num), ++ 0x1 << APBIF_TX_DRQ, 0x0 << APBIF_TX_DRQ); ++ return; ++} ++ ++static void sunxi_ahub_dai_rx_route(struct sunxi_ahub_info *ahub_info, ++ bool enable) ++{ ++ struct regmap *regmap = NULL; ++ unsigned int tdm_num, rx_pin; ++ unsigned int apb_num; ++ ++ SND_LOG_DEBUG(HLOG, "%s\n", enable ? "on" : "off"); ++ ++ regmap = ahub_info->mem_info.regmap; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ rx_pin = ahub_info->dts_info.rx_pin; ++ apb_num = ahub_info->dts_info.apb_num; ++ ++ if (enable) ++ goto rx_route_enable; ++ else ++ goto rx_route_disable; ++ ++rx_route_enable: ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << (I2S_CTL_SDI0_EN + rx_pin), ++ 0x1 << (I2S_CTL_SDI0_EN + rx_pin)); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_RXEN, 0x1 << I2S_CTL_RXEN); ++ /* start apbif rx */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num), ++ 0x1 << APBIF_RX_START, 0x1 << APBIF_RX_START); ++ /* enable rx drq */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_IRQ_CTL(apb_num), ++ 0x1 << APBIF_RX_DRQ, 0x1 << APBIF_RX_DRQ); ++ return; ++ ++rx_route_disable: ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_RXEN, 0x0 << I2S_CTL_RXEN); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << (I2S_CTL_SDI0_EN + rx_pin), ++ 0x0 << (I2S_CTL_SDI0_EN + rx_pin)); ++ /* stop apbif rx */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num), ++ 0x1 << APBIF_RX_START, 0x0 << APBIF_RX_START); ++ /* disable rx drq */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_IRQ_CTL(apb_num), ++ 0x1 << APBIF_RX_DRQ, 0x0 << APBIF_RX_DRQ); ++ return; ++} ++ ++static int sunxi_ahub_dai_trigger(struct snd_pcm_substream *substream, ++ int cmd, ++ struct snd_soc_dai *dai) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null.\n"); ++ return -ENOMEM; ++ } ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ sunxi_ahub_dai_tx_route(ahub_info, true); ++ } else { ++ sunxi_ahub_dai_rx_route(ahub_info, true); ++ } ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ sunxi_ahub_dai_tx_route(ahub_info, false); ++ } else { ++ sunxi_ahub_dai_rx_route(ahub_info, false); ++ } ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_prepare(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int apb_num; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null.\n"); ++ return -ENOMEM; ++ } ++ regmap = ahub_info->mem_info.regmap; ++ apb_num = ahub_info->dts_info.apb_num; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ /* clear txfifo */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num), ++ 0x1 << APBIF_TX_FTX, 0x1 << APBIF_TX_FTX); ++ /* clear tx o/u irq */ ++ regmap_write(regmap, SUNXI_AHUB_APBIF_TX_IRQ_STA(apb_num), ++ (0x1 << APBIF_TX_OV_PEND) | (0x1 << APBIF_TX_EM_PEND)); ++ /* clear tx fifo cnt */ ++ regmap_write(regmap, SUNXI_AHUB_APBIF_TXFIFO_CNT(apb_num), 0); ++ } else { ++ /* clear rxfifo */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num), ++ 0x1 << APBIF_RX_FRX, 0x1 << APBIF_RX_FRX); ++ /* clear rx o/u irq */ ++ regmap_write(regmap, SUNXI_AHUB_APBIF_RX_IRQ_STA(apb_num), ++ (0x1 << APBIF_RX_UV_PEND) | (0x1 << APBIF_RX_AV_PEND)); ++ /* clear rx fifo cnt */ ++ regmap_write(regmap, SUNXI_AHUB_APBIF_RXFIFO_CNT(apb_num), 0); ++ } ++ ++ return 0; ++} ++ ++static void sunxi_ahub_dai_shutdown(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int apb_num, tdm_num; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ regmap = ahub_info->mem_info.regmap; ++ apb_num = ahub_info->dts_info.apb_num; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ ++ /* APBIF & I2S of RST and GAT */ ++ if (tdm_num > 3 || apb_num > 2) { ++ SND_LOG_ERR(HLOG, "unspport tdm num or apbif num\n"); ++ return; ++ } ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ regmap_update_bits(regmap, SUNXI_AHUB_RST, ++ 0x1 << (APBIF_TXDIF0_RST - apb_num), ++ 0x0 << (APBIF_TXDIF0_RST - apb_num)); ++ regmap_update_bits(regmap, SUNXI_AHUB_GAT, ++ 0x1 << (APBIF_TXDIF0_GAT - apb_num), ++ 0x0 << (APBIF_TXDIF0_GAT - apb_num)); ++ } else { ++ regmap_update_bits(regmap, SUNXI_AHUB_RST, ++ 0x1 << (APBIF_RXDIF0_RST - apb_num), ++ 0x0 << (APBIF_RXDIF0_RST - apb_num)); ++ regmap_update_bits(regmap, SUNXI_AHUB_GAT, ++ 0x1 << (APBIF_RXDIF0_GAT - apb_num), ++ 0x0 << (APBIF_RXDIF0_GAT - apb_num)); ++ } ++} ++ ++static const struct snd_soc_dai_ops sunxi_ahub_dai_ops = { ++ /* call by machine */ ++ .set_pll = sunxi_ahub_dai_set_pll, // set pllclk ++ .set_sysclk = sunxi_ahub_dai_set_sysclk, // set mclk ++ .set_bclk_ratio = sunxi_ahub_dai_set_bclk_ratio,// set bclk freq ++ .set_tdm_slot = sunxi_ahub_dai_set_tdm_slot, // set slot num and width ++ .set_fmt = sunxi_ahub_dai_set_fmt, // set tdm fmt ++ /* call by asoc */ ++ .startup = sunxi_ahub_dai_startup, ++ .hw_params = sunxi_ahub_dai_hw_params, // set hardware params ++ .prepare = sunxi_ahub_dai_prepare, // clean irq and fifo ++ .trigger = sunxi_ahub_dai_trigger, // set drq ++ .shutdown = sunxi_ahub_dai_shutdown, ++}; ++ ++static void snd_soc_sunxi_ahub_init(struct sunxi_ahub_info *ahub_info) ++{ ++ struct regmap *regmap = NULL; ++ unsigned int apb_num, tdm_num, tx_pin, rx_pin; ++ unsigned int reg_val = 0; ++ unsigned int rx_pin_map = 0; ++ unsigned int tdm_to_apb = 0; ++ unsigned int apb_to_tdm = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ regmap = ahub_info->mem_info.regmap; ++ apb_num = ahub_info->dts_info.apb_num; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ tx_pin = ahub_info->dts_info.tx_pin; ++ rx_pin = ahub_info->dts_info.rx_pin; ++ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_GEN, 0x1 << I2S_CTL_GEN); ++ regmap_update_bits(regmap, SUNXI_AHUB_RST, ++ 0x1 << (I2S0_RST - tdm_num), ++ 0x1 << (I2S0_RST - tdm_num)); ++ regmap_update_bits(regmap, SUNXI_AHUB_GAT, ++ 0x1 << (I2S0_GAT - tdm_num), ++ 0x1 << (I2S0_GAT - tdm_num)); ++ ++ /* tdm tx channels map */ ++ regmap_write(regmap, SUNXI_AHUB_I2S_OUT_CHMAP0(tdm_num, tx_pin), 0x76543210); ++ regmap_write(regmap, SUNXI_AHUB_I2S_OUT_CHMAP1(tdm_num, tx_pin), 0xFEDCBA98); ++ ++ /* tdm rx channels map */ ++ rx_pin_map = (rx_pin << 4) | (rx_pin << 12) | (rx_pin << 20) | (rx_pin << 28); ++ reg_val = 0x03020100 | rx_pin_map; ++ regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP0(tdm_num), reg_val); ++ reg_val = 0x07060504 | rx_pin_map; ++ regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP1(tdm_num), reg_val); ++ reg_val = 0x0B0A0908 | rx_pin_map; ++ regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP2(tdm_num), reg_val); ++ reg_val = 0x0F0E0D0C | rx_pin_map; ++ regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP3(tdm_num), reg_val); ++ ++ /* tdm tx & rx data fmt ++ * 1. MSB first ++ * 2. transfer 0 after each sample in each slot ++ * 3. linear PCM ++ */ ++ regmap_write(regmap, SUNXI_AHUB_I2S_FMT1(tdm_num), 0x30); ++ ++ /* apbif tx & rx data fmt ++ * 1. MSB first ++ * 2. trigger level tx -> 0x20, rx -> 0x40 ++ */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num), ++ 0x1 << APBIF_TX_TXIM, 0x0 << APBIF_TX_TXIM); ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num), ++ 0x3f << APBIF_TX_LEVEL, 0x20 << APBIF_TX_LEVEL); ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num), ++ 0x3 << APBIF_RX_RXOM, 0x0 << APBIF_RX_RXOM); ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num), ++ 0x7f << APBIF_RX_LEVEL, 0x40 << APBIF_RX_LEVEL); ++ ++ /* apbif <-> tdm */ ++ switch (tdm_num) ++ { ++ case 0: ++ tdm_to_apb = APBIF_RX_I2S0_TXDIF; ++ break; ++ case 1: ++ tdm_to_apb = APBIF_RX_I2S1_TXDIF; ++ break; ++ case 2: ++ tdm_to_apb = APBIF_RX_I2S2_TXDIF; ++ break; ++ case 3: ++ tdm_to_apb = APBIF_RX_I2S3_TXDIF; ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "unspport tdm num\n"); ++ return; ++ } ++ regmap_write(regmap, SUNXI_AHUB_APBIF_RXFIFO_CONT(apb_num), 0x1 << tdm_to_apb); ++ ++ switch (apb_num) ++ { ++ case 0: ++ apb_to_tdm = I2S_RX_APBIF_TXDIF0; ++ break; ++ case 1: ++ apb_to_tdm = I2S_RX_APBIF_TXDIF1; ++ break; ++ case 2: ++ apb_to_tdm = I2S_RX_APBIF_TXDIF2; ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "unspport apb num\n"); ++ return; ++ } ++ regmap_write(regmap, SUNXI_AHUB_I2S_RXCONT(tdm_num), 0x1 << apb_to_tdm); ++ ++ return; ++} ++ ++static int sunxi_ahub_dai_probe(struct snd_soc_dai *dai) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ /* pcm_new will using the dma_param about the cma and fifo params. */ ++ snd_soc_dai_init_dma_data(dai, ++ &ahub_info->playback_dma_param, ++ &ahub_info->capture_dma_param); ++ ++ snd_soc_sunxi_ahub_init(ahub_info); ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_remove(struct snd_soc_dai *dai) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int tdm_num; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ regmap = ahub_info->mem_info.regmap; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_GEN, 0x0 << I2S_CTL_GEN); ++ regmap_update_bits(regmap, SUNXI_AHUB_RST, ++ 0x1 << (I2S0_RST - tdm_num), ++ 0x0 << (I2S0_RST - tdm_num)); ++ regmap_update_bits(regmap, SUNXI_AHUB_GAT, ++ 0x1 << (I2S0_GAT - tdm_num), ++ 0x0 << (I2S0_GAT - tdm_num)); ++ ++ return 0; ++} ++ ++static struct snd_soc_dai_driver sunxi_ahub_dai = { ++ .name = "ahub_plat", ++ .probe = sunxi_ahub_dai_probe, ++ .remove = sunxi_ahub_dai_remove, ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000 ++ | SNDRV_PCM_RATE_KNOT, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE ++ | SNDRV_PCM_FMTBIT_S24_LE ++ | SNDRV_PCM_FMTBIT_S32_LE, ++ }, ++ .capture = { ++ .stream_name = "Capture", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000 ++ | SNDRV_PCM_RATE_KNOT, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE ++ | SNDRV_PCM_FMTBIT_S24_LE ++ | SNDRV_PCM_FMTBIT_S32_LE, ++ }, ++ .ops = &sunxi_ahub_dai_ops, ++}; ++ ++static int sunxi_ahub_probe(struct snd_soc_component *component) ++{ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ return 0; ++} ++ ++static int sunxi_ahub_suspend(struct snd_soc_component *component) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component); ++ struct regmap *regmap = NULL; ++ unsigned int apb_num, tdm_num; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ regmap = ahub_info->mem_info.regmap; ++ apb_num = ahub_info->dts_info.apb_num; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ ++ return 0; ++} ++ ++static int sunxi_ahub_resume(struct snd_soc_component *component) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component); ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ snd_soc_sunxi_ahub_init(ahub_info); ++ ++ return 0; ++} ++ ++int sunxi_loopback_debug_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ unsigned int reg_val; ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component); ++ struct sunxi_ahub_mem_info *mem_info = &ahub_info->mem_info; ++ struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info; ++ ++ regmap_read(mem_info->regmap, SUNXI_AHUB_I2S_CTL(dts_info->tdm_num), ®_val); ++ ucontrol->value.integer.value[0] = ((reg_val & (1 << I2S_CTL_LOOP0)) ? 1 : 0); ++ ++ return 0; ++} ++ ++int sunxi_loopback_debug_set(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component); ++ struct sunxi_ahub_mem_info *mem_info = &ahub_info->mem_info; ++ struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info; ++ ++ switch (ucontrol->value.integer.value[0]) { ++ case 0: ++ regmap_update_bits(mem_info->regmap, ++ SUNXI_AHUB_I2S_CTL(dts_info->tdm_num), ++ 1 << I2S_CTL_LOOP0, 0 << I2S_CTL_LOOP0); ++ break; ++ case 1: ++ regmap_update_bits(mem_info->regmap, ++ SUNXI_AHUB_I2S_CTL(dts_info->tdm_num), ++ 1 << I2S_CTL_LOOP0, 1 << I2S_CTL_LOOP0); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static const struct snd_kcontrol_new sunxi_ahub_controls[] = { ++ SOC_SINGLE_EXT("loopback debug", SND_SOC_NOPM, 0, 1, 0, ++ sunxi_loopback_debug_get, sunxi_loopback_debug_set), ++}; ++ ++static struct snd_soc_component_driver sunxi_ahub_component = { ++ .name = DRV_NAME, ++ .probe = sunxi_ahub_probe, ++ .suspend = sunxi_ahub_suspend, ++ .resume = sunxi_ahub_resume, ++ .controls = sunxi_ahub_controls, ++ .num_controls = ARRAY_SIZE(sunxi_ahub_controls), ++}; ++ ++/******************************************************************************* ++ * for kernel source ++ ******************************************************************************/ ++static int snd_soc_sunxi_ahub_pin_init(struct platform_device *pdev, ++ struct device_node *np, ++ struct sunxi_ahub_pinctl_info *pin_info) ++{ ++ int ret = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (of_property_read_bool(np, "pinctrl_used")) { ++ pin_info->pinctrl_used = 1; ++ } else { ++ pin_info->pinctrl_used = 0; ++ SND_LOG_DEBUG(HLOG, "unused pinctrl\n"); ++ return 0; ++ } ++ ++ pin_info->pinctrl = devm_pinctrl_get(&pdev->dev); ++ if (IS_ERR_OR_NULL(pin_info->pinctrl)) { ++ SND_LOG_ERR(HLOG, "pinctrl get failed\n"); ++ ret = -EINVAL; ++ return ret; ++ } ++ pin_info->pinstate = pinctrl_lookup_state(pin_info->pinctrl, ++ PINCTRL_STATE_DEFAULT); ++ if (IS_ERR_OR_NULL(pin_info->pinstate)) { ++ SND_LOG_ERR(HLOG, "pinctrl default state get fail\n"); ++ ret = -EINVAL; ++ goto err_loopup_pinstate; ++ } ++ pin_info->pinstate_sleep = pinctrl_lookup_state(pin_info->pinctrl, ++ PINCTRL_STATE_SLEEP); ++ if (IS_ERR_OR_NULL(pin_info->pinstate_sleep)) { ++ SND_LOG_ERR(HLOG, "pinctrl sleep state get failed\n"); ++ ret = -EINVAL; ++ goto err_loopup_pin_sleep; ++ } ++ ret = pinctrl_select_state(pin_info->pinctrl, pin_info->pinstate); ++ if (ret < 0) { ++ SND_LOG_ERR(HLOG, "daudio set pinctrl default state fail\n"); ++ ret = -EBUSY; ++ goto err_pinctrl_select_default; ++ } ++ ++ return 0; ++ ++err_pinctrl_select_default: ++err_loopup_pin_sleep: ++err_loopup_pinstate: ++ devm_pinctrl_put(pin_info->pinctrl); ++ return ret; ++} ++ ++static int snd_soc_sunxi_ahub_dts_params_init(struct platform_device *pdev, ++ struct device_node *np, ++ struct sunxi_ahub_dts_info *dts_info) ++{ ++ int ret = 0; ++ unsigned int temp_val = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ /* get tdm fmt of apb_num & tdm_num & tx/rx_pin */ ++ ret = of_property_read_u32(np, "apb_num", &temp_val); ++ if (ret < 0) { ++ SND_LOG_WARN(HLOG, "apb_num config missing\n"); ++ dts_info->apb_num = 0; ++ } else { ++ if (temp_val > 2) { /* APBIFn (n = 0~2) */ ++ dts_info->apb_num = 0; ++ SND_LOG_WARN(HLOG, "apb_num config invalid\n"); ++ } else { ++ dts_info->apb_num = temp_val; ++ } ++ } ++ ret = of_property_read_u32(np, "tdm_num", &temp_val); ++ if (ret < 0) { ++ SND_LOG_WARN(HLOG, "tdm_num config missing\n"); ++ dts_info->tdm_num = 0; ++ } else { ++ if (temp_val > 3) { /* I2Sn (n = 0~3) */ ++ dts_info->tdm_num = 0; ++ SND_LOG_WARN(HLOG, "tdm_num config invalid\n"); ++ } else { ++ dts_info->tdm_num = temp_val; ++ } ++ } ++ ret = of_property_read_u32(np, "tx_pin", &temp_val); ++ if (ret < 0) { ++ SND_LOG_WARN(HLOG, "tx_pin config missing\n"); ++ dts_info->tx_pin = 0; ++ } else { ++ if (temp_val > 3) { /* I2S_DOUTn (n = 0~3) */ ++ dts_info->tx_pin = 0; ++ SND_LOG_WARN(HLOG, "tx_pin config invalid\n"); ++ } else { ++ dts_info->tx_pin = temp_val; ++ } ++ } ++ ret = of_property_read_u32(np, "rx_pin", &temp_val); ++ if (ret < 0) { ++ SND_LOG_WARN(HLOG, "rx_pin config missing\n"); ++ dts_info->rx_pin = 0; ++ } else { ++ if (temp_val > 3) { /* I2S_DINTn (n = 0~3) */ ++ dts_info->rx_pin = 0; ++ SND_LOG_WARN(HLOG, "rx_pin config invalid\n"); ++ } else { ++ dts_info->rx_pin = temp_val; ++ } ++ } ++ ++ SND_LOG_DEBUG(HLOG, "playback_cma : %lu\n", dts_info->playback_cma); ++ SND_LOG_DEBUG(HLOG, "capture_cma : %lu\n", dts_info->capture_cma); ++ SND_LOG_DEBUG(HLOG, "tx_fifo_size : %lu\n", dts_info->playback_fifo_size); ++ SND_LOG_DEBUG(HLOG, "rx_fifo_size : %lu\n", dts_info->capture_fifo_size); ++ SND_LOG_DEBUG(HLOG, "apb_num : %u\n", dts_info->apb_num); ++ SND_LOG_DEBUG(HLOG, "tdm_num : %u\n", dts_info->tdm_num); ++ SND_LOG_DEBUG(HLOG, "tx_pin : %u\n", dts_info->tx_pin); ++ SND_LOG_DEBUG(HLOG, "rx_pin : %u\n", dts_info->rx_pin); ++ ++ return 0; ++}; ++ ++static int snd_soc_sunxi_ahub_regulator_init(struct platform_device *pdev, ++ struct device_node *np, ++ struct sunxi_ahub_regulator_info *regulator_info) ++{ ++ int ret = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ regulator_info->regulator_name = NULL; ++ if (of_property_read_string(np, "ahub_regulator", ®ulator_info->regulator_name)) { ++ SND_LOG_DEBUG(HLOG, "regulator missing\n"); ++ regulator_info->regulator = NULL; ++ return 0; ++ } ++ ++ regulator_info->regulator = regulator_get(NULL, regulator_info->regulator_name); ++ if (IS_ERR_OR_NULL(regulator_info->regulator)) { ++ SND_LOG_ERR(HLOG, "get duaido vcc-pin failed\n"); ++ ret = -EFAULT; ++ goto err_regulator_get; ++ } ++ ret = regulator_set_voltage(regulator_info->regulator, 3300000, 3300000); ++ if (ret < 0) { ++ SND_LOG_ERR(HLOG, "set duaido voltage failed\n"); ++ ret = -EFAULT; ++ goto err_regulator_set_vol; ++ } ++ ret = regulator_enable(regulator_info->regulator); ++ if (ret < 0) { ++ SND_LOG_ERR(HLOG, "enable duaido vcc-pin failed\n"); ++ ret = -EFAULT; ++ goto err_regulator_enable; ++ } ++ ++ return 0; ++ ++err_regulator_enable: ++err_regulator_set_vol: ++ if (regulator_info->regulator) ++ regulator_put(regulator_info->regulator); ++err_regulator_get: ++ return ret; ++}; ++ ++static void snd_soc_sunxi_dma_params_init(struct sunxi_ahub_info *ahub_info) ++{ ++ struct resource *res = ahub_info->mem_info.res; ++ struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ ahub_info->playback_dma_param.addr = ++ res->start + SUNXI_AHUB_APBIF_TXFIFO(dts_info->apb_num); ++ ahub_info->playback_dma_param.maxburst = 8; ++ //ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ ++ ahub_info->capture_dma_param.addr = ++ res->start + SUNXI_AHUB_APBIF_RXFIFO(dts_info->apb_num); ++ ahub_info->capture_dma_param.maxburst = 8; ++ //ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++}; ++ ++static int sunxi_ahub_dev_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct device_node *np = pdev->dev.of_node; ++ struct sunxi_ahub_info *ahub_info = NULL; ++ struct sunxi_ahub_mem_info *mem_info = NULL; ++ struct sunxi_ahub_clk_info *clk_info = NULL; ++ struct sunxi_ahub_pinctl_info *pin_info = NULL; ++ struct sunxi_ahub_dts_info *dts_info = NULL; ++ struct sunxi_ahub_regulator_info *regulator_info = NULL; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ ahub_info = devm_kzalloc(&pdev->dev, ++ sizeof(struct sunxi_ahub_info), ++ GFP_KERNEL); ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "alloc sunxi_ahub_info failed\n"); ++ ret = -ENOMEM; ++ goto err_devm_malloc_sunxi_daudio; ++ } ++ dev_set_drvdata(&pdev->dev, ahub_info); ++ ahub_info->dev = &pdev->dev; ++ mem_info = &ahub_info->mem_info; ++ clk_info = &ahub_info->clk_info; ++ pin_info = &ahub_info->pin_info; ++ dts_info = &ahub_info->dts_info; ++ regulator_info = &ahub_info->regulator_info; ++ ++ ret = snd_soc_sunxi_ahub_mem_get(mem_info); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "remap get failed\n"); ++ ret = -EINVAL; ++ goto err_snd_soc_sunxi_ahub_mem_get; ++ } ++ ++ ret = snd_soc_sunxi_ahub_clk_get(clk_info); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "clk get failed\n"); ++ ret = -EINVAL; ++ goto err_snd_soc_sunxi_ahub_clk_get; ++ } ++ ++ ret = snd_soc_sunxi_ahub_dts_params_init(pdev, np, dts_info); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "dts init failed\n"); ++ ret = -EINVAL; ++ goto err_snd_soc_sunxi_ahub_dts_params_init; ++ } ++ ++ ret = snd_soc_sunxi_ahub_pin_init(pdev, np, pin_info); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "pinctrl init failed\n"); ++ ret = -EINVAL; ++ goto err_snd_soc_sunxi_ahub_pin_init; ++ } ++ ++ ret = snd_soc_sunxi_ahub_regulator_init(pdev, np, regulator_info); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "regulator_info init failed\n"); ++ ret = -EINVAL; ++ goto err_snd_soc_sunxi_ahub_regulator_init; ++ } ++ ++ snd_soc_sunxi_dma_params_init(ahub_info); ++ ++ ret = snd_soc_register_component(&pdev->dev, ++ &sunxi_ahub_component, ++ &sunxi_ahub_dai, 1); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "component register failed\n"); ++ ret = -ENOMEM; ++ goto err_snd_soc_register_component; ++ } ++ ++ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "register ASoC platform failed\n"); ++ ret = -ENOMEM; ++ goto err_snd_soc_sunxi_dma_platform_register; ++ } ++ ++ SND_LOG_DEBUG(HLOG, "register ahub platform success\n"); ++ ++ return 0; ++ ++err_snd_soc_sunxi_dma_platform_register: ++ snd_soc_unregister_component(&pdev->dev); ++err_snd_soc_register_component: ++err_snd_soc_sunxi_ahub_regulator_init: ++err_snd_soc_sunxi_ahub_dts_params_init: ++err_snd_soc_sunxi_ahub_pin_init: ++err_snd_soc_sunxi_ahub_clk_get: ++err_snd_soc_sunxi_ahub_mem_get: ++ devm_kfree(&pdev->dev, ahub_info); ++err_devm_malloc_sunxi_daudio: ++ of_node_put(np); ++ return ret; ++} ++ ++static int sunxi_ahub_dev_remove(struct platform_device *pdev) ++{ ++ struct sunxi_ahub_info *ahub_info = dev_get_drvdata(&pdev->dev); ++ struct sunxi_ahub_pinctl_info *pin_info = &ahub_info->pin_info; ++ struct sunxi_ahub_regulator_info *regulator_info = &ahub_info->regulator_info; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ snd_soc_unregister_component(&pdev->dev); ++ ++ if (regulator_info->regulator) { ++ if (!IS_ERR_OR_NULL(regulator_info->regulator)) { ++ regulator_disable(regulator_info->regulator); ++ regulator_put(regulator_info->regulator); ++ } ++ } ++ if (pin_info->pinctrl_used) { ++ devm_pinctrl_put(pin_info->pinctrl); ++ } ++ ++ devm_kfree(&pdev->dev, ahub_info); ++ ++ SND_LOG_DEBUG(HLOG, "unregister ahub platform success\n"); ++ ++ return 0; ++} ++ ++static const struct of_device_id sunxi_ahub_of_match[] = { ++ { .compatible = "allwinner," DRV_NAME, }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, sunxi_ahub_of_match); ++ ++static struct platform_driver sunxi_ahub_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = sunxi_ahub_of_match, ++ }, ++ .probe = sunxi_ahub_dev_probe, ++ .remove = sunxi_ahub_dev_remove, ++}; ++ ++int __init sunxi_ahub_dev_init(void) ++{ ++ int ret; ++ ++ ret = platform_driver_register(&sunxi_ahub_driver); ++ if (ret != 0) { ++ SND_LOG_ERR(HLOG, "platform driver register failed\n"); ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ ++void __exit sunxi_ahub_dev_exit(void) ++{ ++ platform_driver_unregister(&sunxi_ahub_driver); ++} ++ ++late_initcall(sunxi_ahub_dev_init); ++module_exit(sunxi_ahub_dev_exit); ++ ++MODULE_AUTHOR("Dby@allwinnertech.com"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("sunxi soundcard platform of ahub"); +diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub.h b/sound/soc/sunxi_v2/snd_sunxi_ahub.h +new file mode 100644 +index 000000000..b3c1cc592 +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub.h +@@ -0,0 +1,67 @@ ++/* sound\soc\sunxi\snd_sunxi_ahub.h ++ * (C) Copyright 2021-2025 ++ * Allwinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#ifndef __SND_SUNXI_AHUB_H ++#define __SND_SUNXI_AHUB_H ++ ++#include "snd_sunxi_ahub_dam.h" ++ ++struct sunxi_ahub_pinctl_info { ++ struct pinctrl *pinctrl; ++ struct pinctrl_state *pinstate; ++ struct pinctrl_state *pinstate_sleep; ++ ++ bool pinctrl_used; ++}; ++ ++struct sunxi_ahub_dts_info { ++ unsigned int dai_type; ++ unsigned int apb_num; ++ unsigned int tdm_num; ++ unsigned int tx_pin; ++ unsigned int rx_pin; ++ ++ /* value must be (2^n)Kbyte */ ++ size_t playback_cma; ++ size_t playback_fifo_size; ++ size_t capture_cma; ++ size_t capture_fifo_size; ++}; ++ ++struct sunxi_ahub_regulator_info { ++ struct regulator *regulator; ++ const char *regulator_name; ++}; ++ ++struct sunxi_ahub_info { ++ struct device *dev; ++ ++ struct sunxi_ahub_mem_info mem_info; ++ struct sunxi_ahub_clk_info clk_info; ++ struct sunxi_ahub_pinctl_info pin_info; ++ struct sunxi_ahub_dts_info dts_info; ++ struct sunxi_ahub_regulator_info regulator_info; ++ ++ //struct sunxi_dma_params playback_dma_param; ++ //struct sunxi_dma_params capture_dma_param; ++ struct snd_dmaengine_dai_dma_data playback_dma_param; ++ struct snd_dmaengine_dai_dma_data capture_dma_param; ++ ++ /* for Hardware param setting */ ++ unsigned int fmt; ++ unsigned int pllclk_freq; ++ unsigned int moduleclk_freq; ++ unsigned int mclk_freq; ++ unsigned int lrck_freq; ++ unsigned int bclk_freq; ++}; ++ ++#endif /* __SND_SUNXI_AHUB_H */ +diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c +new file mode 100644 +index 000000000..1fcc8aefd +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c +@@ -0,0 +1,534 @@ ++/* ++ * sound\soc\sunxi\snd_sunxi_ahub_dam.c ++ * (C) Copyright 2021-2025 ++ * AllWinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "snd_sunxi_log.h" ++#include "snd_sunxi_ahub_dam.h" ++ ++#define HLOG "AHUB_DAM" ++#define DRV_NAME "sunxi-snd-plat-ahub_dam" ++ ++static struct resource g_res; ++struct sunxi_ahub_mem_info g_mem_info = { ++ .res = &g_res, ++}; ++static struct sunxi_ahub_clk_info g_clk_info; ++static struct regmap_config g_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = SUNXI_AHUB_MAX_REG, ++ .cache_type = REGCACHE_NONE, ++}; ++ ++static struct snd_soc_dai_driver sunxi_ahub_dam_dai = { ++ .name = "ahub_dam", ++}; ++ ++static int sunxi_ahub_dam_probe(struct snd_soc_component *component) ++{ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dam_suspend(struct snd_soc_component *component) ++{ ++ struct sunxi_ahub_clk_info *clk_info = &g_clk_info; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ clk_disable_unprepare(clk_info->clk_module); ++ clk_disable_unprepare(clk_info->clk_pll); ++ //clk_disable_unprepare(clk_info->clk_pllx4); ++ clk_disable_unprepare(clk_info->clk_bus); ++ reset_control_assert(clk_info->clk_rst); ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dam_resume(struct snd_soc_component *component) ++{ ++ struct sunxi_ahub_clk_info *clk_info = &g_clk_info; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (reset_control_deassert(clk_info->clk_rst)) { ++ SND_LOG_ERR(HLOG, "clk rst deassert failed\n"); ++ return -EINVAL; ++ } ++ if (clk_prepare_enable(clk_info->clk_bus)) { ++ SND_LOG_ERR(HLOG, "clk bus enable failed\n"); ++ return -EBUSY; ++ } ++ if (clk_prepare_enable(clk_info->clk_pll)) { ++ SND_LOG_ERR(HLOG, "clk_pll enable failed\n"); ++ return -EBUSY; ++ } ++ //if (clk_prepare_enable(clk_info->clk_pllx4)) { ++ // SND_LOG_ERR(HLOG, "clk_pllx4 enable failed\n"); ++ // return -EBUSY; ++ //} ++ if (clk_prepare_enable(clk_info->clk_module)) { ++ SND_LOG_ERR(HLOG, "clk_module enable failed\n"); ++ return -EBUSY; ++ } ++ ++ return 0; ++} ++ ++struct str_conv { ++ char *str; ++ unsigned int reg; ++}; ++static struct str_conv ahub_mux_name[] = { ++ {"APBIF0 Src Select", SUNXI_AHUB_APBIF_RXFIFO_CONT(0)}, ++ {"APBIF1 Src Select", SUNXI_AHUB_APBIF_RXFIFO_CONT(1)}, ++ {"APBIF2 Src Select", SUNXI_AHUB_APBIF_RXFIFO_CONT(2)}, ++ {"I2S0 Src Select", SUNXI_AHUB_I2S_RXCONT(0)}, ++ {"I2S1 Src Select", SUNXI_AHUB_I2S_RXCONT(1)}, ++ {"I2S2 Src Select", SUNXI_AHUB_I2S_RXCONT(2)}, ++ {"I2S3 Src Select", SUNXI_AHUB_I2S_RXCONT(3)}, ++ {"DAM0C0 Src Select", SUNXI_AHUB_DAM_RX0_SRC(0)}, ++ {"DAM0C1 Src Select", SUNXI_AHUB_DAM_RX1_SRC(0)}, ++ {"DAM0C2 Src Select", SUNXI_AHUB_DAM_RX2_SRC(0)}, ++ {"DAM1C0 Src Select", SUNXI_AHUB_DAM_RX0_SRC(1)}, ++ {"DAM1C1 Src Select", SUNXI_AHUB_DAM_RX1_SRC(1)}, ++ {"DAM1C2 Src Select", SUNXI_AHUB_DAM_RX2_SRC(1)}, ++}; ++static const char *ahub_mux_text[] = { ++ "NONE", ++ "APBIF_TXDIF0", ++ "APBIF_TXDIF1", ++ "APBIF_TXDIF2", ++ "I2S0_TXDIF", ++ "I2S1_TXDIF", ++ "I2S2_TXDIF", ++ "I2S3_TXDIF", ++ "DAM0_TXDIF", ++ "DAM1_TXDIF", ++}; ++static const unsigned int ahub_mux_values[] = { ++ 0, ++ 1 << I2S_RX_APBIF_TXDIF0, ++ 1 << I2S_RX_APBIF_TXDIF1, ++ 1 << I2S_RX_APBIF_TXDIF2, ++ 1 << I2S_RX_I2S0_TXDIF, ++ 1 << I2S_RX_I2S1_TXDIF, ++ 1 << I2S_RX_I2S2_TXDIF, ++ 1 << I2S_RX_I2S3_TXDIF, ++ 1 << I2S_RX_DAM0_TXDIF, ++ 1 << I2S_RX_DAM1_TXDIF, ++}; ++static SOC_ENUM_SINGLE_EXT_DECL(ahub_mux, ahub_mux_text); ++ ++static int sunxi_ahub_mux_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ int i; ++ unsigned int reg_val; ++ unsigned int src_reg; ++ struct regmap *regmap = g_mem_info.regmap; ++ ++ for (i = 0; i < ARRAY_SIZE(ahub_mux_name); i++) { ++ if (!strncmp(ahub_mux_name[i].str, kcontrol->id.name, ++ strlen(ahub_mux_name[i].str))) { ++ src_reg = ahub_mux_name[i].reg; ++ regmap_read(regmap, src_reg, ®_val); ++ reg_val &= 0xffffc000; ++ break; ++ } ++ } ++ ++ for (i = 1; i < ARRAY_SIZE(ahub_mux_values); i++) { ++ if (reg_val & ahub_mux_values[i]) { ++ ucontrol->value.integer.value[0] = i; ++ return 0; ++ } ++ } ++ ucontrol->value.integer.value[0] = 0; ++ ++ return 0; ++} ++ ++static int sunxi_ahub_mux_set(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ int i; ++ unsigned int src_reg, src_regbit; ++ struct regmap *regmap = g_mem_info.regmap; ++ ++ if (ucontrol->value.integer.value[0] > ARRAY_SIZE(ahub_mux_name)) ++ return -EINVAL; ++ ++ src_regbit = ahub_mux_values[ucontrol->value.integer.value[0]]; ++ for (i = 0; i < ARRAY_SIZE(ahub_mux_name); i++) { ++ if (!strncmp(ahub_mux_name[i].str, kcontrol->id.name, ++ strlen(ahub_mux_name[i].str))) { ++ src_reg = ahub_mux_name[i].reg; ++ regmap_update_bits(regmap, src_reg, 0xffffc000, src_regbit); ++ break; ++ } ++ } ++ ++ return 0; ++} ++ ++static const struct snd_kcontrol_new sunxi_ahub_dam_controls[] = { ++ SOC_ENUM_EXT("APBIF0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("APBIF1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("APBIF2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("I2S0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("I2S1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("I2S2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("I2S3 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("DAM0C0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("DAM0C1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("DAM0C2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("DAM1C0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("DAM1C1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("DAM1C2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++}; ++ ++static struct snd_soc_component_driver sunxi_ahub_dam_dev = { ++ .name = DRV_NAME, ++ .probe = sunxi_ahub_dam_probe, ++ .suspend = sunxi_ahub_dam_suspend, ++ .resume = sunxi_ahub_dam_resume, ++ .controls = sunxi_ahub_dam_controls, ++ .num_controls = ARRAY_SIZE(sunxi_ahub_dam_controls), ++}; ++ ++/******************************************************************************* ++ * for kernel source ++ ******************************************************************************/ ++int snd_soc_sunxi_ahub_mem_get(struct sunxi_ahub_mem_info *mem_info) ++{ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(g_mem_info.regmap)) { ++ SND_LOG_ERR(HLOG, "regmap is invalid\n"); ++ return -EINVAL; ++ } ++ if (IS_ERR_OR_NULL(g_mem_info.res)) { ++ SND_LOG_ERR(HLOG, "res is invalid\n"); ++ return -EINVAL; ++ } ++ ++ mem_info->regmap = g_mem_info.regmap; ++ mem_info->res = g_mem_info.res; ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(snd_soc_sunxi_ahub_mem_get); ++ ++int snd_soc_sunxi_ahub_clk_get(struct sunxi_ahub_clk_info *clk_info) ++{ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(g_clk_info.clk_pll)) { ++ SND_LOG_ERR(HLOG, "clk_pll is invalid\n"); ++ return -EINVAL; ++ } ++ //if (IS_ERR_OR_NULL(g_clk_info.clk_pllx4)) { ++ // SND_LOG_ERR(HLOG, "clk_pllx4 is invalid\n"); ++ // return -EINVAL; ++ //} ++ if (IS_ERR_OR_NULL(g_clk_info.clk_module)) { ++ SND_LOG_ERR(HLOG, "clk_module is invalid\n"); ++ return -EINVAL; ++ } ++ ++ clk_info->clk_pll = g_clk_info.clk_pll; ++ //clk_info->clk_pllx4 = g_clk_info.clk_pllx4; ++ clk_info->clk_module = g_clk_info.clk_module; ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(snd_soc_sunxi_ahub_clk_get); ++ ++static int snd_soc_sunxi_ahub_mem_init(struct platform_device *pdev, ++ struct device_node *np, ++ struct sunxi_ahub_mem_info *mem_info) ++{ ++ int ret = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ ret = of_address_to_resource(np, 0, mem_info->res); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "parse device node resource failed\n"); ++ ret = -EINVAL; ++ goto err_of_addr_to_resource; ++ } ++ ++ mem_info->memregion = devm_request_mem_region(&pdev->dev, ++ mem_info->res->start, ++ resource_size(mem_info->res), ++ DRV_NAME); ++ if (IS_ERR_OR_NULL(mem_info->memregion)) { ++ SND_LOG_ERR(HLOG, "memory region already claimed\n"); ++ ret = -EBUSY; ++ goto err_devm_request_region; ++ } ++ ++ mem_info->membase = devm_ioremap(&pdev->dev, ++ mem_info->memregion->start, ++ resource_size(mem_info->memregion)); ++ if (IS_ERR_OR_NULL(mem_info->membase)) { ++ SND_LOG_ERR(HLOG, "ioremap failed\n"); ++ ret = -EBUSY; ++ goto err_devm_ioremap; ++ } ++ ++ mem_info->regmap = devm_regmap_init_mmio(&pdev->dev, ++ mem_info->membase, ++ &g_regmap_config); ++ if (IS_ERR_OR_NULL(mem_info->regmap)) { ++ SND_LOG_ERR(HLOG, "regmap init failed\n"); ++ ret = -EINVAL; ++ goto err_devm_regmap_init; ++ } ++ ++ return 0; ++ ++err_devm_regmap_init: ++ devm_iounmap(&pdev->dev, mem_info->membase); ++err_devm_ioremap: ++ devm_release_mem_region(&pdev->dev, mem_info->memregion->start, ++ resource_size(mem_info->memregion)); ++err_devm_request_region: ++err_of_addr_to_resource: ++ return ret; ++}; ++ ++static int snd_soc_sunxi_ahub_clk_init(struct platform_device *pdev, ++ struct device_node *np, ++ struct sunxi_ahub_clk_info *clk_info) ++{ ++ int ret = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ /* deassert rst clk */ ++ clk_info->clk_rst = devm_reset_control_get(&pdev->dev, NULL); ++ if (IS_ERR_OR_NULL(clk_info->clk_rst)) { ++ SND_LOG_ERR(HLOG, "clk rst get failed\n"); ++ ret = -EBUSY; ++ goto err_rst_clk; ++ } ++ if (reset_control_deassert(clk_info->clk_rst)) { ++ SND_LOG_ERR(HLOG, "deassert reset clk failed\n"); ++ ret = -EBUSY; ++ goto err_rst_clk; ++ } ++ ++ /* enable ahub bus clk */ ++ clk_info->clk_bus = of_clk_get_by_name(np, "clk_bus_audio_hub"); ++ if (IS_ERR_OR_NULL(clk_info->clk_bus)) { ++ SND_LOG_ERR(HLOG, "clk bus get failed\n"); ++ ret = -EBUSY; ++ goto err_bus_clk; ++ } ++ if (clk_prepare_enable(clk_info->clk_bus)) { ++ SND_LOG_ERR(HLOG, "ahub clk bus enable failed\n"); ++ ret = -EBUSY; ++ goto err_bus_clk; ++ } ++ ++ /* get clk of ahub */ ++ clk_info->clk_module = of_clk_get_by_name(np, "clk_audio_hub"); ++ if (IS_ERR_OR_NULL(clk_info->clk_module)) { ++ SND_LOG_ERR(HLOG, "clk module get failed\n"); ++ ret = -EBUSY; ++ goto err_module_clk; ++ } ++ clk_info->clk_pll = of_clk_get_by_name(np, "clk_pll_audio"); ++ if (IS_ERR_OR_NULL(clk_info->clk_pll)) { ++ SND_LOG_ERR(HLOG, "clk pll get failed\n"); ++ ret = -EBUSY; ++ goto err_pll_clk; ++ } ++ //clk_info->clk_pllx4 = of_clk_get_by_name(np, "clk_pll_audio_4x"); ++ //if (IS_ERR_OR_NULL(clk_info->clk_pllx4)) { ++ // SND_LOG_ERR(HLOG, "clk pllx4 get failed\n"); ++ // ret = -EBUSY; ++ // goto err_pllx4_clk; ++ //} ++ ++ /* set ahub clk parent */ ++ //if (clk_set_parent(clk_info->clk_module, clk_info->clk_pllx4)) { ++ // SND_LOG_ERR(HLOG, "set parent of clk_module to pllx4 failed\n"); ++ // ret = -EINVAL; ++ // goto err_set_parent_clk; ++ //} ++ ++ /* enable clk of ahub */ ++ if (clk_prepare_enable(clk_info->clk_pll)) { ++ SND_LOG_ERR(HLOG, "clk_pll enable failed\n"); ++ ret = -EBUSY; ++ goto err_pll_clk_enable; ++ } ++ //if (clk_prepare_enable(clk_info->clk_pllx4)) { ++ // SND_LOG_ERR(HLOG, "clk_pllx4 enable failed\n"); ++ // ret = -EBUSY; ++ // goto err_pllx4_clk_enable; ++ //} ++ if (clk_prepare_enable(clk_info->clk_module)) { ++ SND_LOG_ERR(HLOG, "clk_module enable failed\n"); ++ ret = -EBUSY; ++ goto err_module_clk_enable; ++ } ++ ++ return 0; ++ ++err_module_clk_enable: ++// clk_disable_unprepare(clk_info->clk_pllx4); ++//err_pllx4_clk_enable: ++ clk_disable_unprepare(clk_info->clk_pll); ++err_pll_clk_enable: ++//err_set_parent_clk: ++// clk_put(clk_info->clk_pllx4); ++//err_pllx4_clk: ++// clk_put(clk_info->clk_pll); ++err_pll_clk: ++ clk_put(clk_info->clk_module); ++err_module_clk: ++ clk_disable_unprepare(clk_info->clk_bus); ++ clk_put(clk_info->clk_bus); ++err_bus_clk: ++ reset_control_assert(clk_info->clk_rst); ++err_rst_clk: ++ return ret; ++} ++ ++static int sunxi_ahub_dam_dev_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct device_node *np = pdev->dev.of_node; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ ret = snd_soc_sunxi_ahub_mem_init(pdev, np, &g_mem_info); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "remap init failed\n"); ++ ret = -EINVAL; ++ goto err_snd_soc_sunxi_ahub_mem_init; ++ } ++ ++ ret = snd_soc_sunxi_ahub_clk_init(pdev, np, &g_clk_info); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "clk init failed\n"); ++ ret = -EINVAL; ++ goto err_snd_soc_sunxi_ahub_clk_init; ++ } ++ ++ ret = snd_soc_register_component(&pdev->dev, ++ &sunxi_ahub_dam_dev, ++ &sunxi_ahub_dam_dai, 1); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "component register failed\n"); ++ ret = -ENOMEM; ++ goto err_snd_soc_register_component; ++ } ++ ++ SND_LOG_DEBUG(HLOG, "register ahub_dam platform success\n"); ++ ++ return 0; ++ ++err_snd_soc_register_component: ++err_snd_soc_sunxi_ahub_clk_init: ++err_snd_soc_sunxi_ahub_mem_init: ++ of_node_put(np); ++ return ret; ++} ++ ++static int sunxi_ahub_dam_dev_remove(struct platform_device *pdev) ++{ ++ struct sunxi_ahub_mem_info *mem_info = &g_mem_info; ++ struct sunxi_ahub_clk_info *clk_info = &g_clk_info; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ snd_soc_unregister_component(&pdev->dev); ++ ++ devm_iounmap(&pdev->dev, mem_info->membase); ++ devm_release_mem_region(&pdev->dev, mem_info->memregion->start, ++ resource_size(mem_info->memregion)); ++ ++ clk_disable_unprepare(clk_info->clk_module); ++ clk_put(clk_info->clk_module); ++ clk_disable_unprepare(clk_info->clk_pll); ++ clk_put(clk_info->clk_pll); ++ //clk_disable_unprepare(clk_info->clk_pllx4); ++ //clk_put(clk_info->clk_pllx4); ++ clk_disable_unprepare(clk_info->clk_bus); ++ clk_put(clk_info->clk_bus); ++ reset_control_assert(clk_info->clk_rst); ++ ++ SND_LOG_DEBUG(HLOG, "unregister ahub_dam platform success\n"); ++ ++ return 0; ++} ++ ++static const struct of_device_id sunxi_ahub_dam_of_match[] = { ++ { .compatible = "allwinner," DRV_NAME, }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, sunxi_ahub_dam_of_match); ++ ++static struct platform_driver sunxi_ahub_dam_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = sunxi_ahub_dam_of_match, ++ }, ++ .probe = sunxi_ahub_dam_dev_probe, ++ .remove = sunxi_ahub_dam_dev_remove, ++}; ++ ++int __init sunxi_ahub_dam_dev_init(void) ++{ ++ int ret; ++ ++ ret = platform_driver_register(&sunxi_ahub_dam_driver); ++ if (ret != 0) { ++ SND_LOG_ERR(HLOG, "platform driver register failed\n"); ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ ++void __exit sunxi_ahub_dam_dev_exit(void) ++{ ++ platform_driver_unregister(&sunxi_ahub_dam_driver); ++} ++ ++late_initcall(sunxi_ahub_dam_dev_init); ++module_exit(sunxi_ahub_dam_dev_exit); ++ ++MODULE_AUTHOR("Dby@allwinnertech.com"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("sunxi soundcard platform of ahub_dam"); +diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h +new file mode 100644 +index 000000000..b7679bf54 +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h +@@ -0,0 +1,291 @@ ++/* sound\soc\sunxi\snd_sunxi_ahub_dam.h ++ * (C) Copyright 2021-2025 ++ * Allwinner Technology Co., Ltd. ++ * Dby ++ * ++ * some simple description for this code ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ */ ++#ifndef __SND_SUNXI_AHUB_DAM_H ++#define __SND_SUNXI_AHUB_DAM_H ++ ++/* SUNXI Audio Hub registers list */ ++#define SUNXI_AHUB_CTL 0x00 ++#define SUNXI_AHUB_VER 0x04 ++#define SUNXI_AHUB_RST 0x08 ++#define SUNXI_AHUB_GAT 0x0c ++ ++#define SUNXI_AHUB_APBIF_TX_CTL(n) (0x10 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_TX_IRQ_CTL(n) (0x14 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_TX_IRQ_STA(n) (0x18 + ((n) * 0x30)) ++ ++#define SUNXI_AHUB_APBIF_TXFIFO_CTL(n) (0x20 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_TXFIFO_STA(n) (0x24 + ((n) * 0x30)) ++ ++#define SUNXI_AHUB_APBIF_TXFIFO(n) (0x30 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_TXFIFO_CNT(n) (0x34 + ((n) * 0x30)) ++ ++#define SUNXI_AHUB_APBIF_RX_CTL(n) (0x100 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_RX_IRQ_CTL(n) (0x104 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_RX_IRQ_STA(n) (0x108 + ((n) * 0x30)) ++ ++#define SUNXI_AHUB_APBIF_RXFIFO_CTL(n) (0x110 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_RXFIFO_STA(n) (0x114 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_RXFIFO_CONT(n) (0x118 + ((n) * 0x30)) ++ ++#define SUNXI_AHUB_APBIF_RXFIFO(n) (0x120 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_RXFIFO_CNT(n) (0x124 + ((n) * 0x30)) ++ ++#define SUNXI_AHUB_I2S_CTL(n) (0x200 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_FMT0(n) (0x204 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_FMT1(n) (0x208 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_CLKD(n) (0x20c + ((n) << 8)) ++ ++#define SUNXI_AHUB_I2S_RXCONT(n) (0x220 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_CHCFG(n) (0x224 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_IRQ_CTL(n) (0x228 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_IRQ_STA(n) (0x22C + ((n) << 8)) ++#define SUNXI_AHUB_I2S_OUT_SLOT(n, m) (0x230 + ((n) << 8) + ((m) << 4)) ++#define SUNXI_AHUB_I2S_OUT_CHMAP0(n, m) (0x234 + ((n) << 8) + ((m) << 4)) ++#define SUNXI_AHUB_I2S_OUT_CHMAP1(n, m) (0x238 + ((n) << 8) + ((m) << 4)) ++ ++#define SUNXI_AHUB_I2S_IN_SLOT(n) (0x270 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_IN_CHMAP0(n) (0x274 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_IN_CHMAP1(n) (0x278 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_IN_CHMAP2(n) (0x27C + ((n) << 8)) ++#define SUNXI_AHUB_I2S_IN_CHMAP3(n) (0x280 + ((n) << 8)) ++ ++#define SUNXI_AHUB_DAM_CTL(n) (0xA00 + ((n) << 7)) ++ ++#define SUNXI_AHUB_DAM_RX0_SRC(n) (0xA10 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_RX1_SRC(n) (0xA14 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_RX2_SRC(n) (0xA18 + ((n) << 7)) ++ ++#define SUNXI_AHUB_DAM_MIX_CTL0(n) (0xA30 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_MIX_CTL1(n) (0xA34 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_MIX_CTL2(n) (0xA38 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_MIX_CTL3(n) (0xA3C + ((n) << 7)) ++#define SUNXI_AHUB_DAM_MIX_CTL4(n) (0xA40 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_MIX_CTL5(n) (0xA44 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_MIX_CTL6(n) (0xA48 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_MIX_CTL7(n) (0xA4C + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL0(n) (0xA50 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL1(n) (0xA54 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL2(n) (0xA58 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL3(n) (0xA5C + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL4(n) (0xA60 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL5(n) (0xA64 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL6(n) (0xA68 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL7(n) (0xA6C + ((n) << 7)) ++ ++#define SUNXI_AHUB_MAX_REG SUNXI_AHUB_DAM_GAIN_CTL7(1) ++ ++/* SUNXI_AHUB_CTL */ ++#define HDMI_SRC_SEL 0x04 ++ ++/* SUNXI_AHUB_RST */ ++#define APBIF_TXDIF0_RST 31 ++#define APBIF_TXDIF1_RST 30 ++#define APBIF_TXDIF2_RST 29 ++#define APBIF_RXDIF0_RST 27 ++#define APBIF_RXDIF1_RST 26 ++#define APBIF_RXDIF2_RST 25 ++#define I2S0_RST 23 ++#define I2S1_RST 22 ++#define I2S2_RST 21 ++#define I2S3_RST 20 ++#define DAM0_RST 15 ++#define DAM1_RST 14 ++ ++/* SUNXI_AHUB_GAT */ ++#define APBIF_TXDIF0_GAT 31 ++#define APBIF_TXDIF1_GAT 30 ++#define APBIF_TXDIF2_GAT 29 ++#define APBIF_RXDIF0_GAT 27 ++#define APBIF_RXDIF1_GAT 26 ++#define APBIF_RXDIF2_GAT 25 ++#define I2S0_GAT 23 ++#define I2S1_GAT 22 ++#define I2S2_GAT 21 ++#define I2S3_GAT 20 ++#define DAM0_GAT 15 ++#define DAM1_GAT 14 ++ ++/* SUNXI_AHUB_APBIF_TX_CTL */ ++#define APBIF_TX_WS 16 ++#define APBIF_TX_CHAN_NUM 8 ++#define APBIF_TX_START 4 ++ ++/* SUNXI_AHUB_APBIF_TX_IRQ_CTL */ ++#define APBIF_TX_DRQ 3 ++#define APBIF_TX_OVEN 1 ++#define APBIF_TX_EMEN 0 ++ ++/* SUNXI_AHUB_APBIF_TX_IRQ_STA */ ++#define APBIF_TX_OV_PEND 2 ++#define APBIF_TX_EM_PEND 0 ++ ++/* SUNXI_AHUB_APBIF_TXFIFO_CTL */ ++#define APBIF_TX_FTX 12 ++#define APBIF_TX_LEVEL 4 ++#define APBIF_TX_TXIM 0 ++ ++/* SUNXI_AHUB_APBIF_TXFIFO_STA */ ++#define APBIF_TX_EMPTY 8 ++#define APBIF_TX_EMCNT 0 ++ ++/* SUNXI_AHUB_APBIF_RX_CTL */ ++#define APBIF_RX_WS 16 ++#define APBIF_RX_CHAN_NUM 8 ++#define APBIF_RX_START 4 ++ ++/* SUNXI_AHUB_APBIF_RX_IRQ_CTL */ ++#define APBIF_RX_DRQ 3 ++#define APBIF_RX_UVEN 2 ++#define APBIF_RX_AVEN 0 ++ ++/* SUNXI_AHUB_APBIF_RX_IRQ_STA */ ++#define APBIF_RX_UV_PEND 2 ++#define APBIF_RX_AV_PEND 0 ++ ++/* SUNXI_AHUB_APBIF_RXFIFO_CTL */ ++#define APBIF_RX_FRX 12 ++#define APBIF_RX_LEVEL 4 ++#define APBIF_RX_RXOM 0 ++ ++/* SUNXI_AHUB_APBIF_RXFIFO_STA */ ++#define APBIF_RX_AVAIL 8 ++#define APBIF_RX_AVCNT 0 ++ ++/* SUNXI_AHUB_APBIF_RXFIFO_CONT */ ++#define APBIF_RX_APBIF_TXDIF0 31 ++#define APBIF_RX_APBIF_TXDIF1 30 ++#define APBIF_RX_APBIF_TXDIF2 29 ++#define APBIF_RX_I2S0_TXDIF 27 ++#define APBIF_RX_I2S1_TXDIF 26 ++#define APBIF_RX_I2S2_TXDIF 25 ++#define APBIF_RX_I2S3_TXDIF 23 ++#define APBIF_RX_DAM0_TXDIF 19 ++#define APBIF_RX_DAM1_TXDIF 15 ++ ++/* SUNXI_AHUB_I2S_CTL */ ++#define I2S_CTL_LOOP3 23 ++#define I2S_CTL_LOOP2 22 ++#define I2S_CTL_LOOP1 21 ++#define I2S_CTL_LOOP0 20 ++#define I2S_CTL_SDI3_EN 15 ++#define I2S_CTL_SDI2_EN 14 ++#define I2S_CTL_SDI1_EN 13 ++#define I2S_CTL_SDI0_EN 12 ++#define I2S_CTL_CLK_OUT 18 ++#define I2S_CTL_SDO3_EN 11 ++#define I2S_CTL_SDO2_EN 10 ++#define I2S_CTL_SDO1_EN 9 ++#define I2S_CTL_SDO0_EN 8 ++#define I2S_CTL_OUT_MUTE 6 ++#define I2S_CTL_MODE 4 ++#define I2S_CTL_TXEN 2 ++#define I2S_CTL_RXEN 1 ++#define I2S_CTL_GEN 0 ++ ++/* SUNXI_AHUB_I2S_FMT0 */ ++#define I2S_FMT0_LRCK_WIDTH 30 ++#define I2S_FMT0_LRCK_POLARITY 19 ++#define I2S_FMT0_LRCK_PERIOD 8 ++#define I2S_FMT0_BCLK_POLARITY 7 ++#define I2S_FMT0_SR 4 ++#define I2S_FMT0_EDGE 3 ++#define I2S_FMT0_SW 0 ++ ++/* SUNXI_AHUB_I2S_FMT1 */ ++#define I2S_FMT1_RX_LSB 7 ++#define I2S_FMT1_TX_LSB 6 ++#define I2S_FMT1_EXT 4 ++#define I2S_FMT1_RX_PDM 2 ++#define I2S_FMT1_TX_PDM 0 ++ ++/* SUNXI_AHUB_I2S_CLKD */ ++#define I2S_CLKD_MCLK 8 ++#define I2S_CLKD_BCLKDIV 4 ++#define I2S_CLKD_MCLKDIV 0 ++ ++/* SUNXI_AHUB_I2S_RXCONT */ ++#define I2S_RX_APBIF_TXDIF0 31 ++#define I2S_RX_APBIF_TXDIF1 30 ++#define I2S_RX_APBIF_TXDIF2 29 ++#define I2S_RX_I2S0_TXDIF 27 ++#define I2S_RX_I2S1_TXDIF 26 ++#define I2S_RX_I2S2_TXDIF 25 ++#define I2S_RX_I2S3_TXDIF 23 ++#define I2S_RX_DAM0_TXDIF 19 ++#define I2S_RX_DAM1_TXDIF 15 ++ ++/* SUNXI_AHUB_I2S_CHCFG */ ++#define I2S_CHCFG_HIZ 9 ++#define I2S_CHCFG_TX_STATE 8 ++#define I2S_CHCFG_RX_CHANNUM 4 ++#define I2S_CHCFG_TX_CHANNUM 0 ++ ++/* SUNXI_AHUB_I2S_IRQ_CTL */ ++#define I2S_IRQ_RXOV_EN 1 ++#define I2S_IRQ_TXUV_EN 0 ++ ++/* SUNXI_AHUB_I2S_IRQ_STA */ ++#define I2S_IRQ_RXOV_PEND 1 ++#define I2S_IRQ_TXUV_PEND 0 ++ ++/* SUNXI_AHUB_I2S_OUT_SLOT */ ++#define I2S_OUT_OFFSET 20 ++#define I2S_OUT_SLOT_NUM 16 ++#define I2S_OUT_SLOT_EN 0 ++ ++/* SUNXI_AHUB_I2S_IN_SLOT */ ++#define I2S_IN_OFFSET 20 ++#define I2S_IN_SLOT_NUM 16 ++ ++/* SUNXI_AHUB_DAM_CTL */ ++#define DAM_CTL_RX2_NUM 24 ++#define DAM_CTL_RX1_NUM 20 ++#define DAM_CTL_RX0_NUM 16 ++#define DAM_CTL_TX_NUM 8 ++#define DAM_CTL_RX2EN 6 ++#define DAM_CTL_RX1EN 5 ++#define DAM_CTL_RX0EN 4 ++#define DAM_CTL_TXEN 0 ++ ++/* SUNXI_AHUB_DAM_RX##chan##_SRC */ ++#define DAM_RX_APBIF_TXDIF0 31 ++#define DAM_RX_APBIF_TXDIF1 30 ++#define DAM_RX_APBIF_TXDIF2 29 ++#define DAM_RX_I2S0_TXDIF 27 ++#define DAM_RX_I2S1_TXDIF 26 ++#define DAM_RX_I2S2_TXDIF 25 ++#define DAM_RX_I2S3_TXDIF 23 ++#define DAM_RX_DAM0_TXDIF 19 ++#define DAM_RX_DAM1_TXDIF 15 ++ ++struct sunxi_ahub_mem_info { ++ char *dev_name; ++ struct resource *res; ++ void __iomem *membase; ++ struct resource *memregion; ++ struct regmap *regmap; ++}; ++ ++struct sunxi_ahub_clk_info { ++ struct clk *clk_pll; ++ struct clk *clk_pllx4; ++ struct clk *clk_module; ++ struct clk *clk_bus; ++ struct reset_control *clk_rst; ++}; ++ ++extern int snd_soc_sunxi_ahub_mem_get(struct sunxi_ahub_mem_info *mem_info); ++extern int snd_soc_sunxi_ahub_clk_get(struct sunxi_ahub_clk_info *clk_info); ++ ++#endif /* __SND_SUNXI_AHUB_DAM_H */ +\ No newline at end of file +diff --git a/sound/soc/sunxi_v2/snd_sunxi_common.c b/sound/soc/sunxi_v2/snd_sunxi_common.c +new file mode 100644 +index 000000000..410ab75ae +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_common.c +@@ -0,0 +1,267 @@ ++/* ++ * sound\soc\sunxi\snd_sunxi_common.c ++ * (C) Copyright 2021-2025 ++ * AllWinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "snd_sunxi_log.h" ++#include "snd_sunxi_common.h" ++ ++#define HLOG "COMMON" ++ ++/* for regmap */ ++int snd_sunxi_mem_init(struct platform_device *pdev, ++ struct sunxi_mem_info *mem_info) ++{ ++ int ret = 0; ++ struct device_node *np = pdev->dev.of_node; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ ret = of_address_to_resource(np, 0, mem_info->res); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "parse device node resource failed\n"); ++ ret = -EINVAL; ++ goto err_of_addr_to_resource; ++ } ++ ++ mem_info->memregion = devm_request_mem_region(&pdev->dev, ++ mem_info->res->start, ++ resource_size(mem_info->res), ++ mem_info->dev_name); ++ if (IS_ERR_OR_NULL(mem_info->memregion)) { ++ SND_LOG_ERR(HLOG, "memory region already claimed\n"); ++ ret = -EBUSY; ++ goto err_devm_request_region; ++ } ++ ++ mem_info->membase = devm_ioremap(&pdev->dev, ++ mem_info->memregion->start, ++ resource_size(mem_info->memregion)); ++ if (IS_ERR_OR_NULL(mem_info->membase)) { ++ SND_LOG_ERR(HLOG, "ioremap failed\n"); ++ ret = -EBUSY; ++ goto err_devm_ioremap; ++ } ++ ++ mem_info->regmap = devm_regmap_init_mmio(&pdev->dev, ++ mem_info->membase, ++ mem_info->regmap_config); ++ if (IS_ERR_OR_NULL(mem_info->regmap)) { ++ SND_LOG_ERR(HLOG, "regmap init failed\n"); ++ ret = -EINVAL; ++ goto err_devm_regmap_init; ++ } ++ ++ return 0; ++ ++err_devm_regmap_init: ++ devm_iounmap(&pdev->dev, mem_info->membase); ++err_devm_ioremap: ++ devm_release_mem_region(&pdev->dev, mem_info->memregion->start, ++ resource_size(mem_info->memregion)); ++err_devm_request_region: ++err_of_addr_to_resource: ++ return ret; ++} ++ ++void snd_sunxi_mem_exit(struct platform_device *pdev, ++ struct sunxi_mem_info *mem_info) ++{ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ devm_iounmap(&pdev->dev, mem_info->membase); ++ devm_release_mem_region(&pdev->dev, mem_info->memregion->start, ++ resource_size(mem_info->memregion)); ++} ++ ++/* for reg labels */ ++int snd_sunxi_save_reg(struct regmap *regmap, struct reg_label *reg_labels) ++{ ++ int i = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ while (reg_labels[i].name != NULL) { ++ regmap_read(regmap, ++ reg_labels[i].address, &(reg_labels[i].value)); ++ i++; ++ } ++ ++ return i; ++} ++ ++int snd_sunxi_echo_reg(struct regmap *regmap, struct reg_label *reg_labels) ++{ ++ int i = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ while (reg_labels[i].name != NULL) { ++ regmap_write(regmap, ++ reg_labels[i].address, reg_labels[i].value); ++ i++; ++ } ++ ++ return i; ++} ++ ++/* for pa config */ ++struct pa_config *snd_sunxi_pa_pin_init(struct platform_device *pdev, ++ u32 *pa_pin_max) ++{ ++ int ret, i; ++ u32 pin_max; ++ u32 gpio_tmp; ++ u32 temp_val; ++ char str[20] = {0}; ++ struct pa_config *pa_cfg; ++ struct device_node *np = pdev->dev.of_node; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ *pa_pin_max = 0; ++ ret = of_property_read_u32(np, "pa_pin_max", &temp_val); ++ if (ret < 0) { ++ SND_LOG_WARN(HLOG, "pa_pin_max get failed, default 0\n"); ++ return NULL; ++ } else { ++ pin_max = temp_val; ++ } ++ ++ pa_cfg = kzalloc(sizeof(struct pa_config) * pin_max, GFP_KERNEL); ++ if (!pa_cfg) { ++ SND_LOG_ERR(HLOG, "can't pa_config memory\n"); ++ return NULL; ++ } ++ ++ for (i = 0; i < pin_max; i++) { ++ sprintf(str, "pa_pin_%d", i); ++ ret = of_get_named_gpio(np, str, 0); ++ if (ret < 0) { ++ SND_LOG_ERR(HLOG, "pa_pin_%u get failed\n", i); ++ pa_cfg[i].used = 0; ++ continue; ++ } ++ gpio_tmp = ret; ++ if (!gpio_is_valid(gpio_tmp)) { ++ SND_LOG_ERR(HLOG, "pa_pin_%u (%u) is invalid\n", ++ i, gpio_tmp); ++ pa_cfg[i].used = 0; ++ continue; ++ } ++ ret = devm_gpio_request(&pdev->dev, gpio_tmp, str); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "pa_pin_%u (%u) request failed\n", ++ i, gpio_tmp); ++ pa_cfg[i].used = 0; ++ continue; ++ } ++ pa_cfg[i].used = 1; ++ pa_cfg[i].pin = gpio_tmp; ++ ++ sprintf(str, "pa_pin_level_%d", i); ++ ret = of_property_read_u32(np, str, &temp_val); ++ if (ret < 0) { ++ SND_LOG_WARN(HLOG, "%s get failed, default low\n", str); ++ pa_cfg[i].level = 0; ++ } else { ++ if (temp_val > 0) ++ pa_cfg[i].level = 1; ++ } ++ sprintf(str, "pa_pin_msleep_%d", i); ++ ret = of_property_read_u32(np, str, &temp_val); ++ if (ret < 0) { ++ SND_LOG_WARN(HLOG, "%s get failed, default 0\n", str); ++ pa_cfg[i].msleep = 0; ++ } else { ++ pa_cfg[i].msleep = temp_val; ++ } ++ } ++ ++ *pa_pin_max = pin_max; ++ snd_sunxi_pa_pin_disable(pa_cfg, pin_max); ++ ++ return pa_cfg; ++} ++ ++void snd_sunxi_pa_pin_exit(struct platform_device *pdev, ++ struct pa_config *pa_cfg, u32 pa_pin_max) ++{ ++ int i; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ snd_sunxi_pa_pin_disable(pa_cfg, pa_pin_max); ++ ++ for (i = 0; i < pa_pin_max; i++) { ++ if (!pa_cfg[i].used) ++ continue; ++ ++ gpio_free(pa_cfg[i].pin); ++ } ++ ++ if (pa_cfg) ++ kfree(pa_cfg); ++} ++ ++int snd_sunxi_pa_pin_enable(struct pa_config *pa_cfg, u32 pa_pin_max) ++{ ++ int i; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (pa_pin_max < 1) { ++ SND_LOG_DEBUG(HLOG, "no pa pin config\n"); ++ return 0; ++ } ++ ++ for (i = 0; i < pa_pin_max; i++) { ++ if (!pa_cfg[i].used) ++ continue; ++ ++ gpio_direction_output(pa_cfg[i].pin, 1); ++ gpio_set_value(pa_cfg[i].pin, pa_cfg[i].level); ++ } ++ ++ return 0; ++} ++ ++void snd_sunxi_pa_pin_disable(struct pa_config *pa_cfg, u32 pa_pin_max) ++{ ++ int i; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (pa_pin_max < 1) { ++ SND_LOG_DEBUG(HLOG, "no pa pin config\n"); ++ return; ++ } ++ ++ for (i = 0; i < pa_pin_max; i++) { ++ if (!pa_cfg[i].used) ++ continue; ++ ++ gpio_direction_output(pa_cfg[i].pin, 1); ++ gpio_set_value(pa_cfg[i].pin, !pa_cfg[i].level); ++ } ++} +diff --git a/sound/soc/sunxi_v2/snd_sunxi_common.h b/sound/soc/sunxi_v2/snd_sunxi_common.h +new file mode 100644 +index 000000000..7b88d20c2 +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_common.h +@@ -0,0 +1,67 @@ ++/* sound\soc\sunxi\snd_sunxi_common.h ++ * (C) Copyright 2021-2025 ++ * Allwinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#ifndef __SND_SUNXI_COMMON_H ++#define __SND_SUNXI_COMMON_H ++ ++/* for regmap */ ++struct sunxi_mem_info { ++ char *dev_name; ++ struct resource *res; ++ struct regmap_config *regmap_config; ++ ++ void __iomem *membase; ++ struct resource *memregion; ++ struct regmap *regmap; ++}; ++ ++int snd_sunxi_mem_init(struct platform_device *pdev, ++ struct sunxi_mem_info *mem_info); ++void snd_sunxi_mem_exit(struct platform_device *pdev, ++ struct sunxi_mem_info *mem_info); ++ ++/* for reg debug */ ++#define REG_LABEL(constant) {#constant, constant, 0} ++#define REG_LABEL_END {NULL, 0, 0} ++ ++struct reg_label { ++ const char *name; ++ const unsigned int address; ++ unsigned int value; ++}; ++ ++/* EX: ++ * static struct reg_label reg_labels[] = { ++ * REG_LABEL(SUNXI_REG_0), ++ * REG_LABEL(SUNXI_REG_1), ++ * REG_LABEL(SUNXI_REG_n), ++ * REG_LABEL_END, ++ * }; ++ */ ++int snd_sunxi_save_reg(struct regmap *regmap, struct reg_label *reg_labels); ++int snd_sunxi_echo_reg(struct regmap *regmap, struct reg_label *reg_labels); ++ ++/* for pa config */ ++struct pa_config { ++ u32 pin; ++ u32 msleep; ++ bool used; ++ bool level; ++}; ++ ++struct pa_config *snd_sunxi_pa_pin_init(struct platform_device *pdev, ++ u32 *pa_pin_max); ++void snd_sunxi_pa_pin_exit(struct platform_device *pdev, ++ struct pa_config *pa_cfg, u32 pa_pin_max); ++int snd_sunxi_pa_pin_enable(struct pa_config *pa_cfg, u32 pa_pin_max); ++void snd_sunxi_pa_pin_disable(struct pa_config *pa_cfg, u32 pa_pin_max); ++ ++#endif /* __SND_SUNXI_COMMON_H */ +\ No newline at end of file +diff --git a/sound/soc/sunxi_v2/snd_sunxi_log.h b/sound/soc/sunxi_v2/snd_sunxi_log.h +new file mode 100644 +index 000000000..89ad9fe71 +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_log.h +@@ -0,0 +1,29 @@ ++/* ++ * sound\soc\sunxi\snd_sunxi_log.h ++ * (C) Copyright 2021-2025 ++ * allwinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#ifndef __SND_SUNXI_LOG_H ++#define __SND_SUNXI_LOG_H ++#include ++ ++#define SND_LOG_ERR(head, fmt, arg...) \ ++ pr_err("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg) ++ ++#define SND_LOG_WARN(head, fmt, arg...) \ ++ pr_warn("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg) ++ ++#define SND_LOG_INFO(head, fmt, arg...) \ ++ pr_info("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg) ++ ++#define SND_LOG_DEBUG(head, fmt, arg...) \ ++ pr_debug("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg) ++ ++#endif /* __SND_SUNXI_LOG_H */ +diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach.c b/sound/soc/sunxi_v2/snd_sunxi_mach.c +new file mode 100644 +index 000000000..27449ad6b +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_mach.c +@@ -0,0 +1,479 @@ ++/* ++ * sound\soc\sunxi\snd_sunxi_mach.c ++ * (C) Copyright 2021-2025 ++ * AllWinner Technology Co., Ltd. ++ * Dby ++ * ++ * based on ${LINUX}/sound/soc/generic/simple-card.c ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++ ++#include "snd_sunxi_log.h" ++#include "snd_sunxi_mach.h" ++ ++#define HLOG "MACH" ++#define DAI "sound-dai" ++#define CELL "#sound-dai-cells" ++#define PREFIX "soundcard-mach," ++ ++#define DRV_NAME "sunxi-snd-mach" ++ ++static void asoc_simple_shutdown(struct snd_pcm_substream *substream) ++{ ++} ++ ++static int asoc_simple_startup(struct snd_pcm_substream *substream) ++{ ++ return 0; ++} ++ ++static int asoc_simple_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); ++ ++ struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0); ++ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); ++ ++ struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(rtd->card); ++ struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, rtd->num); ++ struct simple_dai_props *dai_props = simple_priv_to_props(priv, rtd->num); ++ struct asoc_simple_dai *dais = priv->dais; ++ unsigned int mclk; ++ unsigned int cpu_pll_clk, codec_pll_clk; ++ unsigned int cpu_bclk_ratio, codec_bclk_ratio; ++ unsigned int freq_point; ++ int cpu_clk_div, codec_clk_div; ++ int ret = 0; ++ ++ switch (params_rate(params)) { ++ case 8000: ++ case 12000: ++ case 16000: ++ case 24000: ++ case 32000: ++ case 48000: ++ case 64000: ++ case 96000: ++ case 192000: ++ freq_point = 24576000; ++ break; ++ case 11025: ++ case 22050: ++ case 44100: ++ case 88200: ++ case 176400: ++ freq_point = 22579200; ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "Invalid rate %d\n", params_rate(params)); ++ return -EINVAL; ++ } ++ ++ /* for cpudai pll clk */ ++ cpu_pll_clk = freq_point * dai_props->cpu_pll_fs; ++ codec_pll_clk = freq_point * dai_props->codec_pll_fs; ++ cpu_clk_div = cpu_pll_clk / params_rate(params); ++ codec_clk_div = codec_pll_clk / params_rate(params); ++ SND_LOG_DEBUG(HLOG, "freq point : %u\n", freq_point); ++ SND_LOG_DEBUG(HLOG, "cpu pllclk : %u\n", cpu_pll_clk); ++ SND_LOG_DEBUG(HLOG, "codec pllclk : %u\n", codec_pll_clk); ++ SND_LOG_DEBUG(HLOG, "cpu clk_div : %u\n", cpu_clk_div); ++ SND_LOG_DEBUG(HLOG, "codec clk_div: %u\n", codec_clk_div); ++ ++ if (cpu_dai->driver->ops->set_pll) { ++ ret = snd_soc_dai_set_pll(cpu_dai, substream->stream, 0, ++ cpu_pll_clk, cpu_pll_clk); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cpu_dai set pllclk failed\n"); ++ return ret; ++ } ++ } ++ if (codec_dai->driver->ops->set_pll) { ++ ret = snd_soc_dai_set_pll(codec_dai, substream->stream, 0, ++ codec_pll_clk, codec_pll_clk); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "codec_dai set pllclk failed\n"); ++ return ret; ++ } ++ } ++ ++ if (cpu_dai->driver->ops->set_clkdiv) { ++ ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, cpu_clk_div); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cpu_dai set clk_div failed\n"); ++ return ret; ++ } ++ } ++ if (codec_dai->driver->ops->set_clkdiv) { ++ ret = snd_soc_dai_set_clkdiv(codec_dai, 0, codec_clk_div); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cadec_dai set clk_div failed.\n"); ++ return ret; ++ } ++ } ++ ++ /* use for tdm only */ ++ if (!(dais->slots && dais->slot_width)) ++ return 0; ++ ++ /* for cpudai & codecdai mclk */ ++ if (dai_props->mclk_fp) ++ mclk = (freq_point >> 1) * dai_props->mclk_fs; ++ else ++ mclk = params_rate(params) * dai_props->mclk_fs; ++ cpu_bclk_ratio = cpu_pll_clk / (params_rate(params) * dais->slot_width * dais->slots); ++ codec_bclk_ratio = codec_pll_clk / (params_rate(params) * dais->slot_width * dais->slots); ++ SND_LOG_DEBUG(HLOG, "mclk : %u\n", mclk); ++ SND_LOG_DEBUG(HLOG, "cpu_bclk_ratio : %u\n", cpu_bclk_ratio); ++ SND_LOG_DEBUG(HLOG, "codec_bclk_ratio: %u\n", codec_bclk_ratio); ++ ++ if (cpu_dai->driver->ops->set_sysclk) { ++ ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk, SND_SOC_CLOCK_OUT); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cpu_dai set sysclk(mclk) failed\n"); ++ return ret; ++ } ++ } ++ if (codec_dai->driver->ops->set_sysclk) { ++ ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk, SND_SOC_CLOCK_IN); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cadec_dai set sysclk(mclk) failed\n"); ++ return ret; ++ } ++ } ++ ++ if (cpu_dai->driver->ops->set_bclk_ratio) { ++ ret = snd_soc_dai_set_bclk_ratio(cpu_dai, cpu_bclk_ratio); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cpu_dai set bclk failed\n"); ++ return ret; ++ } ++ } ++ if (codec_dai->driver->ops->set_bclk_ratio) { ++ ret = snd_soc_dai_set_bclk_ratio(codec_dai, codec_bclk_ratio); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "codec_dai set bclk failed\n"); ++ return ret; ++ } ++ } ++ ++ if (cpu_dai->driver->ops->set_fmt) { ++ ret = snd_soc_dai_set_fmt(cpu_dai, dai_link->dai_fmt); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cpu dai set fmt failed\n"); ++ return ret; ++ } ++ } ++ if (codec_dai->driver->ops->set_fmt) { ++ ret = snd_soc_dai_set_fmt(codec_dai, dai_link->dai_fmt); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "codec dai set fmt failed\n"); ++ return ret; ++ } ++ } ++ ++ if (cpu_dai->driver->ops->set_tdm_slot) { ++ ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, 0, dais->slots, dais->slot_width); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cpu dai set tdm slot failed\n"); ++ return ret; ++ } ++ } ++ if (codec_dai->driver->ops->set_tdm_slot) { ++ ret = snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, dais->slots, dais->slot_width); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "codec dai set tdm slot failed\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static struct snd_soc_ops simple_ops = { ++ .startup = asoc_simple_startup, ++ .shutdown = asoc_simple_shutdown, ++ .hw_params = asoc_simple_hw_params, ++}; ++ ++static int asoc_simple_dai_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ int i; ++ struct snd_soc_card *card = rtd->card; ++ struct snd_soc_dapm_context *dapm = &card->dapm; ++ ++ const struct snd_kcontrol_new *controls = card->controls; ++ ++ for (i = 0; i < card->num_controls; i++) ++ if (controls[i].info == snd_soc_dapm_info_pin_switch) ++ snd_soc_dapm_disable_pin(dapm, ++ (const char *)controls[i].private_value); ++ ++ if (card->num_controls) ++ snd_soc_dapm_sync(dapm); ++ ++ /* snd_soc_dai_set_sysclk(); */ ++ /* snd_soc_dai_set_tdm_slot(); */ ++ ++ return 0; ++} ++ ++static int simple_dai_link_of(struct device_node *node, ++ struct asoc_simple_priv *priv) ++{ ++ struct device *dev = simple_priv_to_dev(priv); ++ struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, 0); ++ struct simple_dai_props *dai_props = simple_priv_to_props(priv, 0); ++ struct device_node *top_np = NULL; ++ struct device_node *cpu = NULL; ++ struct device_node *plat = NULL; ++ struct device_node *codec = NULL; ++ char prop[128]; ++ char *prefix = ""; ++ int ret, single_cpu; ++ ++ prefix = PREFIX; ++ top_np = node; ++ ++ snprintf(prop, sizeof(prop), "%scpu", prefix); ++ cpu = of_get_child_by_name(top_np, prop); ++ if (!cpu) { ++ ret = -EINVAL; ++ SND_LOG_ERR(HLOG, "Can't find %s DT node\n", prop); ++ goto dai_link_of_err; ++ } ++ snprintf(prop, sizeof(prop), "%splat", prefix); ++ plat = of_get_child_by_name(top_np, prop); ++ ++ snprintf(prop, sizeof(prop), "%scodec", prefix); ++ codec = of_get_child_by_name(top_np, prop); ++ if (!codec) { ++ ret = -EINVAL; ++ SND_LOG_ERR(HLOG, "Can't find %s DT node\n", prop); ++ goto dai_link_of_err; ++ } ++ ++ ret = asoc_simple_parse_daifmt(top_np, codec, prefix, &dai_link->dai_fmt); ++ if (ret < 0) ++ goto dai_link_of_err; ++ /* sunxi: parse stream direction ++ * ex1) ++ * top_node { ++ * PREFIXplayback-only; ++ * } ++ * ex2) ++ * top_node { ++ * PREFIXcapture-only; ++ * } ++ */ ++ ret = asoc_simple_parse_daistream(top_np, prefix, dai_link); ++ if (ret < 0) ++ goto dai_link_of_err; ++ /* sunxi: parse slot-num & slot-width ++ * ex) ++ * top_node { ++ * PREFIXplayslot-num = ; ++ * PREFIXplayslot-width = ; ++ * } ++ */ ++ ret = asoc_simple_parse_tdm_slot(top_np, prefix, priv->dais); ++ if (ret < 0) ++ goto dai_link_of_err; ++ ++ ret = asoc_simple_parse_cpu(cpu, dai_link, DAI, CELL, &single_cpu); ++ if (ret < 0) ++ goto dai_link_of_err; ++ ret = asoc_simple_parse_codec(codec, dai_link, DAI, CELL); ++ if (ret < 0) { ++ if (ret == -EPROBE_DEFER) ++ goto dai_link_of_err; ++ dai_link->codecs->name = "snd-soc-dummy"; ++ dai_link->codecs->dai_name = "snd-soc-dummy-dai"; ++ /* dai_link->codecs->name = "sunxi-dummy-codec"; */ ++ /* dai_link->codecs->dai_name = "sunxi-dummy-codec-dai"; */ ++ SND_LOG_DEBUG(HLOG, "use dummy codec for simple card.\n"); ++ } ++ ret = asoc_simple_parse_platform(plat, dai_link, DAI, CELL); ++ if (ret < 0) ++ goto dai_link_of_err; ++ ++ /* sunxi: parse pll-fs & mclk-fs ++ * ex) ++ * top_node { ++ * PREFIXcpu { ++ * PREFIXpll-fs = ; ++ * PREFIXmclk-fs = ; ++ * } ++ * } ++ */ ++ ret = asoc_simple_parse_tdm_clk(cpu, codec, prefix, dai_props); ++ if (ret < 0) ++ goto dai_link_of_err; ++ ++ ret = asoc_simple_set_dailink_name(dev, dai_link, ++ "%s-%s", ++ dai_link->cpus->dai_name, ++ dai_link->codecs->dai_name); ++ if (ret < 0) ++ goto dai_link_of_err; ++ ++ dai_link->ops = &simple_ops; ++ dai_link->init = asoc_simple_dai_init; ++ ++ SND_LOG_DEBUG(HLOG, "name : %s\n", dai_link->stream_name); ++ SND_LOG_DEBUG(HLOG, "format : %x\n", dai_link->dai_fmt); ++ SND_LOG_DEBUG(HLOG, "cpu : %s\n", dai_link->cpus->name); ++ SND_LOG_DEBUG(HLOG, "codec : %s\n", dai_link->codecs->name); ++ ++ asoc_simple_canonicalize_cpu(dai_link, single_cpu); ++ asoc_simple_canonicalize_platform(dai_link); ++ ++dai_link_of_err: ++ of_node_put(cpu); ++ of_node_put(plat); ++ of_node_put(codec); ++ ++ return ret; ++} ++ ++static int simple_parse_of(struct asoc_simple_priv *priv) ++{ ++ int ret; ++ struct device *dev = simple_priv_to_dev(priv); ++ struct snd_soc_card *card = simple_priv_to_card(priv); ++ struct device_node *top_np = dev->of_node; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (!top_np) ++ return -EINVAL; ++ ++ /* DAPM widgets */ ++ ret = asoc_simple_parse_widgets(card, PREFIX); ++ if (ret < 0) ++ return ret; ++ ++ /* DAPM routes */ ++ ret = asoc_simple_parse_routing(card, PREFIX); ++ if (ret < 0) ++ return ret; ++ ++ /* DAPM pin_switches */ ++ ret = asoc_simple_parse_pin_switches(card, PREFIX); ++ if (ret < 0) ++ return ret; ++ ++ /* For single DAI link & old style of DT node */ ++ ret = simple_dai_link_of(top_np, priv); ++ if (ret < 0) ++ return ret; ++ ++ ret = asoc_simple_parse_card_name(card, PREFIX); ++ return ret; ++} ++ ++static int simple_soc_probe(struct snd_soc_card *card) ++{ ++ return 0; ++} ++ ++static int asoc_simple_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *top_np = dev->of_node; ++ struct asoc_simple_priv *priv; ++ struct snd_soc_card *card; ++ int ret; ++ ++ /* Allocate the private data and the DAI link array */ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ card = simple_priv_to_card(priv); ++ card->owner = THIS_MODULE; ++ card->dev = dev; ++ card->probe = simple_soc_probe; ++ ++ ret = asoc_simple_init_priv(priv); ++ if (ret < 0) ++ return ret; ++ ++ if (top_np && of_device_is_available(top_np)) { ++ ret = simple_parse_of(priv); ++ if (ret < 0) { ++ if (ret != -EPROBE_DEFER) ++ SND_LOG_ERR(HLOG, "parse error %d\n", ret); ++ goto err; ++ } ++ } else { ++ SND_LOG_ERR(HLOG, "simple card dts available\n"); ++ } ++ ++ snd_soc_card_set_drvdata(card, priv); ++ ++ /* asoc_simple_debug_info(priv); */ ++ ret = devm_snd_soc_register_card(dev, card); ++ if (ret >= 0) ++ return ret; ++err: ++ asoc_simple_clean_reference(card); ++ ++ return ret; ++} ++ ++static int asoc_simple_remove(struct platform_device *pdev) ++{ ++ struct snd_soc_card *card = platform_get_drvdata(pdev); ++ ++ return asoc_simple_clean_reference(card); ++} ++ ++static const struct of_device_id snd_soc_sunxi_of_match[] = { ++ { .compatible = "allwinner," DRV_NAME, }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_soc_sunxi_of_match); ++ ++static struct platform_driver sunxi_soundcard_machine_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .pm = &snd_soc_pm_ops, ++ .of_match_table = snd_soc_sunxi_of_match, ++ }, ++ .probe = asoc_simple_probe, ++ .remove = asoc_simple_remove, ++}; ++ ++int __init sunxi_soundcard_machine_dev_init(void) ++{ ++ int ret; ++ ++ ret = platform_driver_register(&sunxi_soundcard_machine_driver); ++ if (ret != 0) { ++ SND_LOG_ERR(HLOG, "platform driver register failed\n"); ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ ++void __exit sunxi_soundcard_machine_dev_exit(void) ++{ ++ platform_driver_unregister(&sunxi_soundcard_machine_driver); ++} ++ ++late_initcall(sunxi_soundcard_machine_dev_init); ++module_exit(sunxi_soundcard_machine_dev_exit); ++ ++MODULE_AUTHOR("Dby@allwinnertech.com"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("sunxi soundcard machine"); +diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach.h b/sound/soc/sunxi_v2/snd_sunxi_mach.h +new file mode 100644 +index 000000000..ab429c884 +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_mach.h +@@ -0,0 +1,17 @@ ++/* sound\soc\sunxi\snd_sunxi_mach.h ++ * (C) Copyright 2021-2025 ++ * Allwinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#ifndef __SND_SUNXI_MACH_H ++#define __SND_SUNXI_MACH_H ++ ++#include "snd_sunxi_mach_utils.h" ++ ++#endif /* __SND_SUNXI_MACH_H */ +diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c +new file mode 100644 +index 000000000..15f474e5c +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c +@@ -0,0 +1,422 @@ ++/* ++ * sound\soc\sunxi\snd_sunxi_mach_utils.c ++ * (C) Copyright 2021-2025 ++ * AllWinner Technology Co., Ltd. ++ * Dby ++ * ++ * based on ${LINUX}/sound/soc/generic/simple-card.c ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++ ++#include "snd_sunxi_log.h" ++#include "snd_sunxi_mach_utils.h" ++ ++#define HLOG "mach_utils" ++ ++int asoc_simple_clean_reference(struct snd_soc_card *card) ++{ ++ struct snd_soc_dai_link *dai_link; ++ int i; ++ ++ for_each_card_prelinks(card, i, dai_link) { ++ of_node_put(dai_link->cpus->of_node); ++ of_node_put(dai_link->codecs->of_node); ++ } ++ return 0; ++} ++ ++int asoc_simple_init_priv(struct asoc_simple_priv *priv) ++{ ++ struct snd_soc_card *card = simple_priv_to_card(priv); ++ struct device *dev = simple_priv_to_dev(priv); ++ struct snd_soc_dai_link *dai_link; ++ struct simple_dai_props *dai_props; ++ struct asoc_simple_dai *dais; ++ struct snd_soc_codec_conf *cconf = NULL; ++ ++ dai_props = devm_kcalloc(dev, 1, sizeof(*dai_props), GFP_KERNEL); ++ dai_link = devm_kcalloc(dev, 1, sizeof(*dai_link), GFP_KERNEL); ++ dais = devm_kcalloc(dev, 1, sizeof(*dais), GFP_KERNEL); ++ if (!dai_props || !dai_link || !dais) ++ return -ENOMEM; ++ ++ /* ++ if (li->conf) { ++ cconf = devm_kcalloc(dev, li->conf, sizeof(*cconf), GFP_KERNEL); ++ if (!cconf) ++ return -ENOMEM; ++ } ++ */ ++ ++ /* ++ * Use snd_soc_dai_link_component instead of legacy style ++ * It is codec only. but cpu/platform will be supported in the future. ++ * see ++ * soc-core.c :: snd_soc_init_multicodec() ++ * ++ * "platform" might be removed ++ * see ++ * simple-card-utils.c :: asoc_simple_canonicalize_platform() ++ */ ++ dai_link->cpus = &dai_props->cpus; ++ dai_link->num_cpus = 1; ++ dai_link->codecs = &dai_props->codecs; ++ dai_link->num_codecs = 1; ++ dai_link->platforms = &dai_props->platforms; ++ dai_link->num_platforms = 1; ++ ++ priv->dai_props = dai_props; ++ priv->dai_link = dai_link; ++ priv->dais = dais; ++ priv->codec_conf = cconf; ++ ++ card->dai_link = priv->dai_link; ++ card->num_links = 1; ++ card->codec_conf = cconf; ++ card->num_configs = 0; ++ ++ return 0; ++} ++ ++int asoc_simple_parse_widgets(struct snd_soc_card *card, char *prefix) ++{ ++ struct device_node *node = card->dev->of_node; ++ char prop[128]; ++ ++ if (!prefix) ++ prefix = ""; ++ ++ snprintf(prop, sizeof(prop), "%s%s", prefix, "widgets"); ++ ++ if (of_property_read_bool(node, prop)) ++ return snd_soc_of_parse_audio_simple_widgets(card, prop); ++ ++ /* no widgets is not error */ ++ return 0; ++} ++ ++int asoc_simple_parse_routing(struct snd_soc_card *card, char *prefix) ++{ ++ struct device_node *node = card->dev->of_node; ++ char prop[128]; ++ ++ if (!prefix) ++ prefix = ""; ++ ++ snprintf(prop, sizeof(prop), "%s%s", prefix, "routing"); ++ ++ if (!of_property_read_bool(node, prop)) ++ return 0; ++ ++ return snd_soc_of_parse_audio_routing(card, prop); ++} ++ ++int asoc_simple_parse_pin_switches(struct snd_soc_card *card, char *prefix) ++{ ++ const unsigned int nb_controls_max = 16; ++ const char **strings, *control_name; ++ struct snd_kcontrol_new *controls; ++ struct device *dev = card->dev; ++ unsigned int i, nb_controls; ++ char prop[128]; ++ int ret; ++ ++ if (!prefix) ++ prefix = ""; ++ ++ snprintf(prop, sizeof(prop), "%s%s", prefix, "pin-switches"); ++ ++ if (!of_property_read_bool(dev->of_node, prop)) ++ return 0; ++ ++ strings = devm_kcalloc(dev, nb_controls_max, ++ sizeof(*strings), GFP_KERNEL); ++ if (!strings) ++ return -ENOMEM; ++ ++ ret = of_property_read_string_array(dev->of_node, prop, ++ strings, nb_controls_max); ++ if (ret < 0) ++ return ret; ++ ++ nb_controls = (unsigned int)ret; ++ ++ controls = devm_kcalloc(dev, nb_controls, ++ sizeof(*controls), GFP_KERNEL); ++ if (!controls) ++ return -ENOMEM; ++ ++ for (i = 0; i < nb_controls; i++) { ++ control_name = devm_kasprintf(dev, GFP_KERNEL, ++ "%s Switch", strings[i]); ++ if (!control_name) ++ return -ENOMEM; ++ ++ controls[i].iface = SNDRV_CTL_ELEM_IFACE_MIXER; ++ controls[i].name = control_name; ++ controls[i].info = snd_soc_dapm_info_pin_switch; ++ controls[i].get = snd_soc_dapm_get_pin_switch; ++ controls[i].put = snd_soc_dapm_put_pin_switch; ++ controls[i].private_value = (unsigned long)strings[i]; ++ } ++ ++ card->controls = controls; ++ card->num_controls = nb_controls; ++ ++ return 0; ++} ++ ++int asoc_simple_parse_daifmt(struct device_node *node, ++ struct device_node *codec, ++ char *prefix, ++ unsigned int *retfmt) ++{ ++ struct device_node *bitclkmaster = NULL; ++ struct device_node *framemaster = NULL; ++ unsigned int daifmt; ++ ++ daifmt = snd_soc_daifmt_parse_format(node, prefix); ++ ++ snd_soc_daifmt_parse_clock_provider_as_phandle(node, prefix, &bitclkmaster, &framemaster); ++ if (!bitclkmaster && !framemaster) { ++ /* ++ * No dai-link level and master setting was not found from ++ * sound node level, revert back to legacy DT parsing and ++ * take the settings from codec node. ++ */ ++ SND_LOG_DEBUG(HLOG, "Revert to legacy daifmt parsing\n"); ++ ++ daifmt |= snd_soc_daifmt_parse_clock_provider_as_flag(codec, NULL); ++ } else { ++ daifmt |= snd_soc_daifmt_clock_provider_from_bitmap( ++ ((codec == bitclkmaster) << 4) | (codec == framemaster)); ++ } ++ ++ of_node_put(bitclkmaster); ++ of_node_put(framemaster); ++ ++ *retfmt = daifmt; ++ ++ return 0; ++} ++ ++int asoc_simple_parse_daistream(struct device_node *node, char *prefix, ++ struct snd_soc_dai_link *dai_link) ++{ ++ char prop[128]; ++ ++ if (!prefix) ++ prefix = ""; ++ ++ /* check "[prefix]playback-only" */ ++ snprintf(prop, sizeof(prop), "%splayback-only", prefix); ++ if (of_property_read_bool(node, prop)) ++ dai_link->playback_only = 1; ++ ++ /* check "[prefix]capture-only" */ ++ snprintf(prop, sizeof(prop), "%scapture-only", prefix); ++ if (of_property_read_bool(node, prop)) ++ dai_link->capture_only = 1; ++ ++ return 0; ++} ++ ++int asoc_simple_parse_tdm_slot(struct device_node *node, char *prefix, ++ struct asoc_simple_dai *dais) ++{ ++ int ret; ++ char prop[128]; ++ unsigned int val; ++ ++ if (!prefix) ++ prefix = ""; ++ ++ snprintf(prop, sizeof(prop), "%sslot-num", prefix); ++ ret = of_property_read_u32(node, prop, &val); ++ if (!ret) ++ dais->slots = val; ++ ++ snprintf(prop, sizeof(prop), "%sslot-width", prefix); ++ ret = of_property_read_u32(node, prop, &val); ++ if (!ret) ++ dais->slot_width = val; ++ ++ return 0; ++} ++ ++int asoc_simple_parse_tdm_clk(struct device_node *cpu, ++ struct device_node *codec, ++ char *prefix, ++ struct simple_dai_props *dai_props) ++{ ++ int ret; ++ char prop[128]; ++ unsigned int val; ++ ++ if (!prefix) ++ prefix = ""; ++ ++ snprintf(prop, sizeof(prop), "%spll-fs", prefix); ++ ret = of_property_read_u32(cpu, prop, &val); ++ if (ret) ++ dai_props->cpu_pll_fs = 1; /* default sysclk 24.576 or 22.5792MHz * 1 */ ++ else ++ dai_props->cpu_pll_fs = val; ++ ++ ret = of_property_read_u32(codec, prop, &val); ++ if (ret) ++ dai_props->codec_pll_fs = 1; /* default sysclk 24.576 or 22.5792MHz * 1 */ ++ else ++ dai_props->codec_pll_fs = val; ++ ++ snprintf(prop, sizeof(prop), "%smclk-fp", prefix); ++ dai_props->mclk_fp = of_property_read_bool(cpu, prop); ++ ++ snprintf(prop, sizeof(prop), "%smclk-fs", prefix); ++ ret = of_property_read_u32(cpu, prop, &val); ++ if (ret) ++ dai_props->mclk_fs = 0; /* default mclk 0Hz(un output) */ ++ else ++ dai_props->mclk_fs = val; ++ ++ return 0; ++} ++ ++int asoc_simple_parse_card_name(struct snd_soc_card *card, ++ char *prefix) ++{ ++ int ret; ++ ++ if (!prefix) ++ prefix = ""; ++ ++ /* Parse the card name from DT */ ++ ret = snd_soc_of_parse_card_name(card, "label"); ++ if (ret < 0 || !card->name) { ++ char prop[128]; ++ ++ snprintf(prop, sizeof(prop), "%sname", prefix); ++ ret = snd_soc_of_parse_card_name(card, prop); ++ if (ret < 0) ++ return ret; ++ } ++ ++ if (!card->name && card->dai_link) ++ card->name = card->dai_link->name; ++ ++ return 0; ++} ++ ++int asoc_simple_parse_dai(struct device_node *node, ++ struct snd_soc_dai_link_component *dlc, ++ const char *list_name, const char *cells_name, ++ int *is_single_link) ++{ ++ struct of_phandle_args args; ++ int ret; ++ ++ if (!node) ++ return 0; ++ ++ /* ++ * Get node via "sound-dai = <&phandle port>" ++ * it will be used as xxx_of_node on soc_bind_dai_link() ++ */ ++ ret = of_parse_phandle_with_args(node, list_name, cells_name, 0, &args); ++ if (ret) ++ return ret; ++ ++ /* ++ * FIXME ++ * ++ * Here, dlc->dai_name is pointer to CPU/Codec DAI name. ++ * If user unbinded CPU or Codec driver, but not for Sound Card, ++ * dlc->dai_name is keeping unbinded CPU or Codec ++ * driver's pointer. ++ * ++ * If user re-bind CPU or Codec driver again, ALSA SoC will try ++ * to rebind Card via snd_soc_try_rebind_card(), but because of ++ * above reason, it might can't bind Sound Card. ++ * Because Sound Card is pointing to released dai_name pointer. ++ * ++ * To avoid this rebind Card issue, ++ * 1) It needs to alloc memory to keep dai_name eventhough ++ * CPU or Codec driver was unbinded, or ++ * 2) user need to rebind Sound Card everytime ++ * if he unbinded CPU or Codec. ++ */ ++ ret = snd_soc_of_get_dai_name(node, &dlc->dai_name, 0); ++ if (ret < 0) ++ return ret; ++ ++ dlc->of_node = args.np; ++ ++ if (is_single_link) ++ *is_single_link = !args.args_count; ++ ++ return 0; ++} ++ ++int asoc_simple_set_dailink_name(struct device *dev, ++ struct snd_soc_dai_link *dai_link, ++ const char *fmt, ...) ++{ ++ va_list ap; ++ char *name = NULL; ++ int ret = -ENOMEM; ++ ++ va_start(ap, fmt); ++ name = devm_kvasprintf(dev, GFP_KERNEL, fmt, ap); ++ va_end(ap); ++ ++ if (name) { ++ ret = 0; ++ ++ dai_link->name = name; ++ dai_link->stream_name = name; ++ } ++ ++ return ret; ++} ++ ++void asoc_simple_canonicalize_platform(struct snd_soc_dai_link *dai_link) ++{ ++ /* Assumes platform == cpu */ ++ if (!dai_link->platforms->of_node) ++ dai_link->platforms->of_node = dai_link->cpus->of_node; ++ ++ /* ++ * DPCM BE can be no platform. ++ * Alloced memory will be waste, but not leak. ++ */ ++ if (!dai_link->platforms->of_node) ++ dai_link->num_platforms = 0; ++} ++ ++void asoc_simple_canonicalize_cpu(struct snd_soc_dai_link *dai_link, ++ int is_single_links) ++{ ++ /* ++ * In soc_bind_dai_link() will check cpu name after ++ * of_node matching if dai_link has cpu_dai_name. ++ * but, it will never match if name was created by ++ * fmt_single_name() remove cpu_dai_name if cpu_args ++ * was 0. See: ++ * fmt_single_name() ++ * fmt_multiple_name() ++ */ ++ if (is_single_links) ++ dai_link->cpus->dai_name = NULL; ++} ++ ++MODULE_AUTHOR("Dby@allwinnertech.com"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("sunxi soundcard machine utils"); +diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h +new file mode 100644 +index 000000000..a9cffa0d8 +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h +@@ -0,0 +1,116 @@ ++/* sound\soc\sunxi\snd_sunxi_mach_utils.h ++ * (C) Copyright 2021-2025 ++ * Allwinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#ifndef __SND_SUNXI_MACH_UTILS_H ++#define __SND_SUNXI_MACH_UTILS_H ++ ++#define simple_priv_to_card(priv) (&(priv)->snd_card) ++#define simple_priv_to_props(priv, i) ((priv)->dai_props + (i)) ++#define simple_priv_to_dev(priv) (simple_priv_to_card(priv)->dev) ++#define simple_priv_to_link(priv, i) (simple_priv_to_card(priv)->dai_link + (i)) ++ ++#define asoc_simple_parse_cpu(node, dai_link, \ ++ list_name, cells_name, is_single_link) \ ++ asoc_simple_parse_dai(node, dai_link->cpus, \ ++ list_name, cells_name, is_single_link) ++ ++#define asoc_simple_parse_codec(node, dai_link, \ ++ list_name, cells_name) \ ++ asoc_simple_parse_dai(node, dai_link->codecs, \ ++ list_name, cells_name, NULL) ++ ++#define asoc_simple_parse_platform(node, dai_link, \ ++ list_name, cells_name) \ ++ asoc_simple_parse_dai(node, dai_link->platforms, \ ++ list_name, cells_name, NULL) ++ ++struct asoc_simple_dai { ++ const char *name; ++ unsigned int sysclk; ++ int clk_direction; ++ int slots; ++ int slot_width; ++ unsigned int tx_slot_mask; ++ unsigned int rx_slot_mask; ++ struct clk *clk; ++}; ++ ++struct asoc_simple_data { ++ u32 convert_rate; ++ u32 convert_channels; ++}; ++ ++struct asoc_simple_jack { ++ struct snd_soc_jack jack; ++ struct snd_soc_jack_pin pin; ++ struct snd_soc_jack_gpio gpio; ++}; ++ ++struct asoc_simple_priv { ++ struct snd_soc_card snd_card; ++ struct simple_dai_props { ++ struct asoc_simple_dai *cpu_dai; ++ struct asoc_simple_dai *codec_dai; ++ struct snd_soc_dai_link_component cpus; /* single cpu */ ++ struct snd_soc_dai_link_component codecs; /* single codec */ ++ struct snd_soc_dai_link_component platforms; ++ struct asoc_simple_data adata; ++ struct snd_soc_codec_conf *codec_conf; ++ bool mclk_fp; ++ unsigned int mclk_fs; ++ unsigned int cpu_pll_fs; ++ unsigned int codec_pll_fs; ++ } *dai_props; ++ struct asoc_simple_jack hp_jack; ++ struct asoc_simple_jack mic_jack; ++ struct snd_soc_dai_link *dai_link; ++ struct asoc_simple_dai *dais; ++ struct snd_soc_codec_conf *codec_conf; ++ struct gpio_desc *pa_gpio; ++}; ++ ++int asoc_simple_clean_reference(struct snd_soc_card *card); ++int asoc_simple_init_priv(struct asoc_simple_priv *priv); ++ ++int asoc_simple_parse_widgets(struct snd_soc_card *card, char *prefix); ++int asoc_simple_parse_routing(struct snd_soc_card *card, char *prefix); ++int asoc_simple_parse_pin_switches(struct snd_soc_card *card, char *prefix); ++ ++int asoc_simple_parse_daistream(struct device_node *node, ++ char *prefix, ++ struct snd_soc_dai_link *dai_link); ++int asoc_simple_parse_daifmt(struct device_node *node, ++ struct device_node *codec, ++ char *prefix, ++ unsigned int *retfmt); ++int asoc_simple_parse_tdm_slot(struct device_node *node, ++ char *prefix, ++ struct asoc_simple_dai *dais); ++int asoc_simple_parse_tdm_clk(struct device_node *cpu, ++ struct device_node *codec, ++ char *prefix, ++ struct simple_dai_props *dai_props); ++ ++int asoc_simple_parse_card_name(struct snd_soc_card *card, char *prefix); ++int asoc_simple_parse_dai(struct device_node *node, ++ struct snd_soc_dai_link_component *dlc, ++ const char *list_name, ++ const char *cells_name, ++ int *is_single_link); ++ ++int asoc_simple_set_dailink_name(struct device *dev, ++ struct snd_soc_dai_link *dai_link, ++ const char *fmt, ...); ++void asoc_simple_canonicalize_platform(struct snd_soc_dai_link *dai_link); ++void asoc_simple_canonicalize_cpu(struct snd_soc_dai_link *dai_link, ++ int is_single_links); ++ ++#endif /* __SND_SUNXI_MACH_UTILS_H */ +-- +Created with Armbian build tools https://github.com/armbian/build + diff --git a/patch/kernel/archive/sunxi-6.6/series.armbian b/patch/kernel/archive/sunxi-6.6/series.armbian index ba8674060e42..bc85e44bd162 100644 --- a/patch/kernel/archive/sunxi-6.6/series.armbian +++ b/patch/kernel/archive/sunxi-6.6/series.armbian @@ -204,3 +204,4 @@ patches.armbian/arm64-dts-allwinner-sun50i-h616-spi1-cs1-pin.patch patches.armbian/arm64-dts-sun50i-h618-add-overlay.patch patches.armbian/arm-dts-orangepi-one-pinctr-dummy-regulators.patch + patches.armbian/sound-soc-sunxi-h616-h618.patch diff --git a/patch/kernel/archive/sunxi-6.6/series.conf b/patch/kernel/archive/sunxi-6.6/series.conf index 26219744bdfc..b62823777b66 100644 --- a/patch/kernel/archive/sunxi-6.6/series.conf +++ b/patch/kernel/archive/sunxi-6.6/series.conf @@ -473,3 +473,4 @@ patches.armbian/arm64-dts-allwinner-sun50i-h616-spi1-cs1-pin.patch patches.armbian/arm64-dts-sun50i-h618-add-overlay.patch patches.armbian/arm-dts-orangepi-one-pinctr-dummy-regulators.patch + patches.armbian/sound-soc-sunxi-h616-h618.patch diff --git a/patch/kernel/archive/sunxi-6.7/patches.armbian/sound-soc-sunxi-h616-h618.patch b/patch/kernel/archive/sunxi-6.7/patches.armbian/sound-soc-sunxi-h616-h618.patch new file mode 100644 index 000000000000..16dcbdf3d6fa --- /dev/null +++ b/patch/kernel/archive/sunxi-6.7/patches.armbian/sound-soc-sunxi-h616-h618.patch @@ -0,0 +1,5504 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Stephen Graf +Date: Thu, 9 May 2024 20:59:34 -0700 +Subject: Sound for H616, H618 Allwinner SOCs + arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi + arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi + drivers/clk/sunxi-ng/ccu-sun50i-h616.c include/sound/soc-dai.h + sound/soc/Kconfig sound/soc/Makefile sound/soc/soc-core.c + sound/soc/sunxi/Kconfig sound/soc/sunxi/Makefile + sound/soc/sunxi/sun50iw9-codec.c sound/soc/sunxi_v2/Kconfig + sound/soc/sunxi_v2/Makefile sound/soc/sunxi_v2/drv_hdmi.h + sound/soc/sunxi_v2/snd_sunxi_ahub.c sound/soc/sunxi_v2/snd_sunxi_ahub.h + sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c + sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h sound/soc/sunxi_v2/snd_sunxi_common.c + sound/soc/sunxi_v2/snd_sunxi_common.h sound/soc/sunxi_v2/snd_sunxi_log.h + sound/soc/sunxi_v2/snd_sunxi_mach.c sound/soc/sunxi_v2/snd_sunxi_mach.h + sound/soc/sunxi_v2/snd_sunxi_mach_utils.c + sound/soc/sunxi_v2/snd_sunxi_mach_utils.h + +Signed-off-by: Stephen Graf +--- + arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 18 + + arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 83 + + drivers/clk/sunxi-ng/ccu-sun50i-h616.c | 33 +- + include/sound/soc-dai.h | 13 + + sound/soc/Kconfig | 1 + + sound/soc/Makefile | 1 + + sound/soc/soc-core.c | 25 + + sound/soc/sunxi/Kconfig | 8 + + sound/soc/sunxi/Makefile | 1 + + sound/soc/sunxi/sun50iw9-codec.c | 1093 +++++++ + sound/soc/sunxi_v2/Kconfig | 48 + + sound/soc/sunxi_v2/Makefile | 11 + + sound/soc/sunxi_v2/drv_hdmi.h | 63 + + sound/soc/sunxi_v2/snd_sunxi_ahub.c | 1477 ++++++++++ + sound/soc/sunxi_v2/snd_sunxi_ahub.h | 67 + + sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c | 534 ++++ + sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h | 291 ++ + sound/soc/sunxi_v2/snd_sunxi_common.c | 267 ++ + sound/soc/sunxi_v2/snd_sunxi_common.h | 67 + + sound/soc/sunxi_v2/snd_sunxi_log.h | 29 + + sound/soc/sunxi_v2/snd_sunxi_mach.c | 479 +++ + sound/soc/sunxi_v2/snd_sunxi_mach.h | 17 + + sound/soc/sunxi_v2/snd_sunxi_mach_utils.c | 422 +++ + sound/soc/sunxi_v2/snd_sunxi_mach_utils.h | 116 + + 24 files changed, 5147 insertions(+), 17 deletions(-) + +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi +index ce3dc6d9c..23553f224 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi +@@ -103,10 +103,28 @@ wifi_pwrseq: wifi-pwrseq { + + &de { + status = "okay"; + }; + ++&codec { ++ allwinner,audio-routing = ++ "Line Out", "LINEOUT"; ++ status = "okay"; ++}; ++ ++&ahub_dam_plat { ++ status = "okay"; ++}; ++ ++&ahub1_plat { ++ status = "okay"; ++}; ++ ++&ahub1_mach { ++ status = "okay"; ++}; ++ + &ehci1 { + status = "okay"; + }; + + /* USB 2 & 3 are on headers only. */ +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +index 36c75d783..1b004503b 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +@@ -180,10 +180,82 @@ dma: dma-controller@3002000 { + dma-requests = <49>; + resets = <&ccu RST_BUS_DMA>; + #dma-cells = <1>; + }; + ++ codec: codec@05096000 { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sun50i-h616-codec"; ++ reg = <0x05096000 0x31c>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_AUDIO_CODEC>, ++ <&ccu CLK_AUDIO_CODEC_1X>, ++ <&ccu CLK_AUDIO_CODEC_4X>; ++ clock-names = "apb", "audio-codec-1x", "audio-codec-4x"; ++ resets = <&ccu RST_BUS_AUDIO_CODEC>; ++ dmas = <&dma 6>; ++ dma-names = "tx"; ++ status = "disabled"; ++ }; ++ ++ ahub_dam_plat:ahub_dam_plat@5097000 { ++ #sound-dai-cells = <0>; ++ /* sound card without pcm for hardware mix setting */ ++ compatible = "allwinner,sunxi-snd-plat-ahub_dam"; ++ reg = <0x05097000 0x1000>; ++ resets = <&ccu RST_BUS_AUDIO_HUB>; ++ clocks = <&ccu CLK_AUDIO_CODEC_1X>, ++ <&ccu CLK_AUDIO_CODEC_4X>, ++ <&ccu CLK_AUDIO_HUB>, ++ <&ccu CLK_BUS_AUDIO_HUB>; ++ clock-names = "clk_pll_audio", ++ "clk_pll_audio_4x", ++ "clk_audio_hub", ++ "clk_bus_audio_hub"; ++ status = "disabled"; ++ }; ++ ++ ahub1_plat:ahub1_plat { ++ #sound-dai-cells = <0>; ++ compatible = "allwinner,sunxi-snd-plat-ahub"; ++ apb_num = <1>; /* for dma port 4 */ ++ dmas = <&dma 4>, <&dma 4>; ++ dma-names = "tx", "rx"; ++ playback_cma = <128>; ++ capture_cma = <128>; ++ tx_fifo_size = <128>; ++ rx_fifo_size = <128>; ++ ++ tdm_num = <1>; ++ tx_pin = <0>; ++ rx_pin = <0>; ++ status = "disabled"; ++ }; ++ ++ ahub1_mach:ahub1_mach { ++ compatible = "allwinner,sunxi-snd-mach"; ++ soundcard-mach,name = "HDMI"; ++ ++ soundcard-mach,format = "i2s"; ++ soundcard-mach,frame-master = <&ahub1_cpu>; ++ soundcard-mach,bitclock-master = <&ahub1_cpu>; ++ /* soundcard-mach,frame-inversion; */ ++ /* soundcard-mach,bitclock-inversion; */ ++ soundcard-mach,slot-num = <2>; ++ soundcard-mach,slot-width = <32>; ++ status = "disabled"; ++ ahub1_cpu: soundcard-mach,cpu { ++ sound-dai = <&ahub1_plat>; ++ soundcard-mach,pll-fs = <4>; ++ soundcard-mach,mclk-fs = <0>; ++ }; ++ ++ ahub1_codec: soundcard-mach,codec { ++ sound-dai = <&hdmi>; ++ }; ++ }; ++ + gpu: gpu@1800000 { + compatible = "allwinner,sun50i-h616-mali", + "arm,mali-bifrost"; + reg = <0x1800000 0x40000>; + interrupts = , +@@ -455,10 +527,21 @@ gic: interrupt-controller@3021000 { + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + ++ iommu: iommu@30f0000 { ++ compatible = "allwinner,sun50i-h616-iommu", ++ "allwinner,sun50i-h6-iommu"; ++ reg = <0x030f0000 0x10000>; ++ interrupts = ; ++ clocks = <&ccu CLK_BUS_IOMMU>; ++ resets = <&ccu RST_BUS_IOMMU>; ++ #iommu-cells = <1>; ++ status = "okay"; ++ }; ++ + mmc0: mmc@4020000 { + compatible = "allwinner,sun50i-h616-mmc", + "allwinner,sun50i-a100-mmc"; + reg = <0x04020000 0x1000>; + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; +diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c +index 21e918582..ab2628596 100644 +--- a/drivers/clk/sunxi-ng/ccu-sun50i-h616.c ++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h616.c +@@ -213,24 +213,26 @@ static struct ccu_nkmp pll_de_clk = { + &ccu_nkmp_ops, + CLK_SET_RATE_UNGATE), + }, + }; + +-/* +- * TODO: Determine SDM settings for the audio PLL. The manual suggests +- * PLL_FACTOR_N=16, PLL_POST_DIV_P=2, OUTPUT_DIV=2, pattern=0xe000c49b +- * for 24.576 MHz, and PLL_FACTOR_N=22, PLL_POST_DIV_P=3, OUTPUT_DIV=2, +- * pattern=0xe001288c for 22.5792 MHz. +- * This clashes with our fixed PLL_POST_DIV_P. +- */ + #define SUN50I_H616_PLL_AUDIO_REG 0x078 ++ ++static struct ccu_sdm_setting pll_audio_sdm_table[] = { ++ { .rate = 90316800, .pattern = 0xc001288d, .m = 3, .n = 22 }, ++ { .rate = 98304000, .pattern = 0xc001eb85, .m = 5, .n = 40 }, ++}; ++ + static struct ccu_nm pll_audio_hs_clk = { + .enable = BIT(31), + .lock = BIT(28), + .n = _SUNXI_CCU_MULT_MIN(8, 8, 12), +- .m = _SUNXI_CCU_DIV(1, 1), /* input divider */ ++ .m = _SUNXI_CCU_DIV(16, 6), ++ .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, ++ BIT(24), 0x178, BIT(31)), + .common = { ++ .features = CCU_FEATURE_SIGMA_DELTA_MOD, + .reg = 0x078, + .hw.init = CLK_HW_INIT("pll-audio-hs", "osc24M", + &ccu_nm_ops, + CLK_SET_RATE_UNGATE), + }, +@@ -686,17 +688,17 @@ static const struct clk_hw *clk_parent_pll_audio[] = { + * The divider of pll-audio is fixed to 24 for now, so 24576000 and 22579200 + * rates can be set exactly in conjunction with sigma-delta modulation. + */ + static CLK_FIXED_FACTOR_HWS(pll_audio_1x_clk, "pll-audio-1x", + clk_parent_pll_audio, +- 96, 1, CLK_SET_RATE_PARENT); ++ 4, 1, CLK_SET_RATE_PARENT); + static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x", + clk_parent_pll_audio, +- 48, 1, CLK_SET_RATE_PARENT); ++ 2, 1, CLK_SET_RATE_PARENT); + static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x", + clk_parent_pll_audio, +- 24, 1, CLK_SET_RATE_PARENT); ++ 1, 1, CLK_SET_RATE_PARENT); + + static const struct clk_hw *pll_periph0_parents[] = { + &pll_periph0_clk.common.hw + }; + +@@ -1128,17 +1130,14 @@ static int sun50i_h616_ccu_probe(struct platform_device *pdev) + val = readl(reg + usb2_clk_regs[i]); + val &= ~GENMASK(25, 24); + writel(val, reg + usb2_clk_regs[i]); + } + +- /* +- * Force the post-divider of pll-audio to 12 and the output divider +- * of it to 2, so 24576000 and 22579200 rates can be set exactly. +- */ + val = readl(reg + SUN50I_H616_PLL_AUDIO_REG); +- val &= ~(GENMASK(21, 16) | BIT(0)); +- writel(val | (11 << 16) | BIT(0), reg + SUN50I_H616_PLL_AUDIO_REG); ++ val &= ~BIT(1); ++ val |= BIT(0); ++ writel(val, reg + SUN50I_H616_PLL_AUDIO_REG); + + /* + * First clock parent (osc32K) is unusable for CEC. But since there + * is no good way to force parent switch (both run with same frequency), + * just set second clock parent here. +diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h +index adcd8719d..778751096 100644 +--- a/include/sound/soc-dai.h ++++ b/include/sound/soc-dai.h +@@ -413,20 +413,33 @@ struct snd_soc_dai_driver { + unsigned int id; + unsigned int base; + struct snd_soc_dobj dobj; + struct of_phandle_args *dai_args; + ++ /* DAI driver callbacks */ ++ int (*probe)(struct snd_soc_dai *dai); ++ int (*remove)(struct snd_soc_dai *dai); ++ /* compress dai */ ++ int (*compress_new)(struct snd_soc_pcm_runtime *rtd, int num); ++ /* Optional Callback used at pcm creation*/ ++ int (*pcm_new)(struct snd_soc_pcm_runtime *rtd, ++ struct snd_soc_dai *dai); ++ + /* ops */ + const struct snd_soc_dai_ops *ops; + const struct snd_soc_cdai_ops *cops; + + /* DAI capabilities */ + struct snd_soc_pcm_stream capture; + struct snd_soc_pcm_stream playback; + unsigned int symmetric_rate:1; + unsigned int symmetric_channels:1; + unsigned int symmetric_sample_bits:1; ++ ++ /* probe ordering - for components with runtime dependencies */ ++ int probe_order; ++ int remove_order; + }; + + /* for Playback/Capture */ + struct snd_soc_dai_stream { + struct snd_soc_dapm_widget *widget; +diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig +index 439fa631c..7dc3967cc 100644 +--- a/sound/soc/Kconfig ++++ b/sound/soc/Kconfig +@@ -106,10 +106,11 @@ source "sound/soc/spear/Kconfig" + source "sound/soc/sprd/Kconfig" + source "sound/soc/starfive/Kconfig" + source "sound/soc/sti/Kconfig" + source "sound/soc/stm/Kconfig" + source "sound/soc/sunxi/Kconfig" ++source "sound/soc/sunxi_v2/Kconfig" + source "sound/soc/tegra/Kconfig" + source "sound/soc/ti/Kconfig" + source "sound/soc/uniphier/Kconfig" + source "sound/soc/ux500/Kconfig" + source "sound/soc/xilinx/Kconfig" +diff --git a/sound/soc/Makefile b/sound/soc/Makefile +index 8376fdb21..79b48e8b3 100644 +--- a/sound/soc/Makefile ++++ b/sound/soc/Makefile +@@ -63,10 +63,11 @@ obj-$(CONFIG_SND_SOC) += spear/ + obj-$(CONFIG_SND_SOC) += sprd/ + obj-$(CONFIG_SND_SOC) += starfive/ + obj-$(CONFIG_SND_SOC) += sti/ + obj-$(CONFIG_SND_SOC) += stm/ + obj-$(CONFIG_SND_SOC) += sunxi/ ++obj-$(CONFIG_SND_SOC) += sunxi_v2/ + obj-$(CONFIG_SND_SOC) += tegra/ + obj-$(CONFIG_SND_SOC) += ti/ + obj-$(CONFIG_SND_SOC) += uniphier/ + obj-$(CONFIG_SND_SOC) += ux500/ + obj-$(CONFIG_SND_SOC) += xilinx/ +diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c +index b2bd45e87..723c19fb4 100644 +--- a/sound/soc/soc-core.c ++++ b/sound/soc/soc-core.c +@@ -2518,10 +2518,11 @@ struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component, + struct snd_soc_dai_driver *dai_drv, + bool legacy_dai_naming) + { + struct device *dev = component->dev; + struct snd_soc_dai *dai; ++ struct snd_soc_dai_ops *ops; /* REMOVE ME */ + + lockdep_assert_held(&client_mutex); + + dai = devm_kzalloc(dev, sizeof(*dai), GFP_KERNEL); + if (dai == NULL) +@@ -2546,10 +2547,34 @@ struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component, + dai->id = component->num_dai; + } + if (!dai->name) + return NULL; + ++ /* REMOVE ME */ ++ if (dai_drv->probe || ++ dai_drv->remove || ++ dai_drv->compress_new || ++ dai_drv->pcm_new || ++ dai_drv->probe_order || ++ dai_drv->remove_order) { ++ ++ ops = devm_kzalloc(dev, sizeof(struct snd_soc_dai_ops), GFP_KERNEL); ++ if (!ops) ++ return NULL; ++ if (dai_drv->ops) ++ memcpy(ops, dai_drv->ops, sizeof(struct snd_soc_dai_ops)); ++ ++ ops->probe = dai_drv->probe; ++ ops->remove = dai_drv->remove; ++ ops->compress_new = dai_drv->compress_new; ++ ops->pcm_new = dai_drv->pcm_new; ++ ops->probe_order = dai_drv->probe_order; ++ ops->remove_order = dai_drv->remove_order; ++ ++ dai_drv->ops = ops; ++ } ++ + dai->component = component; + dai->dev = dev; + dai->driver = dai_drv; + + /* see for_each_component_dais */ +diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig +index 753c38c5d..0f6579ea7 100644 +--- a/sound/soc/sunxi/Kconfig ++++ b/sound/soc/sunxi/Kconfig +@@ -8,10 +8,18 @@ config SND_SUN4I_CODEC + select REGMAP_MMIO + help + Select Y or M to add support for the Codec embedded in the Allwinner + A10 and affiliated SoCs. + ++config SND_SUN50IW9_CODEC ++ tristate "Allwinner H616 Codec Support" ++ select SND_SOC_GENERIC_DMAENGINE_PCM ++ select REGMAP_MMIO ++ help ++ Select Y or M to add support for the Codec embedded in the Allwinner ++ H616 and affiliated SoCs. ++ + config SND_SUN8I_CODEC + tristate "Allwinner SUN8I audio codec" + depends on OF + depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST + depends on COMMON_CLK +diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile +index b0b976a3d..f72d94f30 100644 +--- a/sound/soc/sunxi/Makefile ++++ b/sound/soc/sunxi/Makefile +@@ -1,8 +1,9 @@ + # SPDX-License-Identifier: GPL-2.0 + obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o + obj-$(CONFIG_SND_SUN4I_CODEC) += sun4i-codec.o ++obj-$(CONFIG_SND_SUN50IW9_CODEC) += sun50iw9-codec.o + obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o + obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o + obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o + obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o + obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o +diff --git a/sound/soc/sunxi/sun50iw9-codec.c b/sound/soc/sunxi/sun50iw9-codec.c +new file mode 100644 +index 000000000..38b1d3824 +--- /dev/null ++++ b/sound/soc/sunxi/sun50iw9-codec.c +@@ -0,0 +1,1093 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Copyright 2014 Emilio López ++ * Copyright 2014 Jon Smirl ++ * Copyright 2015 Maxime Ripard ++ * Copyright 2015 Adam Sampson ++ * Copyright 2016 Chen-Yu Tsai ++ * Copyright 2021 gryzun ++ * ++ * Based on the Allwinner SDK driver, released under the GPL. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#define SUNXI_DAC_DPC (0x00) ++#define SUNXI_DAC_DPC_EN_DA (31) ++#define SUNXI_DAC_DPC_DVOL (12) ++#define SUNXI_DAC_DPC_HPF_EN (18) ++ ++#define SUNXI_DAC_FIFOC (0x10) ++#define SUNXI_DAC_FIFOC_DAC_FS (29) ++#define SUNXI_DAC_FIFOC_TX_FIFO_MODE (24) ++#define SUNXI_DAC_FIFOC_DRQ_CLR_CNT (21) ++#define SUNXI_DAC_FIFOC_MONO_EN (6) ++#define SUNXI_DAC_FIFOC_TX_SAMPLE_BITS (5) ++#define SUNXI_DAC_FIFOC_DAC_DRQ_EN (4) ++#define SUNXI_DAC_FIFOC_FIFO_FLUSH (0) ++ ++#define SUNXI_DAC_FIFO_STA (0x14) ++#define SUNXI_DAC_TXE_INT (3) ++#define SUNXI_DAC_TXU_INT (2) ++#define SUNXI_DAC_TXO_INT (1) ++#define SUNXI_DAC_TXDATA (0x20) ++#define SUNXI_DAC_CNT (0x24) ++#define SUNXI_DAC_DG_REG (0x28) ++#define SUNXI_DAC_DAP_CTL (0xf0) ++ ++#define SUNXI_DAC_AC_DAC_REG (0x310) ++#define SUNXI_DAC_LEN (15) ++#define SUNXI_DAC_REN (14) ++#define SUNXI_LINEOUTL_EN (13) ++#define SUNXI_LMUTE (12) ++#define SUNXI_LINEOUTR_EN (11) ++#define SUNXI_RMUTE (10) ++#define SUNXI_RSWITCH (9) ++#define SUNXI_RAMPEN (8) ++#define SUNXI_LINEOUTL_SEL (6) ++#define SUNXI_LINEOUTR_SEL (5) ++#define SUNXI_LINEOUT_VOL (0) ++ ++#define SUNXI_DAC_AC_MIXER_REG (0x314) ++#define SUNXI_LMIX_LDAC (21) ++#define SUNXI_LMIX_RDAC (20) ++#define SUNXI_RMIX_RDAC (17) ++#define SUNXI_RMIX_LDAC (16) ++#define SUNXI_LMIXEN (11) ++#define SUNXI_RMIXEN (10) ++ ++#define SUNXI_DAC_AC_RAMP_REG (0x31c) ++#define SUNXI_RAMP_STEP (4) ++#define SUNXI_RDEN (0) ++ ++#define LABEL(constant) \ ++ { \ ++#constant, constant, 0 \ ++ } ++#define LABEL_END \ ++ { \ ++ NULL, 0, -1 \ ++ } ++ ++struct audiocodec_reg_label ++{ ++ const char *name; ++ const unsigned int address; ++ int value; ++}; ++ ++static struct audiocodec_reg_label reg_labels[] = { ++ LABEL(SUNXI_DAC_DPC), ++ LABEL(SUNXI_DAC_FIFOC), ++ LABEL(SUNXI_DAC_FIFO_STA), ++ LABEL(SUNXI_DAC_CNT), ++ LABEL(SUNXI_DAC_DG_REG), ++ LABEL(SUNXI_DAC_DAP_CTL), ++ LABEL(SUNXI_DAC_AC_DAC_REG), ++ LABEL(SUNXI_DAC_AC_MIXER_REG), ++ LABEL(SUNXI_DAC_AC_RAMP_REG), ++ LABEL_END, ++}; ++ ++struct regmap *codec_regmap_debug = NULL; ++ ++struct sun50i_h616_codec ++{ ++ unsigned char *name; ++ struct device *dev; ++ struct regmap *regmap; ++ struct clk *clk_apb; ++ struct clk *clk_module; ++ struct reset_control *rst; ++ struct gpio_desc *gpio_pa; ++ ++ /* ADC_FIFOC register is at different offset on different SoCs */ ++ struct regmap_field *reg_adc_fifoc; ++ ++ struct snd_dmaengine_dai_dma_data playback_dma_data; ++}; ++ ++static void sun50i_h616_codec_start_playback(struct sun50i_h616_codec *scodec) ++{ ++ /* Flush TX FIFO */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_FIFO_FLUSH), ++ BIT(SUNXI_DAC_FIFOC_FIFO_FLUSH)); ++ ++ /* Enable DAC DRQ */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_DAC_DRQ_EN), ++ BIT(SUNXI_DAC_FIFOC_DAC_DRQ_EN)); ++} ++ ++static void sun50i_h616_codec_stop_playback(struct sun50i_h616_codec *scodec) ++{ ++ /* Disable DAC DRQ */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_DAC_DRQ_EN), ++ 0); ++} ++ ++static int sun50i_h616_codec_trigger(struct snd_pcm_substream *substream, int cmd, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card); ++ ++ switch (cmd) ++ { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN), ++ (0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN)); ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x1 << SUNXI_DAC_FIFOC_DAC_DRQ_EN), ++ (0x0 << SUNXI_DAC_FIFOC_DAC_DRQ_EN)); ++ break; ++ default: ++ return -EINVAL; ++ } ++ return 0; ++} ++ ++static int sun50i_h616_codec_prepare(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ (0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH), ++ (0x1 << SUNXI_DAC_FIFOC_FIFO_FLUSH)); ++ regmap_write(scodec->regmap, SUNXI_DAC_FIFO_STA, ++ (0x1 << SUNXI_DAC_TXE_INT | 1 << SUNXI_DAC_TXU_INT | 0x1 << SUNXI_DAC_TXO_INT)); ++ regmap_write(scodec->regmap, SUNXI_DAC_CNT, 0); ++ ++ return 0; ++} ++ ++static unsigned long sun50i_h616_codec_get_mod_freq(struct snd_pcm_hw_params *params) ++{ ++ unsigned int rate = params_rate(params); ++ ++ switch (rate) ++ { ++ case 176400: ++ case 88200: ++ case 44100: ++ case 33075: ++ case 22050: ++ case 14700: ++ case 11025: ++ case 7350: ++ return 22579200; ++ ++ case 192000: ++ case 96000: ++ case 48000: ++ case 32000: ++ case 24000: ++ case 16000: ++ case 12000: ++ case 8000: ++ return 24576000; ++ ++ default: ++ return 0; ++ } ++} ++ ++static int sun50i_h616_codec_get_hw_rate(struct snd_pcm_hw_params *params) ++{ ++ unsigned int rate = params_rate(params); ++ ++ switch (rate) ++ { ++ case 192000: ++ case 176400: ++ return 6; ++ ++ case 96000: ++ case 88200: ++ return 7; ++ ++ case 48000: ++ case 44100: ++ return 0; ++ ++ case 32000: ++ case 33075: ++ return 1; ++ ++ case 24000: ++ case 22050: ++ return 2; ++ ++ case 16000: ++ case 14700: ++ return 3; ++ ++ case 12000: ++ case 11025: ++ return 4; ++ ++ case 8000: ++ case 7350: ++ return 5; ++ ++ default: ++ return -EINVAL; ++ } ++} ++ ++static int sun50i_h616_codec_hw_params_playback(struct sun50i_h616_codec *scodec, ++ struct snd_pcm_hw_params *params, ++ unsigned int hwrate) ++{ ++ u32 val; ++ ++ /* Set DAC sample rate */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ 7 << SUNXI_DAC_FIFOC_DAC_FS, ++ hwrate << SUNXI_DAC_FIFOC_DAC_FS); ++ ++ /* Set the number of channels we want to use */ ++ if (params_channels(params) == 1) ++ val = BIT(SUNXI_DAC_FIFOC_MONO_EN); ++ else ++ val = 0; ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_MONO_EN), ++ val); ++ ++ /* Set the number of sample bits to either 16 or 24 bits */ ++ if (hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min == 32) ++ { ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_TX_SAMPLE_BITS), ++ BIT(SUNXI_DAC_FIFOC_TX_SAMPLE_BITS)); ++ ++ /* Set TX FIFO mode to padding the LSBs with 0 */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_TX_FIFO_MODE), ++ 0); ++ ++ scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ } ++ else ++ { ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_TX_SAMPLE_BITS), ++ 0); ++ ++ /* Set TX FIFO mode to repeat the MSB */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ BIT(SUNXI_DAC_FIFOC_TX_FIFO_MODE), ++ BIT(SUNXI_DAC_FIFOC_TX_FIFO_MODE)); ++ ++ scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ } ++ ++ return 0; ++} ++ ++struct sample_rate ++{ ++ unsigned int samplerate; ++ unsigned int rate_bit; ++}; ++ ++static const struct sample_rate sample_rate_conv[] = { ++ {44100, 0}, ++ {48000, 0}, ++ {8000, 5}, ++ {32000, 1}, ++ {22050, 2}, ++ {24000, 2}, ++ {16000, 3}, ++ {11025, 4}, ++ {12000, 4}, ++ {192000, 6}, ++ {96000, 7}, ++}; ++ ++static int sun50i_h616_codec_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card); ++ unsigned long clk_freq; ++ int ret, hwrate; ++ int i; ++ ++ clk_freq = sun50i_h616_codec_get_mod_freq(params); ++ if (!clk_freq) ++ return -EINVAL; ++ ++ ret = clk_set_rate(scodec->clk_module, clk_freq * 2); ++ if (ret) ++ return ret; ++ ++ hwrate = sun50i_h616_codec_get_hw_rate(params); ++ if (hwrate < 0) ++ return hwrate; ++ ++ switch (params_format(params)) ++ { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ { ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x3 << SUNXI_DAC_FIFOC_TX_FIFO_MODE), ++ (0x3 << SUNXI_DAC_FIFOC_TX_FIFO_MODE)); ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x1 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS), ++ (0x0 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS)); ++ } ++ break; ++ case SNDRV_PCM_FORMAT_S24_LE: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ { ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x3 << SUNXI_DAC_FIFOC_TX_FIFO_MODE), ++ (0x0 << SUNXI_DAC_FIFOC_TX_FIFO_MODE)); ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x1 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS), ++ (0x1 << SUNXI_DAC_FIFOC_TX_SAMPLE_BITS)); ++ } ++ break; ++ default: ++ break; ++ } ++ ++ for (i = 0; i < ARRAY_SIZE(sample_rate_conv); i++) ++ { ++ if (sample_rate_conv[i].samplerate == params_rate(params)) ++ { ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ { ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x7 << SUNXI_DAC_FIFOC_DAC_FS), ++ (sample_rate_conv[i].rate_bit << SUNXI_DAC_FIFOC_DAC_FS)); ++ } ++ } ++ } ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ++ { ++ switch (params_channels(params)) ++ { ++ case 1: ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x1 << SUNXI_DAC_FIFOC_MONO_EN), ++ (0x1 << SUNXI_DAC_FIFOC_MONO_EN)); ++ break; ++ case 2: ++ regmap_update_bits(scodec->regmap, ++ SUNXI_DAC_FIFOC, ++ (0x1 << SUNXI_DAC_FIFOC_MONO_EN), ++ (0x0 << SUNXI_DAC_FIFOC_MONO_EN)); ++ break; ++ default: ++ pr_err("[%s] Playback cannot support %d channels.\n", ++ __func__, params_channels(params)); ++ return -EINVAL; ++ } ++ } ++ ++ return 0; ++} ++ ++static unsigned int sun50i_h616_codec_src_rates[] = { ++ 8000, 11025, 12000, 16000, 22050, 24000, 32000, ++ 44100, 48000, 96000, 192000}; ++ ++static struct snd_pcm_hw_constraint_list sun50i_h616_codec_constraints = { ++ .count = ARRAY_SIZE(sun50i_h616_codec_src_rates), ++ .list = sun50i_h616_codec_src_rates, ++}; ++ ++static int sun50i_h616_codec_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card); ++ ++ snd_pcm_hw_constraint_list(substream->runtime, 0, ++ SNDRV_PCM_HW_PARAM_RATE, &sun50i_h616_codec_constraints); ++ ++ /* ++ * Stop issuing DRQ when we have room for less than 16 samples ++ * in our TX FIFO ++ */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_FIFOC, ++ 3 << SUNXI_DAC_FIFOC_DRQ_CLR_CNT, ++ 3 << SUNXI_DAC_FIFOC_DRQ_CLR_CNT); ++ ++ return clk_prepare_enable(scodec->clk_module); ++} ++ ++static void sun50i_h616_codec_shutdown(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(rtd->card); ++ ++ clk_disable_unprepare(scodec->clk_module); ++} ++ ++static const struct snd_soc_dai_ops sun50i_h616_codec_dai_ops = { ++ .startup = sun50i_h616_codec_startup, ++ .shutdown = sun50i_h616_codec_shutdown, ++ .trigger = sun50i_h616_codec_trigger, ++ .hw_params = sun50i_h616_codec_hw_params, ++ .prepare = sun50i_h616_codec_prepare, ++}; ++ ++static struct snd_soc_dai_driver sun50i_h616_codec_dai = { ++ .name = "Codec", ++ .ops = &sun50i_h616_codec_dai_ops, ++ .playback = { ++ .stream_name = "Codec Playback", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rate_min = 8000, ++ .rate_max = 192000, ++ .rates = SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S24_LE, ++ .sig_bits = 24, ++ }, ++}; ++ ++static int sunxi_lineout_event(struct snd_soc_dapm_widget *w, ++ struct snd_kcontrol *k, int event) ++{ ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card); ++ ++ switch (event) ++ { ++ case SND_SOC_DAPM_POST_PMU: ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG, ++ (0x1 << SUNXI_RDEN), (0x1 << SUNXI_RDEN)); ++ msleep(25); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_LINEOUTL_EN) | (0x1 << SUNXI_LINEOUTR_EN), ++ (0x1 << SUNXI_LINEOUTL_EN) | (0x1 << SUNXI_LINEOUTR_EN)); ++ break; ++ case SND_SOC_DAPM_PRE_PMD: ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG, ++ (0x1 << SUNXI_RDEN), (0x0 << SUNXI_RDEN)); ++ msleep(25); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_LINEOUTL_EN) | (0x1 << SUNXI_LINEOUTR_EN), ++ (0x0 << SUNXI_LINEOUTL_EN) | (0x0 << SUNXI_LINEOUTR_EN)); ++ ++ break; ++ default: ++ break; ++ } ++ ++ return 0; ++} ++ ++static const DECLARE_TLV_DB_SCALE(digital_tlv, 0, -116, -7424); ++static const DECLARE_TLV_DB_SCALE(linein_to_l_r_mix_vol_tlv, -450, 150, 0); ++static const DECLARE_TLV_DB_SCALE(fmin_to_l_r_mix_vol_tlv, -450, 150, 0); ++ ++static const unsigned int lineout_tlv[] = { ++ TLV_DB_RANGE_HEAD(2), ++ 0, ++ 0, ++ TLV_DB_SCALE_ITEM(0, 0, 1), ++ 1, ++ 31, ++ TLV_DB_SCALE_ITEM(-4350, 150, 1), ++}; ++ ++/*lineoutL mux select */ ++const char *const left_lineoutl_text[] = { ++ "LOMixer", ++ "LROMixer", ++}; ++ ++static const struct soc_enum left_lineout_enum = ++ SOC_ENUM_SINGLE(SUNXI_DAC_AC_DAC_REG, SUNXI_LINEOUTL_SEL, ++ ARRAY_SIZE(left_lineoutl_text), left_lineoutl_text); ++ ++static const struct snd_kcontrol_new left_lineout_mux = ++ SOC_DAPM_ENUM("Left LINEOUT Mux", left_lineout_enum); ++ ++/*lineoutR mux select */ ++const char *const right_lineoutr_text[] = { ++ "ROMixer", ++ "LROMixer", ++}; ++ ++static const struct soc_enum right_lineout_enum = ++ SOC_ENUM_SINGLE(SUNXI_DAC_AC_DAC_REG, SUNXI_LINEOUTR_SEL, ++ ARRAY_SIZE(right_lineoutr_text), right_lineoutr_text); ++ ++static const struct snd_kcontrol_new right_lineout_mux = ++ SOC_DAPM_ENUM("Right LINEOUT Mux", right_lineout_enum); ++ ++static const struct snd_kcontrol_new sun50i_h616_codec_codec_controls[] = { ++ ++ SOC_SINGLE_TLV("digital volume", SUNXI_DAC_DPC, ++ SUNXI_DAC_DPC_DVOL, 0x3F, 0, digital_tlv), ++ ++ SOC_SINGLE_TLV("LINEOUT volume", SUNXI_DAC_AC_DAC_REG, ++ SUNXI_LINEOUT_VOL, 0x1F, 0, lineout_tlv), ++}; ++ ++static const struct snd_kcontrol_new left_output_mixer[] = { ++ SOC_DAPM_SINGLE("DACL Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_LMIX_LDAC, 1, 0), ++ SOC_DAPM_SINGLE("DACR Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_LMIX_RDAC, 1, 0), ++}; ++ ++static const struct snd_kcontrol_new right_output_mixer[] = { ++ SOC_DAPM_SINGLE("DACL Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_RMIX_LDAC, 1, 0), ++ SOC_DAPM_SINGLE("DACR Switch", SUNXI_DAC_AC_MIXER_REG, SUNXI_RMIX_RDAC, 1, 0), ++}; ++ ++static const struct snd_soc_dapm_widget sun50i_h616_codec_codec_widgets[] = { ++ ++ /* Digital parts of the DACs */ ++ SND_SOC_DAPM_SUPPLY("DAC Enable", SUNXI_DAC_DPC, ++ SUNXI_DAC_DPC_EN_DA, 0, NULL, 0), ++ ++ SND_SOC_DAPM_AIF_IN_E("DACL", "Codec Playback", 0, SUNXI_DAC_AC_DAC_REG, SUNXI_DAC_LEN, 0, ++ NULL, 0), ++ SND_SOC_DAPM_AIF_IN_E("DACR", "Codec Playback", 0, SUNXI_DAC_AC_DAC_REG, SUNXI_DAC_REN, 0, ++ NULL, 0), ++ ++ SND_SOC_DAPM_MIXER("Left Output Mixer", SUNXI_DAC_AC_MIXER_REG, SUNXI_LMIXEN, 0, ++ left_output_mixer, ARRAY_SIZE(left_output_mixer)), ++ SND_SOC_DAPM_MIXER("Right Output Mixer", SUNXI_DAC_AC_MIXER_REG, SUNXI_RMIXEN, 0, ++ right_output_mixer, ARRAY_SIZE(right_output_mixer)), ++ ++ SND_SOC_DAPM_MUX("Left LINEOUT Mux", SND_SOC_NOPM, ++ 0, 0, &left_lineout_mux), ++ SND_SOC_DAPM_MUX("Right LINEOUT Mux", SND_SOC_NOPM, ++ 0, 0, &right_lineout_mux), ++ ++ SND_SOC_DAPM_OUTPUT("LINEOUTL"), ++ SND_SOC_DAPM_OUTPUT("LINEOUTR"), ++ ++ SND_SOC_DAPM_LINE("LINEOUT", sunxi_lineout_event), ++}; ++ ++static const struct snd_soc_component_driver sun50i_h616_codec_codec = { ++ .controls = sun50i_h616_codec_codec_controls, ++ .num_controls = ARRAY_SIZE(sun50i_h616_codec_codec_controls), ++ .dapm_widgets = sun50i_h616_codec_codec_widgets, ++ .num_dapm_widgets = ARRAY_SIZE(sun50i_h616_codec_codec_widgets), ++ .idle_bias_on = 1, ++ .use_pmdown_time = 1, ++ .endianness = 1, ++}; ++ ++static const struct snd_soc_component_driver sun50i_h616_codec_component = { ++ .name = "sun50i_h616-codec", ++ .legacy_dai_naming = 1, ++#ifdef CONFIG_DEBUG_FS ++ .debugfs_prefix = "cpu", ++#endif ++}; ++ ++#define SUN50IW9_CODEC_RATES (SNDRV_PCM_RATE_8000_192000 | SNDRV_PCM_RATE_KNOT) ++#define SUN50IW9_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S24_LE) ++ ++static int sun50i_h616_codec_dai_probe(struct snd_soc_dai *dai) ++{ ++ struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(card); ++ ++ snd_soc_dai_init_dma_data(dai, &scodec->playback_dma_data, ++ NULL); ++ ++ return 0; ++} ++ ++static struct snd_soc_dai_driver dummy_cpu_dai = { ++ .name = "sun50i_h616-codec-cpu-dai", ++ .probe = sun50i_h616_codec_dai_probe, ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = SUN50IW9_CODEC_RATES, ++ .formats = SUN50IW9_CODEC_FORMATS, ++ .sig_bits = 24, ++ }, ++}; ++ ++static struct snd_soc_dai_link *sun50i_h616_codec_create_link(struct device *dev, ++ int *num_links) ++{ ++ struct snd_soc_dai_link *link = devm_kzalloc(dev, sizeof(*link), ++ GFP_KERNEL); ++ struct snd_soc_dai_link_component *dlc = devm_kzalloc(dev, ++ 3 * sizeof(*dlc), GFP_KERNEL); ++ if (!link || !dlc) ++ return NULL; ++ ++ link->cpus = &dlc[0]; ++ link->codecs = &dlc[1]; ++ link->platforms = &dlc[2]; ++ ++ link->num_cpus = 1; ++ link->num_codecs = 1; ++ link->num_platforms = 1; ++ ++ link->name = "cdc"; ++ link->stream_name = "CDC PCM"; ++ link->codecs->dai_name = "Codec"; ++ link->cpus->dai_name = dev_name(dev); ++ link->codecs->name = dev_name(dev); ++ link->platforms->name = dev_name(dev); ++ link->dai_fmt = SND_SOC_DAIFMT_I2S; ++ link->playback_only = true; ++ link->capture_only = false; ++ ++ *num_links = 1; ++ ++ return link; ++}; ++ ++static int sun50i_h616_codec_spk_event(struct snd_soc_dapm_widget *w, ++ struct snd_kcontrol *k, int event) ++{ ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(w->dapm->card); ++ ++ gpiod_set_value_cansleep(scodec->gpio_pa, ++ !!SND_SOC_DAPM_EVENT_ON(event)); ++ ++ if (SND_SOC_DAPM_EVENT_ON(event)) ++ { ++ /* ++ * Need a delay to wait for DAC to push the data. 700ms seems ++ * to be the best compromise not to feel this delay while ++ * playing a sound. ++ */ ++ msleep(700); ++ } ++ ++ return 0; ++} ++ ++static const struct snd_soc_dapm_widget sun6i_codec_card_dapm_widgets[] = { ++ SND_SOC_DAPM_LINE("Line Out", NULL), ++ SND_SOC_DAPM_SPK("Speaker", sun50i_h616_codec_spk_event), ++}; ++ ++/* Connect digital side enables to analog side widgets */ ++static const struct snd_soc_dapm_route sun8i_codec_card_routes[] = { ++ /* DAC Routes */ ++ {"DACR", NULL, "DAC Enable"}, ++ {"DACL", NULL, "DAC Enable"}, ++ ++ {"Left Output Mixer", "DACR Switch", "DACR"}, ++ {"Left Output Mixer", "DACL Switch", "DACL"}, ++ ++ {"Right Output Mixer", "DACL Switch", "DACL"}, ++ {"Right Output Mixer", "DACR Switch", "DACR"}, ++ ++ {"Left LINEOUT Mux", "LOMixer", "Left Output Mixer"}, ++ {"Left LINEOUT Mux", "LROMixer", "Right Output Mixer"}, ++ {"Right LINEOUT Mux", "ROMixer", "Right Output Mixer"}, ++ {"Right LINEOUT Mux", "LROMixer", "Left Output Mixer"}, ++ ++ {"LINEOUTL", NULL, "Left LINEOUT Mux"}, ++ {"LINEOUTR", NULL, "Right LINEOUT Mux"}, ++ ++ {"LINEOUT", NULL, "LINEOUTL"}, ++ {"LINEOUT", NULL, "LINEOUTR"}, ++ ++ {"Speaker", NULL, "LINEOUTL"}, ++ {"Speaker", NULL, "LINEOUTR"}, ++}; ++ ++static const struct snd_kcontrol_new sunxi_card_controls[] = { ++ SOC_DAPM_PIN_SWITCH("LINEOUT"), ++}; ++ ++static struct snd_soc_card *sun50i_h616_codec_create_card(struct device *dev) ++{ ++ struct snd_soc_card *card; ++ int ret; ++ ++ card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL); ++ if (!card) ++ return ERR_PTR(-ENOMEM); ++ ++ card->dai_link = sun50i_h616_codec_create_link(dev, &card->num_links); ++ if (!card->dai_link) ++ return ERR_PTR(-ENOMEM); ++ ++ card->dev = dev; ++ card->owner = THIS_MODULE; ++ card->name = "audiocodec"; ++ card->controls = sunxi_card_controls; ++ card->num_controls = ARRAY_SIZE(sunxi_card_controls), ++ card->dapm_widgets = sun6i_codec_card_dapm_widgets; ++ card->num_dapm_widgets = ARRAY_SIZE(sun6i_codec_card_dapm_widgets); ++ card->dapm_routes = sun8i_codec_card_routes; ++ card->num_dapm_routes = ARRAY_SIZE(sun8i_codec_card_routes); ++ card->fully_routed = true; ++ ++ ret = snd_soc_of_parse_audio_routing(card, "allwinner,audio-routing"); ++ if (ret) ++ dev_warn(dev, "failed to parse audio-routing: %d\n", ret); ++ ++ return card; ++}; ++ ++static const struct regmap_config sun50i_h616_codec_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = SUNXI_DAC_AC_RAMP_REG, ++ .cache_type = REGCACHE_NONE, ++}; ++ ++struct sun50i_h616_codec_quirks ++{ ++ const struct regmap_config *regmap_config; ++ const struct snd_soc_component_driver *codec; ++ struct snd_soc_card *(*create_card)(struct device *dev); ++ struct reg_field reg_adc_fifoc; /* used for regmap_field */ ++ unsigned int reg_dac_txdata; /* TX FIFO offset for DMA config */ ++ unsigned int reg_adc_rxdata; /* RX FIFO offset for DMA config */ ++ bool has_reset; ++}; ++ ++static const struct sun50i_h616_codec_quirks sun50i_h616_codec_quirks = { ++ .regmap_config = &sun50i_h616_codec_regmap_config, ++ .codec = &sun50i_h616_codec_codec, ++ .create_card = sun50i_h616_codec_create_card, ++ .reg_dac_txdata = SUNXI_DAC_TXDATA, ++ .has_reset = true, ++}; ++ ++static const struct of_device_id sun50i_h616_codec_of_match[] = { ++ { ++ .compatible = "allwinner,sun50i-h616-codec", ++ .data = &sun50i_h616_codec_quirks, ++ }, ++ {}}; ++MODULE_DEVICE_TABLE(of, sun50i_h616_codec_of_match); ++ ++static ssize_t show_audio_reg(struct device *dev, ++ struct device_attribute *attr, char *buf) ++{ ++ int count = 0, i = 0; ++ unsigned int reg_val; ++ unsigned int size = ARRAY_SIZE(reg_labels); ++ ++ count += sprintf(buf, "dump audiocodec reg:\n"); ++ ++ while ((i < size) && (reg_labels[i].name != NULL)) ++ { ++ regmap_read(codec_regmap_debug, ++ reg_labels[i].address, ®_val); ++ count += sprintf(buf + count, "%-20s [0x%03x]: 0x%-10x save_val:0x%x\n", ++ reg_labels[i].name, (reg_labels[i].address), ++ reg_val, reg_labels[i].value); ++ i++; ++ } ++ ++ return count; ++} ++ ++static DEVICE_ATTR(audio_reg, 0644, show_audio_reg, NULL); ++ ++static struct attribute *audio_debug_attrs[] = { ++ &dev_attr_audio_reg.attr, ++ NULL, ++}; ++ ++static struct attribute_group audio_debug_attr_group = { ++ .name = "audio_reg_debug", ++ .attrs = audio_debug_attrs, ++}; ++ ++static void sunxi_codec_init(struct sun50i_h616_codec *scodec) ++{ ++ /* Disable DRC function for playback */ ++ regmap_write(scodec->regmap, SUNXI_DAC_DAP_CTL, 0); ++ ++ /* Enable HPF(high passed filter) */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_DPC, ++ (0x1 << SUNXI_DAC_DPC_HPF_EN), (0x1 << SUNXI_DAC_DPC_HPF_EN)); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1f << SUNXI_LINEOUT_VOL), ++ (0x1a << SUNXI_LINEOUT_VOL)); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_DPC, ++ (0x3f << SUNXI_DAC_DPC_DVOL), (0 << SUNXI_DAC_DPC_DVOL)); ++ ++ /* Mixer to channel LINEOUT MUTE control init */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_LMUTE), (0x1 << SUNXI_LMUTE)); ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_RMUTE), (0x1 << SUNXI_RMUTE)); ++ ++ /* ramp func about */ ++ if (0) ++ { ++ /* Not used the ramp func cause there is the MUTE to avoid pop noise */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_RSWITCH), (0x1 << SUNXI_RSWITCH)); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_RAMPEN), (0x0 << SUNXI_RAMPEN)); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG, ++ (0x7 << SUNXI_RAMP_STEP), (0x0 << SUNXI_RAMP_STEP)); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG, ++ (0x1 << SUNXI_RDEN), (0x0 << SUNXI_RDEN)); ++ } ++ else ++ { ++ /* If no MUTE to avoid pop, just use the ramp func to avoid it */ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_RSWITCH), (0x0 << SUNXI_RSWITCH)); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_DAC_REG, ++ (0x1 << SUNXI_RAMPEN), (0x1 << SUNXI_RAMPEN)); ++ ++ regmap_update_bits(scodec->regmap, SUNXI_DAC_AC_RAMP_REG, ++ (0x7 << SUNXI_RAMP_STEP), (0x1 << SUNXI_RAMP_STEP)); ++ } ++} ++ ++static int sun50i_h616_codec_probe(struct platform_device *pdev) ++{ ++ struct snd_soc_card *card; ++ struct sun50i_h616_codec *scodec; ++ const struct sun50i_h616_codec_quirks *quirks; ++ struct resource *res; ++ void __iomem *base; ++ int ret; ++ ++ scodec = devm_kzalloc(&pdev->dev, sizeof(struct sun50i_h616_codec), GFP_KERNEL); ++ if (!scodec) ++ return -ENOMEM; ++ ++ scodec->dev = &pdev->dev; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ base = devm_ioremap_resource(&pdev->dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ quirks = of_device_get_match_data(&pdev->dev); ++ if (quirks == NULL) ++ { ++ dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); ++ return -ENODEV; ++ } ++ ++ scodec->regmap = devm_regmap_init_mmio(&pdev->dev, base, ++ quirks->regmap_config); ++ if (IS_ERR(scodec->regmap)) ++ { ++ dev_err(&pdev->dev, "Failed to create our regmap\n"); ++ return PTR_ERR(scodec->regmap); ++ } ++ ++ /* Get the clocks from the DT */ ++ scodec->clk_apb = devm_clk_get(&pdev->dev, "apb"); ++ if (IS_ERR(scodec->clk_apb)) ++ { ++ dev_err(&pdev->dev, "Failed to get the APB clock\n"); ++ return PTR_ERR(scodec->clk_apb); ++ } ++ ++ scodec->clk_module = devm_clk_get(&pdev->dev, "audio-codec-1x"); ++ if (IS_ERR(scodec->clk_module)) ++ { ++ dev_err(&pdev->dev, "Failed to get the codec module clock\n"); ++ return PTR_ERR(scodec->clk_module); ++ } ++ ++ if (quirks->has_reset) ++ { ++ scodec->rst = devm_reset_control_get_exclusive(&pdev->dev, ++ NULL); ++ if (IS_ERR(scodec->rst)) ++ { ++ dev_err(&pdev->dev, "Failed to get reset control\n"); ++ return PTR_ERR(scodec->rst); ++ } ++ } ++ ++ scodec->gpio_pa = devm_gpiod_get_optional(&pdev->dev, "allwinner,pa", ++ GPIOD_OUT_LOW); ++ if (IS_ERR(scodec->gpio_pa)) ++ { ++ ret = PTR_ERR(scodec->gpio_pa); ++ if (ret != -EPROBE_DEFER) ++ dev_err(&pdev->dev, "Failed to get pa gpio: %d\n", ret); ++ return ret; ++ } ++ ++ /* Enable the bus clock */ ++ if (clk_prepare_enable(scodec->clk_apb)) ++ { ++ dev_err(&pdev->dev, "Failed to enable the APB clock\n"); ++ return -EINVAL; ++ } ++ ++ /* Deassert the reset control */ ++ if (scodec->rst) ++ { ++ ret = reset_control_deassert(scodec->rst); ++ if (ret) ++ { ++ dev_err(&pdev->dev, ++ "Failed to deassert the reset control\n"); ++ goto err_clk_disable; ++ } ++ } ++ ++ /* DMA configuration for TX FIFO */ ++ scodec->playback_dma_data.addr = res->start + quirks->reg_dac_txdata; ++ scodec->playback_dma_data.maxburst = 8; ++ scodec->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ ++ ret = devm_snd_soc_register_component(&pdev->dev, quirks->codec, ++ &sun50i_h616_codec_dai, 1); ++ if (ret) ++ { ++ dev_err(&pdev->dev, "Failed to register our codec\n"); ++ goto err_assert_reset; ++ } ++ ++ ret = devm_snd_soc_register_component(&pdev->dev, ++ &sun50i_h616_codec_component, ++ &dummy_cpu_dai, 1); ++ if (ret) ++ { ++ dev_err(&pdev->dev, "Failed to register our DAI\n"); ++ goto err_assert_reset; ++ } ++ ++ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); ++ if (ret) ++ { ++ dev_err(&pdev->dev, "Failed to register against DMAEngine\n"); ++ goto err_assert_reset; ++ } ++ ++ card = quirks->create_card(&pdev->dev); ++ if (IS_ERR(card)) ++ { ++ ret = PTR_ERR(card); ++ dev_err(&pdev->dev, "Failed to create our card\n"); ++ goto err_assert_reset; ++ } ++ ++ snd_soc_card_set_drvdata(card, scodec); ++ ++ codec_regmap_debug = scodec->regmap; ++ ++ ret = snd_soc_register_card(card); ++ if (ret) ++ { ++ dev_err(&pdev->dev, "Failed to register our card\n"); ++ goto err_assert_reset; ++ } ++ ++ ret = sysfs_create_group(&pdev->dev.kobj, &audio_debug_attr_group); ++ if (ret) ++ dev_warn(&pdev->dev, "failed to create attr group\n"); ++ ++ sunxi_codec_init(scodec); ++ ++ return 0; ++ ++err_assert_reset: ++ if (scodec->rst) ++ reset_control_assert(scodec->rst); ++err_clk_disable: ++ clk_disable_unprepare(scodec->clk_apb); ++ return ret; ++} ++ ++static int sun50i_h616_codec_remove(struct platform_device *pdev) ++{ ++ struct snd_soc_card *card = platform_get_drvdata(pdev); ++ struct sun50i_h616_codec *scodec = snd_soc_card_get_drvdata(card); ++ ++ snd_soc_unregister_card(card); ++ if (scodec->rst) ++ reset_control_assert(scodec->rst); ++ clk_disable_unprepare(scodec->clk_apb); ++ ++ return 0; ++} ++ ++static struct platform_driver sun50i_h616_codec_driver = { ++ .driver = { ++ .name = "sun50i-h616-codec", ++ .of_match_table = sun50i_h616_codec_of_match, ++ }, ++ .probe = sun50i_h616_codec_probe, ++ .remove = sun50i_h616_codec_remove, ++}; ++module_platform_driver(sun50i_h616_codec_driver); ++ ++MODULE_DESCRIPTION("Allwinner H616 codec driver"); ++MODULE_AUTHOR("Emilio López "); ++MODULE_AUTHOR("Jon Smirl "); ++MODULE_AUTHOR("Maxime Ripard "); ++MODULE_AUTHOR("Chen-Yu Tsai "); ++MODULE_AUTHOR("Leeboby "); ++MODULE_LICENSE("GPL"); +diff --git a/sound/soc/sunxi_v2/Kconfig b/sound/soc/sunxi_v2/Kconfig +new file mode 100644 +index 000000000..37fc579ba +--- /dev/null ++++ b/sound/soc/sunxi_v2/Kconfig +@@ -0,0 +1,48 @@ ++# common ++config SND_SOC_SUNXI_MACH ++ tristate ++ ++# ahub dam ++config SND_SOC_SUNXI_AHUB_DAM ++ tristate ++ ++config SND_SOC_SUNXI_INTERNALCODEC ++ tristate ++ ++config SND_SOC_SUNXI_SUN50IW9_CODEC ++ tristate ++ ++# menu select ++menu "Allwinner SoC Audio support V2" ++ depends on ARCH_SUNXI ++ ++# aaudio ++config SND_SOC_SUNXI_AAUDIO ++ tristate "Allwinner AAUDIO support" ++ select REGMAP_MMIO ++ select SND_SOC_GENERIC_DMAENGINE_PCM ++ select SND_SOC_SUNXI_MACH ++ select SND_SOC_SUNXI_INTERNALCODEC ++ select SND_SOC_SUNXI_SUN50IW9_CODEC ++ depends on ARCH_SUNXI ++ help ++ Select Y or M to support analog-audio Module in the Allwinner SoCs. ++ ++# ahub ++config SND_SOC_SUNXI_AHUB ++ tristate "Allwinner AHUB Support" ++ select REGMAP_MMIO ++ select SND_SOC_GENERIC_DMAENGINE_PCM ++ select SND_SOC_SUNXI_MACH ++ select SND_SOC_SUNXI_AHUB_DAM ++ depends on ARCH_SUNXI ++ help ++ Select Y or M to support audio-hub Module in Allwinner SoCs. ++ ++config SND_SOC_SUNXI_DEBUG ++ tristate "Components Debug" ++ depends on SND_SOC_SUNXI_COMPONENTS ++ help ++ Select Y or M to support debug components. ++ ++endmenu +diff --git a/sound/soc/sunxi_v2/Makefile b/sound/soc/sunxi_v2/Makefile +new file mode 100644 +index 000000000..c7c2ef8f9 +--- /dev/null ++++ b/sound/soc/sunxi_v2/Makefile +@@ -0,0 +1,11 @@ ++# platform -> ahub ++snd_soc_sunxi_ahub_dam-objs += snd_sunxi_ahub_dam.o ++obj-$(CONFIG_SND_SOC_SUNXI_AHUB_DAM) += snd_soc_sunxi_ahub_dam.o ++ ++snd_soc_sunxi_ahub-objs += snd_sunxi_ahub.o ++obj-$(CONFIG_SND_SOC_SUNXI_AHUB) += snd_soc_sunxi_ahub.o ++ ++# common -> machine (note: Finally compile, save system startup time) ++snd_soc_sunxi_machine-objs += snd_sunxi_mach.o ++snd_soc_sunxi_machine-objs += snd_sunxi_mach_utils.o ++obj-$(CONFIG_SND_SOC_SUNXI_MACH) += snd_soc_sunxi_machine.o +diff --git a/sound/soc/sunxi_v2/drv_hdmi.h b/sound/soc/sunxi_v2/drv_hdmi.h +new file mode 100644 +index 000000000..2e05489b0 +--- /dev/null ++++ b/sound/soc/sunxi_v2/drv_hdmi.h +@@ -0,0 +1,63 @@ ++/* ++ * Allwinner SoCs hdmi driver. ++ * ++ * Copyright (C) 2016 Allwinner. ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++#ifndef __DRV_HDMI_H__ ++#define __DRV_HDMI_H__ ++ ++typedef struct { ++ __u8 hw_intf; /* 0:iis 1:spdif 2:pcm */ ++ __u16 fs_between; /* fs */ ++ __u32 sample_rate; /*sample rate*/ ++ __u8 clk_edge; /* 0:*/ ++ __u8 ch0_en; /* 1 */ ++ __u8 ch1_en; /* 0 */ ++ __u8 ch2_en; /* 0 */ ++ __u8 ch3_en; /* 0 */ ++ __u8 word_length; /* 32 */ ++ __u8 shift_ctl; /* 0 */ ++ __u8 dir_ctl; /* 0 */ ++ __u8 ws_pol; ++ __u8 just_pol; ++ __u8 channel_num; ++ __u8 data_raw; ++ __u8 sample_bit; ++ __u8 ca; /* channel allocation */ ++} hdmi_audio_t; ++ ++typedef struct { ++ __s32 (*hdmi_audio_enable)(__u8 mode, __u8 channel); ++ __s32 (*hdmi_set_audio_para)(hdmi_audio_t *audio_para); ++ __s32 (*hdmi_is_playback)(void); ++} __audio_hdmi_func; ++ ++enum hdmi_hpd_status { ++ STATUE_CLOSE = 0, ++ STATUE_OPEN = 1, ++}; ++ ++void audio_set_hdmi_func(__audio_hdmi_func *hdmi_func); ++#if defined(CONFIG_SND_SUNXI_SOC_AUDIOHUB_INTERFACE) ++void audio_set_muti_hdmi_func(__audio_hdmi_func *hdmi_func); ++#endif ++ ++/******************** SND_HDMI for sunxi_v2 begain ***************************/ ++#if IS_ENABLED(CONFIG_HDMI2_DISP2_SUNXI) ++extern int snd_hdmi_get_func(__audio_hdmi_func *hdmi_func); ++#else ++static inline int snd_hdmi_get_func(__audio_hdmi_func *hdmi_func) ++{ ++ pr_err("HDMI Audio API is disable\n"); ++ ++ return -1; ++} ++#endif ++/******************** SND_HDMI for sunxi_v2 end ******************************/ ++ ++#endif +diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub.c b/sound/soc/sunxi_v2/snd_sunxi_ahub.c +new file mode 100644 +index 000000000..8a1065e91 +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub.c +@@ -0,0 +1,1477 @@ ++/* ++ * sound\soc\sunxi\snd_sunxi_ahub.c ++ * (C) Copyright 2021-2025 ++ * AllWinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "snd_sunxi_log.h" ++#include "snd_sunxi_ahub.h" ++ ++#define HLOG "AHUB" ++#define DRV_NAME "sunxi-snd-plat-ahub" ++ ++static int sunxi_ahub_dai_startup(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int apb_num, tdm_num; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ regmap = ahub_info->mem_info.regmap; ++ apb_num = ahub_info->dts_info.apb_num; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ snd_soc_dai_set_dma_data(dai, substream, ++ &ahub_info->playback_dma_param); ++ } else { ++ snd_soc_dai_set_dma_data(dai, substream, ++ &ahub_info->capture_dma_param); ++ } ++ ++ /* APBIF & I2S of RST and GAT */ ++ if (tdm_num > 3 || apb_num > 2) { ++ SND_LOG_ERR(HLOG, "unspport tdm num or apbif num\n"); ++ return -EINVAL; ++ } ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ regmap_update_bits(regmap, SUNXI_AHUB_RST, ++ 0x1 << (APBIF_TXDIF0_RST - apb_num), ++ 0x1 << (APBIF_TXDIF0_RST - apb_num)); ++ regmap_update_bits(regmap, SUNXI_AHUB_GAT, ++ 0x1 << (APBIF_TXDIF0_GAT - apb_num), ++ 0x1 << (APBIF_TXDIF0_GAT - apb_num)); ++ } else { ++ regmap_update_bits(regmap, SUNXI_AHUB_RST, ++ 0x1 << (APBIF_RXDIF0_RST - apb_num), ++ 0x1 << (APBIF_RXDIF0_RST - apb_num)); ++ regmap_update_bits(regmap, SUNXI_AHUB_GAT, ++ 0x1 << (APBIF_RXDIF0_GAT - apb_num), ++ 0x1 << (APBIF_RXDIF0_GAT - apb_num)); ++ } ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_set_pll(struct snd_soc_dai *dai, ++ int pll_id, int source, ++ unsigned int freq_in, unsigned int freq_out) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct sunxi_ahub_clk_info *clk_info = NULL; ++ ++ SND_LOG_DEBUG(HLOG, "stream -> %s, freq_in ->%u, freq_out ->%u\n", ++ pll_id ? "IN" : "OUT", freq_in, freq_out); ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null.\n"); ++ return -ENOMEM; ++ } ++ clk_info = &ahub_info->clk_info; ++ ++ if (freq_in > 24576000) { ++ //if (clk_set_parent(clk_info->clk_module, clk_info->clk_pllx4)) { ++ // SND_LOG_ERR(HLOG, "set parent of clk_module to pllx4 failed\n"); ++ // return -EINVAL; ++ //} ++ ++ if (clk_set_rate(clk_info->clk_pll, freq_in)) { ++ SND_LOG_ERR(HLOG, "freq : %u pllx4 clk unsupport\n", freq_in); ++ return -EINVAL; ++ } ++ } else { ++ //if (clk_set_parent(clk_info->clk_module, clk_info->clk_pll)) { ++ // SND_LOG_ERR(HLOG, "set parent of clk_module to pll failed\n"); ++ // return -EINVAL; ++ //} ++ if (clk_set_rate(clk_info->clk_pll, freq_in)) { ++ SND_LOG_ERR(HLOG, "freq : %u pll clk unsupport\n", freq_in); ++ return -EINVAL; ++ } ++ } ++ if (clk_set_rate(clk_info->clk_module, freq_out / 2)) { ++ SND_LOG_ERR(HLOG, "freq : %u module clk unsupport\n", freq_out); ++ return -EINVAL; ++ } ++ ++ ahub_info->pllclk_freq = freq_in; ++ ahub_info->mclk_freq = freq_out; ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id, ++ unsigned int freq, int dir) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int tdm_num; ++ unsigned int mclk_ratio, mclk_ratio_map; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null.\n"); ++ return -ENOMEM; ++ } ++ regmap = ahub_info->mem_info.regmap; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ ++ if (freq == 0) { ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num), ++ 0x1 << I2S_CLKD_MCLK, 0x0 << I2S_CLKD_MCLK); ++ SND_LOG_DEBUG(HLOG, "mclk freq: 0\n"); ++ return 0; ++ } ++ if (ahub_info->pllclk_freq == 0) { ++ SND_LOG_ERR(HLOG, "pllclk freq is invalid\n"); ++ return -ENOMEM; ++ } ++ mclk_ratio = ahub_info->pllclk_freq / freq; ++ ++ switch (mclk_ratio) { ++ case 1: ++ mclk_ratio_map = 1; ++ break; ++ case 2: ++ mclk_ratio_map = 2; ++ break; ++ case 4: ++ mclk_ratio_map = 3; ++ break; ++ case 6: ++ mclk_ratio_map = 4; ++ break; ++ case 8: ++ mclk_ratio_map = 5; ++ break; ++ case 12: ++ mclk_ratio_map = 6; ++ break; ++ case 16: ++ mclk_ratio_map = 7; ++ break; ++ case 24: ++ mclk_ratio_map = 8; ++ break; ++ case 32: ++ mclk_ratio_map = 9; ++ break; ++ case 48: ++ mclk_ratio_map = 10; ++ break; ++ case 64: ++ mclk_ratio_map = 11; ++ break; ++ case 96: ++ mclk_ratio_map = 12; ++ break; ++ case 128: ++ mclk_ratio_map = 13; ++ break; ++ case 176: ++ mclk_ratio_map = 14; ++ break; ++ case 192: ++ mclk_ratio_map = 15; ++ break; ++ default: ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num), ++ 0x1 << I2S_CLKD_MCLK, 0x0 << I2S_CLKD_MCLK); ++ SND_LOG_ERR(HLOG, "mclk freq div unsupport\n"); ++ return -EINVAL; ++ } ++ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num), ++ 0xf << I2S_CLKD_MCLKDIV, ++ mclk_ratio_map << I2S_CLKD_MCLKDIV); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num), ++ 0x1 << I2S_CLKD_MCLK, 0x1 << I2S_CLKD_MCLK); ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int tdm_num; ++ unsigned int bclk_ratio; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null.\n"); ++ return -ENOMEM; ++ } ++ regmap = ahub_info->mem_info.regmap; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ ++ /* ratio -> cpudai pllclk / pcm rate */ ++ switch (ratio) { ++ case 1: ++ bclk_ratio = 1; ++ break; ++ case 2: ++ bclk_ratio = 2; ++ break; ++ case 4: ++ bclk_ratio = 3; ++ break; ++ case 6: ++ bclk_ratio = 4; ++ break; ++ case 8: ++ bclk_ratio = 5; ++ break; ++ case 12: ++ bclk_ratio = 6; ++ break; ++ case 16: ++ bclk_ratio = 7; ++ break; ++ case 24: ++ bclk_ratio = 8; ++ break; ++ case 32: ++ bclk_ratio = 9; ++ break; ++ case 48: ++ bclk_ratio = 10; ++ break; ++ case 64: ++ bclk_ratio = 11; ++ break; ++ case 96: ++ bclk_ratio = 12; ++ break; ++ case 128: ++ bclk_ratio = 13; ++ break; ++ case 176: ++ bclk_ratio = 14; ++ break; ++ case 192: ++ bclk_ratio = 15; ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "bclk freq div unsupport\n"); ++ return -EINVAL; ++ } ++ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num), ++ 0xf << I2S_CLKD_BCLKDIV, ++ (bclk_ratio - 2) << I2S_CLKD_BCLKDIV); ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int tdm_num, tx_pin, rx_pin; ++ unsigned int mode, offset; ++ unsigned int lrck_polarity, brck_polarity; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ ahub_info->fmt = fmt; ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null.\n"); ++ return -ENOMEM; ++ } ++ regmap = ahub_info->mem_info.regmap; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ tx_pin = ahub_info->dts_info.tx_pin; ++ rx_pin = ahub_info->dts_info.rx_pin; ++ ++ /* set TDM format */ ++ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ mode = 1; ++ offset = 1; ++ break; ++ case SND_SOC_DAIFMT_RIGHT_J: ++ mode = 2; ++ offset = 0; ++ break; ++ case SND_SOC_DAIFMT_LEFT_J: ++ mode = 1; ++ offset = 0; ++ break; ++ case SND_SOC_DAIFMT_DSP_A: ++ mode = 0; ++ offset = 1; ++ /* L data MSB after FRM LRC (short frame) */ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x1 << I2S_FMT0_LRCK_WIDTH, ++ 0x0 << I2S_FMT0_LRCK_WIDTH); ++ break; ++ case SND_SOC_DAIFMT_DSP_B: ++ mode = 0; ++ offset = 0; ++ /* L data MSB during FRM LRC (long frame) */ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x1 << I2S_FMT0_LRCK_WIDTH, ++ 0x1 << I2S_FMT0_LRCK_WIDTH); ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "format setting failed\n"); ++ return -EINVAL; ++ } ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x3 << I2S_CTL_MODE, mode << I2S_CTL_MODE); ++ /* regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin), ++ * 0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET); ++ */ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 0), ++ 0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 1), ++ 0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 2), ++ 0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 3), ++ 0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_IN_SLOT(tdm_num), ++ 0x3 << I2S_IN_OFFSET, offset << I2S_IN_OFFSET); ++ ++ /* set lrck & bclk polarity */ ++ switch (fmt & SND_SOC_DAIFMT_INV_MASK) { ++ case SND_SOC_DAIFMT_NB_NF: ++ lrck_polarity = 0; ++ brck_polarity = 0; ++ break; ++ case SND_SOC_DAIFMT_NB_IF: ++ lrck_polarity = 1; ++ brck_polarity = 0; ++ break; ++ case SND_SOC_DAIFMT_IB_NF: ++ lrck_polarity = 0; ++ brck_polarity = 1; ++ break; ++ case SND_SOC_DAIFMT_IB_IF: ++ lrck_polarity = 1; ++ brck_polarity = 1; ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "invert clk setting failed\n"); ++ return -EINVAL; ++ } ++ if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_A) || ++ ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_B)) ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x1 << I2S_FMT0_LRCK_POLARITY, ++ (lrck_polarity^1) << I2S_FMT0_LRCK_POLARITY); ++ else ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x1 << I2S_FMT0_LRCK_POLARITY, ++ lrck_polarity << I2S_FMT0_LRCK_POLARITY); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x1 << I2S_FMT0_BCLK_POLARITY, ++ brck_polarity << I2S_FMT0_BCLK_POLARITY); ++ ++ /* set master/slave */ ++ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { ++ case SND_SOC_DAIFMT_CBM_CFM: ++ /* lrck & bclk dir output */ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_CLK_OUT, 0x0 << I2S_CTL_CLK_OUT); ++ break; ++ case SND_SOC_DAIFMT_CBS_CFS: ++ /* lrck & bclk dir input */ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_CLK_OUT, 0x1 << I2S_CTL_CLK_OUT); ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "unknown master/slave format\n"); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_set_tdm_slot(struct snd_soc_dai *dai, ++ unsigned int tx_mask, unsigned int rx_mask, ++ int slots, int slot_width) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int tdm_num, tx_pin, rx_pin; ++ unsigned int slot_width_map, lrck_width_map; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null\n"); ++ return -ENOMEM; ++ } ++ regmap = ahub_info->mem_info.regmap; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ tx_pin = ahub_info->dts_info.tx_pin; ++ rx_pin = ahub_info->dts_info.rx_pin; ++ ++ switch (slot_width) { ++ case 8: ++ slot_width_map = 1; ++ break; ++ case 12: ++ slot_width_map = 2; ++ break; ++ case 16: ++ slot_width_map = 3; ++ break; ++ case 20: ++ slot_width_map = 4; ++ break; ++ case 24: ++ slot_width_map = 5; ++ break; ++ case 28: ++ slot_width_map = 6; ++ break; ++ case 32: ++ slot_width_map = 7; ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "unknown slot width\n"); ++ return -EINVAL; ++ } ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x7 << I2S_FMT0_SW, slot_width_map << I2S_FMT0_SW); ++ ++ /* bclk num of per channel ++ * I2S/RIGHT_J/LEFT_J -> lrck long total is lrck_width_map * 2 ++ * DSP_A/DAP_B -> lrck long total is lrck_width_map * 1 ++ */ ++ switch (ahub_info->fmt & SND_SOC_DAIFMT_FORMAT_MASK) { ++ case SND_SOC_DAIFMT_I2S: ++ case SND_SOC_DAIFMT_RIGHT_J: ++ case SND_SOC_DAIFMT_LEFT_J: ++ slots /= 2; ++ break; ++ case SND_SOC_DAIFMT_DSP_A: ++ case SND_SOC_DAIFMT_DSP_B: ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "unsupoort format\n"); ++ return -EINVAL; ++ } ++ lrck_width_map = slots * slot_width - 1; ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x3ff << I2S_FMT0_LRCK_PERIOD, ++ lrck_width_map << I2S_FMT0_LRCK_PERIOD); ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params, ++ struct snd_soc_dai *dai) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int apb_num, tdm_num, tx_pin, rx_pin; ++ unsigned int channels; ++ unsigned int channels_en[16] = { ++ 0x0001, 0x0003, 0x0007, 0x000f, 0x001f, 0x003f, 0x007f, 0x00ff, ++ 0x01ff, 0x03ff, 0x07ff, 0x0fff, 0x1fff, 0x3fff, 0x7fff, 0xffff ++ }; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null.\n"); ++ return -ENOMEM; ++ } ++ regmap = ahub_info->mem_info.regmap; ++ apb_num = ahub_info->dts_info.apb_num; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ tx_pin = ahub_info->dts_info.tx_pin; ++ rx_pin = ahub_info->dts_info.rx_pin; ++ ++ /* configure DMA */ ++ switch (params_physical_width(params)) { ++ case 16: ++ ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; ++ break; ++ case 24: ++ case 32: ++ ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ break; ++ default: ++ dev_err(dai->dev, "Unsupported physical sample width: %d\n", ++ params_physical_width(params)); ++ return -EINVAL; ++ } ++ ++ /* set bits */ ++ switch (params_format(params)) { ++ case SNDRV_PCM_FORMAT_S16_LE: ++ /* apbifn bits */ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ regmap_update_bits(regmap, ++ SUNXI_AHUB_APBIF_TX_CTL(apb_num), ++ 0x7 << APBIF_TX_WS, ++ 0x3 << APBIF_TX_WS); ++ regmap_update_bits(regmap, ++ SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num), ++ 0x1 << APBIF_TX_TXIM, ++ 0x1 << APBIF_TX_TXIM); ++ } else { ++ regmap_update_bits(regmap, ++ SUNXI_AHUB_APBIF_RX_CTL(apb_num), ++ 0x7 << APBIF_RX_WS, ++ 0x3 << APBIF_RX_WS); ++ regmap_update_bits(regmap, ++ SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num), ++ 0x3 << APBIF_RX_RXOM, ++ 0x1 << APBIF_RX_RXOM); ++ } ++ ++ regmap_update_bits(regmap, ++ SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x7 << I2S_FMT0_SR, ++ 0x3 << I2S_FMT0_SR); ++ break; ++ case SNDRV_PCM_FORMAT_S20_3LE: ++ case SNDRV_PCM_FORMAT_S24_LE: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num), ++ 0x7 << APBIF_TX_WS, 0x5 << APBIF_TX_WS); ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num), ++ 0x1 << APBIF_TX_TXIM, 0x1 << APBIF_TX_TXIM); ++ } else { ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num), ++ 0x7 << APBIF_RX_WS, 0x5 << APBIF_RX_WS); ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num), ++ 0x3 << APBIF_RX_RXOM, 0x1 << APBIF_RX_RXOM); ++ } ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x7 << I2S_FMT0_SR, 0x5 << I2S_FMT0_SR); ++ break; ++ case SNDRV_PCM_FORMAT_S32_LE: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num), ++ 0x7 << APBIF_TX_WS, 0x7 << APBIF_TX_WS); ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num), ++ 0x1 << APBIF_TX_TXIM, 0x1 << APBIF_TX_TXIM); ++ } else { ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num), ++ 0x7 << APBIF_RX_WS, 0x7 << APBIF_RX_WS); ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num), ++ 0x3 << APBIF_RX_RXOM, 0x1 << APBIF_RX_RXOM); ++ } ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num), ++ 0x7 << I2S_FMT0_SR, 0x7 << I2S_FMT0_SR); ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "unrecognized format bits\n"); ++ return -EINVAL; ++ } ++ ++ /* set channels */ ++ channels = params_channels(params); ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ /* apbifn channels */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num), ++ 0xf << APBIF_TX_CHAN_NUM, ++ (channels - 1) << APBIF_TX_CHAN_NUM); ++ /* tdmn channels */ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CHCFG(tdm_num), ++ 0xf << I2S_CHCFG_TX_CHANNUM, ++ (channels - 1) << I2S_CHCFG_TX_CHANNUM); ++ ++ regmap_update_bits(regmap, ++ SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin), ++ 0xf << I2S_OUT_SLOT_NUM, ++ (channels - 1) << I2S_OUT_SLOT_NUM); ++ regmap_update_bits(regmap, ++ SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin), ++ 0xffff << I2S_OUT_SLOT_EN, ++ channels_en[channels - 1] << I2S_OUT_SLOT_EN); ++ } else { ++ /* apbifn channels */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num), ++ 0xf << APBIF_RX_CHAN_NUM, ++ (channels - 1) << APBIF_RX_CHAN_NUM); ++ /* tdmn channels */ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CHCFG(tdm_num), ++ 0xf << I2S_CHCFG_RX_CHANNUM, ++ (channels - 1) << I2S_CHCFG_RX_CHANNUM); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_IN_SLOT(tdm_num), ++ 0xf << I2S_IN_SLOT_NUM, ++ (channels - 1) << I2S_IN_SLOT_NUM); ++ } ++ ++ return 0; ++} ++ ++static void sunxi_ahub_dai_tx_route(struct sunxi_ahub_info *ahub_info, ++ bool enable) ++{ ++ struct regmap *regmap = NULL; ++ unsigned int tdm_num, tx_pin; ++ unsigned int apb_num; ++ ++ SND_LOG_DEBUG(HLOG, "%s\n", enable ? "on" : "off"); ++ ++ regmap = ahub_info->mem_info.regmap; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ tx_pin = ahub_info->dts_info.tx_pin; ++ apb_num = ahub_info->dts_info.apb_num; ++ ++ if (enable) ++ goto tx_route_enable; ++ else ++ goto tx_route_disable; ++ ++tx_route_enable: ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << (I2S_CTL_SDO0_EN + tx_pin), ++ 0x1 << (I2S_CTL_SDO0_EN + tx_pin)); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_TXEN, 0x1 << I2S_CTL_TXEN); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_OUT_MUTE, 0x0 << I2S_CTL_OUT_MUTE); ++ /* start apbif tx */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num), ++ 0x1 << APBIF_TX_START, 0x1 << APBIF_TX_START); ++ /* enable tx drq */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_IRQ_CTL(apb_num), ++ 0x1 << APBIF_TX_DRQ, 0x1 << APBIF_TX_DRQ); ++ return; ++ ++tx_route_disable: ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_OUT_MUTE, 0x1 << I2S_CTL_OUT_MUTE); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_TXEN, 0x0 << I2S_CTL_TXEN); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << (I2S_CTL_SDO0_EN + tx_pin), ++ 0x0 << (I2S_CTL_SDO0_EN + tx_pin)); ++ /* stop apbif tx */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num), ++ 0x1 << APBIF_TX_START, 0x0 << APBIF_TX_START); ++ /* disable tx drq */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_IRQ_CTL(apb_num), ++ 0x1 << APBIF_TX_DRQ, 0x0 << APBIF_TX_DRQ); ++ return; ++} ++ ++static void sunxi_ahub_dai_rx_route(struct sunxi_ahub_info *ahub_info, ++ bool enable) ++{ ++ struct regmap *regmap = NULL; ++ unsigned int tdm_num, rx_pin; ++ unsigned int apb_num; ++ ++ SND_LOG_DEBUG(HLOG, "%s\n", enable ? "on" : "off"); ++ ++ regmap = ahub_info->mem_info.regmap; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ rx_pin = ahub_info->dts_info.rx_pin; ++ apb_num = ahub_info->dts_info.apb_num; ++ ++ if (enable) ++ goto rx_route_enable; ++ else ++ goto rx_route_disable; ++ ++rx_route_enable: ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << (I2S_CTL_SDI0_EN + rx_pin), ++ 0x1 << (I2S_CTL_SDI0_EN + rx_pin)); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_RXEN, 0x1 << I2S_CTL_RXEN); ++ /* start apbif rx */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num), ++ 0x1 << APBIF_RX_START, 0x1 << APBIF_RX_START); ++ /* enable rx drq */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_IRQ_CTL(apb_num), ++ 0x1 << APBIF_RX_DRQ, 0x1 << APBIF_RX_DRQ); ++ return; ++ ++rx_route_disable: ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_RXEN, 0x0 << I2S_CTL_RXEN); ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << (I2S_CTL_SDI0_EN + rx_pin), ++ 0x0 << (I2S_CTL_SDI0_EN + rx_pin)); ++ /* stop apbif rx */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num), ++ 0x1 << APBIF_RX_START, 0x0 << APBIF_RX_START); ++ /* disable rx drq */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_IRQ_CTL(apb_num), ++ 0x1 << APBIF_RX_DRQ, 0x0 << APBIF_RX_DRQ); ++ return; ++} ++ ++static int sunxi_ahub_dai_trigger(struct snd_pcm_substream *substream, ++ int cmd, ++ struct snd_soc_dai *dai) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null.\n"); ++ return -ENOMEM; ++ } ++ ++ switch (cmd) { ++ case SNDRV_PCM_TRIGGER_START: ++ case SNDRV_PCM_TRIGGER_RESUME: ++ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ sunxi_ahub_dai_tx_route(ahub_info, true); ++ } else { ++ sunxi_ahub_dai_rx_route(ahub_info, true); ++ } ++ break; ++ case SNDRV_PCM_TRIGGER_STOP: ++ case SNDRV_PCM_TRIGGER_SUSPEND: ++ case SNDRV_PCM_TRIGGER_PAUSE_PUSH: ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ sunxi_ahub_dai_tx_route(ahub_info, false); ++ } else { ++ sunxi_ahub_dai_rx_route(ahub_info, false); ++ } ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_prepare(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int apb_num; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "ahub_info is null.\n"); ++ return -ENOMEM; ++ } ++ regmap = ahub_info->mem_info.regmap; ++ apb_num = ahub_info->dts_info.apb_num; ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ /* clear txfifo */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num), ++ 0x1 << APBIF_TX_FTX, 0x1 << APBIF_TX_FTX); ++ /* clear tx o/u irq */ ++ regmap_write(regmap, SUNXI_AHUB_APBIF_TX_IRQ_STA(apb_num), ++ (0x1 << APBIF_TX_OV_PEND) | (0x1 << APBIF_TX_EM_PEND)); ++ /* clear tx fifo cnt */ ++ regmap_write(regmap, SUNXI_AHUB_APBIF_TXFIFO_CNT(apb_num), 0); ++ } else { ++ /* clear rxfifo */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num), ++ 0x1 << APBIF_RX_FRX, 0x1 << APBIF_RX_FRX); ++ /* clear rx o/u irq */ ++ regmap_write(regmap, SUNXI_AHUB_APBIF_RX_IRQ_STA(apb_num), ++ (0x1 << APBIF_RX_UV_PEND) | (0x1 << APBIF_RX_AV_PEND)); ++ /* clear rx fifo cnt */ ++ regmap_write(regmap, SUNXI_AHUB_APBIF_RXFIFO_CNT(apb_num), 0); ++ } ++ ++ return 0; ++} ++ ++static void sunxi_ahub_dai_shutdown(struct snd_pcm_substream *substream, ++ struct snd_soc_dai *dai) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int apb_num, tdm_num; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ regmap = ahub_info->mem_info.regmap; ++ apb_num = ahub_info->dts_info.apb_num; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ ++ /* APBIF & I2S of RST and GAT */ ++ if (tdm_num > 3 || apb_num > 2) { ++ SND_LOG_ERR(HLOG, "unspport tdm num or apbif num\n"); ++ return; ++ } ++ ++ if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { ++ regmap_update_bits(regmap, SUNXI_AHUB_RST, ++ 0x1 << (APBIF_TXDIF0_RST - apb_num), ++ 0x0 << (APBIF_TXDIF0_RST - apb_num)); ++ regmap_update_bits(regmap, SUNXI_AHUB_GAT, ++ 0x1 << (APBIF_TXDIF0_GAT - apb_num), ++ 0x0 << (APBIF_TXDIF0_GAT - apb_num)); ++ } else { ++ regmap_update_bits(regmap, SUNXI_AHUB_RST, ++ 0x1 << (APBIF_RXDIF0_RST - apb_num), ++ 0x0 << (APBIF_RXDIF0_RST - apb_num)); ++ regmap_update_bits(regmap, SUNXI_AHUB_GAT, ++ 0x1 << (APBIF_RXDIF0_GAT - apb_num), ++ 0x0 << (APBIF_RXDIF0_GAT - apb_num)); ++ } ++} ++ ++static const struct snd_soc_dai_ops sunxi_ahub_dai_ops = { ++ /* call by machine */ ++ .set_pll = sunxi_ahub_dai_set_pll, // set pllclk ++ .set_sysclk = sunxi_ahub_dai_set_sysclk, // set mclk ++ .set_bclk_ratio = sunxi_ahub_dai_set_bclk_ratio,// set bclk freq ++ .set_tdm_slot = sunxi_ahub_dai_set_tdm_slot, // set slot num and width ++ .set_fmt = sunxi_ahub_dai_set_fmt, // set tdm fmt ++ /* call by asoc */ ++ .startup = sunxi_ahub_dai_startup, ++ .hw_params = sunxi_ahub_dai_hw_params, // set hardware params ++ .prepare = sunxi_ahub_dai_prepare, // clean irq and fifo ++ .trigger = sunxi_ahub_dai_trigger, // set drq ++ .shutdown = sunxi_ahub_dai_shutdown, ++}; ++ ++static void snd_soc_sunxi_ahub_init(struct sunxi_ahub_info *ahub_info) ++{ ++ struct regmap *regmap = NULL; ++ unsigned int apb_num, tdm_num, tx_pin, rx_pin; ++ unsigned int reg_val = 0; ++ unsigned int rx_pin_map = 0; ++ unsigned int tdm_to_apb = 0; ++ unsigned int apb_to_tdm = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ regmap = ahub_info->mem_info.regmap; ++ apb_num = ahub_info->dts_info.apb_num; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ tx_pin = ahub_info->dts_info.tx_pin; ++ rx_pin = ahub_info->dts_info.rx_pin; ++ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_GEN, 0x1 << I2S_CTL_GEN); ++ regmap_update_bits(regmap, SUNXI_AHUB_RST, ++ 0x1 << (I2S0_RST - tdm_num), ++ 0x1 << (I2S0_RST - tdm_num)); ++ regmap_update_bits(regmap, SUNXI_AHUB_GAT, ++ 0x1 << (I2S0_GAT - tdm_num), ++ 0x1 << (I2S0_GAT - tdm_num)); ++ ++ /* tdm tx channels map */ ++ regmap_write(regmap, SUNXI_AHUB_I2S_OUT_CHMAP0(tdm_num, tx_pin), 0x76543210); ++ regmap_write(regmap, SUNXI_AHUB_I2S_OUT_CHMAP1(tdm_num, tx_pin), 0xFEDCBA98); ++ ++ /* tdm rx channels map */ ++ rx_pin_map = (rx_pin << 4) | (rx_pin << 12) | (rx_pin << 20) | (rx_pin << 28); ++ reg_val = 0x03020100 | rx_pin_map; ++ regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP0(tdm_num), reg_val); ++ reg_val = 0x07060504 | rx_pin_map; ++ regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP1(tdm_num), reg_val); ++ reg_val = 0x0B0A0908 | rx_pin_map; ++ regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP2(tdm_num), reg_val); ++ reg_val = 0x0F0E0D0C | rx_pin_map; ++ regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP3(tdm_num), reg_val); ++ ++ /* tdm tx & rx data fmt ++ * 1. MSB first ++ * 2. transfer 0 after each sample in each slot ++ * 3. linear PCM ++ */ ++ regmap_write(regmap, SUNXI_AHUB_I2S_FMT1(tdm_num), 0x30); ++ ++ /* apbif tx & rx data fmt ++ * 1. MSB first ++ * 2. trigger level tx -> 0x20, rx -> 0x40 ++ */ ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num), ++ 0x1 << APBIF_TX_TXIM, 0x0 << APBIF_TX_TXIM); ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num), ++ 0x3f << APBIF_TX_LEVEL, 0x20 << APBIF_TX_LEVEL); ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num), ++ 0x3 << APBIF_RX_RXOM, 0x0 << APBIF_RX_RXOM); ++ regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num), ++ 0x7f << APBIF_RX_LEVEL, 0x40 << APBIF_RX_LEVEL); ++ ++ /* apbif <-> tdm */ ++ switch (tdm_num) ++ { ++ case 0: ++ tdm_to_apb = APBIF_RX_I2S0_TXDIF; ++ break; ++ case 1: ++ tdm_to_apb = APBIF_RX_I2S1_TXDIF; ++ break; ++ case 2: ++ tdm_to_apb = APBIF_RX_I2S2_TXDIF; ++ break; ++ case 3: ++ tdm_to_apb = APBIF_RX_I2S3_TXDIF; ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "unspport tdm num\n"); ++ return; ++ } ++ regmap_write(regmap, SUNXI_AHUB_APBIF_RXFIFO_CONT(apb_num), 0x1 << tdm_to_apb); ++ ++ switch (apb_num) ++ { ++ case 0: ++ apb_to_tdm = I2S_RX_APBIF_TXDIF0; ++ break; ++ case 1: ++ apb_to_tdm = I2S_RX_APBIF_TXDIF1; ++ break; ++ case 2: ++ apb_to_tdm = I2S_RX_APBIF_TXDIF2; ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "unspport apb num\n"); ++ return; ++ } ++ regmap_write(regmap, SUNXI_AHUB_I2S_RXCONT(tdm_num), 0x1 << apb_to_tdm); ++ ++ return; ++} ++ ++static int sunxi_ahub_dai_probe(struct snd_soc_dai *dai) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ /* pcm_new will using the dma_param about the cma and fifo params. */ ++ snd_soc_dai_init_dma_data(dai, ++ &ahub_info->playback_dma_param, ++ &ahub_info->capture_dma_param); ++ ++ snd_soc_sunxi_ahub_init(ahub_info); ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dai_remove(struct snd_soc_dai *dai) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai); ++ struct regmap *regmap = NULL; ++ unsigned int tdm_num; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ regmap = ahub_info->mem_info.regmap; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ ++ regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num), ++ 0x1 << I2S_CTL_GEN, 0x0 << I2S_CTL_GEN); ++ regmap_update_bits(regmap, SUNXI_AHUB_RST, ++ 0x1 << (I2S0_RST - tdm_num), ++ 0x0 << (I2S0_RST - tdm_num)); ++ regmap_update_bits(regmap, SUNXI_AHUB_GAT, ++ 0x1 << (I2S0_GAT - tdm_num), ++ 0x0 << (I2S0_GAT - tdm_num)); ++ ++ return 0; ++} ++ ++static struct snd_soc_dai_driver sunxi_ahub_dai = { ++ .name = "ahub_plat", ++ .probe = sunxi_ahub_dai_probe, ++ .remove = sunxi_ahub_dai_remove, ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000 ++ | SNDRV_PCM_RATE_KNOT, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE ++ | SNDRV_PCM_FMTBIT_S24_LE ++ | SNDRV_PCM_FMTBIT_S32_LE, ++ }, ++ .capture = { ++ .stream_name = "Capture", ++ .channels_min = 1, ++ .channels_max = 2, ++ .rates = SNDRV_PCM_RATE_8000_192000 ++ | SNDRV_PCM_RATE_KNOT, ++ .formats = SNDRV_PCM_FMTBIT_S16_LE ++ | SNDRV_PCM_FMTBIT_S24_LE ++ | SNDRV_PCM_FMTBIT_S32_LE, ++ }, ++ .ops = &sunxi_ahub_dai_ops, ++}; ++ ++static int sunxi_ahub_probe(struct snd_soc_component *component) ++{ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ return 0; ++} ++ ++static int sunxi_ahub_suspend(struct snd_soc_component *component) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component); ++ struct regmap *regmap = NULL; ++ unsigned int apb_num, tdm_num; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ regmap = ahub_info->mem_info.regmap; ++ apb_num = ahub_info->dts_info.apb_num; ++ tdm_num = ahub_info->dts_info.tdm_num; ++ ++ return 0; ++} ++ ++static int sunxi_ahub_resume(struct snd_soc_component *component) ++{ ++ struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component); ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ snd_soc_sunxi_ahub_init(ahub_info); ++ ++ return 0; ++} ++ ++int sunxi_loopback_debug_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ unsigned int reg_val; ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component); ++ struct sunxi_ahub_mem_info *mem_info = &ahub_info->mem_info; ++ struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info; ++ ++ regmap_read(mem_info->regmap, SUNXI_AHUB_I2S_CTL(dts_info->tdm_num), ®_val); ++ ucontrol->value.integer.value[0] = ((reg_val & (1 << I2S_CTL_LOOP0)) ? 1 : 0); ++ ++ return 0; ++} ++ ++int sunxi_loopback_debug_set(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol); ++ struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component); ++ struct sunxi_ahub_mem_info *mem_info = &ahub_info->mem_info; ++ struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info; ++ ++ switch (ucontrol->value.integer.value[0]) { ++ case 0: ++ regmap_update_bits(mem_info->regmap, ++ SUNXI_AHUB_I2S_CTL(dts_info->tdm_num), ++ 1 << I2S_CTL_LOOP0, 0 << I2S_CTL_LOOP0); ++ break; ++ case 1: ++ regmap_update_bits(mem_info->regmap, ++ SUNXI_AHUB_I2S_CTL(dts_info->tdm_num), ++ 1 << I2S_CTL_LOOP0, 1 << I2S_CTL_LOOP0); ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static const struct snd_kcontrol_new sunxi_ahub_controls[] = { ++ SOC_SINGLE_EXT("loopback debug", SND_SOC_NOPM, 0, 1, 0, ++ sunxi_loopback_debug_get, sunxi_loopback_debug_set), ++}; ++ ++static struct snd_soc_component_driver sunxi_ahub_component = { ++ .name = DRV_NAME, ++ .probe = sunxi_ahub_probe, ++ .suspend = sunxi_ahub_suspend, ++ .resume = sunxi_ahub_resume, ++ .controls = sunxi_ahub_controls, ++ .num_controls = ARRAY_SIZE(sunxi_ahub_controls), ++}; ++ ++/******************************************************************************* ++ * for kernel source ++ ******************************************************************************/ ++static int snd_soc_sunxi_ahub_pin_init(struct platform_device *pdev, ++ struct device_node *np, ++ struct sunxi_ahub_pinctl_info *pin_info) ++{ ++ int ret = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (of_property_read_bool(np, "pinctrl_used")) { ++ pin_info->pinctrl_used = 1; ++ } else { ++ pin_info->pinctrl_used = 0; ++ SND_LOG_DEBUG(HLOG, "unused pinctrl\n"); ++ return 0; ++ } ++ ++ pin_info->pinctrl = devm_pinctrl_get(&pdev->dev); ++ if (IS_ERR_OR_NULL(pin_info->pinctrl)) { ++ SND_LOG_ERR(HLOG, "pinctrl get failed\n"); ++ ret = -EINVAL; ++ return ret; ++ } ++ pin_info->pinstate = pinctrl_lookup_state(pin_info->pinctrl, ++ PINCTRL_STATE_DEFAULT); ++ if (IS_ERR_OR_NULL(pin_info->pinstate)) { ++ SND_LOG_ERR(HLOG, "pinctrl default state get fail\n"); ++ ret = -EINVAL; ++ goto err_loopup_pinstate; ++ } ++ pin_info->pinstate_sleep = pinctrl_lookup_state(pin_info->pinctrl, ++ PINCTRL_STATE_SLEEP); ++ if (IS_ERR_OR_NULL(pin_info->pinstate_sleep)) { ++ SND_LOG_ERR(HLOG, "pinctrl sleep state get failed\n"); ++ ret = -EINVAL; ++ goto err_loopup_pin_sleep; ++ } ++ ret = pinctrl_select_state(pin_info->pinctrl, pin_info->pinstate); ++ if (ret < 0) { ++ SND_LOG_ERR(HLOG, "daudio set pinctrl default state fail\n"); ++ ret = -EBUSY; ++ goto err_pinctrl_select_default; ++ } ++ ++ return 0; ++ ++err_pinctrl_select_default: ++err_loopup_pin_sleep: ++err_loopup_pinstate: ++ devm_pinctrl_put(pin_info->pinctrl); ++ return ret; ++} ++ ++static int snd_soc_sunxi_ahub_dts_params_init(struct platform_device *pdev, ++ struct device_node *np, ++ struct sunxi_ahub_dts_info *dts_info) ++{ ++ int ret = 0; ++ unsigned int temp_val = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ /* get tdm fmt of apb_num & tdm_num & tx/rx_pin */ ++ ret = of_property_read_u32(np, "apb_num", &temp_val); ++ if (ret < 0) { ++ SND_LOG_WARN(HLOG, "apb_num config missing\n"); ++ dts_info->apb_num = 0; ++ } else { ++ if (temp_val > 2) { /* APBIFn (n = 0~2) */ ++ dts_info->apb_num = 0; ++ SND_LOG_WARN(HLOG, "apb_num config invalid\n"); ++ } else { ++ dts_info->apb_num = temp_val; ++ } ++ } ++ ret = of_property_read_u32(np, "tdm_num", &temp_val); ++ if (ret < 0) { ++ SND_LOG_WARN(HLOG, "tdm_num config missing\n"); ++ dts_info->tdm_num = 0; ++ } else { ++ if (temp_val > 3) { /* I2Sn (n = 0~3) */ ++ dts_info->tdm_num = 0; ++ SND_LOG_WARN(HLOG, "tdm_num config invalid\n"); ++ } else { ++ dts_info->tdm_num = temp_val; ++ } ++ } ++ ret = of_property_read_u32(np, "tx_pin", &temp_val); ++ if (ret < 0) { ++ SND_LOG_WARN(HLOG, "tx_pin config missing\n"); ++ dts_info->tx_pin = 0; ++ } else { ++ if (temp_val > 3) { /* I2S_DOUTn (n = 0~3) */ ++ dts_info->tx_pin = 0; ++ SND_LOG_WARN(HLOG, "tx_pin config invalid\n"); ++ } else { ++ dts_info->tx_pin = temp_val; ++ } ++ } ++ ret = of_property_read_u32(np, "rx_pin", &temp_val); ++ if (ret < 0) { ++ SND_LOG_WARN(HLOG, "rx_pin config missing\n"); ++ dts_info->rx_pin = 0; ++ } else { ++ if (temp_val > 3) { /* I2S_DINTn (n = 0~3) */ ++ dts_info->rx_pin = 0; ++ SND_LOG_WARN(HLOG, "rx_pin config invalid\n"); ++ } else { ++ dts_info->rx_pin = temp_val; ++ } ++ } ++ ++ SND_LOG_DEBUG(HLOG, "playback_cma : %lu\n", dts_info->playback_cma); ++ SND_LOG_DEBUG(HLOG, "capture_cma : %lu\n", dts_info->capture_cma); ++ SND_LOG_DEBUG(HLOG, "tx_fifo_size : %lu\n", dts_info->playback_fifo_size); ++ SND_LOG_DEBUG(HLOG, "rx_fifo_size : %lu\n", dts_info->capture_fifo_size); ++ SND_LOG_DEBUG(HLOG, "apb_num : %u\n", dts_info->apb_num); ++ SND_LOG_DEBUG(HLOG, "tdm_num : %u\n", dts_info->tdm_num); ++ SND_LOG_DEBUG(HLOG, "tx_pin : %u\n", dts_info->tx_pin); ++ SND_LOG_DEBUG(HLOG, "rx_pin : %u\n", dts_info->rx_pin); ++ ++ return 0; ++}; ++ ++static int snd_soc_sunxi_ahub_regulator_init(struct platform_device *pdev, ++ struct device_node *np, ++ struct sunxi_ahub_regulator_info *regulator_info) ++{ ++ int ret = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ regulator_info->regulator_name = NULL; ++ if (of_property_read_string(np, "ahub_regulator", ®ulator_info->regulator_name)) { ++ SND_LOG_DEBUG(HLOG, "regulator missing\n"); ++ regulator_info->regulator = NULL; ++ return 0; ++ } ++ ++ regulator_info->regulator = regulator_get(NULL, regulator_info->regulator_name); ++ if (IS_ERR_OR_NULL(regulator_info->regulator)) { ++ SND_LOG_ERR(HLOG, "get duaido vcc-pin failed\n"); ++ ret = -EFAULT; ++ goto err_regulator_get; ++ } ++ ret = regulator_set_voltage(regulator_info->regulator, 3300000, 3300000); ++ if (ret < 0) { ++ SND_LOG_ERR(HLOG, "set duaido voltage failed\n"); ++ ret = -EFAULT; ++ goto err_regulator_set_vol; ++ } ++ ret = regulator_enable(regulator_info->regulator); ++ if (ret < 0) { ++ SND_LOG_ERR(HLOG, "enable duaido vcc-pin failed\n"); ++ ret = -EFAULT; ++ goto err_regulator_enable; ++ } ++ ++ return 0; ++ ++err_regulator_enable: ++err_regulator_set_vol: ++ if (regulator_info->regulator) ++ regulator_put(regulator_info->regulator); ++err_regulator_get: ++ return ret; ++}; ++ ++static void snd_soc_sunxi_dma_params_init(struct sunxi_ahub_info *ahub_info) ++{ ++ struct resource *res = ahub_info->mem_info.res; ++ struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ ahub_info->playback_dma_param.addr = ++ res->start + SUNXI_AHUB_APBIF_TXFIFO(dts_info->apb_num); ++ ahub_info->playback_dma_param.maxburst = 8; ++ //ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++ ++ ahub_info->capture_dma_param.addr = ++ res->start + SUNXI_AHUB_APBIF_RXFIFO(dts_info->apb_num); ++ ahub_info->capture_dma_param.maxburst = 8; ++ //ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; ++}; ++ ++static int sunxi_ahub_dev_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct device_node *np = pdev->dev.of_node; ++ struct sunxi_ahub_info *ahub_info = NULL; ++ struct sunxi_ahub_mem_info *mem_info = NULL; ++ struct sunxi_ahub_clk_info *clk_info = NULL; ++ struct sunxi_ahub_pinctl_info *pin_info = NULL; ++ struct sunxi_ahub_dts_info *dts_info = NULL; ++ struct sunxi_ahub_regulator_info *regulator_info = NULL; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ ahub_info = devm_kzalloc(&pdev->dev, ++ sizeof(struct sunxi_ahub_info), ++ GFP_KERNEL); ++ if (IS_ERR_OR_NULL(ahub_info)) { ++ SND_LOG_ERR(HLOG, "alloc sunxi_ahub_info failed\n"); ++ ret = -ENOMEM; ++ goto err_devm_malloc_sunxi_daudio; ++ } ++ dev_set_drvdata(&pdev->dev, ahub_info); ++ ahub_info->dev = &pdev->dev; ++ mem_info = &ahub_info->mem_info; ++ clk_info = &ahub_info->clk_info; ++ pin_info = &ahub_info->pin_info; ++ dts_info = &ahub_info->dts_info; ++ regulator_info = &ahub_info->regulator_info; ++ ++ ret = snd_soc_sunxi_ahub_mem_get(mem_info); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "remap get failed\n"); ++ ret = -EINVAL; ++ goto err_snd_soc_sunxi_ahub_mem_get; ++ } ++ ++ ret = snd_soc_sunxi_ahub_clk_get(clk_info); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "clk get failed\n"); ++ ret = -EINVAL; ++ goto err_snd_soc_sunxi_ahub_clk_get; ++ } ++ ++ ret = snd_soc_sunxi_ahub_dts_params_init(pdev, np, dts_info); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "dts init failed\n"); ++ ret = -EINVAL; ++ goto err_snd_soc_sunxi_ahub_dts_params_init; ++ } ++ ++ ret = snd_soc_sunxi_ahub_pin_init(pdev, np, pin_info); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "pinctrl init failed\n"); ++ ret = -EINVAL; ++ goto err_snd_soc_sunxi_ahub_pin_init; ++ } ++ ++ ret = snd_soc_sunxi_ahub_regulator_init(pdev, np, regulator_info); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "regulator_info init failed\n"); ++ ret = -EINVAL; ++ goto err_snd_soc_sunxi_ahub_regulator_init; ++ } ++ ++ snd_soc_sunxi_dma_params_init(ahub_info); ++ ++ ret = snd_soc_register_component(&pdev->dev, ++ &sunxi_ahub_component, ++ &sunxi_ahub_dai, 1); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "component register failed\n"); ++ ret = -ENOMEM; ++ goto err_snd_soc_register_component; ++ } ++ ++ ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "register ASoC platform failed\n"); ++ ret = -ENOMEM; ++ goto err_snd_soc_sunxi_dma_platform_register; ++ } ++ ++ SND_LOG_DEBUG(HLOG, "register ahub platform success\n"); ++ ++ return 0; ++ ++err_snd_soc_sunxi_dma_platform_register: ++ snd_soc_unregister_component(&pdev->dev); ++err_snd_soc_register_component: ++err_snd_soc_sunxi_ahub_regulator_init: ++err_snd_soc_sunxi_ahub_dts_params_init: ++err_snd_soc_sunxi_ahub_pin_init: ++err_snd_soc_sunxi_ahub_clk_get: ++err_snd_soc_sunxi_ahub_mem_get: ++ devm_kfree(&pdev->dev, ahub_info); ++err_devm_malloc_sunxi_daudio: ++ of_node_put(np); ++ return ret; ++} ++ ++static int sunxi_ahub_dev_remove(struct platform_device *pdev) ++{ ++ struct sunxi_ahub_info *ahub_info = dev_get_drvdata(&pdev->dev); ++ struct sunxi_ahub_pinctl_info *pin_info = &ahub_info->pin_info; ++ struct sunxi_ahub_regulator_info *regulator_info = &ahub_info->regulator_info; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ snd_soc_unregister_component(&pdev->dev); ++ ++ if (regulator_info->regulator) { ++ if (!IS_ERR_OR_NULL(regulator_info->regulator)) { ++ regulator_disable(regulator_info->regulator); ++ regulator_put(regulator_info->regulator); ++ } ++ } ++ if (pin_info->pinctrl_used) { ++ devm_pinctrl_put(pin_info->pinctrl); ++ } ++ ++ devm_kfree(&pdev->dev, ahub_info); ++ ++ SND_LOG_DEBUG(HLOG, "unregister ahub platform success\n"); ++ ++ return 0; ++} ++ ++static const struct of_device_id sunxi_ahub_of_match[] = { ++ { .compatible = "allwinner," DRV_NAME, }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, sunxi_ahub_of_match); ++ ++static struct platform_driver sunxi_ahub_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = sunxi_ahub_of_match, ++ }, ++ .probe = sunxi_ahub_dev_probe, ++ .remove = sunxi_ahub_dev_remove, ++}; ++ ++int __init sunxi_ahub_dev_init(void) ++{ ++ int ret; ++ ++ ret = platform_driver_register(&sunxi_ahub_driver); ++ if (ret != 0) { ++ SND_LOG_ERR(HLOG, "platform driver register failed\n"); ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ ++void __exit sunxi_ahub_dev_exit(void) ++{ ++ platform_driver_unregister(&sunxi_ahub_driver); ++} ++ ++late_initcall(sunxi_ahub_dev_init); ++module_exit(sunxi_ahub_dev_exit); ++ ++MODULE_AUTHOR("Dby@allwinnertech.com"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("sunxi soundcard platform of ahub"); +diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub.h b/sound/soc/sunxi_v2/snd_sunxi_ahub.h +new file mode 100644 +index 000000000..b3c1cc592 +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub.h +@@ -0,0 +1,67 @@ ++/* sound\soc\sunxi\snd_sunxi_ahub.h ++ * (C) Copyright 2021-2025 ++ * Allwinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#ifndef __SND_SUNXI_AHUB_H ++#define __SND_SUNXI_AHUB_H ++ ++#include "snd_sunxi_ahub_dam.h" ++ ++struct sunxi_ahub_pinctl_info { ++ struct pinctrl *pinctrl; ++ struct pinctrl_state *pinstate; ++ struct pinctrl_state *pinstate_sleep; ++ ++ bool pinctrl_used; ++}; ++ ++struct sunxi_ahub_dts_info { ++ unsigned int dai_type; ++ unsigned int apb_num; ++ unsigned int tdm_num; ++ unsigned int tx_pin; ++ unsigned int rx_pin; ++ ++ /* value must be (2^n)Kbyte */ ++ size_t playback_cma; ++ size_t playback_fifo_size; ++ size_t capture_cma; ++ size_t capture_fifo_size; ++}; ++ ++struct sunxi_ahub_regulator_info { ++ struct regulator *regulator; ++ const char *regulator_name; ++}; ++ ++struct sunxi_ahub_info { ++ struct device *dev; ++ ++ struct sunxi_ahub_mem_info mem_info; ++ struct sunxi_ahub_clk_info clk_info; ++ struct sunxi_ahub_pinctl_info pin_info; ++ struct sunxi_ahub_dts_info dts_info; ++ struct sunxi_ahub_regulator_info regulator_info; ++ ++ //struct sunxi_dma_params playback_dma_param; ++ //struct sunxi_dma_params capture_dma_param; ++ struct snd_dmaengine_dai_dma_data playback_dma_param; ++ struct snd_dmaengine_dai_dma_data capture_dma_param; ++ ++ /* for Hardware param setting */ ++ unsigned int fmt; ++ unsigned int pllclk_freq; ++ unsigned int moduleclk_freq; ++ unsigned int mclk_freq; ++ unsigned int lrck_freq; ++ unsigned int bclk_freq; ++}; ++ ++#endif /* __SND_SUNXI_AHUB_H */ +diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c +new file mode 100644 +index 000000000..1fcc8aefd +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c +@@ -0,0 +1,534 @@ ++/* ++ * sound\soc\sunxi\snd_sunxi_ahub_dam.c ++ * (C) Copyright 2021-2025 ++ * AllWinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "snd_sunxi_log.h" ++#include "snd_sunxi_ahub_dam.h" ++ ++#define HLOG "AHUB_DAM" ++#define DRV_NAME "sunxi-snd-plat-ahub_dam" ++ ++static struct resource g_res; ++struct sunxi_ahub_mem_info g_mem_info = { ++ .res = &g_res, ++}; ++static struct sunxi_ahub_clk_info g_clk_info; ++static struct regmap_config g_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = SUNXI_AHUB_MAX_REG, ++ .cache_type = REGCACHE_NONE, ++}; ++ ++static struct snd_soc_dai_driver sunxi_ahub_dam_dai = { ++ .name = "ahub_dam", ++}; ++ ++static int sunxi_ahub_dam_probe(struct snd_soc_component *component) ++{ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dam_suspend(struct snd_soc_component *component) ++{ ++ struct sunxi_ahub_clk_info *clk_info = &g_clk_info; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ clk_disable_unprepare(clk_info->clk_module); ++ clk_disable_unprepare(clk_info->clk_pll); ++ //clk_disable_unprepare(clk_info->clk_pllx4); ++ clk_disable_unprepare(clk_info->clk_bus); ++ reset_control_assert(clk_info->clk_rst); ++ ++ return 0; ++} ++ ++static int sunxi_ahub_dam_resume(struct snd_soc_component *component) ++{ ++ struct sunxi_ahub_clk_info *clk_info = &g_clk_info; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (reset_control_deassert(clk_info->clk_rst)) { ++ SND_LOG_ERR(HLOG, "clk rst deassert failed\n"); ++ return -EINVAL; ++ } ++ if (clk_prepare_enable(clk_info->clk_bus)) { ++ SND_LOG_ERR(HLOG, "clk bus enable failed\n"); ++ return -EBUSY; ++ } ++ if (clk_prepare_enable(clk_info->clk_pll)) { ++ SND_LOG_ERR(HLOG, "clk_pll enable failed\n"); ++ return -EBUSY; ++ } ++ //if (clk_prepare_enable(clk_info->clk_pllx4)) { ++ // SND_LOG_ERR(HLOG, "clk_pllx4 enable failed\n"); ++ // return -EBUSY; ++ //} ++ if (clk_prepare_enable(clk_info->clk_module)) { ++ SND_LOG_ERR(HLOG, "clk_module enable failed\n"); ++ return -EBUSY; ++ } ++ ++ return 0; ++} ++ ++struct str_conv { ++ char *str; ++ unsigned int reg; ++}; ++static struct str_conv ahub_mux_name[] = { ++ {"APBIF0 Src Select", SUNXI_AHUB_APBIF_RXFIFO_CONT(0)}, ++ {"APBIF1 Src Select", SUNXI_AHUB_APBIF_RXFIFO_CONT(1)}, ++ {"APBIF2 Src Select", SUNXI_AHUB_APBIF_RXFIFO_CONT(2)}, ++ {"I2S0 Src Select", SUNXI_AHUB_I2S_RXCONT(0)}, ++ {"I2S1 Src Select", SUNXI_AHUB_I2S_RXCONT(1)}, ++ {"I2S2 Src Select", SUNXI_AHUB_I2S_RXCONT(2)}, ++ {"I2S3 Src Select", SUNXI_AHUB_I2S_RXCONT(3)}, ++ {"DAM0C0 Src Select", SUNXI_AHUB_DAM_RX0_SRC(0)}, ++ {"DAM0C1 Src Select", SUNXI_AHUB_DAM_RX1_SRC(0)}, ++ {"DAM0C2 Src Select", SUNXI_AHUB_DAM_RX2_SRC(0)}, ++ {"DAM1C0 Src Select", SUNXI_AHUB_DAM_RX0_SRC(1)}, ++ {"DAM1C1 Src Select", SUNXI_AHUB_DAM_RX1_SRC(1)}, ++ {"DAM1C2 Src Select", SUNXI_AHUB_DAM_RX2_SRC(1)}, ++}; ++static const char *ahub_mux_text[] = { ++ "NONE", ++ "APBIF_TXDIF0", ++ "APBIF_TXDIF1", ++ "APBIF_TXDIF2", ++ "I2S0_TXDIF", ++ "I2S1_TXDIF", ++ "I2S2_TXDIF", ++ "I2S3_TXDIF", ++ "DAM0_TXDIF", ++ "DAM1_TXDIF", ++}; ++static const unsigned int ahub_mux_values[] = { ++ 0, ++ 1 << I2S_RX_APBIF_TXDIF0, ++ 1 << I2S_RX_APBIF_TXDIF1, ++ 1 << I2S_RX_APBIF_TXDIF2, ++ 1 << I2S_RX_I2S0_TXDIF, ++ 1 << I2S_RX_I2S1_TXDIF, ++ 1 << I2S_RX_I2S2_TXDIF, ++ 1 << I2S_RX_I2S3_TXDIF, ++ 1 << I2S_RX_DAM0_TXDIF, ++ 1 << I2S_RX_DAM1_TXDIF, ++}; ++static SOC_ENUM_SINGLE_EXT_DECL(ahub_mux, ahub_mux_text); ++ ++static int sunxi_ahub_mux_get(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ int i; ++ unsigned int reg_val; ++ unsigned int src_reg; ++ struct regmap *regmap = g_mem_info.regmap; ++ ++ for (i = 0; i < ARRAY_SIZE(ahub_mux_name); i++) { ++ if (!strncmp(ahub_mux_name[i].str, kcontrol->id.name, ++ strlen(ahub_mux_name[i].str))) { ++ src_reg = ahub_mux_name[i].reg; ++ regmap_read(regmap, src_reg, ®_val); ++ reg_val &= 0xffffc000; ++ break; ++ } ++ } ++ ++ for (i = 1; i < ARRAY_SIZE(ahub_mux_values); i++) { ++ if (reg_val & ahub_mux_values[i]) { ++ ucontrol->value.integer.value[0] = i; ++ return 0; ++ } ++ } ++ ucontrol->value.integer.value[0] = 0; ++ ++ return 0; ++} ++ ++static int sunxi_ahub_mux_set(struct snd_kcontrol *kcontrol, ++ struct snd_ctl_elem_value *ucontrol) ++{ ++ int i; ++ unsigned int src_reg, src_regbit; ++ struct regmap *regmap = g_mem_info.regmap; ++ ++ if (ucontrol->value.integer.value[0] > ARRAY_SIZE(ahub_mux_name)) ++ return -EINVAL; ++ ++ src_regbit = ahub_mux_values[ucontrol->value.integer.value[0]]; ++ for (i = 0; i < ARRAY_SIZE(ahub_mux_name); i++) { ++ if (!strncmp(ahub_mux_name[i].str, kcontrol->id.name, ++ strlen(ahub_mux_name[i].str))) { ++ src_reg = ahub_mux_name[i].reg; ++ regmap_update_bits(regmap, src_reg, 0xffffc000, src_regbit); ++ break; ++ } ++ } ++ ++ return 0; ++} ++ ++static const struct snd_kcontrol_new sunxi_ahub_dam_controls[] = { ++ SOC_ENUM_EXT("APBIF0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("APBIF1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("APBIF2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("I2S0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("I2S1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("I2S2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("I2S3 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("DAM0C0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("DAM0C1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("DAM0C2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("DAM1C0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("DAM1C1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++ SOC_ENUM_EXT("DAM1C2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set), ++}; ++ ++static struct snd_soc_component_driver sunxi_ahub_dam_dev = { ++ .name = DRV_NAME, ++ .probe = sunxi_ahub_dam_probe, ++ .suspend = sunxi_ahub_dam_suspend, ++ .resume = sunxi_ahub_dam_resume, ++ .controls = sunxi_ahub_dam_controls, ++ .num_controls = ARRAY_SIZE(sunxi_ahub_dam_controls), ++}; ++ ++/******************************************************************************* ++ * for kernel source ++ ******************************************************************************/ ++int snd_soc_sunxi_ahub_mem_get(struct sunxi_ahub_mem_info *mem_info) ++{ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(g_mem_info.regmap)) { ++ SND_LOG_ERR(HLOG, "regmap is invalid\n"); ++ return -EINVAL; ++ } ++ if (IS_ERR_OR_NULL(g_mem_info.res)) { ++ SND_LOG_ERR(HLOG, "res is invalid\n"); ++ return -EINVAL; ++ } ++ ++ mem_info->regmap = g_mem_info.regmap; ++ mem_info->res = g_mem_info.res; ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(snd_soc_sunxi_ahub_mem_get); ++ ++int snd_soc_sunxi_ahub_clk_get(struct sunxi_ahub_clk_info *clk_info) ++{ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (IS_ERR_OR_NULL(g_clk_info.clk_pll)) { ++ SND_LOG_ERR(HLOG, "clk_pll is invalid\n"); ++ return -EINVAL; ++ } ++ //if (IS_ERR_OR_NULL(g_clk_info.clk_pllx4)) { ++ // SND_LOG_ERR(HLOG, "clk_pllx4 is invalid\n"); ++ // return -EINVAL; ++ //} ++ if (IS_ERR_OR_NULL(g_clk_info.clk_module)) { ++ SND_LOG_ERR(HLOG, "clk_module is invalid\n"); ++ return -EINVAL; ++ } ++ ++ clk_info->clk_pll = g_clk_info.clk_pll; ++ //clk_info->clk_pllx4 = g_clk_info.clk_pllx4; ++ clk_info->clk_module = g_clk_info.clk_module; ++ ++ return 0; ++} ++EXPORT_SYMBOL_GPL(snd_soc_sunxi_ahub_clk_get); ++ ++static int snd_soc_sunxi_ahub_mem_init(struct platform_device *pdev, ++ struct device_node *np, ++ struct sunxi_ahub_mem_info *mem_info) ++{ ++ int ret = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ ret = of_address_to_resource(np, 0, mem_info->res); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "parse device node resource failed\n"); ++ ret = -EINVAL; ++ goto err_of_addr_to_resource; ++ } ++ ++ mem_info->memregion = devm_request_mem_region(&pdev->dev, ++ mem_info->res->start, ++ resource_size(mem_info->res), ++ DRV_NAME); ++ if (IS_ERR_OR_NULL(mem_info->memregion)) { ++ SND_LOG_ERR(HLOG, "memory region already claimed\n"); ++ ret = -EBUSY; ++ goto err_devm_request_region; ++ } ++ ++ mem_info->membase = devm_ioremap(&pdev->dev, ++ mem_info->memregion->start, ++ resource_size(mem_info->memregion)); ++ if (IS_ERR_OR_NULL(mem_info->membase)) { ++ SND_LOG_ERR(HLOG, "ioremap failed\n"); ++ ret = -EBUSY; ++ goto err_devm_ioremap; ++ } ++ ++ mem_info->regmap = devm_regmap_init_mmio(&pdev->dev, ++ mem_info->membase, ++ &g_regmap_config); ++ if (IS_ERR_OR_NULL(mem_info->regmap)) { ++ SND_LOG_ERR(HLOG, "regmap init failed\n"); ++ ret = -EINVAL; ++ goto err_devm_regmap_init; ++ } ++ ++ return 0; ++ ++err_devm_regmap_init: ++ devm_iounmap(&pdev->dev, mem_info->membase); ++err_devm_ioremap: ++ devm_release_mem_region(&pdev->dev, mem_info->memregion->start, ++ resource_size(mem_info->memregion)); ++err_devm_request_region: ++err_of_addr_to_resource: ++ return ret; ++}; ++ ++static int snd_soc_sunxi_ahub_clk_init(struct platform_device *pdev, ++ struct device_node *np, ++ struct sunxi_ahub_clk_info *clk_info) ++{ ++ int ret = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ /* deassert rst clk */ ++ clk_info->clk_rst = devm_reset_control_get(&pdev->dev, NULL); ++ if (IS_ERR_OR_NULL(clk_info->clk_rst)) { ++ SND_LOG_ERR(HLOG, "clk rst get failed\n"); ++ ret = -EBUSY; ++ goto err_rst_clk; ++ } ++ if (reset_control_deassert(clk_info->clk_rst)) { ++ SND_LOG_ERR(HLOG, "deassert reset clk failed\n"); ++ ret = -EBUSY; ++ goto err_rst_clk; ++ } ++ ++ /* enable ahub bus clk */ ++ clk_info->clk_bus = of_clk_get_by_name(np, "clk_bus_audio_hub"); ++ if (IS_ERR_OR_NULL(clk_info->clk_bus)) { ++ SND_LOG_ERR(HLOG, "clk bus get failed\n"); ++ ret = -EBUSY; ++ goto err_bus_clk; ++ } ++ if (clk_prepare_enable(clk_info->clk_bus)) { ++ SND_LOG_ERR(HLOG, "ahub clk bus enable failed\n"); ++ ret = -EBUSY; ++ goto err_bus_clk; ++ } ++ ++ /* get clk of ahub */ ++ clk_info->clk_module = of_clk_get_by_name(np, "clk_audio_hub"); ++ if (IS_ERR_OR_NULL(clk_info->clk_module)) { ++ SND_LOG_ERR(HLOG, "clk module get failed\n"); ++ ret = -EBUSY; ++ goto err_module_clk; ++ } ++ clk_info->clk_pll = of_clk_get_by_name(np, "clk_pll_audio"); ++ if (IS_ERR_OR_NULL(clk_info->clk_pll)) { ++ SND_LOG_ERR(HLOG, "clk pll get failed\n"); ++ ret = -EBUSY; ++ goto err_pll_clk; ++ } ++ //clk_info->clk_pllx4 = of_clk_get_by_name(np, "clk_pll_audio_4x"); ++ //if (IS_ERR_OR_NULL(clk_info->clk_pllx4)) { ++ // SND_LOG_ERR(HLOG, "clk pllx4 get failed\n"); ++ // ret = -EBUSY; ++ // goto err_pllx4_clk; ++ //} ++ ++ /* set ahub clk parent */ ++ //if (clk_set_parent(clk_info->clk_module, clk_info->clk_pllx4)) { ++ // SND_LOG_ERR(HLOG, "set parent of clk_module to pllx4 failed\n"); ++ // ret = -EINVAL; ++ // goto err_set_parent_clk; ++ //} ++ ++ /* enable clk of ahub */ ++ if (clk_prepare_enable(clk_info->clk_pll)) { ++ SND_LOG_ERR(HLOG, "clk_pll enable failed\n"); ++ ret = -EBUSY; ++ goto err_pll_clk_enable; ++ } ++ //if (clk_prepare_enable(clk_info->clk_pllx4)) { ++ // SND_LOG_ERR(HLOG, "clk_pllx4 enable failed\n"); ++ // ret = -EBUSY; ++ // goto err_pllx4_clk_enable; ++ //} ++ if (clk_prepare_enable(clk_info->clk_module)) { ++ SND_LOG_ERR(HLOG, "clk_module enable failed\n"); ++ ret = -EBUSY; ++ goto err_module_clk_enable; ++ } ++ ++ return 0; ++ ++err_module_clk_enable: ++// clk_disable_unprepare(clk_info->clk_pllx4); ++//err_pllx4_clk_enable: ++ clk_disable_unprepare(clk_info->clk_pll); ++err_pll_clk_enable: ++//err_set_parent_clk: ++// clk_put(clk_info->clk_pllx4); ++//err_pllx4_clk: ++// clk_put(clk_info->clk_pll); ++err_pll_clk: ++ clk_put(clk_info->clk_module); ++err_module_clk: ++ clk_disable_unprepare(clk_info->clk_bus); ++ clk_put(clk_info->clk_bus); ++err_bus_clk: ++ reset_control_assert(clk_info->clk_rst); ++err_rst_clk: ++ return ret; ++} ++ ++static int sunxi_ahub_dam_dev_probe(struct platform_device *pdev) ++{ ++ int ret; ++ struct device_node *np = pdev->dev.of_node; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ ret = snd_soc_sunxi_ahub_mem_init(pdev, np, &g_mem_info); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "remap init failed\n"); ++ ret = -EINVAL; ++ goto err_snd_soc_sunxi_ahub_mem_init; ++ } ++ ++ ret = snd_soc_sunxi_ahub_clk_init(pdev, np, &g_clk_info); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "clk init failed\n"); ++ ret = -EINVAL; ++ goto err_snd_soc_sunxi_ahub_clk_init; ++ } ++ ++ ret = snd_soc_register_component(&pdev->dev, ++ &sunxi_ahub_dam_dev, ++ &sunxi_ahub_dam_dai, 1); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "component register failed\n"); ++ ret = -ENOMEM; ++ goto err_snd_soc_register_component; ++ } ++ ++ SND_LOG_DEBUG(HLOG, "register ahub_dam platform success\n"); ++ ++ return 0; ++ ++err_snd_soc_register_component: ++err_snd_soc_sunxi_ahub_clk_init: ++err_snd_soc_sunxi_ahub_mem_init: ++ of_node_put(np); ++ return ret; ++} ++ ++static int sunxi_ahub_dam_dev_remove(struct platform_device *pdev) ++{ ++ struct sunxi_ahub_mem_info *mem_info = &g_mem_info; ++ struct sunxi_ahub_clk_info *clk_info = &g_clk_info; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ snd_soc_unregister_component(&pdev->dev); ++ ++ devm_iounmap(&pdev->dev, mem_info->membase); ++ devm_release_mem_region(&pdev->dev, mem_info->memregion->start, ++ resource_size(mem_info->memregion)); ++ ++ clk_disable_unprepare(clk_info->clk_module); ++ clk_put(clk_info->clk_module); ++ clk_disable_unprepare(clk_info->clk_pll); ++ clk_put(clk_info->clk_pll); ++ //clk_disable_unprepare(clk_info->clk_pllx4); ++ //clk_put(clk_info->clk_pllx4); ++ clk_disable_unprepare(clk_info->clk_bus); ++ clk_put(clk_info->clk_bus); ++ reset_control_assert(clk_info->clk_rst); ++ ++ SND_LOG_DEBUG(HLOG, "unregister ahub_dam platform success\n"); ++ ++ return 0; ++} ++ ++static const struct of_device_id sunxi_ahub_dam_of_match[] = { ++ { .compatible = "allwinner," DRV_NAME, }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, sunxi_ahub_dam_of_match); ++ ++static struct platform_driver sunxi_ahub_dam_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ .of_match_table = sunxi_ahub_dam_of_match, ++ }, ++ .probe = sunxi_ahub_dam_dev_probe, ++ .remove = sunxi_ahub_dam_dev_remove, ++}; ++ ++int __init sunxi_ahub_dam_dev_init(void) ++{ ++ int ret; ++ ++ ret = platform_driver_register(&sunxi_ahub_dam_driver); ++ if (ret != 0) { ++ SND_LOG_ERR(HLOG, "platform driver register failed\n"); ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ ++void __exit sunxi_ahub_dam_dev_exit(void) ++{ ++ platform_driver_unregister(&sunxi_ahub_dam_driver); ++} ++ ++late_initcall(sunxi_ahub_dam_dev_init); ++module_exit(sunxi_ahub_dam_dev_exit); ++ ++MODULE_AUTHOR("Dby@allwinnertech.com"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("sunxi soundcard platform of ahub_dam"); +diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h +new file mode 100644 +index 000000000..b7679bf54 +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h +@@ -0,0 +1,291 @@ ++/* sound\soc\sunxi\snd_sunxi_ahub_dam.h ++ * (C) Copyright 2021-2025 ++ * Allwinner Technology Co., Ltd. ++ * Dby ++ * ++ * some simple description for this code ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ */ ++#ifndef __SND_SUNXI_AHUB_DAM_H ++#define __SND_SUNXI_AHUB_DAM_H ++ ++/* SUNXI Audio Hub registers list */ ++#define SUNXI_AHUB_CTL 0x00 ++#define SUNXI_AHUB_VER 0x04 ++#define SUNXI_AHUB_RST 0x08 ++#define SUNXI_AHUB_GAT 0x0c ++ ++#define SUNXI_AHUB_APBIF_TX_CTL(n) (0x10 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_TX_IRQ_CTL(n) (0x14 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_TX_IRQ_STA(n) (0x18 + ((n) * 0x30)) ++ ++#define SUNXI_AHUB_APBIF_TXFIFO_CTL(n) (0x20 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_TXFIFO_STA(n) (0x24 + ((n) * 0x30)) ++ ++#define SUNXI_AHUB_APBIF_TXFIFO(n) (0x30 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_TXFIFO_CNT(n) (0x34 + ((n) * 0x30)) ++ ++#define SUNXI_AHUB_APBIF_RX_CTL(n) (0x100 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_RX_IRQ_CTL(n) (0x104 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_RX_IRQ_STA(n) (0x108 + ((n) * 0x30)) ++ ++#define SUNXI_AHUB_APBIF_RXFIFO_CTL(n) (0x110 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_RXFIFO_STA(n) (0x114 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_RXFIFO_CONT(n) (0x118 + ((n) * 0x30)) ++ ++#define SUNXI_AHUB_APBIF_RXFIFO(n) (0x120 + ((n) * 0x30)) ++#define SUNXI_AHUB_APBIF_RXFIFO_CNT(n) (0x124 + ((n) * 0x30)) ++ ++#define SUNXI_AHUB_I2S_CTL(n) (0x200 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_FMT0(n) (0x204 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_FMT1(n) (0x208 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_CLKD(n) (0x20c + ((n) << 8)) ++ ++#define SUNXI_AHUB_I2S_RXCONT(n) (0x220 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_CHCFG(n) (0x224 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_IRQ_CTL(n) (0x228 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_IRQ_STA(n) (0x22C + ((n) << 8)) ++#define SUNXI_AHUB_I2S_OUT_SLOT(n, m) (0x230 + ((n) << 8) + ((m) << 4)) ++#define SUNXI_AHUB_I2S_OUT_CHMAP0(n, m) (0x234 + ((n) << 8) + ((m) << 4)) ++#define SUNXI_AHUB_I2S_OUT_CHMAP1(n, m) (0x238 + ((n) << 8) + ((m) << 4)) ++ ++#define SUNXI_AHUB_I2S_IN_SLOT(n) (0x270 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_IN_CHMAP0(n) (0x274 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_IN_CHMAP1(n) (0x278 + ((n) << 8)) ++#define SUNXI_AHUB_I2S_IN_CHMAP2(n) (0x27C + ((n) << 8)) ++#define SUNXI_AHUB_I2S_IN_CHMAP3(n) (0x280 + ((n) << 8)) ++ ++#define SUNXI_AHUB_DAM_CTL(n) (0xA00 + ((n) << 7)) ++ ++#define SUNXI_AHUB_DAM_RX0_SRC(n) (0xA10 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_RX1_SRC(n) (0xA14 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_RX2_SRC(n) (0xA18 + ((n) << 7)) ++ ++#define SUNXI_AHUB_DAM_MIX_CTL0(n) (0xA30 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_MIX_CTL1(n) (0xA34 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_MIX_CTL2(n) (0xA38 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_MIX_CTL3(n) (0xA3C + ((n) << 7)) ++#define SUNXI_AHUB_DAM_MIX_CTL4(n) (0xA40 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_MIX_CTL5(n) (0xA44 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_MIX_CTL6(n) (0xA48 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_MIX_CTL7(n) (0xA4C + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL0(n) (0xA50 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL1(n) (0xA54 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL2(n) (0xA58 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL3(n) (0xA5C + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL4(n) (0xA60 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL5(n) (0xA64 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL6(n) (0xA68 + ((n) << 7)) ++#define SUNXI_AHUB_DAM_GAIN_CTL7(n) (0xA6C + ((n) << 7)) ++ ++#define SUNXI_AHUB_MAX_REG SUNXI_AHUB_DAM_GAIN_CTL7(1) ++ ++/* SUNXI_AHUB_CTL */ ++#define HDMI_SRC_SEL 0x04 ++ ++/* SUNXI_AHUB_RST */ ++#define APBIF_TXDIF0_RST 31 ++#define APBIF_TXDIF1_RST 30 ++#define APBIF_TXDIF2_RST 29 ++#define APBIF_RXDIF0_RST 27 ++#define APBIF_RXDIF1_RST 26 ++#define APBIF_RXDIF2_RST 25 ++#define I2S0_RST 23 ++#define I2S1_RST 22 ++#define I2S2_RST 21 ++#define I2S3_RST 20 ++#define DAM0_RST 15 ++#define DAM1_RST 14 ++ ++/* SUNXI_AHUB_GAT */ ++#define APBIF_TXDIF0_GAT 31 ++#define APBIF_TXDIF1_GAT 30 ++#define APBIF_TXDIF2_GAT 29 ++#define APBIF_RXDIF0_GAT 27 ++#define APBIF_RXDIF1_GAT 26 ++#define APBIF_RXDIF2_GAT 25 ++#define I2S0_GAT 23 ++#define I2S1_GAT 22 ++#define I2S2_GAT 21 ++#define I2S3_GAT 20 ++#define DAM0_GAT 15 ++#define DAM1_GAT 14 ++ ++/* SUNXI_AHUB_APBIF_TX_CTL */ ++#define APBIF_TX_WS 16 ++#define APBIF_TX_CHAN_NUM 8 ++#define APBIF_TX_START 4 ++ ++/* SUNXI_AHUB_APBIF_TX_IRQ_CTL */ ++#define APBIF_TX_DRQ 3 ++#define APBIF_TX_OVEN 1 ++#define APBIF_TX_EMEN 0 ++ ++/* SUNXI_AHUB_APBIF_TX_IRQ_STA */ ++#define APBIF_TX_OV_PEND 2 ++#define APBIF_TX_EM_PEND 0 ++ ++/* SUNXI_AHUB_APBIF_TXFIFO_CTL */ ++#define APBIF_TX_FTX 12 ++#define APBIF_TX_LEVEL 4 ++#define APBIF_TX_TXIM 0 ++ ++/* SUNXI_AHUB_APBIF_TXFIFO_STA */ ++#define APBIF_TX_EMPTY 8 ++#define APBIF_TX_EMCNT 0 ++ ++/* SUNXI_AHUB_APBIF_RX_CTL */ ++#define APBIF_RX_WS 16 ++#define APBIF_RX_CHAN_NUM 8 ++#define APBIF_RX_START 4 ++ ++/* SUNXI_AHUB_APBIF_RX_IRQ_CTL */ ++#define APBIF_RX_DRQ 3 ++#define APBIF_RX_UVEN 2 ++#define APBIF_RX_AVEN 0 ++ ++/* SUNXI_AHUB_APBIF_RX_IRQ_STA */ ++#define APBIF_RX_UV_PEND 2 ++#define APBIF_RX_AV_PEND 0 ++ ++/* SUNXI_AHUB_APBIF_RXFIFO_CTL */ ++#define APBIF_RX_FRX 12 ++#define APBIF_RX_LEVEL 4 ++#define APBIF_RX_RXOM 0 ++ ++/* SUNXI_AHUB_APBIF_RXFIFO_STA */ ++#define APBIF_RX_AVAIL 8 ++#define APBIF_RX_AVCNT 0 ++ ++/* SUNXI_AHUB_APBIF_RXFIFO_CONT */ ++#define APBIF_RX_APBIF_TXDIF0 31 ++#define APBIF_RX_APBIF_TXDIF1 30 ++#define APBIF_RX_APBIF_TXDIF2 29 ++#define APBIF_RX_I2S0_TXDIF 27 ++#define APBIF_RX_I2S1_TXDIF 26 ++#define APBIF_RX_I2S2_TXDIF 25 ++#define APBIF_RX_I2S3_TXDIF 23 ++#define APBIF_RX_DAM0_TXDIF 19 ++#define APBIF_RX_DAM1_TXDIF 15 ++ ++/* SUNXI_AHUB_I2S_CTL */ ++#define I2S_CTL_LOOP3 23 ++#define I2S_CTL_LOOP2 22 ++#define I2S_CTL_LOOP1 21 ++#define I2S_CTL_LOOP0 20 ++#define I2S_CTL_SDI3_EN 15 ++#define I2S_CTL_SDI2_EN 14 ++#define I2S_CTL_SDI1_EN 13 ++#define I2S_CTL_SDI0_EN 12 ++#define I2S_CTL_CLK_OUT 18 ++#define I2S_CTL_SDO3_EN 11 ++#define I2S_CTL_SDO2_EN 10 ++#define I2S_CTL_SDO1_EN 9 ++#define I2S_CTL_SDO0_EN 8 ++#define I2S_CTL_OUT_MUTE 6 ++#define I2S_CTL_MODE 4 ++#define I2S_CTL_TXEN 2 ++#define I2S_CTL_RXEN 1 ++#define I2S_CTL_GEN 0 ++ ++/* SUNXI_AHUB_I2S_FMT0 */ ++#define I2S_FMT0_LRCK_WIDTH 30 ++#define I2S_FMT0_LRCK_POLARITY 19 ++#define I2S_FMT0_LRCK_PERIOD 8 ++#define I2S_FMT0_BCLK_POLARITY 7 ++#define I2S_FMT0_SR 4 ++#define I2S_FMT0_EDGE 3 ++#define I2S_FMT0_SW 0 ++ ++/* SUNXI_AHUB_I2S_FMT1 */ ++#define I2S_FMT1_RX_LSB 7 ++#define I2S_FMT1_TX_LSB 6 ++#define I2S_FMT1_EXT 4 ++#define I2S_FMT1_RX_PDM 2 ++#define I2S_FMT1_TX_PDM 0 ++ ++/* SUNXI_AHUB_I2S_CLKD */ ++#define I2S_CLKD_MCLK 8 ++#define I2S_CLKD_BCLKDIV 4 ++#define I2S_CLKD_MCLKDIV 0 ++ ++/* SUNXI_AHUB_I2S_RXCONT */ ++#define I2S_RX_APBIF_TXDIF0 31 ++#define I2S_RX_APBIF_TXDIF1 30 ++#define I2S_RX_APBIF_TXDIF2 29 ++#define I2S_RX_I2S0_TXDIF 27 ++#define I2S_RX_I2S1_TXDIF 26 ++#define I2S_RX_I2S2_TXDIF 25 ++#define I2S_RX_I2S3_TXDIF 23 ++#define I2S_RX_DAM0_TXDIF 19 ++#define I2S_RX_DAM1_TXDIF 15 ++ ++/* SUNXI_AHUB_I2S_CHCFG */ ++#define I2S_CHCFG_HIZ 9 ++#define I2S_CHCFG_TX_STATE 8 ++#define I2S_CHCFG_RX_CHANNUM 4 ++#define I2S_CHCFG_TX_CHANNUM 0 ++ ++/* SUNXI_AHUB_I2S_IRQ_CTL */ ++#define I2S_IRQ_RXOV_EN 1 ++#define I2S_IRQ_TXUV_EN 0 ++ ++/* SUNXI_AHUB_I2S_IRQ_STA */ ++#define I2S_IRQ_RXOV_PEND 1 ++#define I2S_IRQ_TXUV_PEND 0 ++ ++/* SUNXI_AHUB_I2S_OUT_SLOT */ ++#define I2S_OUT_OFFSET 20 ++#define I2S_OUT_SLOT_NUM 16 ++#define I2S_OUT_SLOT_EN 0 ++ ++/* SUNXI_AHUB_I2S_IN_SLOT */ ++#define I2S_IN_OFFSET 20 ++#define I2S_IN_SLOT_NUM 16 ++ ++/* SUNXI_AHUB_DAM_CTL */ ++#define DAM_CTL_RX2_NUM 24 ++#define DAM_CTL_RX1_NUM 20 ++#define DAM_CTL_RX0_NUM 16 ++#define DAM_CTL_TX_NUM 8 ++#define DAM_CTL_RX2EN 6 ++#define DAM_CTL_RX1EN 5 ++#define DAM_CTL_RX0EN 4 ++#define DAM_CTL_TXEN 0 ++ ++/* SUNXI_AHUB_DAM_RX##chan##_SRC */ ++#define DAM_RX_APBIF_TXDIF0 31 ++#define DAM_RX_APBIF_TXDIF1 30 ++#define DAM_RX_APBIF_TXDIF2 29 ++#define DAM_RX_I2S0_TXDIF 27 ++#define DAM_RX_I2S1_TXDIF 26 ++#define DAM_RX_I2S2_TXDIF 25 ++#define DAM_RX_I2S3_TXDIF 23 ++#define DAM_RX_DAM0_TXDIF 19 ++#define DAM_RX_DAM1_TXDIF 15 ++ ++struct sunxi_ahub_mem_info { ++ char *dev_name; ++ struct resource *res; ++ void __iomem *membase; ++ struct resource *memregion; ++ struct regmap *regmap; ++}; ++ ++struct sunxi_ahub_clk_info { ++ struct clk *clk_pll; ++ struct clk *clk_pllx4; ++ struct clk *clk_module; ++ struct clk *clk_bus; ++ struct reset_control *clk_rst; ++}; ++ ++extern int snd_soc_sunxi_ahub_mem_get(struct sunxi_ahub_mem_info *mem_info); ++extern int snd_soc_sunxi_ahub_clk_get(struct sunxi_ahub_clk_info *clk_info); ++ ++#endif /* __SND_SUNXI_AHUB_DAM_H */ +\ No newline at end of file +diff --git a/sound/soc/sunxi_v2/snd_sunxi_common.c b/sound/soc/sunxi_v2/snd_sunxi_common.c +new file mode 100644 +index 000000000..410ab75ae +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_common.c +@@ -0,0 +1,267 @@ ++/* ++ * sound\soc\sunxi\snd_sunxi_common.c ++ * (C) Copyright 2021-2025 ++ * AllWinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#include "snd_sunxi_log.h" ++#include "snd_sunxi_common.h" ++ ++#define HLOG "COMMON" ++ ++/* for regmap */ ++int snd_sunxi_mem_init(struct platform_device *pdev, ++ struct sunxi_mem_info *mem_info) ++{ ++ int ret = 0; ++ struct device_node *np = pdev->dev.of_node; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ ret = of_address_to_resource(np, 0, mem_info->res); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "parse device node resource failed\n"); ++ ret = -EINVAL; ++ goto err_of_addr_to_resource; ++ } ++ ++ mem_info->memregion = devm_request_mem_region(&pdev->dev, ++ mem_info->res->start, ++ resource_size(mem_info->res), ++ mem_info->dev_name); ++ if (IS_ERR_OR_NULL(mem_info->memregion)) { ++ SND_LOG_ERR(HLOG, "memory region already claimed\n"); ++ ret = -EBUSY; ++ goto err_devm_request_region; ++ } ++ ++ mem_info->membase = devm_ioremap(&pdev->dev, ++ mem_info->memregion->start, ++ resource_size(mem_info->memregion)); ++ if (IS_ERR_OR_NULL(mem_info->membase)) { ++ SND_LOG_ERR(HLOG, "ioremap failed\n"); ++ ret = -EBUSY; ++ goto err_devm_ioremap; ++ } ++ ++ mem_info->regmap = devm_regmap_init_mmio(&pdev->dev, ++ mem_info->membase, ++ mem_info->regmap_config); ++ if (IS_ERR_OR_NULL(mem_info->regmap)) { ++ SND_LOG_ERR(HLOG, "regmap init failed\n"); ++ ret = -EINVAL; ++ goto err_devm_regmap_init; ++ } ++ ++ return 0; ++ ++err_devm_regmap_init: ++ devm_iounmap(&pdev->dev, mem_info->membase); ++err_devm_ioremap: ++ devm_release_mem_region(&pdev->dev, mem_info->memregion->start, ++ resource_size(mem_info->memregion)); ++err_devm_request_region: ++err_of_addr_to_resource: ++ return ret; ++} ++ ++void snd_sunxi_mem_exit(struct platform_device *pdev, ++ struct sunxi_mem_info *mem_info) ++{ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ devm_iounmap(&pdev->dev, mem_info->membase); ++ devm_release_mem_region(&pdev->dev, mem_info->memregion->start, ++ resource_size(mem_info->memregion)); ++} ++ ++/* for reg labels */ ++int snd_sunxi_save_reg(struct regmap *regmap, struct reg_label *reg_labels) ++{ ++ int i = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ while (reg_labels[i].name != NULL) { ++ regmap_read(regmap, ++ reg_labels[i].address, &(reg_labels[i].value)); ++ i++; ++ } ++ ++ return i; ++} ++ ++int snd_sunxi_echo_reg(struct regmap *regmap, struct reg_label *reg_labels) ++{ ++ int i = 0; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ while (reg_labels[i].name != NULL) { ++ regmap_write(regmap, ++ reg_labels[i].address, reg_labels[i].value); ++ i++; ++ } ++ ++ return i; ++} ++ ++/* for pa config */ ++struct pa_config *snd_sunxi_pa_pin_init(struct platform_device *pdev, ++ u32 *pa_pin_max) ++{ ++ int ret, i; ++ u32 pin_max; ++ u32 gpio_tmp; ++ u32 temp_val; ++ char str[20] = {0}; ++ struct pa_config *pa_cfg; ++ struct device_node *np = pdev->dev.of_node; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ *pa_pin_max = 0; ++ ret = of_property_read_u32(np, "pa_pin_max", &temp_val); ++ if (ret < 0) { ++ SND_LOG_WARN(HLOG, "pa_pin_max get failed, default 0\n"); ++ return NULL; ++ } else { ++ pin_max = temp_val; ++ } ++ ++ pa_cfg = kzalloc(sizeof(struct pa_config) * pin_max, GFP_KERNEL); ++ if (!pa_cfg) { ++ SND_LOG_ERR(HLOG, "can't pa_config memory\n"); ++ return NULL; ++ } ++ ++ for (i = 0; i < pin_max; i++) { ++ sprintf(str, "pa_pin_%d", i); ++ ret = of_get_named_gpio(np, str, 0); ++ if (ret < 0) { ++ SND_LOG_ERR(HLOG, "pa_pin_%u get failed\n", i); ++ pa_cfg[i].used = 0; ++ continue; ++ } ++ gpio_tmp = ret; ++ if (!gpio_is_valid(gpio_tmp)) { ++ SND_LOG_ERR(HLOG, "pa_pin_%u (%u) is invalid\n", ++ i, gpio_tmp); ++ pa_cfg[i].used = 0; ++ continue; ++ } ++ ret = devm_gpio_request(&pdev->dev, gpio_tmp, str); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "pa_pin_%u (%u) request failed\n", ++ i, gpio_tmp); ++ pa_cfg[i].used = 0; ++ continue; ++ } ++ pa_cfg[i].used = 1; ++ pa_cfg[i].pin = gpio_tmp; ++ ++ sprintf(str, "pa_pin_level_%d", i); ++ ret = of_property_read_u32(np, str, &temp_val); ++ if (ret < 0) { ++ SND_LOG_WARN(HLOG, "%s get failed, default low\n", str); ++ pa_cfg[i].level = 0; ++ } else { ++ if (temp_val > 0) ++ pa_cfg[i].level = 1; ++ } ++ sprintf(str, "pa_pin_msleep_%d", i); ++ ret = of_property_read_u32(np, str, &temp_val); ++ if (ret < 0) { ++ SND_LOG_WARN(HLOG, "%s get failed, default 0\n", str); ++ pa_cfg[i].msleep = 0; ++ } else { ++ pa_cfg[i].msleep = temp_val; ++ } ++ } ++ ++ *pa_pin_max = pin_max; ++ snd_sunxi_pa_pin_disable(pa_cfg, pin_max); ++ ++ return pa_cfg; ++} ++ ++void snd_sunxi_pa_pin_exit(struct platform_device *pdev, ++ struct pa_config *pa_cfg, u32 pa_pin_max) ++{ ++ int i; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ snd_sunxi_pa_pin_disable(pa_cfg, pa_pin_max); ++ ++ for (i = 0; i < pa_pin_max; i++) { ++ if (!pa_cfg[i].used) ++ continue; ++ ++ gpio_free(pa_cfg[i].pin); ++ } ++ ++ if (pa_cfg) ++ kfree(pa_cfg); ++} ++ ++int snd_sunxi_pa_pin_enable(struct pa_config *pa_cfg, u32 pa_pin_max) ++{ ++ int i; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (pa_pin_max < 1) { ++ SND_LOG_DEBUG(HLOG, "no pa pin config\n"); ++ return 0; ++ } ++ ++ for (i = 0; i < pa_pin_max; i++) { ++ if (!pa_cfg[i].used) ++ continue; ++ ++ gpio_direction_output(pa_cfg[i].pin, 1); ++ gpio_set_value(pa_cfg[i].pin, pa_cfg[i].level); ++ } ++ ++ return 0; ++} ++ ++void snd_sunxi_pa_pin_disable(struct pa_config *pa_cfg, u32 pa_pin_max) ++{ ++ int i; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (pa_pin_max < 1) { ++ SND_LOG_DEBUG(HLOG, "no pa pin config\n"); ++ return; ++ } ++ ++ for (i = 0; i < pa_pin_max; i++) { ++ if (!pa_cfg[i].used) ++ continue; ++ ++ gpio_direction_output(pa_cfg[i].pin, 1); ++ gpio_set_value(pa_cfg[i].pin, !pa_cfg[i].level); ++ } ++} +diff --git a/sound/soc/sunxi_v2/snd_sunxi_common.h b/sound/soc/sunxi_v2/snd_sunxi_common.h +new file mode 100644 +index 000000000..7b88d20c2 +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_common.h +@@ -0,0 +1,67 @@ ++/* sound\soc\sunxi\snd_sunxi_common.h ++ * (C) Copyright 2021-2025 ++ * Allwinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#ifndef __SND_SUNXI_COMMON_H ++#define __SND_SUNXI_COMMON_H ++ ++/* for regmap */ ++struct sunxi_mem_info { ++ char *dev_name; ++ struct resource *res; ++ struct regmap_config *regmap_config; ++ ++ void __iomem *membase; ++ struct resource *memregion; ++ struct regmap *regmap; ++}; ++ ++int snd_sunxi_mem_init(struct platform_device *pdev, ++ struct sunxi_mem_info *mem_info); ++void snd_sunxi_mem_exit(struct platform_device *pdev, ++ struct sunxi_mem_info *mem_info); ++ ++/* for reg debug */ ++#define REG_LABEL(constant) {#constant, constant, 0} ++#define REG_LABEL_END {NULL, 0, 0} ++ ++struct reg_label { ++ const char *name; ++ const unsigned int address; ++ unsigned int value; ++}; ++ ++/* EX: ++ * static struct reg_label reg_labels[] = { ++ * REG_LABEL(SUNXI_REG_0), ++ * REG_LABEL(SUNXI_REG_1), ++ * REG_LABEL(SUNXI_REG_n), ++ * REG_LABEL_END, ++ * }; ++ */ ++int snd_sunxi_save_reg(struct regmap *regmap, struct reg_label *reg_labels); ++int snd_sunxi_echo_reg(struct regmap *regmap, struct reg_label *reg_labels); ++ ++/* for pa config */ ++struct pa_config { ++ u32 pin; ++ u32 msleep; ++ bool used; ++ bool level; ++}; ++ ++struct pa_config *snd_sunxi_pa_pin_init(struct platform_device *pdev, ++ u32 *pa_pin_max); ++void snd_sunxi_pa_pin_exit(struct platform_device *pdev, ++ struct pa_config *pa_cfg, u32 pa_pin_max); ++int snd_sunxi_pa_pin_enable(struct pa_config *pa_cfg, u32 pa_pin_max); ++void snd_sunxi_pa_pin_disable(struct pa_config *pa_cfg, u32 pa_pin_max); ++ ++#endif /* __SND_SUNXI_COMMON_H */ +\ No newline at end of file +diff --git a/sound/soc/sunxi_v2/snd_sunxi_log.h b/sound/soc/sunxi_v2/snd_sunxi_log.h +new file mode 100644 +index 000000000..89ad9fe71 +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_log.h +@@ -0,0 +1,29 @@ ++/* ++ * sound\soc\sunxi\snd_sunxi_log.h ++ * (C) Copyright 2021-2025 ++ * allwinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#ifndef __SND_SUNXI_LOG_H ++#define __SND_SUNXI_LOG_H ++#include ++ ++#define SND_LOG_ERR(head, fmt, arg...) \ ++ pr_err("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg) ++ ++#define SND_LOG_WARN(head, fmt, arg...) \ ++ pr_warn("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg) ++ ++#define SND_LOG_INFO(head, fmt, arg...) \ ++ pr_info("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg) ++ ++#define SND_LOG_DEBUG(head, fmt, arg...) \ ++ pr_debug("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg) ++ ++#endif /* __SND_SUNXI_LOG_H */ +diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach.c b/sound/soc/sunxi_v2/snd_sunxi_mach.c +new file mode 100644 +index 000000000..27449ad6b +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_mach.c +@@ -0,0 +1,479 @@ ++/* ++ * sound\soc\sunxi\snd_sunxi_mach.c ++ * (C) Copyright 2021-2025 ++ * AllWinner Technology Co., Ltd. ++ * Dby ++ * ++ * based on ${LINUX}/sound/soc/generic/simple-card.c ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++ ++#include "snd_sunxi_log.h" ++#include "snd_sunxi_mach.h" ++ ++#define HLOG "MACH" ++#define DAI "sound-dai" ++#define CELL "#sound-dai-cells" ++#define PREFIX "soundcard-mach," ++ ++#define DRV_NAME "sunxi-snd-mach" ++ ++static void asoc_simple_shutdown(struct snd_pcm_substream *substream) ++{ ++} ++ ++static int asoc_simple_startup(struct snd_pcm_substream *substream) ++{ ++ return 0; ++} ++ ++static int asoc_simple_hw_params(struct snd_pcm_substream *substream, ++ struct snd_pcm_hw_params *params) ++{ ++ struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream); ++ ++ struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0); ++ struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0); ++ ++ struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(rtd->card); ++ struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, rtd->num); ++ struct simple_dai_props *dai_props = simple_priv_to_props(priv, rtd->num); ++ struct asoc_simple_dai *dais = priv->dais; ++ unsigned int mclk; ++ unsigned int cpu_pll_clk, codec_pll_clk; ++ unsigned int cpu_bclk_ratio, codec_bclk_ratio; ++ unsigned int freq_point; ++ int cpu_clk_div, codec_clk_div; ++ int ret = 0; ++ ++ switch (params_rate(params)) { ++ case 8000: ++ case 12000: ++ case 16000: ++ case 24000: ++ case 32000: ++ case 48000: ++ case 64000: ++ case 96000: ++ case 192000: ++ freq_point = 24576000; ++ break; ++ case 11025: ++ case 22050: ++ case 44100: ++ case 88200: ++ case 176400: ++ freq_point = 22579200; ++ break; ++ default: ++ SND_LOG_ERR(HLOG, "Invalid rate %d\n", params_rate(params)); ++ return -EINVAL; ++ } ++ ++ /* for cpudai pll clk */ ++ cpu_pll_clk = freq_point * dai_props->cpu_pll_fs; ++ codec_pll_clk = freq_point * dai_props->codec_pll_fs; ++ cpu_clk_div = cpu_pll_clk / params_rate(params); ++ codec_clk_div = codec_pll_clk / params_rate(params); ++ SND_LOG_DEBUG(HLOG, "freq point : %u\n", freq_point); ++ SND_LOG_DEBUG(HLOG, "cpu pllclk : %u\n", cpu_pll_clk); ++ SND_LOG_DEBUG(HLOG, "codec pllclk : %u\n", codec_pll_clk); ++ SND_LOG_DEBUG(HLOG, "cpu clk_div : %u\n", cpu_clk_div); ++ SND_LOG_DEBUG(HLOG, "codec clk_div: %u\n", codec_clk_div); ++ ++ if (cpu_dai->driver->ops->set_pll) { ++ ret = snd_soc_dai_set_pll(cpu_dai, substream->stream, 0, ++ cpu_pll_clk, cpu_pll_clk); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cpu_dai set pllclk failed\n"); ++ return ret; ++ } ++ } ++ if (codec_dai->driver->ops->set_pll) { ++ ret = snd_soc_dai_set_pll(codec_dai, substream->stream, 0, ++ codec_pll_clk, codec_pll_clk); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "codec_dai set pllclk failed\n"); ++ return ret; ++ } ++ } ++ ++ if (cpu_dai->driver->ops->set_clkdiv) { ++ ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, cpu_clk_div); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cpu_dai set clk_div failed\n"); ++ return ret; ++ } ++ } ++ if (codec_dai->driver->ops->set_clkdiv) { ++ ret = snd_soc_dai_set_clkdiv(codec_dai, 0, codec_clk_div); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cadec_dai set clk_div failed.\n"); ++ return ret; ++ } ++ } ++ ++ /* use for tdm only */ ++ if (!(dais->slots && dais->slot_width)) ++ return 0; ++ ++ /* for cpudai & codecdai mclk */ ++ if (dai_props->mclk_fp) ++ mclk = (freq_point >> 1) * dai_props->mclk_fs; ++ else ++ mclk = params_rate(params) * dai_props->mclk_fs; ++ cpu_bclk_ratio = cpu_pll_clk / (params_rate(params) * dais->slot_width * dais->slots); ++ codec_bclk_ratio = codec_pll_clk / (params_rate(params) * dais->slot_width * dais->slots); ++ SND_LOG_DEBUG(HLOG, "mclk : %u\n", mclk); ++ SND_LOG_DEBUG(HLOG, "cpu_bclk_ratio : %u\n", cpu_bclk_ratio); ++ SND_LOG_DEBUG(HLOG, "codec_bclk_ratio: %u\n", codec_bclk_ratio); ++ ++ if (cpu_dai->driver->ops->set_sysclk) { ++ ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk, SND_SOC_CLOCK_OUT); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cpu_dai set sysclk(mclk) failed\n"); ++ return ret; ++ } ++ } ++ if (codec_dai->driver->ops->set_sysclk) { ++ ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk, SND_SOC_CLOCK_IN); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cadec_dai set sysclk(mclk) failed\n"); ++ return ret; ++ } ++ } ++ ++ if (cpu_dai->driver->ops->set_bclk_ratio) { ++ ret = snd_soc_dai_set_bclk_ratio(cpu_dai, cpu_bclk_ratio); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cpu_dai set bclk failed\n"); ++ return ret; ++ } ++ } ++ if (codec_dai->driver->ops->set_bclk_ratio) { ++ ret = snd_soc_dai_set_bclk_ratio(codec_dai, codec_bclk_ratio); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "codec_dai set bclk failed\n"); ++ return ret; ++ } ++ } ++ ++ if (cpu_dai->driver->ops->set_fmt) { ++ ret = snd_soc_dai_set_fmt(cpu_dai, dai_link->dai_fmt); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cpu dai set fmt failed\n"); ++ return ret; ++ } ++ } ++ if (codec_dai->driver->ops->set_fmt) { ++ ret = snd_soc_dai_set_fmt(codec_dai, dai_link->dai_fmt); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "codec dai set fmt failed\n"); ++ return ret; ++ } ++ } ++ ++ if (cpu_dai->driver->ops->set_tdm_slot) { ++ ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, 0, dais->slots, dais->slot_width); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "cpu dai set tdm slot failed\n"); ++ return ret; ++ } ++ } ++ if (codec_dai->driver->ops->set_tdm_slot) { ++ ret = snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, dais->slots, dais->slot_width); ++ if (ret) { ++ SND_LOG_ERR(HLOG, "codec dai set tdm slot failed\n"); ++ return ret; ++ } ++ } ++ ++ return 0; ++} ++ ++static struct snd_soc_ops simple_ops = { ++ .startup = asoc_simple_startup, ++ .shutdown = asoc_simple_shutdown, ++ .hw_params = asoc_simple_hw_params, ++}; ++ ++static int asoc_simple_dai_init(struct snd_soc_pcm_runtime *rtd) ++{ ++ int i; ++ struct snd_soc_card *card = rtd->card; ++ struct snd_soc_dapm_context *dapm = &card->dapm; ++ ++ const struct snd_kcontrol_new *controls = card->controls; ++ ++ for (i = 0; i < card->num_controls; i++) ++ if (controls[i].info == snd_soc_dapm_info_pin_switch) ++ snd_soc_dapm_disable_pin(dapm, ++ (const char *)controls[i].private_value); ++ ++ if (card->num_controls) ++ snd_soc_dapm_sync(dapm); ++ ++ /* snd_soc_dai_set_sysclk(); */ ++ /* snd_soc_dai_set_tdm_slot(); */ ++ ++ return 0; ++} ++ ++static int simple_dai_link_of(struct device_node *node, ++ struct asoc_simple_priv *priv) ++{ ++ struct device *dev = simple_priv_to_dev(priv); ++ struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, 0); ++ struct simple_dai_props *dai_props = simple_priv_to_props(priv, 0); ++ struct device_node *top_np = NULL; ++ struct device_node *cpu = NULL; ++ struct device_node *plat = NULL; ++ struct device_node *codec = NULL; ++ char prop[128]; ++ char *prefix = ""; ++ int ret, single_cpu; ++ ++ prefix = PREFIX; ++ top_np = node; ++ ++ snprintf(prop, sizeof(prop), "%scpu", prefix); ++ cpu = of_get_child_by_name(top_np, prop); ++ if (!cpu) { ++ ret = -EINVAL; ++ SND_LOG_ERR(HLOG, "Can't find %s DT node\n", prop); ++ goto dai_link_of_err; ++ } ++ snprintf(prop, sizeof(prop), "%splat", prefix); ++ plat = of_get_child_by_name(top_np, prop); ++ ++ snprintf(prop, sizeof(prop), "%scodec", prefix); ++ codec = of_get_child_by_name(top_np, prop); ++ if (!codec) { ++ ret = -EINVAL; ++ SND_LOG_ERR(HLOG, "Can't find %s DT node\n", prop); ++ goto dai_link_of_err; ++ } ++ ++ ret = asoc_simple_parse_daifmt(top_np, codec, prefix, &dai_link->dai_fmt); ++ if (ret < 0) ++ goto dai_link_of_err; ++ /* sunxi: parse stream direction ++ * ex1) ++ * top_node { ++ * PREFIXplayback-only; ++ * } ++ * ex2) ++ * top_node { ++ * PREFIXcapture-only; ++ * } ++ */ ++ ret = asoc_simple_parse_daistream(top_np, prefix, dai_link); ++ if (ret < 0) ++ goto dai_link_of_err; ++ /* sunxi: parse slot-num & slot-width ++ * ex) ++ * top_node { ++ * PREFIXplayslot-num = ; ++ * PREFIXplayslot-width = ; ++ * } ++ */ ++ ret = asoc_simple_parse_tdm_slot(top_np, prefix, priv->dais); ++ if (ret < 0) ++ goto dai_link_of_err; ++ ++ ret = asoc_simple_parse_cpu(cpu, dai_link, DAI, CELL, &single_cpu); ++ if (ret < 0) ++ goto dai_link_of_err; ++ ret = asoc_simple_parse_codec(codec, dai_link, DAI, CELL); ++ if (ret < 0) { ++ if (ret == -EPROBE_DEFER) ++ goto dai_link_of_err; ++ dai_link->codecs->name = "snd-soc-dummy"; ++ dai_link->codecs->dai_name = "snd-soc-dummy-dai"; ++ /* dai_link->codecs->name = "sunxi-dummy-codec"; */ ++ /* dai_link->codecs->dai_name = "sunxi-dummy-codec-dai"; */ ++ SND_LOG_DEBUG(HLOG, "use dummy codec for simple card.\n"); ++ } ++ ret = asoc_simple_parse_platform(plat, dai_link, DAI, CELL); ++ if (ret < 0) ++ goto dai_link_of_err; ++ ++ /* sunxi: parse pll-fs & mclk-fs ++ * ex) ++ * top_node { ++ * PREFIXcpu { ++ * PREFIXpll-fs = ; ++ * PREFIXmclk-fs = ; ++ * } ++ * } ++ */ ++ ret = asoc_simple_parse_tdm_clk(cpu, codec, prefix, dai_props); ++ if (ret < 0) ++ goto dai_link_of_err; ++ ++ ret = asoc_simple_set_dailink_name(dev, dai_link, ++ "%s-%s", ++ dai_link->cpus->dai_name, ++ dai_link->codecs->dai_name); ++ if (ret < 0) ++ goto dai_link_of_err; ++ ++ dai_link->ops = &simple_ops; ++ dai_link->init = asoc_simple_dai_init; ++ ++ SND_LOG_DEBUG(HLOG, "name : %s\n", dai_link->stream_name); ++ SND_LOG_DEBUG(HLOG, "format : %x\n", dai_link->dai_fmt); ++ SND_LOG_DEBUG(HLOG, "cpu : %s\n", dai_link->cpus->name); ++ SND_LOG_DEBUG(HLOG, "codec : %s\n", dai_link->codecs->name); ++ ++ asoc_simple_canonicalize_cpu(dai_link, single_cpu); ++ asoc_simple_canonicalize_platform(dai_link); ++ ++dai_link_of_err: ++ of_node_put(cpu); ++ of_node_put(plat); ++ of_node_put(codec); ++ ++ return ret; ++} ++ ++static int simple_parse_of(struct asoc_simple_priv *priv) ++{ ++ int ret; ++ struct device *dev = simple_priv_to_dev(priv); ++ struct snd_soc_card *card = simple_priv_to_card(priv); ++ struct device_node *top_np = dev->of_node; ++ ++ SND_LOG_DEBUG(HLOG, "\n"); ++ ++ if (!top_np) ++ return -EINVAL; ++ ++ /* DAPM widgets */ ++ ret = asoc_simple_parse_widgets(card, PREFIX); ++ if (ret < 0) ++ return ret; ++ ++ /* DAPM routes */ ++ ret = asoc_simple_parse_routing(card, PREFIX); ++ if (ret < 0) ++ return ret; ++ ++ /* DAPM pin_switches */ ++ ret = asoc_simple_parse_pin_switches(card, PREFIX); ++ if (ret < 0) ++ return ret; ++ ++ /* For single DAI link & old style of DT node */ ++ ret = simple_dai_link_of(top_np, priv); ++ if (ret < 0) ++ return ret; ++ ++ ret = asoc_simple_parse_card_name(card, PREFIX); ++ return ret; ++} ++ ++static int simple_soc_probe(struct snd_soc_card *card) ++{ ++ return 0; ++} ++ ++static int asoc_simple_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct device_node *top_np = dev->of_node; ++ struct asoc_simple_priv *priv; ++ struct snd_soc_card *card; ++ int ret; ++ ++ /* Allocate the private data and the DAI link array */ ++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); ++ if (!priv) ++ return -ENOMEM; ++ ++ card = simple_priv_to_card(priv); ++ card->owner = THIS_MODULE; ++ card->dev = dev; ++ card->probe = simple_soc_probe; ++ ++ ret = asoc_simple_init_priv(priv); ++ if (ret < 0) ++ return ret; ++ ++ if (top_np && of_device_is_available(top_np)) { ++ ret = simple_parse_of(priv); ++ if (ret < 0) { ++ if (ret != -EPROBE_DEFER) ++ SND_LOG_ERR(HLOG, "parse error %d\n", ret); ++ goto err; ++ } ++ } else { ++ SND_LOG_ERR(HLOG, "simple card dts available\n"); ++ } ++ ++ snd_soc_card_set_drvdata(card, priv); ++ ++ /* asoc_simple_debug_info(priv); */ ++ ret = devm_snd_soc_register_card(dev, card); ++ if (ret >= 0) ++ return ret; ++err: ++ asoc_simple_clean_reference(card); ++ ++ return ret; ++} ++ ++static int asoc_simple_remove(struct platform_device *pdev) ++{ ++ struct snd_soc_card *card = platform_get_drvdata(pdev); ++ ++ return asoc_simple_clean_reference(card); ++} ++ ++static const struct of_device_id snd_soc_sunxi_of_match[] = { ++ { .compatible = "allwinner," DRV_NAME, }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, snd_soc_sunxi_of_match); ++ ++static struct platform_driver sunxi_soundcard_machine_driver = { ++ .driver = { ++ .name = DRV_NAME, ++ .pm = &snd_soc_pm_ops, ++ .of_match_table = snd_soc_sunxi_of_match, ++ }, ++ .probe = asoc_simple_probe, ++ .remove = asoc_simple_remove, ++}; ++ ++int __init sunxi_soundcard_machine_dev_init(void) ++{ ++ int ret; ++ ++ ret = platform_driver_register(&sunxi_soundcard_machine_driver); ++ if (ret != 0) { ++ SND_LOG_ERR(HLOG, "platform driver register failed\n"); ++ return -EINVAL; ++ } ++ ++ return ret; ++} ++ ++void __exit sunxi_soundcard_machine_dev_exit(void) ++{ ++ platform_driver_unregister(&sunxi_soundcard_machine_driver); ++} ++ ++late_initcall(sunxi_soundcard_machine_dev_init); ++module_exit(sunxi_soundcard_machine_dev_exit); ++ ++MODULE_AUTHOR("Dby@allwinnertech.com"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("sunxi soundcard machine"); +diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach.h b/sound/soc/sunxi_v2/snd_sunxi_mach.h +new file mode 100644 +index 000000000..ab429c884 +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_mach.h +@@ -0,0 +1,17 @@ ++/* sound\soc\sunxi\snd_sunxi_mach.h ++ * (C) Copyright 2021-2025 ++ * Allwinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#ifndef __SND_SUNXI_MACH_H ++#define __SND_SUNXI_MACH_H ++ ++#include "snd_sunxi_mach_utils.h" ++ ++#endif /* __SND_SUNXI_MACH_H */ +diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c +new file mode 100644 +index 000000000..15f474e5c +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c +@@ -0,0 +1,422 @@ ++/* ++ * sound\soc\sunxi\snd_sunxi_mach_utils.c ++ * (C) Copyright 2021-2025 ++ * AllWinner Technology Co., Ltd. ++ * Dby ++ * ++ * based on ${LINUX}/sound/soc/generic/simple-card.c ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#include ++#include ++#include ++ ++#include "snd_sunxi_log.h" ++#include "snd_sunxi_mach_utils.h" ++ ++#define HLOG "mach_utils" ++ ++int asoc_simple_clean_reference(struct snd_soc_card *card) ++{ ++ struct snd_soc_dai_link *dai_link; ++ int i; ++ ++ for_each_card_prelinks(card, i, dai_link) { ++ of_node_put(dai_link->cpus->of_node); ++ of_node_put(dai_link->codecs->of_node); ++ } ++ return 0; ++} ++ ++int asoc_simple_init_priv(struct asoc_simple_priv *priv) ++{ ++ struct snd_soc_card *card = simple_priv_to_card(priv); ++ struct device *dev = simple_priv_to_dev(priv); ++ struct snd_soc_dai_link *dai_link; ++ struct simple_dai_props *dai_props; ++ struct asoc_simple_dai *dais; ++ struct snd_soc_codec_conf *cconf = NULL; ++ ++ dai_props = devm_kcalloc(dev, 1, sizeof(*dai_props), GFP_KERNEL); ++ dai_link = devm_kcalloc(dev, 1, sizeof(*dai_link), GFP_KERNEL); ++ dais = devm_kcalloc(dev, 1, sizeof(*dais), GFP_KERNEL); ++ if (!dai_props || !dai_link || !dais) ++ return -ENOMEM; ++ ++ /* ++ if (li->conf) { ++ cconf = devm_kcalloc(dev, li->conf, sizeof(*cconf), GFP_KERNEL); ++ if (!cconf) ++ return -ENOMEM; ++ } ++ */ ++ ++ /* ++ * Use snd_soc_dai_link_component instead of legacy style ++ * It is codec only. but cpu/platform will be supported in the future. ++ * see ++ * soc-core.c :: snd_soc_init_multicodec() ++ * ++ * "platform" might be removed ++ * see ++ * simple-card-utils.c :: asoc_simple_canonicalize_platform() ++ */ ++ dai_link->cpus = &dai_props->cpus; ++ dai_link->num_cpus = 1; ++ dai_link->codecs = &dai_props->codecs; ++ dai_link->num_codecs = 1; ++ dai_link->platforms = &dai_props->platforms; ++ dai_link->num_platforms = 1; ++ ++ priv->dai_props = dai_props; ++ priv->dai_link = dai_link; ++ priv->dais = dais; ++ priv->codec_conf = cconf; ++ ++ card->dai_link = priv->dai_link; ++ card->num_links = 1; ++ card->codec_conf = cconf; ++ card->num_configs = 0; ++ ++ return 0; ++} ++ ++int asoc_simple_parse_widgets(struct snd_soc_card *card, char *prefix) ++{ ++ struct device_node *node = card->dev->of_node; ++ char prop[128]; ++ ++ if (!prefix) ++ prefix = ""; ++ ++ snprintf(prop, sizeof(prop), "%s%s", prefix, "widgets"); ++ ++ if (of_property_read_bool(node, prop)) ++ return snd_soc_of_parse_audio_simple_widgets(card, prop); ++ ++ /* no widgets is not error */ ++ return 0; ++} ++ ++int asoc_simple_parse_routing(struct snd_soc_card *card, char *prefix) ++{ ++ struct device_node *node = card->dev->of_node; ++ char prop[128]; ++ ++ if (!prefix) ++ prefix = ""; ++ ++ snprintf(prop, sizeof(prop), "%s%s", prefix, "routing"); ++ ++ if (!of_property_read_bool(node, prop)) ++ return 0; ++ ++ return snd_soc_of_parse_audio_routing(card, prop); ++} ++ ++int asoc_simple_parse_pin_switches(struct snd_soc_card *card, char *prefix) ++{ ++ const unsigned int nb_controls_max = 16; ++ const char **strings, *control_name; ++ struct snd_kcontrol_new *controls; ++ struct device *dev = card->dev; ++ unsigned int i, nb_controls; ++ char prop[128]; ++ int ret; ++ ++ if (!prefix) ++ prefix = ""; ++ ++ snprintf(prop, sizeof(prop), "%s%s", prefix, "pin-switches"); ++ ++ if (!of_property_read_bool(dev->of_node, prop)) ++ return 0; ++ ++ strings = devm_kcalloc(dev, nb_controls_max, ++ sizeof(*strings), GFP_KERNEL); ++ if (!strings) ++ return -ENOMEM; ++ ++ ret = of_property_read_string_array(dev->of_node, prop, ++ strings, nb_controls_max); ++ if (ret < 0) ++ return ret; ++ ++ nb_controls = (unsigned int)ret; ++ ++ controls = devm_kcalloc(dev, nb_controls, ++ sizeof(*controls), GFP_KERNEL); ++ if (!controls) ++ return -ENOMEM; ++ ++ for (i = 0; i < nb_controls; i++) { ++ control_name = devm_kasprintf(dev, GFP_KERNEL, ++ "%s Switch", strings[i]); ++ if (!control_name) ++ return -ENOMEM; ++ ++ controls[i].iface = SNDRV_CTL_ELEM_IFACE_MIXER; ++ controls[i].name = control_name; ++ controls[i].info = snd_soc_dapm_info_pin_switch; ++ controls[i].get = snd_soc_dapm_get_pin_switch; ++ controls[i].put = snd_soc_dapm_put_pin_switch; ++ controls[i].private_value = (unsigned long)strings[i]; ++ } ++ ++ card->controls = controls; ++ card->num_controls = nb_controls; ++ ++ return 0; ++} ++ ++int asoc_simple_parse_daifmt(struct device_node *node, ++ struct device_node *codec, ++ char *prefix, ++ unsigned int *retfmt) ++{ ++ struct device_node *bitclkmaster = NULL; ++ struct device_node *framemaster = NULL; ++ unsigned int daifmt; ++ ++ daifmt = snd_soc_daifmt_parse_format(node, prefix); ++ ++ snd_soc_daifmt_parse_clock_provider_as_phandle(node, prefix, &bitclkmaster, &framemaster); ++ if (!bitclkmaster && !framemaster) { ++ /* ++ * No dai-link level and master setting was not found from ++ * sound node level, revert back to legacy DT parsing and ++ * take the settings from codec node. ++ */ ++ SND_LOG_DEBUG(HLOG, "Revert to legacy daifmt parsing\n"); ++ ++ daifmt |= snd_soc_daifmt_parse_clock_provider_as_flag(codec, NULL); ++ } else { ++ daifmt |= snd_soc_daifmt_clock_provider_from_bitmap( ++ ((codec == bitclkmaster) << 4) | (codec == framemaster)); ++ } ++ ++ of_node_put(bitclkmaster); ++ of_node_put(framemaster); ++ ++ *retfmt = daifmt; ++ ++ return 0; ++} ++ ++int asoc_simple_parse_daistream(struct device_node *node, char *prefix, ++ struct snd_soc_dai_link *dai_link) ++{ ++ char prop[128]; ++ ++ if (!prefix) ++ prefix = ""; ++ ++ /* check "[prefix]playback-only" */ ++ snprintf(prop, sizeof(prop), "%splayback-only", prefix); ++ if (of_property_read_bool(node, prop)) ++ dai_link->playback_only = 1; ++ ++ /* check "[prefix]capture-only" */ ++ snprintf(prop, sizeof(prop), "%scapture-only", prefix); ++ if (of_property_read_bool(node, prop)) ++ dai_link->capture_only = 1; ++ ++ return 0; ++} ++ ++int asoc_simple_parse_tdm_slot(struct device_node *node, char *prefix, ++ struct asoc_simple_dai *dais) ++{ ++ int ret; ++ char prop[128]; ++ unsigned int val; ++ ++ if (!prefix) ++ prefix = ""; ++ ++ snprintf(prop, sizeof(prop), "%sslot-num", prefix); ++ ret = of_property_read_u32(node, prop, &val); ++ if (!ret) ++ dais->slots = val; ++ ++ snprintf(prop, sizeof(prop), "%sslot-width", prefix); ++ ret = of_property_read_u32(node, prop, &val); ++ if (!ret) ++ dais->slot_width = val; ++ ++ return 0; ++} ++ ++int asoc_simple_parse_tdm_clk(struct device_node *cpu, ++ struct device_node *codec, ++ char *prefix, ++ struct simple_dai_props *dai_props) ++{ ++ int ret; ++ char prop[128]; ++ unsigned int val; ++ ++ if (!prefix) ++ prefix = ""; ++ ++ snprintf(prop, sizeof(prop), "%spll-fs", prefix); ++ ret = of_property_read_u32(cpu, prop, &val); ++ if (ret) ++ dai_props->cpu_pll_fs = 1; /* default sysclk 24.576 or 22.5792MHz * 1 */ ++ else ++ dai_props->cpu_pll_fs = val; ++ ++ ret = of_property_read_u32(codec, prop, &val); ++ if (ret) ++ dai_props->codec_pll_fs = 1; /* default sysclk 24.576 or 22.5792MHz * 1 */ ++ else ++ dai_props->codec_pll_fs = val; ++ ++ snprintf(prop, sizeof(prop), "%smclk-fp", prefix); ++ dai_props->mclk_fp = of_property_read_bool(cpu, prop); ++ ++ snprintf(prop, sizeof(prop), "%smclk-fs", prefix); ++ ret = of_property_read_u32(cpu, prop, &val); ++ if (ret) ++ dai_props->mclk_fs = 0; /* default mclk 0Hz(un output) */ ++ else ++ dai_props->mclk_fs = val; ++ ++ return 0; ++} ++ ++int asoc_simple_parse_card_name(struct snd_soc_card *card, ++ char *prefix) ++{ ++ int ret; ++ ++ if (!prefix) ++ prefix = ""; ++ ++ /* Parse the card name from DT */ ++ ret = snd_soc_of_parse_card_name(card, "label"); ++ if (ret < 0 || !card->name) { ++ char prop[128]; ++ ++ snprintf(prop, sizeof(prop), "%sname", prefix); ++ ret = snd_soc_of_parse_card_name(card, prop); ++ if (ret < 0) ++ return ret; ++ } ++ ++ if (!card->name && card->dai_link) ++ card->name = card->dai_link->name; ++ ++ return 0; ++} ++ ++int asoc_simple_parse_dai(struct device_node *node, ++ struct snd_soc_dai_link_component *dlc, ++ const char *list_name, const char *cells_name, ++ int *is_single_link) ++{ ++ struct of_phandle_args args; ++ int ret; ++ ++ if (!node) ++ return 0; ++ ++ /* ++ * Get node via "sound-dai = <&phandle port>" ++ * it will be used as xxx_of_node on soc_bind_dai_link() ++ */ ++ ret = of_parse_phandle_with_args(node, list_name, cells_name, 0, &args); ++ if (ret) ++ return ret; ++ ++ /* ++ * FIXME ++ * ++ * Here, dlc->dai_name is pointer to CPU/Codec DAI name. ++ * If user unbinded CPU or Codec driver, but not for Sound Card, ++ * dlc->dai_name is keeping unbinded CPU or Codec ++ * driver's pointer. ++ * ++ * If user re-bind CPU or Codec driver again, ALSA SoC will try ++ * to rebind Card via snd_soc_try_rebind_card(), but because of ++ * above reason, it might can't bind Sound Card. ++ * Because Sound Card is pointing to released dai_name pointer. ++ * ++ * To avoid this rebind Card issue, ++ * 1) It needs to alloc memory to keep dai_name eventhough ++ * CPU or Codec driver was unbinded, or ++ * 2) user need to rebind Sound Card everytime ++ * if he unbinded CPU or Codec. ++ */ ++ ret = snd_soc_of_get_dai_name(node, &dlc->dai_name, 0); ++ if (ret < 0) ++ return ret; ++ ++ dlc->of_node = args.np; ++ ++ if (is_single_link) ++ *is_single_link = !args.args_count; ++ ++ return 0; ++} ++ ++int asoc_simple_set_dailink_name(struct device *dev, ++ struct snd_soc_dai_link *dai_link, ++ const char *fmt, ...) ++{ ++ va_list ap; ++ char *name = NULL; ++ int ret = -ENOMEM; ++ ++ va_start(ap, fmt); ++ name = devm_kvasprintf(dev, GFP_KERNEL, fmt, ap); ++ va_end(ap); ++ ++ if (name) { ++ ret = 0; ++ ++ dai_link->name = name; ++ dai_link->stream_name = name; ++ } ++ ++ return ret; ++} ++ ++void asoc_simple_canonicalize_platform(struct snd_soc_dai_link *dai_link) ++{ ++ /* Assumes platform == cpu */ ++ if (!dai_link->platforms->of_node) ++ dai_link->platforms->of_node = dai_link->cpus->of_node; ++ ++ /* ++ * DPCM BE can be no platform. ++ * Alloced memory will be waste, but not leak. ++ */ ++ if (!dai_link->platforms->of_node) ++ dai_link->num_platforms = 0; ++} ++ ++void asoc_simple_canonicalize_cpu(struct snd_soc_dai_link *dai_link, ++ int is_single_links) ++{ ++ /* ++ * In soc_bind_dai_link() will check cpu name after ++ * of_node matching if dai_link has cpu_dai_name. ++ * but, it will never match if name was created by ++ * fmt_single_name() remove cpu_dai_name if cpu_args ++ * was 0. See: ++ * fmt_single_name() ++ * fmt_multiple_name() ++ */ ++ if (is_single_links) ++ dai_link->cpus->dai_name = NULL; ++} ++ ++MODULE_AUTHOR("Dby@allwinnertech.com"); ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("sunxi soundcard machine utils"); +diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h +new file mode 100644 +index 000000000..a9cffa0d8 +--- /dev/null ++++ b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h +@@ -0,0 +1,116 @@ ++/* sound\soc\sunxi\snd_sunxi_mach_utils.h ++ * (C) Copyright 2021-2025 ++ * Allwinner Technology Co., Ltd. ++ * Dby ++ * ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ */ ++ ++#ifndef __SND_SUNXI_MACH_UTILS_H ++#define __SND_SUNXI_MACH_UTILS_H ++ ++#define simple_priv_to_card(priv) (&(priv)->snd_card) ++#define simple_priv_to_props(priv, i) ((priv)->dai_props + (i)) ++#define simple_priv_to_dev(priv) (simple_priv_to_card(priv)->dev) ++#define simple_priv_to_link(priv, i) (simple_priv_to_card(priv)->dai_link + (i)) ++ ++#define asoc_simple_parse_cpu(node, dai_link, \ ++ list_name, cells_name, is_single_link) \ ++ asoc_simple_parse_dai(node, dai_link->cpus, \ ++ list_name, cells_name, is_single_link) ++ ++#define asoc_simple_parse_codec(node, dai_link, \ ++ list_name, cells_name) \ ++ asoc_simple_parse_dai(node, dai_link->codecs, \ ++ list_name, cells_name, NULL) ++ ++#define asoc_simple_parse_platform(node, dai_link, \ ++ list_name, cells_name) \ ++ asoc_simple_parse_dai(node, dai_link->platforms, \ ++ list_name, cells_name, NULL) ++ ++struct asoc_simple_dai { ++ const char *name; ++ unsigned int sysclk; ++ int clk_direction; ++ int slots; ++ int slot_width; ++ unsigned int tx_slot_mask; ++ unsigned int rx_slot_mask; ++ struct clk *clk; ++}; ++ ++struct asoc_simple_data { ++ u32 convert_rate; ++ u32 convert_channels; ++}; ++ ++struct asoc_simple_jack { ++ struct snd_soc_jack jack; ++ struct snd_soc_jack_pin pin; ++ struct snd_soc_jack_gpio gpio; ++}; ++ ++struct asoc_simple_priv { ++ struct snd_soc_card snd_card; ++ struct simple_dai_props { ++ struct asoc_simple_dai *cpu_dai; ++ struct asoc_simple_dai *codec_dai; ++ struct snd_soc_dai_link_component cpus; /* single cpu */ ++ struct snd_soc_dai_link_component codecs; /* single codec */ ++ struct snd_soc_dai_link_component platforms; ++ struct asoc_simple_data adata; ++ struct snd_soc_codec_conf *codec_conf; ++ bool mclk_fp; ++ unsigned int mclk_fs; ++ unsigned int cpu_pll_fs; ++ unsigned int codec_pll_fs; ++ } *dai_props; ++ struct asoc_simple_jack hp_jack; ++ struct asoc_simple_jack mic_jack; ++ struct snd_soc_dai_link *dai_link; ++ struct asoc_simple_dai *dais; ++ struct snd_soc_codec_conf *codec_conf; ++ struct gpio_desc *pa_gpio; ++}; ++ ++int asoc_simple_clean_reference(struct snd_soc_card *card); ++int asoc_simple_init_priv(struct asoc_simple_priv *priv); ++ ++int asoc_simple_parse_widgets(struct snd_soc_card *card, char *prefix); ++int asoc_simple_parse_routing(struct snd_soc_card *card, char *prefix); ++int asoc_simple_parse_pin_switches(struct snd_soc_card *card, char *prefix); ++ ++int asoc_simple_parse_daistream(struct device_node *node, ++ char *prefix, ++ struct snd_soc_dai_link *dai_link); ++int asoc_simple_parse_daifmt(struct device_node *node, ++ struct device_node *codec, ++ char *prefix, ++ unsigned int *retfmt); ++int asoc_simple_parse_tdm_slot(struct device_node *node, ++ char *prefix, ++ struct asoc_simple_dai *dais); ++int asoc_simple_parse_tdm_clk(struct device_node *cpu, ++ struct device_node *codec, ++ char *prefix, ++ struct simple_dai_props *dai_props); ++ ++int asoc_simple_parse_card_name(struct snd_soc_card *card, char *prefix); ++int asoc_simple_parse_dai(struct device_node *node, ++ struct snd_soc_dai_link_component *dlc, ++ const char *list_name, ++ const char *cells_name, ++ int *is_single_link); ++ ++int asoc_simple_set_dailink_name(struct device *dev, ++ struct snd_soc_dai_link *dai_link, ++ const char *fmt, ...); ++void asoc_simple_canonicalize_platform(struct snd_soc_dai_link *dai_link); ++void asoc_simple_canonicalize_cpu(struct snd_soc_dai_link *dai_link, ++ int is_single_links); ++ ++#endif /* __SND_SUNXI_MACH_UTILS_H */ +-- +Created with Armbian build tools https://github.com/armbian/build + diff --git a/patch/kernel/archive/sunxi-6.7/series.armbian b/patch/kernel/archive/sunxi-6.7/series.armbian index c9b30d77cb78..5f3193917c72 100644 --- a/patch/kernel/archive/sunxi-6.7/series.armbian +++ b/patch/kernel/archive/sunxi-6.7/series.armbian @@ -203,3 +203,4 @@ patches.armbian/arm64-dts-allwinner-sun50i-h616-PG-12c-pins.patch patches.armbian/arm64-dts-allwinner-sun50i-h616-spi1-cs1-pin.patch patches.armbian/arm64-dts-sun50i-h618-add-overlay.patch + patches.armbian/sound-soc-sunxi-h616-h618.patch diff --git a/patch/kernel/archive/sunxi-6.7/series.conf b/patch/kernel/archive/sunxi-6.7/series.conf index c45b98131985..88c515575f4e 100644 --- a/patch/kernel/archive/sunxi-6.7/series.conf +++ b/patch/kernel/archive/sunxi-6.7/series.conf @@ -525,3 +525,4 @@ patches.armbian/arm64-dts-allwinner-sun50i-h616-PG-12c-pins.patch patches.armbian/arm64-dts-allwinner-sun50i-h616-spi1-cs1-pin.patch patches.armbian/arm64-dts-sun50i-h618-add-overlay.patch + patches.armbian/sound-soc-sunxi-h616-h618.patch diff --git a/patch/misc/wireless-rtl8723cs/8723cs-Port-to-6.9.patch b/patch/misc/wireless-rtl8723cs/8723cs-Port-to-6.9.patch new file mode 100644 index 000000000000..420feffa55b3 --- /dev/null +++ b/patch/misc/wireless-rtl8723cs/8723cs-Port-to-6.9.patch @@ -0,0 +1,31 @@ +From 4d13c6ecde5727adcf46bb9895c07f1dbb92f8d7 Mon Sep 17 00:00:00 2001 +From: Ondrej Jirman +Date: Fri, 15 Mar 2024 23:04:21 +0100 +Subject: [PATCH] 8723cs: Port to v6.9 + +Signed-off-by: Ondrej Jirman +--- + drivers/staging/rtl8723cs/os_dep/linux/ioctl_cfg80211.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/staging/rtl8723cs/os_dep/linux/ioctl_cfg80211.c b/drivers/staging/rtl8723cs/os_dep/linux/ioctl_cfg80211.c +index 817041e4644b..9bf7bb782b7e 100644 +--- a/drivers/staging/rtl8723cs/os_dep/linux/ioctl_cfg80211.c ++++ b/drivers/staging/rtl8723cs/os_dep/linux/ioctl_cfg80211.c +@@ -452,14 +452,14 @@ u8 rtw_cfg80211_ch_switch_notify(_adapter *adapter, u8 ch, u8 bw, u8 offset, + goto exit; + + if (started) { +- cfg80211_ch_switch_started_notify(adapter->pnetdev, &chdef, 0, 0, false, 0); ++ cfg80211_ch_switch_started_notify(adapter->pnetdev, &chdef, 0, 0, false); + goto exit; + } + + if (!rtw_cfg80211_allow_ch_switch_notify(adapter)) + goto exit; + +- cfg80211_ch_switch_notify(adapter->pnetdev, &chdef, 0, 0); ++ cfg80211_ch_switch_notify(adapter->pnetdev, &chdef, 0); + + exit: + return ret; diff --git a/patch/misc/wireless-uwe5622/uwe5622-v6.9.patch b/patch/misc/wireless-uwe5622/uwe5622-v6.9.patch new file mode 100644 index 000000000000..ec07823c2e74 --- /dev/null +++ b/patch/misc/wireless-uwe5622/uwe5622-v6.9.patch @@ -0,0 +1,33 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: John Doe +Date: Thu, 6 Jun 2024 13:25:27 +0000 +Subject: Patching kernel rockchip64 files + drivers/net/wireless/uwe5622/unisocwifi/cmdevt.c + +Signed-off-by: John Doe +--- + drivers/net/wireless/uwe5622/unisocwifi/cmdevt.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/net/wireless/uwe5622/unisocwifi/cmdevt.c b/drivers/net/wireless/uwe5622/unisocwifi/cmdevt.c +index 1f2f6efb9184..dfe03b0636da 100755 +--- a/drivers/net/wireless/uwe5622/unisocwifi/cmdevt.c ++++ b/drivers/net/wireless/uwe5622/unisocwifi/cmdevt.c +@@ -3299,11 +3299,13 @@ void sprdwl_event_chan_changed(struct sprdwl_vif *vif, u8 *data, u16 len) + /* we will be active on the channel */ + cfg80211_chandef_create(&chandef, ch, + NL80211_CHAN_HT20); + else + wl_err("%s, ch is null!\n", __func__); +-#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,19, 2)) ++#if (LINUX_VERSION_CODE >= KERNEL_VERSION(6,9, 0)) ++ cfg80211_ch_switch_notify(vif->ndev, &chandef, 0); ++#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5,19, 2)) + cfg80211_ch_switch_notify(vif->ndev, &chandef, 0, 0); + #else + cfg80211_ch_switch_notify(vif->ndev, &chandef); + #endif + } +-- +Created with Armbian build tools https://github.com/armbian/build + diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/0000.patching_config.yaml b/patch/u-boot/legacy/u-boot-radxa-rk3588/0000.patching_config.yaml new file mode 100644 index 000000000000..719cf56a8c70 --- /dev/null +++ b/patch/u-boot/legacy/u-boot-radxa-rk3588/0000.patching_config.yaml @@ -0,0 +1,5 @@ +config: + + overlay-directories: + - { source: "defconfig", target: "configs" } # copies all files in defconfig dir to the configs/ dir in the u-boot source tree + - { source: "dt", target: "arch/arm/dts" } # copies all files in dt dir to the arch/arm/dts dir in the u-boot source tree diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/0001-Add-defconfig-and-dtb-of-nanopi6.patch b/patch/u-boot/legacy/u-boot-radxa-rk3588/0001-Add-defconfig-and-dtb-of-nanopi6.patch deleted file mode 100644 index 38f1a5abd89c..000000000000 --- a/patch/u-boot/legacy/u-boot-radxa-rk3588/0001-Add-defconfig-and-dtb-of-nanopi6.patch +++ /dev/null @@ -1,370 +0,0 @@ -From 70d65e65db965295ddd23d5db752aad1c035c205 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Muhammed=20Efe=20=C3=87etin?= -Date: Sat, 15 Apr 2023 23:12:17 +0300 -Subject: [PATCH] Add defconfig and dtb of nanopi6 - ---- - arch/arm/dts/rk3588s-nanopi-r6s.dts | 126 ++++++++++++++++ - configs/nanopi-r6s-rk3588s_defconfig | 217 +++++++++++++++++++++++++++ - 2 files changed, 343 insertions(+) - create mode 100644 arch/arm/dts/rk3588s-nanopi-r6s.dts - create mode 100644 configs/nanopi-r6s-rk3588s_defconfig - -diff --git a/arch/arm/dts/rk3588s-nanopi-r6s.dts b/arch/arm/dts/rk3588s-nanopi-r6s.dts -new file mode 100644 -index 0000000000..4899e23fa3 ---- /dev/null -+++ b/arch/arm/dts/rk3588s-nanopi-r6s.dts -@@ -0,0 +1,126 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd -+ * -+ */ -+ -+/dts-v1/; -+#include "rk3588.dtsi" -+#include "rk3588-u-boot.dtsi" -+#include -+ -+/ { -+ model = "NanoPi R6S"; -+ compatible = "nanopi,nanopi-r6s", "rockchip,rk3588"; -+ -+ vcc12v_dcin: vcc12v-dcin { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ vcc_5v0: vcc-5v0 { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_5v0"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ enable-active-high; -+ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_5v0_en>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_host: vcc5v0-host-regulator { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_host"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host_en>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ led_sys: led-sys { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "led_sys"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; // Turn on user led -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&usb2phy0_grf { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+ -+&u2phy0 { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&usb2phy2_grf { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&u2phy2 { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&u2phy2_host { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&pinctrl { -+ usb { -+ u-boot,dm-pre-reloc; -+ vcc5v0_host_en: vcc5v0-host-en { -+ u-boot,dm-pre-reloc; -+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ power { -+ u-boot,dm-spl; -+ vcc_5v0_en: vcc-5v0-en { -+ u-boot,dm-spl; -+ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -diff --git a/configs/nanopi-r6s-rk3588s_defconfig b/configs/nanopi-r6s-rk3588s_defconfig -new file mode 100644 -index 0000000000..19bae55629 ---- /dev/null -+++ b/configs/nanopi-r6s-rk3588s_defconfig -@@ -0,0 +1,217 @@ -+CONFIG_ARM=y -+CONFIG_ARM_CPU_SUSPEND=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SPL_GPIO_SUPPORT=y -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_SYS_MALLOC_F_LEN=0x80000 -+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" -+CONFIG_ROCKCHIP_RK3588=y -+CONFIG_ROCKCHIP_USB_BOOT=y -+CONFIG_ROCKCHIP_FIT_IMAGE=y -+CONFIG_ROCKCHIP_HWID_DTB=y -+CONFIG_ROCKCHIP_VENDOR_PARTITION=y -+CONFIG_USING_KERNEL_DTB_V2=y -+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y -+CONFIG_ROCKCHIP_NEW_IDB=y -+CONFIG_LOADER_INI="RK3588MINIALL.ini" -+CONFIG_TRUST_INI="RK3588TRUST.ini" -+CONFIG_SPL_SERIAL_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -+CONFIG_TARGET_EVB_RK3588=y -+CONFIG_SPL_LIBDISK_SUPPORT=y -+CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_SPI_SUPPORT=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3588s-nanopi-r6s" -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_IMAGE_POST_PROCESS=y -+CONFIG_FIT_HW_CRYPTO=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y -+CONFIG_SPL_FIT_HW_CRYPTO=y -+# CONFIG_SPL_SYS_DCACHE_OFF is not set -+CONFIG_BOOTDELAY=0 -+CONFIG_SYS_CONSOLE_INFO_QUIET=y -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_ANDROID_BOOTLOADER=y -+CONFIG_ANDROID_AVB=y -+CONFIG_ANDROID_BOOT_IMAGE_HASH=y -+CONFIG_SPL_BOARD_INIT=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 -+CONFIG_SPL_MMC_WRITE=y -+CONFIG_SPL_MTD_SUPPORT=y -+CONFIG_SPL_ATF=y -+CONFIG_FASTBOOT_BUF_ADDR=0xc00800 -+CONFIG_FASTBOOT_BUF_SIZE=0x04000000 -+CONFIG_FASTBOOT_FLASH=y -+CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_DTIMG=y -+# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_IMI is not set -+# CONFIG_CMD_IMLS is not set -+# CONFIG_CMD_XIMG is not set -+# CONFIG_CMD_LZMADEC is not set -+# CONFIG_CMD_UNZIP is not set -+# CONFIG_CMD_FLASH is not set -+# CONFIG_CMD_FPGA is not set -+CONFIG_CMD_GPT=y -+# CONFIG_CMD_LOADB is not set -+# CONFIG_CMD_LOADS is not set -+CONFIG_CMD_BOOT_ANDROID=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_SF=y -+CONFIG_CMD_SPI=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_USB_MASS_STORAGE=y -+# CONFIG_CMD_ITEST is not set -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TFTPPUT=y -+CONFIG_CMD_TFTP_BOOTM=y -+CONFIG_CMD_TFTP_FLASH=y -+# CONFIG_CMD_MISC is not set -+CONFIG_CMD_MTD_BLK=y -+# CONFIG_SPL_DOS_PARTITION is not set -+# CONFIG_ISO_PARTITION is not set -+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_SPL_DTB_MINIMUM=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+# CONFIG_NET_TFTP_VARS is not set -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+# CONFIG_SARADC_ROCKCHIP is not set -+CONFIG_SARADC_ROCKCHIP_V2=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_SPL_CLK_SCMI=y -+CONFIG_DM_CRYPTO=y -+CONFIG_SPL_DM_CRYPTO=y -+CONFIG_ROCKCHIP_CRYPTO_V2=y -+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y -+CONFIG_SCMI_FIRMWARE=y -+CONFIG_SPL_SCMI_FIRMWARE=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_ROCKCHIP_GPIO_V2=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_DM_KEY=y -+CONFIG_ADC_KEY=y -+CONFIG_MISC=y -+CONFIG_SPL_MISC=y -+CONFIG_MISC_DECOMPRESS=y -+CONFIG_SPL_MISC_DECOMPRESS=y -+CONFIG_ROCKCHIP_OTP=y -+CONFIG_ROCKCHIP_HW_DECOMPRESS=y -+CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y -+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_MTD=y -+CONFIG_MTD_BLK=y -+CONFIG_MTD_DEVICE=y -+CONFIG_NAND=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_SPI_FLASH=y -+CONFIG_SF_DEFAULT_SPEED=80000000 -+CONFIG_SPI_FLASH_EON=y -+CONFIG_SPI_FLASH_GIGADEVICE=y -+CONFIG_SPI_FLASH_MACRONIX=y -+CONFIG_SPI_FLASH_SST=y -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_SPI_FLASH_XMC=y -+CONFIG_SPI_FLASH_XTX=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_DM_ETH=y -+CONFIG_DM_ETH_PHY=y -+CONFIG_DWC_ETH_QOS=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_NVME=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_DM_PCI_COMPAT=y -+CONFIG_PCIE_DW_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y -+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_SPI_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_REGULATOR_RK860X=y -+CONFIG_REGULATOR_RK806=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_ROCKCHIP_SDRAM_COMMON=y -+CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 -+CONFIG_DM_RESET=y -+CONFIG_SPL_DM_RESET=y -+CONFIG_SPL_RESET_ROCKCHIP=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_BASE=0xFEB50000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_ROCKCHIP_SPI=y -+CONFIG_ROCKCHIP_SFC=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_XHCI_PCI=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GADGET=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_USB_STORAGE=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_MANUFACTURER="Rockchip" -+CONFIG_USB_GADGET_VENDOR_NUM=0x2207 -+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a -+CONFIG_USB_GADGET_DOWNLOAD=y -+CONFIG_DM_VIDEO=y -+CONFIG_DISPLAY=y -+CONFIG_DRM_ROCKCHIP=y -+CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y -+CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y -+CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y -+CONFIG_USE_TINY_PRINTF=y -+CONFIG_LIB_RAND=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_RSA=y -+CONFIG_SPL_RSA=y -+CONFIG_RSA_N_SIZE=0x200 -+CONFIG_RSA_E_SIZE=0x10 -+CONFIG_RSA_C_SIZE=0x20 -+CONFIG_LZ4=y -+CONFIG_ERRNO_STR=y -+# CONFIG_EFI_LOADER is not set -+CONFIG_AVB_LIBAVB=y -+CONFIG_AVB_LIBAVB_AB=y -+CONFIG_AVB_LIBAVB_ATX=y -+CONFIG_AVB_LIBAVB_USER=y -+CONFIG_RK_AVB_LIBAVB_USER=y -+CONFIG_OPTEE_CLIENT=y -+CONFIG_OPTEE_V2=y -+CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y --- -2.39.2 - diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/0002-add-defconfig-and-dtb-for-nanopc-t6.patch b/patch/u-boot/legacy/u-boot-radxa-rk3588/0002-add-defconfig-and-dtb-for-nanopc-t6.patch deleted file mode 100644 index 90f9f6a16374..000000000000 --- a/patch/u-boot/legacy/u-boot-radxa-rk3588/0002-add-defconfig-and-dtb-for-nanopc-t6.patch +++ /dev/null @@ -1,407 +0,0 @@ -From 1e186b0bdf9bf23e75da633f0338a77f527b8ebb Mon Sep 17 00:00:00 2001 -From: Joshua-Riek -Date: Thu, 10 Aug 2023 00:00:30 -0400 -Subject: [PATCH] add defconfig and dtb for nanopc t6 - ---- - arch/arm/dts/rk3588-nanopc-t6.dts | 161 ++++++++++++++++++++++ - configs/nanopc_t6_defconfig | 218 ++++++++++++++++++++++++++++++ - 2 files changed, 379 insertions(+) - create mode 100644 arch/arm/dts/rk3588-nanopc-t6.dts - create mode 100644 configs/nanopc_t6_defconfig - -diff --git a/arch/arm/dts/rk3588-nanopc-t6.dts b/arch/arm/dts/rk3588-nanopc-t6.dts -new file mode 100644 -index 0000000000..ee7c7f005c ---- /dev/null -+++ b/arch/arm/dts/rk3588-nanopc-t6.dts -@@ -0,0 +1,161 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd -+ * -+ */ -+ -+/dts-v1/; -+#include "rk3588.dtsi" -+#include "rk3588-u-boot.dtsi" -+#include -+ -+/ { -+ model = "NanoPC-T6"; -+ compatible = "nanopc,nanopc-t6", "rockchip,rk3588"; -+ -+ vcc12v_dcin: vcc12v-dcin { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ vcc_5v0: vcc-5v0 { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_5v0"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ enable-active-high; -+ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_5v0_en>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_host: vcc5v0-host-regulator { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_host"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host_en>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_pcie30: vcc3v3-pcie30 { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie30"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; -+ regulator-boot-on; -+ regulator-always-on; -+ startup-delay-us = <50000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ led_sys: led-sys { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "led_sys"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; // Turn on user led -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&pcie3x4 { -+ u-boot,dm-pre-reloc; -+ vpcie3v3-supply = <&vcc3v3_pcie30>; -+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+}; -+ -+&pcie30phy { -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+}; -+ -+&combphy0_ps { -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+}; -+ -+&combphy2_psu { -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+}; -+ -+&usb2phy0_grf { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&usb2phy2_grf { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&u2phy2 { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&u2phy2_host { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&pinctrl { -+ usb { -+ u-boot,dm-pre-reloc; -+ vcc5v0_host_en: vcc5v0-host-en { -+ u-boot,dm-pre-reloc; -+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ power { -+ u-boot,dm-spl; -+ vcc_5v0_en: vcc-5v0-en { -+ u-boot,dm-spl; -+ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -diff --git a/configs/nanopc_t6_defconfig b/configs/nanopc_t6_defconfig -new file mode 100644 -index 0000000000..6915379076 ---- /dev/null -+++ b/configs/nanopc_t6_defconfig -@@ -0,0 +1,218 @@ -+CONFIG_ARM=y -+CONFIG_ARM_CPU_SUSPEND=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SPL_GPIO_SUPPORT=y -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_SYS_MALLOC_F_LEN=0x80000 -+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" -+CONFIG_ROCKCHIP_RK3588=y -+CONFIG_ROCKCHIP_USB_BOOT=y -+CONFIG_ROCKCHIP_FIT_IMAGE=y -+CONFIG_ROCKCHIP_HWID_DTB=y -+CONFIG_ROCKCHIP_VENDOR_PARTITION=y -+CONFIG_USING_KERNEL_DTB_V2=y -+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y -+CONFIG_ROCKCHIP_NEW_IDB=y -+CONFIG_LOADER_INI="RK3588MINIALL.ini" -+CONFIG_TRUST_INI="RK3588TRUST.ini" -+CONFIG_SPL_SERIAL_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -+CONFIG_TARGET_EVB_RK3588=y -+CONFIG_SPL_LIBDISK_SUPPORT=y -+CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_SPI_SUPPORT=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6" -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_IMAGE_POST_PROCESS=y -+CONFIG_FIT_HW_CRYPTO=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y -+CONFIG_SPL_FIT_HW_CRYPTO=y -+# CONFIG_SPL_SYS_DCACHE_OFF is not set -+CONFIG_BOOTDELAY=2 -+CONFIG_SYS_CONSOLE_INFO_QUIET=y -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_ANDROID_BOOTLOADER=y -+CONFIG_ANDROID_AVB=y -+CONFIG_ANDROID_BOOT_IMAGE_HASH=y -+CONFIG_SPL_BOARD_INIT=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 -+CONFIG_SPL_MMC_WRITE=y -+CONFIG_SPL_MTD_SUPPORT=y -+CONFIG_SPL_ATF=y -+CONFIG_FASTBOOT_BUF_ADDR=0xc00800 -+CONFIG_FASTBOOT_BUF_SIZE=0x04000000 -+CONFIG_FASTBOOT_FLASH=y -+CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_DTIMG=y -+# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_IMI is not set -+# CONFIG_CMD_IMLS is not set -+# CONFIG_CMD_XIMG is not set -+# CONFIG_CMD_LZMADEC is not set -+# CONFIG_CMD_UNZIP is not set -+# CONFIG_CMD_FLASH is not set -+# CONFIG_CMD_FPGA is not set -+CONFIG_CMD_GPT=y -+# CONFIG_CMD_LOADB is not set -+# CONFIG_CMD_LOADS is not set -+CONFIG_CMD_BOOT_ANDROID=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_SF=y -+CONFIG_CMD_SPI=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_USB_MASS_STORAGE=y -+# CONFIG_CMD_ITEST is not set -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TFTPPUT=y -+CONFIG_CMD_TFTP_BOOTM=y -+CONFIG_CMD_TFTP_FLASH=y -+# CONFIG_CMD_MISC is not set -+CONFIG_CMD_MTD_BLK=y -+# CONFIG_SPL_DOS_PARTITION is not set -+# CONFIG_ISO_PARTITION is not set -+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_SPL_DTB_MINIMUM=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+# CONFIG_NET_TFTP_VARS is not set -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+# CONFIG_SARADC_ROCKCHIP is not set -+CONFIG_SARADC_ROCKCHIP_V2=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_SPL_CLK_SCMI=y -+CONFIG_DM_CRYPTO=y -+CONFIG_SPL_DM_CRYPTO=y -+CONFIG_ROCKCHIP_CRYPTO_V2=y -+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y -+CONFIG_SCMI_FIRMWARE=y -+CONFIG_SPL_SCMI_FIRMWARE=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_ROCKCHIP_GPIO_V2=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_DM_KEY=y -+CONFIG_ADC_KEY=y -+CONFIG_MISC=y -+CONFIG_SPL_MISC=y -+CONFIG_MISC_DECOMPRESS=y -+CONFIG_SPL_MISC_DECOMPRESS=y -+CONFIG_ROCKCHIP_OTP=y -+CONFIG_ROCKCHIP_HW_DECOMPRESS=y -+CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y -+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_MTD=y -+CONFIG_MTD_BLK=y -+CONFIG_MTD_DEVICE=y -+CONFIG_NAND=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_SPI_FLASH=y -+CONFIG_SF_DEFAULT_SPEED=80000000 -+CONFIG_SPI_FLASH_EON=y -+CONFIG_SPI_FLASH_GIGADEVICE=y -+CONFIG_SPI_FLASH_MACRONIX=y -+CONFIG_SPI_FLASH_SST=y -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_SPI_FLASH_XMC=y -+CONFIG_SPI_FLASH_XTX=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_DM_ETH=y -+CONFIG_DM_ETH_PHY=y -+CONFIG_DWC_ETH_QOS=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_NVME=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_DM_PCI_COMPAT=y -+CONFIG_PCIE_DW_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y -+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_SPI_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_REGULATOR_RK860X=y -+CONFIG_REGULATOR_RK806=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_ROCKCHIP_SDRAM_COMMON=y -+CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 -+CONFIG_DM_RESET=y -+CONFIG_SPL_DM_RESET=y -+CONFIG_SPL_RESET_ROCKCHIP=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_BASE=0xFEB50000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_ROCKCHIP_SPI=y -+CONFIG_ROCKCHIP_SFC=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_XHCI_PCI=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GADGET=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_USB_STORAGE=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_MANUFACTURER="Rockchip" -+CONFIG_USB_GADGET_VENDOR_NUM=0x2207 -+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a -+CONFIG_USB_GADGET_DOWNLOAD=y -+CONFIG_DM_VIDEO=y -+CONFIG_DISPLAY=y -+CONFIG_DRM_ROCKCHIP=y -+CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y -+CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y -+CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y -+CONFIG_USE_TINY_PRINTF=y -+CONFIG_LIB_RAND=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_RSA=y -+CONFIG_SPL_RSA=y -+CONFIG_RSA_N_SIZE=0x200 -+CONFIG_RSA_E_SIZE=0x10 -+CONFIG_RSA_C_SIZE=0x20 -+CONFIG_LZ4=y -+CONFIG_ERRNO_STR=y -+# CONFIG_EFI_LOADER is not set -+CONFIG_AVB_LIBAVB=y -+CONFIG_AVB_LIBAVB_AB=y -+CONFIG_AVB_LIBAVB_ATX=y -+CONFIG_AVB_LIBAVB_USER=y -+CONFIG_RK_AVB_LIBAVB_USER=y -+CONFIG_OPTEE_CLIENT=y -+CONFIG_OPTEE_V2=y -+CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y --- -2.25.1 - - diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/0103-U-Boot-Add-defconfig-and-dts-for-FriendlyElec-CM3588.patch b/patch/u-boot/legacy/u-boot-radxa-rk3588/0103-U-Boot-Add-defconfig-and-dts-for-FriendlyElec-CM3588.patch deleted file mode 100644 index bc031cb1df7f..000000000000 --- a/patch/u-boot/legacy/u-boot-radxa-rk3588/0103-U-Boot-Add-defconfig-and-dts-for-FriendlyElec-CM3588.patch +++ /dev/null @@ -1,480 +0,0 @@ -From 72941e1891dfdc8a23ae01dc478ab6ac19fbbb4a Mon Sep 17 00:00:00 2001 -From: ColorfulRhino <131405023+ColorfulRhino@users.noreply.github.com> -Date: Tue, 5 Mar 2024 20:38:59 +0000 -Subject: [PATCH] U-Boot: Add defconfig and dts for FriendlyElec CM3588 - ---- - arch/arm/dts/rk3588-nanopc-cm3588.dts | 235 ++++++++++++++++++++++++++ - configs/nanopc_cm3588_defconfig | 218 ++++++++++++++++++++++++ - 2 files changed, 453 insertions(+) - create mode 100644 arch/arm/dts/rk3588-nanopc-cm3588.dts - create mode 100644 configs/nanopc_cm3588_defconfig - -diff --git a/arch/arm/dts/rk3588-nanopc-cm3588.dts b/arch/arm/dts/rk3588-nanopc-cm3588.dts -new file mode 100644 -index 0000000..b8a8c64 ---- /dev/null -+++ b/arch/arm/dts/rk3588-nanopc-cm3588.dts -@@ -0,0 +1,235 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd -+ * -+ */ -+ -+/dts-v1/; -+#include -+#include "rk3588.dtsi" -+#include "rk3588-u-boot.dtsi" -+ -+/ { -+ model = "FriendlyElec CM3588"; -+ compatible = "friendlyelec,cm3588", "rockchip,rk3588"; -+ -+ vcc12v_dcin: vcc12v-dcin { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ vcc_5v0: vcc-5v0 { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc_5v0"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ regulator-boot-on; -+ regulator-always-on; -+ enable-active-high; -+ gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc_5v0_en>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc5v0_host: vcc5v0-host-regulator { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_host"; -+ regulator-boot-on; -+ regulator-always-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ enable-active-high; -+ gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&vcc5v0_host_en>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ vcc3v3_pcie30: vcc3v3-pcie30 { -+ u-boot,dm-pre-reloc; -+ startup-delay-us = <50000>; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie30"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ led_sys: led-sys { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "led_sys"; -+ enable-active-high; -+ gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; // Turn on user led -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&pcie2x1l0 { -+ u-boot,dm-pre-reloc; -+ /* 2. CON14: pcie30phy port0 lane1 */ -+ max-link-speed = <3>; -+ num-lanes = <1>; -+ phys = <&pcie30phy>; -+ reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie30>; -+ status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00200000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ nvme1: pcie@20,0 { -+ reg = <0x000000 0 0 0 0>; -+ }; -+ }; -+}; -+ -+&pcie2x1l1 { -+ u-boot,dm-pre-reloc; -+ /* 4. CON16: pcie30phy port1 lane1 */ -+ max-link-speed = <3>; -+ num-lanes = <1>; -+ phys = <&pcie30phy>; -+ reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie30>; -+ status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00300000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ nvme3: pcie@30,0 { -+ reg = <0x000000 0 0 0 0>; -+ }; -+ }; -+}; -+ -+&pcie3x4 { -+ u-boot,dm-pre-reloc; -+ /* 1. CON13: pcie30phy port0 lane0 */ -+ max-link-speed = <3>; -+ num-lanes = <1>; -+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie30>; -+ status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00000000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ nvme0: pcie@0,0 { -+ reg = <0x000000 0 0 0 0>; -+ }; -+ }; -+}; -+ -+&pcie3x2 { -+ u-boot,dm-pre-reloc; -+ /* 3. CON15: pcie30phy port1 lane0 */ -+ max-link-speed = <3>; -+ num-lanes = <1>; -+ reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; -+ vpcie3v3-supply = <&vcc3v3_pcie30>; -+ status = "okay"; -+ -+ pcie@0,0 { -+ reg = <0x00100000 0 0 0 0>; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ nvme2: pcie@10,0 { -+ reg = <0x000000 0 0 0 0>; -+ }; -+ }; -+}; -+ -+&pcie30phy { -+ u-boot,dm-pre-reloc; -+ rockchip,pcie30-phymode = ; -+ status = "okay"; -+}; -+ -+&combphy0_ps { -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+}; -+ -+&combphy2_psu { -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+}; -+ -+&usb2phy0_grf { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&u2phy0 { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&u2phy0_otg { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&usb2phy2_grf { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&u2phy2 { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&u2phy2_host { -+ status = "okay"; -+ u-boot,dm-pre-reloc; -+}; -+ -+&pinctrl { -+ usb { -+ u-boot,dm-pre-reloc; -+ vcc5v0_host_en: vcc5v0-host-en { -+ u-boot,dm-pre-reloc; -+ rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+ -+ power { -+ u-boot,dm-spl; -+ vcc_5v0_en: vcc-5v0-en { -+ u-boot,dm-spl; -+ rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; -+ }; -+ }; -+}; -diff --git a/configs/nanopc_cm3588_defconfig b/configs/nanopc_cm3588_defconfig -new file mode 100644 -index 0000000..885f958 ---- /dev/null -+++ b/configs/nanopc_cm3588_defconfig -@@ -0,0 +1,218 @@ -+CONFIG_ARM=y -+CONFIG_ARM_CPU_SUSPEND=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SPL_GPIO_SUPPORT=y -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_SYS_MALLOC_F_LEN=0x80000 -+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" -+CONFIG_ROCKCHIP_RK3588=y -+CONFIG_ROCKCHIP_USB_BOOT=y -+CONFIG_ROCKCHIP_FIT_IMAGE=y -+CONFIG_ROCKCHIP_HWID_DTB=y -+CONFIG_ROCKCHIP_VENDOR_PARTITION=y -+CONFIG_USING_KERNEL_DTB_V2=y -+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y -+CONFIG_ROCKCHIP_NEW_IDB=y -+CONFIG_LOADER_INI="RK3588MINIALL.ini" -+CONFIG_TRUST_INI="RK3588TRUST.ini" -+CONFIG_SPL_SERIAL_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -+CONFIG_TARGET_EVB_RK3588=y -+CONFIG_SPL_LIBDISK_SUPPORT=y -+CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_SPI_SUPPORT=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-cm3588" -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_IMAGE_POST_PROCESS=y -+CONFIG_FIT_HW_CRYPTO=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y -+CONFIG_SPL_FIT_HW_CRYPTO=y -+# CONFIG_SPL_SYS_DCACHE_OFF is not set -+CONFIG_BOOTDELAY=2 -+CONFIG_SYS_CONSOLE_INFO_QUIET=y -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_ANDROID_BOOTLOADER=y -+CONFIG_ANDROID_AVB=y -+CONFIG_ANDROID_BOOT_IMAGE_HASH=y -+CONFIG_SPL_BOARD_INIT=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 -+CONFIG_SPL_MMC_WRITE=y -+CONFIG_SPL_MTD_SUPPORT=y -+CONFIG_SPL_ATF=y -+CONFIG_FASTBOOT_BUF_ADDR=0xc00800 -+CONFIG_FASTBOOT_BUF_SIZE=0x04000000 -+CONFIG_FASTBOOT_FLASH=y -+CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_DTIMG=y -+# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_IMI is not set -+# CONFIG_CMD_IMLS is not set -+# CONFIG_CMD_XIMG is not set -+# CONFIG_CMD_LZMADEC is not set -+# CONFIG_CMD_UNZIP is not set -+# CONFIG_CMD_FLASH is not set -+# CONFIG_CMD_FPGA is not set -+CONFIG_CMD_GPT=y -+# CONFIG_CMD_LOADB is not set -+# CONFIG_CMD_LOADS is not set -+CONFIG_CMD_BOOT_ANDROID=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_SF=y -+CONFIG_CMD_SPI=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_USB_MASS_STORAGE=y -+# CONFIG_CMD_ITEST is not set -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TFTPPUT=y -+CONFIG_CMD_TFTP_BOOTM=y -+CONFIG_CMD_TFTP_FLASH=y -+# CONFIG_CMD_MISC is not set -+CONFIG_CMD_MTD_BLK=y -+# CONFIG_SPL_DOS_PARTITION is not set -+# CONFIG_ISO_PARTITION is not set -+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_SPL_DTB_MINIMUM=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+# CONFIG_NET_TFTP_VARS is not set -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+# CONFIG_SARADC_ROCKCHIP is not set -+CONFIG_SARADC_ROCKCHIP_V2=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_SPL_CLK_SCMI=y -+CONFIG_DM_CRYPTO=y -+CONFIG_SPL_DM_CRYPTO=y -+CONFIG_ROCKCHIP_CRYPTO_V2=y -+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y -+CONFIG_SCMI_FIRMWARE=y -+CONFIG_SPL_SCMI_FIRMWARE=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_ROCKCHIP_GPIO_V2=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_DM_KEY=y -+CONFIG_ADC_KEY=y -+CONFIG_MISC=y -+CONFIG_SPL_MISC=y -+CONFIG_MISC_DECOMPRESS=y -+CONFIG_SPL_MISC_DECOMPRESS=y -+CONFIG_ROCKCHIP_OTP=y -+CONFIG_ROCKCHIP_HW_DECOMPRESS=y -+CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y -+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_MTD=y -+CONFIG_MTD_BLK=y -+CONFIG_MTD_DEVICE=y -+CONFIG_NAND=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_SPI_FLASH=y -+CONFIG_SF_DEFAULT_SPEED=80000000 -+CONFIG_SPI_FLASH_EON=y -+CONFIG_SPI_FLASH_GIGADEVICE=y -+CONFIG_SPI_FLASH_MACRONIX=y -+CONFIG_SPI_FLASH_SST=y -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_SPI_FLASH_XMC=y -+CONFIG_SPI_FLASH_XTX=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_DM_ETH=y -+CONFIG_DM_ETH_PHY=y -+CONFIG_DWC_ETH_QOS=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_NVME=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_DM_PCI_COMPAT=y -+CONFIG_PCIE_DW_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y -+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_SPI_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_REGULATOR_RK860X=y -+CONFIG_REGULATOR_RK806=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_ROCKCHIP_SDRAM_COMMON=y -+CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 -+CONFIG_DM_RESET=y -+CONFIG_SPL_DM_RESET=y -+CONFIG_SPL_RESET_ROCKCHIP=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_BASE=0xFEB50000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_ROCKCHIP_SPI=y -+CONFIG_ROCKCHIP_SFC=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_XHCI_PCI=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GADGET=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_USB_STORAGE=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_MANUFACTURER="Rockchip" -+CONFIG_USB_GADGET_VENDOR_NUM=0x2207 -+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a -+CONFIG_USB_GADGET_DOWNLOAD=y -+CONFIG_DM_VIDEO=y -+CONFIG_DISPLAY=y -+CONFIG_DRM_ROCKCHIP=y -+CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y -+CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y -+CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y -+CONFIG_USE_TINY_PRINTF=y -+CONFIG_LIB_RAND=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_RSA=y -+CONFIG_SPL_RSA=y -+CONFIG_RSA_N_SIZE=0x200 -+CONFIG_RSA_E_SIZE=0x10 -+CONFIG_RSA_C_SIZE=0x20 -+CONFIG_LZ4=y -+CONFIG_ERRNO_STR=y -+# CONFIG_EFI_LOADER is not set -+CONFIG_AVB_LIBAVB=y -+CONFIG_AVB_LIBAVB_AB=y -+CONFIG_AVB_LIBAVB_ATX=y -+CONFIG_AVB_LIBAVB_USER=y -+CONFIG_RK_AVB_LIBAVB_USER=y -+CONFIG_OPTEE_CLIENT=y -+CONFIG_OPTEE_V2=y -+CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y --- -2.34.1 - diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/0104-Add-ArmSoM-w3-defines.patch b/patch/u-boot/legacy/u-boot-radxa-rk3588/0104-Add-ArmSoM-w3-defines.patch deleted file mode 100644 index 62bfb826e655..000000000000 --- a/patch/u-boot/legacy/u-boot-radxa-rk3588/0104-Add-ArmSoM-w3-defines.patch +++ /dev/null @@ -1,329 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: jack -Date: Wed, 1 Nov 2023 08:28:02 +0800 -Subject: Add defconfig and dtb of armsom-w3 - ---- - arch/arm/dts/rk3588-armsom-w3.dts | 88 ++++ - configs/armsom-w3-rk3588_defconfig | 216 ++++++++++ - 2 files changed, 304 insertions(+) - -diff --git a/arch/arm/dts/rk3588-armsom-w3.dts b/arch/arm/dts/rk3588-armsom-w3.dts -new file mode 100644 -index 000000000000..6a51591301bb ---- /dev/null -+++ b/arch/arm/dts/rk3588-armsom-w3.dts -@@ -0,0 +1,88 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd -+ * -+ */ -+ -+/dts-v1/; -+#include "rk3588.dtsi" -+#include "rk3588-u-boot.dtsi" -+#include -+ -+/ { -+ model = "ArmSoM W3 (LGA Module ArmSoM-LM5 LP4x) V1.1"; -+ compatible = "rockchip,rk3588-armsom-w3", "rockchip,rk3588"; -+ -+ vcc12v_dcin: vcc12v-dcin { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ led_sys: led-sys { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "led_sys"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; // Turn on user led -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ adc-keys { -+ compatible = "adc-keys"; -+ io-channels = <&saradc 1>; -+ io-channel-names = "buttons"; -+ keyup-threshold-microvolt = <1800000>; -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+ -+ volumeup-key { -+ u-boot,dm-pre-reloc; -+ linux,code = ; -+ label = "volume up"; -+ press-threshold-microvolt = <1750>; -+ }; -+ }; -+ -+ vcc3v3_pcie30: vcc3v3-pcie30 { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie30"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&pcie3x4 { -+ u-boot,dm-pre-reloc; -+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+}; -+ -+&pcie30phy { -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+}; -diff --git a/configs/armsom-w3-rk3588_defconfig b/configs/armsom-w3-rk3588_defconfig -new file mode 100644 -index 000000000000..e22682f5beef ---- /dev/null -+++ b/configs/armsom-w3-rk3588_defconfig -@@ -0,0 +1,216 @@ -+CONFIG_ARM=y -+CONFIG_ARM_CPU_SUSPEND=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SPL_GPIO_SUPPORT=y -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_SYS_MALLOC_F_LEN=0x80000 -+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" -+CONFIG_ROCKCHIP_RK3588=y -+CONFIG_ROCKCHIP_FIT_IMAGE=y -+CONFIG_ROCKCHIP_HWID_DTB=y -+CONFIG_ROCKCHIP_VENDOR_PARTITION=y -+CONFIG_USING_KERNEL_DTB_V2=y -+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y -+CONFIG_ROCKCHIP_NEW_IDB=y -+CONFIG_LOADER_INI="RK3588MINIALL.ini" -+CONFIG_TRUST_INI="RK3588TRUST.ini" -+CONFIG_SPL_SERIAL_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -+CONFIG_TARGET_EVB_RK3588=y -+CONFIG_SPL_LIBDISK_SUPPORT=y -+CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_SPI_SUPPORT=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3588-armsom-w3" -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_IMAGE_POST_PROCESS=y -+CONFIG_FIT_HW_CRYPTO=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y -+CONFIG_SPL_FIT_HW_CRYPTO=y -+# CONFIG_SPL_SYS_DCACHE_OFF is not set -+CONFIG_BOOTDELAY=0 -+CONFIG_DISABLE_CONSOLE=y -+CONFIG_SYS_CONSOLE_INFO_QUIET=y -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_ANDROID_BOOTLOADER=y -+CONFIG_ANDROID_AVB=y -+CONFIG_ANDROID_BOOT_IMAGE_HASH=y -+CONFIG_SPL_BOARD_INIT=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 -+CONFIG_SPL_MMC_WRITE=y -+CONFIG_SPL_MTD_SUPPORT=y -+CONFIG_SPL_ATF=y -+CONFIG_FASTBOOT_BUF_ADDR=0xc00800 -+CONFIG_FASTBOOT_BUF_SIZE=0x04000000 -+CONFIG_FASTBOOT_FLASH=y -+CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_DTIMG=y -+# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_IMI is not set -+# CONFIG_CMD_IMLS is not set -+# CONFIG_CMD_XIMG is not set -+# CONFIG_CMD_LZMADEC is not set -+# CONFIG_CMD_UNZIP is not set -+# CONFIG_CMD_FLASH is not set -+# CONFIG_CMD_FPGA is not set -+CONFIG_CMD_GPT=y -+# CONFIG_CMD_LOADB is not set -+# CONFIG_CMD_LOADS is not set -+CONFIG_CMD_BOOT_ANDROID=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_SF=y -+CONFIG_CMD_SPI=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_USB_MASS_STORAGE=y -+# CONFIG_CMD_ITEST is not set -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TFTPPUT=y -+CONFIG_CMD_TFTP_BOOTM=y -+CONFIG_CMD_TFTP_FLASH=y -+# CONFIG_CMD_MISC is not set -+CONFIG_CMD_MTD_BLK=y -+# CONFIG_SPL_DOS_PARTITION is not set -+# CONFIG_ISO_PARTITION is not set -+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_SPL_DTB_MINIMUM=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+# CONFIG_NET_TFTP_VARS is not set -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+# CONFIG_SARADC_ROCKCHIP is not set -+CONFIG_SARADC_ROCKCHIP_V2=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_SPL_CLK_SCMI=y -+CONFIG_DM_CRYPTO=y -+CONFIG_SPL_DM_CRYPTO=y -+CONFIG_ROCKCHIP_CRYPTO_V2=y -+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y -+CONFIG_SCMI_FIRMWARE=y -+CONFIG_SPL_SCMI_FIRMWARE=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_ROCKCHIP_GPIO_V2=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_DM_KEY=y -+CONFIG_ADC_KEY=y -+CONFIG_MISC=y -+CONFIG_SPL_MISC=y -+CONFIG_MISC_DECOMPRESS=y -+CONFIG_SPL_MISC_DECOMPRESS=y -+CONFIG_ROCKCHIP_OTP=y -+CONFIG_ROCKCHIP_HW_DECOMPRESS=y -+CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y -+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_MTD=y -+CONFIG_MTD_BLK=y -+CONFIG_MTD_DEVICE=y -+CONFIG_NAND=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_SPI_FLASH=y -+CONFIG_SF_DEFAULT_SPEED=80000000 -+CONFIG_SPI_FLASH_EON=y -+CONFIG_SPI_FLASH_GIGADEVICE=y -+CONFIG_SPI_FLASH_MACRONIX=y -+CONFIG_SPI_FLASH_SST=y -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_SPI_FLASH_XMC=y -+CONFIG_SPI_FLASH_XTX=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_DM_ETH=y -+CONFIG_DM_ETH_PHY=y -+CONFIG_DWC_ETH_QOS=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_NVME=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_DM_PCI_COMPAT=y -+CONFIG_PCIE_DW_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y -+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_SPI_RK8XX=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_REGULATOR_RK860X=y -+CONFIG_REGULATOR_RK806=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_ROCKCHIP_SDRAM_COMMON=y -+CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 -+CONFIG_DM_RESET=y -+CONFIG_SPL_DM_RESET=y -+CONFIG_SPL_RESET_ROCKCHIP=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_BASE=0xFEB50000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_ROCKCHIP_SPI=y -+CONFIG_ROCKCHIP_SFC=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_XHCI_PCI=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GADGET=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_USB_STORAGE=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_MANUFACTURER="Rockchip" -+CONFIG_USB_GADGET_VENDOR_NUM=0x2207 -+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a -+CONFIG_USB_GADGET_DOWNLOAD=y -+CONFIG_DM_VIDEO=y -+CONFIG_DISPLAY=y -+CONFIG_DRM_ROCKCHIP=y -+CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y -+CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y -+CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y -+CONFIG_USE_TINY_PRINTF=y -+CONFIG_LIB_RAND=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_RSA=y -+CONFIG_SPL_RSA=y -+CONFIG_RSA_N_SIZE=0x200 -+CONFIG_RSA_E_SIZE=0x10 -+CONFIG_RSA_C_SIZE=0x20 -+CONFIG_LZ4=y -+CONFIG_ERRNO_STR=y -+# CONFIG_EFI_LOADER is not set -+CONFIG_AVB_LIBAVB=y -+CONFIG_AVB_LIBAVB_AB=y -+CONFIG_AVB_LIBAVB_ATX=y -+CONFIG_AVB_LIBAVB_USER=y -+CONFIG_RK_AVB_LIBAVB_USER=y -+CONFIG_OPTEE_CLIENT=y -+CONFIG_OPTEE_V2=y --- -Armbian - diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/0105-Add-defconfig-and-dtb-of-armsom-sige7.patch b/patch/u-boot/legacy/u-boot-radxa-rk3588/0105-Add-defconfig-and-dtb-of-armsom-sige7.patch deleted file mode 100644 index 1d12407850b5..000000000000 --- a/patch/u-boot/legacy/u-boot-radxa-rk3588/0105-Add-defconfig-and-dtb-of-armsom-sige7.patch +++ /dev/null @@ -1,409 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: amazingfate -Date: Thu, 2 May 2024 01:44:49 +0800 -Subject: Add defconfig and dtb of armsom-sige7 - ---- - arch/arm/dts/rk3588-armsom-sige7.dts | 161 +++++++ - configs/armsom-sige7-rk3588_defconfig | 223 ++++++++++ - 2 files changed, 384 insertions(+) - -diff --git a/arch/arm/dts/rk3588-armsom-sige7.dts b/arch/arm/dts/rk3588-armsom-sige7.dts -new file mode 100755 -index 000000000000..39400da5e7e2 ---- /dev/null -+++ b/arch/arm/dts/rk3588-armsom-sige7.dts -@@ -0,0 +1,161 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd -+ * -+ */ -+ -+/dts-v1/; -+#include "rk3588.dtsi" -+#include "rk3588-u-boot.dtsi" -+#include -+#include -+ -+/ { -+ model = "ArmSoM SIGE7"; -+ compatible = "armsom,armsom-sige7", "rockchip,rk3588"; -+ -+ vcc12v_dcin: vcc12v-dcin { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc12v_dcin"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <12000000>; -+ regulator-max-microvolt = <12000000>; -+ }; -+ -+ vcc5v0_sys: vcc5v0-sys { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc5v0_sys"; -+ regulator-always-on; -+ regulator-boot-on; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ vin-supply = <&vcc12v_dcin>; -+ }; -+ -+ led_sys: led-sys { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "led_sys"; -+ enable-active-high; -+ gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; // Turn on user led -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+ -+ adc-keys { -+ compatible = "adc-keys"; -+ io-channels = <&saradc 1>; -+ io-channel-names = "buttons"; -+ keyup-threshold-microvolt = <1800000>; -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+ -+ volumeup-key { -+ u-boot,dm-pre-reloc; -+ linux,code = ; -+ label = "volume up"; -+ press-threshold-microvolt = <1750>; -+ }; -+ }; -+ -+ vcc3v3_pcie30: vcc3v3-pcie30 { -+ u-boot,dm-pre-reloc; -+ compatible = "regulator-fixed"; -+ regulator-name = "vcc3v3_pcie30"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ enable-active-high; -+ gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; -+ regulator-boot-on; -+ regulator-always-on; -+ vin-supply = <&vcc5v0_sys>; -+ }; -+}; -+ -+&i2c3 { -+ u-boot,dm-pre-reloc; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&i2c3m0_xfer>; -+ -+ status = "okay"; -+ -+ usbc0: fusb302@22 { -+ compatible = "fcs,fusb302"; -+ u-boot,dm-pre-reloc; -+ reg = <0x22>; -+ interrupt-parent = <&gpio3>; -+ interrupts = ; -+ int-n-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&usbc0_int>; -+ // vbus-supply = <&vcc12v_dcin>; -+ status = "okay"; -+ -+ usb_con: connector { -+ u-boot,dm-pre-reloc; -+ compatible = "usb-c-connector"; -+ label = "USB-C"; -+ data-role = "dual"; -+ power-role = "sink"; -+ try-power-role = "sink"; -+ op-sink-microwatt = <1000000>; -+ sink-pdos = -+ ; -+ }; -+ }; -+}; -+ -+&pinctrl { -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+ -+ usbc { -+ u-boot,dm-pre-reloc; -+ usbc0_int: usbc0-int { -+ u-boot,dm-pre-reloc; -+ rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; -+ }; -+ }; -+}; -+ -+&i2c3m0_xfer { -+ u-boot,dm-pre-reloc; -+}; -+ -+&php_grf { -+ u-boot,dm-pre-reloc; -+}; -+ -+&ioc { -+ u-boot,dm-pre-reloc; -+}; -+ -+&cru { -+ u-boot,dm-pre-reloc; -+}; -+ -+&pcfg_pull_none_smt { -+ u-boot,dm-pre-reloc; -+}; -+ -+&gpio3 { -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+}; -+ -+&pcie3x4 { -+ u-boot,dm-pre-reloc; -+ reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; -+ status = "okay"; -+ -+}; -+ -+&pcie30phy { -+ u-boot,dm-pre-reloc; -+ status = "okay"; -+}; -diff --git a/configs/armsom-sige7-rk3588_defconfig b/configs/armsom-sige7-rk3588_defconfig -new file mode 100755 -index 000000000000..41fc8c029c67 ---- /dev/null -+++ b/configs/armsom-sige7-rk3588_defconfig -@@ -0,0 +1,223 @@ -+CONFIG_ARM=y -+CONFIG_ARM_CPU_SUSPEND=y -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_SPL_GPIO_SUPPORT=y -+CONFIG_SPL_LIBCOMMON_SUPPORT=y -+CONFIG_SPL_LIBGENERIC_SUPPORT=y -+CONFIG_SYS_MALLOC_F_LEN=0x80000 -+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" -+CONFIG_ROCKCHIP_RK3588=y -+CONFIG_ROCKCHIP_FIT_IMAGE=y -+CONFIG_ROCKCHIP_HWID_DTB=y -+CONFIG_ROCKCHIP_VENDOR_PARTITION=y -+CONFIG_USING_KERNEL_DTB_V2=y -+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y -+CONFIG_ROCKCHIP_NEW_IDB=y -+CONFIG_LOADER_INI="RK3588MINIALL.ini" -+CONFIG_TRUST_INI="RK3588TRUST.ini" -+CONFIG_SPL_SERIAL_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -+CONFIG_TARGET_EVB_RK3588=y -+CONFIG_SPL_LIBDISK_SUPPORT=y -+CONFIG_SPL_SPI_FLASH_SUPPORT=y -+CONFIG_SPL_SPI_SUPPORT=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3588-armsom-sige7" -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_IMAGE_POST_PROCESS=y -+CONFIG_FIT_HW_CRYPTO=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y -+CONFIG_SPL_FIT_HW_CRYPTO=y -+# CONFIG_SPL_SYS_DCACHE_OFF is not set -+CONFIG_BOOTDELAY=0 -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_ANDROID_BOOTLOADER=y -+CONFIG_ANDROID_AVB=y -+CONFIG_ANDROID_BOOT_IMAGE_HASH=y -+CONFIG_SPL_BOARD_INIT=y -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set -+CONFIG_SPL_SEPARATE_BSS=y -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y -+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 -+CONFIG_SPL_MMC_WRITE=y -+CONFIG_SPL_MTD_SUPPORT=y -+CONFIG_SPL_ATF=y -+CONFIG_FASTBOOT_BUF_ADDR=0xc00800 -+CONFIG_FASTBOOT_BUF_SIZE=0x04000000 -+CONFIG_FASTBOOT_FLASH=y -+CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -+CONFIG_CMD_BOOTZ=y -+CONFIG_CMD_DTIMG=y -+# CONFIG_CMD_ELF is not set -+# CONFIG_CMD_IMI is not set -+# CONFIG_CMD_IMLS is not set -+# CONFIG_CMD_XIMG is not set -+# CONFIG_CMD_LZMADEC is not set -+# CONFIG_CMD_UNZIP is not set -+# CONFIG_CMD_FLASH is not set -+# CONFIG_CMD_FPGA is not set -+CONFIG_CMD_GPT=y -+# CONFIG_CMD_LOADB is not set -+# CONFIG_CMD_LOADS is not set -+CONFIG_CMD_BOOT_ANDROID=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_SF=y -+CONFIG_CMD_SPI=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_USB_MASS_STORAGE=y -+# CONFIG_CMD_ITEST is not set -+# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_TFTPPUT=y -+CONFIG_CMD_TFTP_BOOTM=y -+CONFIG_CMD_TFTP_FLASH=y -+# CONFIG_CMD_MISC is not set -+CONFIG_CMD_MTD_BLK=y -+# CONFIG_SPL_DOS_PARTITION is not set -+# CONFIG_ISO_PARTITION is not set -+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_SPL_DTB_MINIMUM=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_OF_U_BOOT_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+# CONFIG_NET_TFTP_VARS is not set -+CONFIG_REGMAP=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SYSCON=y -+CONFIG_SPL_SYSCON=y -+# CONFIG_SARADC_ROCKCHIP is not set -+CONFIG_SARADC_ROCKCHIP_V2=y -+CONFIG_CLK=y -+CONFIG_SPL_CLK=y -+CONFIG_CLK_SCMI=y -+CONFIG_SPL_CLK_SCMI=y -+CONFIG_DM_CRYPTO=y -+CONFIG_SPL_DM_CRYPTO=y -+CONFIG_ROCKCHIP_CRYPTO_V2=y -+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y -+CONFIG_DM_RNG=y -+CONFIG_RNG_ROCKCHIP=y -+CONFIG_SCMI_FIRMWARE=y -+CONFIG_SPL_SCMI_FIRMWARE=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_ROCKCHIP_GPIO_V2=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_I2C_MUX=y -+CONFIG_DM_KEY=y -+CONFIG_ADC_KEY=y -+CONFIG_MISC=y -+CONFIG_SPL_MISC=y -+CONFIG_MISC_DECOMPRESS=y -+CONFIG_SPL_MISC_DECOMPRESS=y -+CONFIG_ROCKCHIP_OTP=y -+CONFIG_ROCKCHIP_HW_DECOMPRESS=y -+CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y -+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_MTD=y -+CONFIG_MTD_BLK=y -+CONFIG_MTD_DEVICE=y -+CONFIG_NAND=y -+CONFIG_MTD_SPI_NAND=y -+CONFIG_SPI_FLASH=y -+CONFIG_SF_DEFAULT_SPEED=80000000 -+CONFIG_SPI_FLASH_EON=y -+CONFIG_SPI_FLASH_GIGADEVICE=y -+CONFIG_SPI_FLASH_MACRONIX=y -+CONFIG_SPI_FLASH_SST=y -+CONFIG_SPI_FLASH_WINBOND=y -+CONFIG_SPI_FLASH_XMC=y -+CONFIG_SPI_FLASH_XTX=y -+CONFIG_SPI_FLASH_MTD=y -+CONFIG_DM_ETH=y -+CONFIG_DM_ETH_PHY=y -+CONFIG_DWC_ETH_QOS=y -+CONFIG_GMAC_ROCKCHIP=y -+CONFIG_NVME=y -+CONFIG_PCI=y -+CONFIG_DM_PCI=y -+CONFIG_DM_PCI_COMPAT=y -+CONFIG_PCIE_DW_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y -+CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y -+CONFIG_PINCTRL=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_SPI_RK8XX=y -+CONFIG_DM_POWER_DELIVERY=y -+CONFIG_TYPEC_TCPM=y -+CONFIG_TYPEC_TCPCI=y -+CONFIG_TYPEC_HUSB311=y -+CONFIG_TYPEC_FUSB302=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_REGULATOR_GPIO=y -+CONFIG_REGULATOR_RK860X=y -+CONFIG_REGULATOR_RK806=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_RAM=y -+CONFIG_SPL_RAM=y -+CONFIG_TPL_RAM=y -+CONFIG_ROCKCHIP_SDRAM_COMMON=y -+CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 -+CONFIG_DM_RESET=y -+CONFIG_SPL_DM_RESET=y -+CONFIG_SPL_RESET_ROCKCHIP=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_BASE=0xFEB50000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_ROCKCHIP_SPI=y -+CONFIG_ROCKCHIP_SFC=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DWC3=y -+CONFIG_USB_XHCI_PCI=y -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_GENERIC=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_GENERIC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GADGET=y -+CONFIG_USB_DWC3_GENERIC=y -+CONFIG_USB_STORAGE=y -+CONFIG_USB_GADGET=y -+CONFIG_USB_GADGET_MANUFACTURER="Rockchip" -+CONFIG_USB_GADGET_VENDOR_NUM=0x2207 -+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a -+CONFIG_USB_GADGET_DOWNLOAD=y -+CONFIG_DM_VIDEO=y -+CONFIG_DISPLAY=y -+CONFIG_DRM_ROCKCHIP=y -+CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y -+CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y -+CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y -+CONFIG_USE_TINY_PRINTF=y -+CONFIG_LIB_RAND=y -+CONFIG_SPL_TINY_MEMSET=y -+CONFIG_RSA=y -+CONFIG_SPL_RSA=y -+CONFIG_RSA_N_SIZE=0x200 -+CONFIG_RSA_E_SIZE=0x10 -+CONFIG_RSA_C_SIZE=0x20 -+CONFIG_LZ4=y -+CONFIG_ERRNO_STR=y -+# CONFIG_EFI_LOADER is not set -+CONFIG_AVB_LIBAVB=y -+CONFIG_AVB_LIBAVB_AB=y -+CONFIG_AVB_LIBAVB_ATX=y -+CONFIG_AVB_LIBAVB_USER=y -+CONFIG_RK_AVB_LIBAVB_USER=y -+CONFIG_OPTEE_CLIENT=y -+CONFIG_OPTEE_V2=y -+CONFIG_CMD_CHARGE_DISPLAY=y -+CONFIG_DM_CHARGE_DISPLAY=y --- -Armbian - diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/armsom-sige7-rk3588_defconfig b/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/armsom-sige7-rk3588_defconfig new file mode 100644 index 000000000000..41fc8c029c67 --- /dev/null +++ b/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/armsom-sige7-rk3588_defconfig @@ -0,0 +1,223 @@ +CONFIG_ARM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x80000 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_FIT_IMAGE=y +CONFIG_ROCKCHIP_HWID_DTB=y +CONFIG_ROCKCHIP_VENDOR_PARTITION=y +CONFIG_USING_KERNEL_DTB_V2=y +CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y +CONFIG_ROCKCHIP_NEW_IDB=y +CONFIG_LOADER_INI="RK3588MINIALL.ini" +CONFIG_TRUST_INI="RK3588TRUST.ini" +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="rk3588-armsom-sige7" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_FIT_HW_CRYPTO=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_FIT_HW_CRYPTO=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_BOOTDELAY=0 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_ANDROID_BOOTLOADER=y +CONFIG_ANDROID_AVB=y +CONFIG_ANDROID_BOOT_IMAGE_HASH=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 +CONFIG_SPL_MMC_WRITE=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_FASTBOOT_BUF_ADDR=0xc00800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_BOOT_ANDROID=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTP_BOOTM=y +CONFIG_CMD_TFTP_FLASH=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTD_BLK=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DTB_MINIMUM=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_U_BOOT_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +# CONFIG_NET_TFTP_VARS is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SARADC_ROCKCHIP is not set +CONFIG_SARADC_ROCKCHIP_V2=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_DM_CRYPTO=y +CONFIG_SPL_DM_CRYPTO=y +CONFIG_ROCKCHIP_CRYPTO_V2=y +CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_SCMI_FIRMWARE=y +CONFIG_SPL_SCMI_FIRMWARE=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_GPIO_V2=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_I2C_MUX=y +CONFIG_DM_KEY=y +CONFIG_ADC_KEY=y +CONFIG_MISC=y +CONFIG_SPL_MISC=y +CONFIG_MISC_DECOMPRESS=y +CONFIG_SPL_MISC_DECOMPRESS=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_SECURE_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_MTD_BLK=y +CONFIG_MTD_DEVICE=y +CONFIG_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_SPI_RK8XX=y +CONFIG_DM_POWER_DELIVERY=y +CONFIG_TYPEC_TCPM=y +CONFIG_TYPEC_TCPCI=y +CONFIG_TYPEC_HUSB311=y +CONFIG_TYPEC_FUSB302=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK860X=y +CONFIG_REGULATOR_RK806=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 +CONFIG_DM_RESET=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_RESET_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x350a +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y +CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y +CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_LIB_RAND=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_N_SIZE=0x200 +CONFIG_RSA_E_SIZE=0x10 +CONFIG_RSA_C_SIZE=0x20 +CONFIG_LZ4=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set +CONFIG_AVB_LIBAVB=y +CONFIG_AVB_LIBAVB_AB=y +CONFIG_AVB_LIBAVB_ATX=y +CONFIG_AVB_LIBAVB_USER=y +CONFIG_RK_AVB_LIBAVB_USER=y +CONFIG_OPTEE_CLIENT=y +CONFIG_OPTEE_V2=y +CONFIG_CMD_CHARGE_DISPLAY=y +CONFIG_DM_CHARGE_DISPLAY=y diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/armsom-w3-rk3588_defconfig b/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/armsom-w3-rk3588_defconfig new file mode 100644 index 000000000000..e22682f5beef --- /dev/null +++ b/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/armsom-w3-rk3588_defconfig @@ -0,0 +1,216 @@ +CONFIG_ARM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x80000 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_FIT_IMAGE=y +CONFIG_ROCKCHIP_HWID_DTB=y +CONFIG_ROCKCHIP_VENDOR_PARTITION=y +CONFIG_USING_KERNEL_DTB_V2=y +CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y +CONFIG_ROCKCHIP_NEW_IDB=y +CONFIG_LOADER_INI="RK3588MINIALL.ini" +CONFIG_TRUST_INI="RK3588TRUST.ini" +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="rk3588-armsom-w3" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_FIT_HW_CRYPTO=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_FIT_HW_CRYPTO=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_BOOTDELAY=0 +CONFIG_DISABLE_CONSOLE=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_ANDROID_BOOTLOADER=y +CONFIG_ANDROID_AVB=y +CONFIG_ANDROID_BOOT_IMAGE_HASH=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 +CONFIG_SPL_MMC_WRITE=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_FASTBOOT_BUF_ADDR=0xc00800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_BOOT_ANDROID=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTP_BOOTM=y +CONFIG_CMD_TFTP_FLASH=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTD_BLK=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DTB_MINIMUM=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +# CONFIG_NET_TFTP_VARS is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SARADC_ROCKCHIP is not set +CONFIG_SARADC_ROCKCHIP_V2=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_DM_CRYPTO=y +CONFIG_SPL_DM_CRYPTO=y +CONFIG_ROCKCHIP_CRYPTO_V2=y +CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_SCMI_FIRMWARE=y +CONFIG_SPL_SCMI_FIRMWARE=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_GPIO_V2=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_DM_KEY=y +CONFIG_ADC_KEY=y +CONFIG_MISC=y +CONFIG_SPL_MISC=y +CONFIG_MISC_DECOMPRESS=y +CONFIG_SPL_MISC_DECOMPRESS=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_SECURE_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_MTD_BLK=y +CONFIG_MTD_DEVICE=y +CONFIG_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_SPI_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK860X=y +CONFIG_REGULATOR_RK806=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 +CONFIG_DM_RESET=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_RESET_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x350a +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y +CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y +CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_LIB_RAND=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_N_SIZE=0x200 +CONFIG_RSA_E_SIZE=0x10 +CONFIG_RSA_C_SIZE=0x20 +CONFIG_LZ4=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set +CONFIG_AVB_LIBAVB=y +CONFIG_AVB_LIBAVB_AB=y +CONFIG_AVB_LIBAVB_ATX=y +CONFIG_AVB_LIBAVB_USER=y +CONFIG_RK_AVB_LIBAVB_USER=y +CONFIG_OPTEE_CLIENT=y +CONFIG_OPTEE_V2=y diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/nanopc_cm3588_defconfig b/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/nanopc_cm3588_defconfig new file mode 100644 index 000000000000..47bed0ea5316 --- /dev/null +++ b/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/nanopc_cm3588_defconfig @@ -0,0 +1,216 @@ +CONFIG_ARM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x80000 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_USB_BOOT=y +CONFIG_ROCKCHIP_FIT_IMAGE=y +CONFIG_ROCKCHIP_HWID_DTB=y +CONFIG_ROCKCHIP_VENDOR_PARTITION=y +CONFIG_USING_KERNEL_DTB_V2=y +CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y +CONFIG_ROCKCHIP_NEW_IDB=y +CONFIG_LOADER_INI="RK3588MINIALL.ini" +CONFIG_TRUST_INI="RK3588TRUST.ini" +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-cm3588" +CONFIG_DEBUG_UART=y +CONFIG_LOCALVERSION="-armbian" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_FIT=y +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_FIT_HW_CRYPTO=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_FIT_HW_CRYPTO=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_BOOTDELAY=0 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_ANDROID_BOOTLOADER=y +CONFIG_ANDROID_AVB=y +CONFIG_ANDROID_BOOT_IMAGE_HASH=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 +CONFIG_SPL_MMC_WRITE=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_FASTBOOT_BUF_ADDR=0xc00800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_BOOT_ANDROID=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTP_BOOTM=y +CONFIG_CMD_TFTP_FLASH=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTD_BLK=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DTB_MINIMUM=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +# CONFIG_NET_TFTP_VARS is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SARADC_ROCKCHIP is not set +CONFIG_SARADC_ROCKCHIP_V2=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_DM_CRYPTO=y +CONFIG_SPL_DM_CRYPTO=y +CONFIG_ROCKCHIP_CRYPTO_V2=y +CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_SCMI_FIRMWARE=y +CONFIG_SPL_SCMI_FIRMWARE=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_GPIO_V2=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_DM_KEY=y +CONFIG_ADC_KEY=y +CONFIG_MISC=y +CONFIG_SPL_MISC=y +CONFIG_MISC_DECOMPRESS=y +CONFIG_SPL_MISC_DECOMPRESS=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_SECURE_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_MTD_BLK=y +CONFIG_MTD_DEVICE=y +CONFIG_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_SPI_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK860X=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 +CONFIG_DM_RESET=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_RESET_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x350a +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y +CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y +CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_LIB_RAND=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_N_SIZE=0x200 +CONFIG_RSA_E_SIZE=0x10 +CONFIG_RSA_C_SIZE=0x20 +CONFIG_LZ4=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set +CONFIG_AVB_LIBAVB=y +CONFIG_AVB_LIBAVB_AB=y +CONFIG_AVB_LIBAVB_ATX=y +CONFIG_AVB_LIBAVB_USER=y +CONFIG_RK_AVB_LIBAVB_USER=y diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/nanopc_t6_defconfig b/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/nanopc_t6_defconfig new file mode 100644 index 000000000000..9dde4b386a83 --- /dev/null +++ b/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/nanopc_t6_defconfig @@ -0,0 +1,216 @@ +CONFIG_ARM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x80000 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_USB_BOOT=y +CONFIG_ROCKCHIP_FIT_IMAGE=y +CONFIG_ROCKCHIP_HWID_DTB=y +CONFIG_ROCKCHIP_VENDOR_PARTITION=y +CONFIG_USING_KERNEL_DTB_V2=y +CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y +CONFIG_ROCKCHIP_NEW_IDB=y +CONFIG_LOADER_INI="RK3588MINIALL.ini" +CONFIG_TRUST_INI="RK3588TRUST.ini" +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="rk3588-nanopc-t6" +CONFIG_DEBUG_UART=y +CONFIG_LOCALVERSION="-armbian" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_FIT=y +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_FIT_HW_CRYPTO=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_FIT_HW_CRYPTO=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_BOOTDELAY=0 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_ANDROID_BOOTLOADER=y +CONFIG_ANDROID_AVB=y +CONFIG_ANDROID_BOOT_IMAGE_HASH=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 +CONFIG_SPL_MMC_WRITE=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_FASTBOOT_BUF_ADDR=0xc00800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_BOOT_ANDROID=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTP_BOOTM=y +CONFIG_CMD_TFTP_FLASH=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTD_BLK=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DTB_MINIMUM=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +# CONFIG_NET_TFTP_VARS is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SARADC_ROCKCHIP is not set +CONFIG_SARADC_ROCKCHIP_V2=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_DM_CRYPTO=y +CONFIG_SPL_DM_CRYPTO=y +CONFIG_ROCKCHIP_CRYPTO_V2=y +CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_SCMI_FIRMWARE=y +CONFIG_SPL_SCMI_FIRMWARE=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_GPIO_V2=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_DM_KEY=y +CONFIG_ADC_KEY=y +CONFIG_MISC=y +CONFIG_SPL_MISC=y +CONFIG_MISC_DECOMPRESS=y +CONFIG_SPL_MISC_DECOMPRESS=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_SECURE_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_MTD_BLK=y +CONFIG_MTD_DEVICE=y +CONFIG_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_SPI_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK860X=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 +CONFIG_DM_RESET=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_RESET_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x350a +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y +CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y +CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_LIB_RAND=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_N_SIZE=0x200 +CONFIG_RSA_E_SIZE=0x10 +CONFIG_RSA_C_SIZE=0x20 +CONFIG_LZ4=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set +CONFIG_AVB_LIBAVB=y +CONFIG_AVB_LIBAVB_AB=y +CONFIG_AVB_LIBAVB_ATX=y +CONFIG_AVB_LIBAVB_USER=y +CONFIG_RK_AVB_LIBAVB_USER=y diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/nanopi-r6s-rk3588s_defconfig b/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/nanopi-r6s-rk3588s_defconfig new file mode 100644 index 000000000000..19bae5562928 --- /dev/null +++ b/patch/u-boot/legacy/u-boot-radxa-rk3588/defconfig/nanopi-r6s-rk3588s_defconfig @@ -0,0 +1,217 @@ +CONFIG_ARM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x80000 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_USB_BOOT=y +CONFIG_ROCKCHIP_FIT_IMAGE=y +CONFIG_ROCKCHIP_HWID_DTB=y +CONFIG_ROCKCHIP_VENDOR_PARTITION=y +CONFIG_USING_KERNEL_DTB_V2=y +CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y +CONFIG_ROCKCHIP_NEW_IDB=y +CONFIG_LOADER_INI="RK3588MINIALL.ini" +CONFIG_TRUST_INI="RK3588TRUST.ini" +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-nanopi-r6s" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_FIT_HW_CRYPTO=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_FIT_HW_CRYPTO=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_BOOTDELAY=0 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_ANDROID_BOOTLOADER=y +CONFIG_ANDROID_AVB=y +CONFIG_ANDROID_BOOT_IMAGE_HASH=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 +CONFIG_SPL_MMC_WRITE=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_FASTBOOT_BUF_ADDR=0xc00800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_BOOT_ANDROID=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTP_BOOTM=y +CONFIG_CMD_TFTP_FLASH=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTD_BLK=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DTB_MINIMUM=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +# CONFIG_NET_TFTP_VARS is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SARADC_ROCKCHIP is not set +CONFIG_SARADC_ROCKCHIP_V2=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_DM_CRYPTO=y +CONFIG_SPL_DM_CRYPTO=y +CONFIG_ROCKCHIP_CRYPTO_V2=y +CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_SCMI_FIRMWARE=y +CONFIG_SPL_SCMI_FIRMWARE=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_GPIO_V2=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_DM_KEY=y +CONFIG_ADC_KEY=y +CONFIG_MISC=y +CONFIG_SPL_MISC=y +CONFIG_MISC_DECOMPRESS=y +CONFIG_SPL_MISC_DECOMPRESS=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_SECURE_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_MTD_BLK=y +CONFIG_MTD_DEVICE=y +CONFIG_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y +CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_SPI_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK860X=y +CONFIG_REGULATOR_RK806=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 +CONFIG_DM_RESET=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_RESET_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x350a +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y +CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y +CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_LIB_RAND=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_N_SIZE=0x200 +CONFIG_RSA_E_SIZE=0x10 +CONFIG_RSA_C_SIZE=0x20 +CONFIG_LZ4=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set +CONFIG_AVB_LIBAVB=y +CONFIG_AVB_LIBAVB_AB=y +CONFIG_AVB_LIBAVB_ATX=y +CONFIG_AVB_LIBAVB_USER=y +CONFIG_RK_AVB_LIBAVB_USER=y +CONFIG_OPTEE_CLIENT=y +CONFIG_OPTEE_V2=y +CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588-armsom-sige7.dts b/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588-armsom-sige7.dts new file mode 100644 index 000000000000..39400da5e7e2 --- /dev/null +++ b/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588-armsom-sige7.dts @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; +#include "rk3588.dtsi" +#include "rk3588-u-boot.dtsi" +#include +#include + +/ { + model = "ArmSoM SIGE7"; + compatible = "armsom,armsom-sige7", "rockchip,rk3588"; + + vcc12v_dcin: vcc12v-dcin { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + led_sys: led-sys { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "led_sys"; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; // Turn on user led + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + u-boot,dm-pre-reloc; + status = "okay"; + + volumeup-key { + u-boot,dm-pre-reloc; + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <1750>; + }; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&i2c3 { + u-boot,dm-pre-reloc; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3m0_xfer>; + + status = "okay"; + + usbc0: fusb302@22 { + compatible = "fcs,fusb302"; + u-boot,dm-pre-reloc; + reg = <0x22>; + interrupt-parent = <&gpio3>; + interrupts = ; + int-n-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&usbc0_int>; + // vbus-supply = <&vcc12v_dcin>; + status = "okay"; + + usb_con: connector { + u-boot,dm-pre-reloc; + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "sink"; + try-power-role = "sink"; + op-sink-microwatt = <1000000>; + sink-pdos = + ; + }; + }; +}; + +&pinctrl { + u-boot,dm-pre-reloc; + status = "okay"; + + usbc { + u-boot,dm-pre-reloc; + usbc0_int: usbc0-int { + u-boot,dm-pre-reloc; + rockchip,pins = <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; +}; + +&i2c3m0_xfer { + u-boot,dm-pre-reloc; +}; + +&php_grf { + u-boot,dm-pre-reloc; +}; + +&ioc { + u-boot,dm-pre-reloc; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&pcfg_pull_none_smt { + u-boot,dm-pre-reloc; +}; + +&gpio3 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&pcie3x4 { + u-boot,dm-pre-reloc; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; + +}; + +&pcie30phy { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588-armsom-w3.dts b/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588-armsom-w3.dts new file mode 100644 index 000000000000..6a51591301bb --- /dev/null +++ b/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588-armsom-w3.dts @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; +#include "rk3588.dtsi" +#include "rk3588-u-boot.dtsi" +#include + +/ { + model = "ArmSoM W3 (LGA Module ArmSoM-LM5 LP4x) V1.1"; + compatible = "rockchip,rk3588-armsom-w3", "rockchip,rk3588"; + + vcc12v_dcin: vcc12v-dcin { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + led_sys: led-sys { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "led_sys"; + enable-active-high; + gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; // Turn on user led + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; + + adc-keys { + compatible = "adc-keys"; + io-channels = <&saradc 1>; + io-channel-names = "buttons"; + keyup-threshold-microvolt = <1800000>; + u-boot,dm-pre-reloc; + status = "okay"; + + volumeup-key { + u-boot,dm-pre-reloc; + linux,code = ; + label = "volume up"; + press-threshold-microvolt = <1750>; + }; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&pcie3x4 { + u-boot,dm-pre-reloc; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; + +}; + +&pcie30phy { + u-boot,dm-pre-reloc; + status = "okay"; +}; diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588-nanopc-cm3588.dts b/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588-nanopc-cm3588.dts new file mode 100644 index 000000000000..b8a8c64ee6a7 --- /dev/null +++ b/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588-nanopc-cm3588.dts @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; +#include +#include "rk3588.dtsi" +#include "rk3588-u-boot.dtsi" + +/ { + model = "FriendlyElec CM3588"; + compatible = "friendlyelec,cm3588", "rockchip,rk3588"; + + vcc12v_dcin: vcc12v-dcin { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_5v0: vcc-5v0 { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + u-boot,dm-pre-reloc; + startup-delay-us = <50000>; + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc5v0_sys>; + }; + + led_sys: led-sys { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "led_sys"; + enable-active-high; + gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; // Turn on user led + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&pcie2x1l0 { + u-boot,dm-pre-reloc; + /* 2. CON14: pcie30phy port0 lane1 */ + max-link-speed = <3>; + num-lanes = <1>; + phys = <&pcie30phy>; + reset-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; + + pcie@0,0 { + reg = <0x00200000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + nvme1: pcie@20,0 { + reg = <0x000000 0 0 0 0>; + }; + }; +}; + +&pcie2x1l1 { + u-boot,dm-pre-reloc; + /* 4. CON16: pcie30phy port1 lane1 */ + max-link-speed = <3>; + num-lanes = <1>; + phys = <&pcie30phy>; + reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; + + pcie@0,0 { + reg = <0x00300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + nvme3: pcie@30,0 { + reg = <0x000000 0 0 0 0>; + }; + }; +}; + +&pcie3x4 { + u-boot,dm-pre-reloc; + /* 1. CON13: pcie30phy port0 lane0 */ + max-link-speed = <3>; + num-lanes = <1>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; + + pcie@0,0 { + reg = <0x00000000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + nvme0: pcie@0,0 { + reg = <0x000000 0 0 0 0>; + }; + }; +}; + +&pcie3x2 { + u-boot,dm-pre-reloc; + /* 3. CON15: pcie30phy port1 lane0 */ + max-link-speed = <3>; + num-lanes = <1>; + reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; + + pcie@0,0 { + reg = <0x00100000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + + nvme2: pcie@10,0 { + reg = <0x000000 0 0 0 0>; + }; + }; +}; + +&pcie30phy { + u-boot,dm-pre-reloc; + rockchip,pcie30-phymode = ; + status = "okay"; +}; + +&combphy0_ps { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&combphy2_psu { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb2phy0_grf { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&u2phy0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&u2phy0_otg { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&usb2phy2_grf { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&u2phy2 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&u2phy2_host { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&pinctrl { + usb { + u-boot,dm-pre-reloc; + vcc5v0_host_en: vcc5v0-host-en { + u-boot,dm-pre-reloc; + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + power { + u-boot,dm-spl; + vcc_5v0_en: vcc-5v0-en { + u-boot,dm-spl; + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588-nanopc-t6.dts b/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588-nanopc-t6.dts new file mode 100644 index 000000000000..ee7c7f005cc5 --- /dev/null +++ b/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588-nanopc-t6.dts @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; +#include "rk3588.dtsi" +#include "rk3588-u-boot.dtsi" +#include + +/ { + model = "NanoPC-T6"; + compatible = "nanopc,nanopc-t6", "rockchip,rk3588"; + + vcc12v_dcin: vcc12v-dcin { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_5v0: vcc-5v0 { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc3v3_pcie30: vcc3v3-pcie30 { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_pcie30"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; + regulator-boot-on; + regulator-always-on; + startup-delay-us = <50000>; + vin-supply = <&vcc5v0_sys>; + }; + + led_sys: led-sys { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "led_sys"; + enable-active-high; + gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; // Turn on user led + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&pcie3x4 { + u-boot,dm-pre-reloc; + vpcie3v3-supply = <&vcc3v3_pcie30>; + reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie30phy { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&combphy0_ps { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&combphy2_psu { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb2phy0_grf { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&u2phy0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&u2phy0_otg { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&usb2phy2_grf { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&u2phy2 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&u2phy2_host { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&pinctrl { + usb { + u-boot,dm-pre-reloc; + vcc5v0_host_en: vcc5v0-host-en { + u-boot,dm-pre-reloc; + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + power { + u-boot,dm-spl; + vcc_5v0_en: vcc-5v0-en { + u-boot,dm-spl; + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588s-nanopi-r6s.dts b/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588s-nanopi-r6s.dts new file mode 100644 index 000000000000..4899e23fa3aa --- /dev/null +++ b/patch/u-boot/legacy/u-boot-radxa-rk3588/dt/rk3588s-nanopi-r6s.dts @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; +#include "rk3588.dtsi" +#include "rk3588-u-boot.dtsi" +#include + +/ { + model = "NanoPi R6S"; + compatible = "nanopi,nanopi-r6s", "rockchip,rk3588"; + + vcc12v_dcin: vcc12v-dcin { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc12v_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + }; + + vcc5v0_sys: vcc5v0-sys { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc12v_dcin>; + }; + + vcc_5v0: vcc-5v0 { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + enable-active-high; + gpio = <&gpio4 RK_PA3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc_5v0_en>; + vin-supply = <&vcc5v0_sys>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vcc5v0_host_en>; + vin-supply = <&vcc5v0_sys>; + }; + + led_sys: led-sys { + u-boot,dm-pre-reloc; + compatible = "regulator-fixed"; + regulator-name = "led_sys"; + enable-active-high; + gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>; // Turn on user led + regulator-boot-on; + regulator-always-on; + vin-supply = <&vcc5v0_sys>; + }; +}; + +&usb2phy0_grf { + status = "okay"; + u-boot,dm-pre-reloc; +}; + + +&u2phy0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&u2phy0_otg { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&usb2phy2_grf { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&u2phy2 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&u2phy2_host { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&pinctrl { + usb { + u-boot,dm-pre-reloc; + vcc5v0_host_en: vcc5v0-host-en { + u-boot,dm-pre-reloc; + rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + power { + u-boot,dm-spl; + vcc_5v0_en: vcc-5v0-en { + u-boot,dm-spl; + rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +};